Solenoid valve single-line communication control system and method capable of automatically distributing address codes

Abstract

The invention provides an electromagnetic valve single-line communication control system and method capable of automatically distributing address codes, and each electromagnetic valve is provided with an independent control circuit board which comprises a control chip, an input interface, a communication switching circuit, an output interface and a coil driving circuit; the control chip realizes data receiving, data verification, data analysis, data forwarding, communication link switching, address code storage, control output and the like; and the communication switching circuit is controlled according to the received instruction so as to switch the connection mode of the output interface signal line. The electromagnetic valves are cascaded through input and output interfaces; the control chip controls the electromagnetic valve coil to be powered on and powered off through the coil driving circuit. Address codes of the electromagnetic valves are automatically distributed, and the number is flexibly increased and decreased; switching of a serial link and a parallel link is achieved through the communication switching circuit, after address allocation is completed, all the electromagnetic valves receive broadcast data of a bus controller or an upper computer in a parallel state, high-speed response is achieved, no control time difference exists, and real-time performance and stability are improved.

Description

Technical Field

[0001] This invention relates to the field of solenoid valve control technology, and in particular to a solenoid valve single-line communication control system and method with automatic address code allocation. Background Technology

[0002] Solenoid valves are fundamental automation components that use electromagnetic force to control the on / off state or flow direction of fluids. They are widely used in industrial automation, machinery manufacturing, hydraulic and pneumatic systems, and other fields. Today's automated equipment and production lines are becoming increasingly comprehensive and complex, often using dozens or even hundreds of solenoid valves. However, several pain points arise in practical applications: 1. A single-coil solenoid valve requires two wires, while a double-coil solenoid valve requires at least three. When the number of solenoid valves is large and they are far from the programmable controller (PLC), the amount of wire used and the cost of wiring increase proportionally, and subsequent maintenance and troubleshooting become more difficult. 2. In traditional control methods, each solenoid valve coil requires an output port of the PLC. To address insufficient output capacity of the PLC or to prevent direct damage to the output port, many devices add intermediate relays (or solid-state relays) to increase driving capability and achieve safety isolation. Undoubtedly, this approach significantly increases cost, power consumption, and workload.

[0003] To address the first problem mentioned above, multi-pin interface integrated valve manifolds emerged, simplifying pneumatic system wiring through multi-pin plugs and multi-strand cables. However, these valve manifolds require dedicated under-panel manifolds, and the number of manifolds per unit is limited by the number of pins on the connector. While this method reduced wiring difficulty, it did not significantly improve operating costs, and may even have increased them. Furthermore, this approach did not solve the second problem. To address both issues, the introduction of fieldbus technology completely resolved the multi-strand cable wiring problem, significantly reducing wiring workload and the number of programmable controller output ports required. Currently, commercially available fieldbus valve manifolds all use integrated fieldbus controller I / O to drive solenoid valve coils, employing under-panel manifolds with built-in circuit boards. Users can only purchase a fixed quantity, and the price is high; the number of solenoid valves cannot be freely increased or decreased later due to changes in the control scheme. Later, modular and intelligent valve manifolds only improved integration, aesthetics, and local functionality, offering no substantial difference compared to earlier fieldbus valve manifolds.

[0004] The aforementioned solutions addressed wiring and programmable controller output port occupancy issues to varying degrees, but none of them solved the problem of flexible expansion for users, and their cost-effectiveness was not high.

[0005] Using communication methods such as CAN, LIN, and 485 to achieve bus connection of individual solenoid valves is technically feasible and can be expanded freely and flexibly. However, the master-slave communication method requires that each solenoid valve be pre-set with an address code. Moreover, such solutions are costly, complex to use, and difficult to integrate in a small size, making them difficult to promote and apply.

[0006] In addition, some engineers use a single-wire return-to-zero code serial cascading communication method to achieve address-code-free cascading. For example, patent application CN118669586A discloses a method for free cascading control of solenoid valves without address codes. This method involves connecting the output of the preceding stage to the input of the following stage, with the bus controller sending a fixed-format data sequence. Each solenoid valve latches the first segment of data for its own control and forwards the remaining data, thus achieving free cascading control. In fact, this method has been used in the LED lighting industry for several years, such as in dedicated RGB control chips like the WS2811 and TM1804. While this solution is simple to apply and low-cost, it suffers from the problem of no verification mechanism and complete openness in data stream transmission. Furthermore, to achieve a high refresh rate, a high baud rate is required for step-by-step forwarding, making it difficult to meet the stability, reliability, and security requirements of industrial control.

[0007] In view of this, it is necessary to improve the existing solenoid valve control technology to solve the above problems. Summary of the Invention

[0008] The technical problem to be solved by this invention is: in order to overcome the shortcomings of the prior art, this invention provides a single-line communication control system and method for solenoid valves with automatic address code allocation, which solves the pain point of traditional bus-type solenoid valve groups being difficult to expand flexibly, as well as the slow response speed and unreliability of valve groups in the single-line return-to-zero code serial cascade method. Ultimately, it realizes a flexibly expandable bus valve group in a cost-controllable and cost-effective manner, and promotes its application in the field of industrial control.

[0009] The technical solution adopted by this invention to solve its technical problem is: a single-line communication control system for an automatically assigned address code solenoid valve, comprising a valve group, wherein the valve group includes several solenoid valves, each solenoid valve having an independent control circuit board, the control circuit board including at least a control chip, an input interface, a signal waveform shaping and driving circuit, a communication switching circuit, an output interface, and a coil driving circuit, wherein... The input and output interfaces have the same wiring sequence, including a pair of power supply lines and a communication signal line. The communication switching circuit includes at least two input terminals and one output terminal. One end of the input interface communication signal line is connected to the output interface of the preceding adjacent solenoid valve or the host computer. The other end is split into two paths after passing through the signal waveform shaping and driving circuit. One path is connected to the data input pin RXD of the control chip, and the other path is connected to one input terminal of the communication switching circuit. The data output pin TXD of the control chip is connected to the other input terminal of the communication switching circuit. The communication switching circuit can switch between the two input terminals and connect one of the input terminals to the output terminal of the communication switching circuit. The output terminal of the communication switching circuit is connected to one end of the output interface communication signal line, and the other end of the output interface communication signal line is connected to the input interface of the following adjacent solenoid valve. The solenoid valves are cascaded through the input and output interfaces of the control circuit board. The control chip is also connected to the coil driving circuit for outputting driving signals to drive the solenoid valve coil.

[0010] Specifically, the communication switching circuit uses a single-pole double-throw multiplexer. Its common terminal serves as the output terminal, connected to the communication signal line of the output interface. The normally open terminal serves as an input terminal, connected to the data input pin RXD of the control chip. The normally closed terminal serves as another input terminal, connected to the data output pin TXD of the control chip. The control chip can control the switching of the multiplexer between the normally open and normally closed terminals according to the received instructions, so as to switch the connection mode of the output interface signal line.

[0011] Furthermore, it also includes a voltage regulator circuit and an indicator light circuit. The voltage regulator circuit is connected between the power supply terminal of the input interface and the power supply terminal of the control chip to provide a suitable operating power for the control chip. The indicator light circuit is connected to the control chip and is used to indicate the address allocation status and data reception status of the solenoid valve.

[0012] Specifically, the control circuit board includes a control chip U4, an input interface P1, a signal waveform shaping and driving circuit, a multiplexer U2, an output interface P2, a coil driving circuit, a voltage regulator circuit, and an indicator light circuit. The signal waveform shaping and driving circuit uses a Schmitt trigger buffer U3. The Din pin of the input interface P1 is connected to the input pin IN_A of the Schmitt trigger buffer U3. The output pin OUT_Y of the Schmitt trigger buffer U3 is divided into two paths. One path is connected to the RXD pin of the control chip U4 through resistor R1, and the other path is connected to the NO pin of the multiplexer U2. The NC pin of the multiplexer U2 is connected to the TXD pin of the control chip U4. The COM pin of the multiplexer U2 is connected to the Dout pin of the output interface P2. The IN pin of the multiplexer U2 is connected to the DIR pin of the control chip U4. The communication signal line of the input interface is connected to the input of Schmitt buffer U3, and the output of Schmitt buffer U3 is connected to the data receiving pin of control chip U4. Through the Schmitt threshold characteristic, the noise signal generated by electromagnetic interference is filtered out; the distorted and blurred digital signal is corrected into a standard square wave signal; the data signal input on the communication signal line of each solenoid valve input interface first passes through the Schmitt buffer before being output, realizing step-by-step relay drive, improving the signal load capacity, driving more subsequent circuits or long-distance transmission, avoiding signal attenuation, so as to achieve a longer transmission distance and better anti-interference performance.

[0013] The coil drive circuit includes resistors R3, R4, and R5, a field-effect transistor Q1, a diode D4, and a light-emitting diode D2. The solenoid valve coil has two terminals P3 and P4. The OUTPUT pin of the control chip U4 is connected to one end of resistor R4, and the other end of resistor R4 is connected to the gate of the field-effect transistor Q1. The drain of the field-effect transistor Q1 is grounded to GND. Resistor R5 is connected in parallel between the gate and drain of the field-effect transistor Q1. The source of the field-effect transistor Q1 is connected to the anode of the diode D4, and the cathode of the diode D4 is connected to the power supply VCC. The light-emitting diode D2 and resistor R3 are connected in series and then in parallel between terminals P3 and P4. The anode of the light-emitting diode D2 and terminal P3 are both connected to the power supply VCC. The voltage regulator circuit includes a voltage regulator chip U1, a Zener diode D1, and capacitors C1, C2, and C3. The INPUT pin of the voltage regulator chip U1 is connected to a 24V power supply, the OUTPUT pin outputs a 5V power supply, and the GND pin is grounded. The Zener diode D1 and capacitor C1 are connected in parallel between the INPUT pin and ground, with the cathode of the Zener diode D1 connected to the INPUT pin. Capacitors C1 and C2 are connected in parallel between the OUTPUT pin and ground. A fuse F1 is also connected in series between the 24V power supply and the VCC power supply. The VCC pin of the control chip U4 is connected to a 5V power supply, the GND pin is grounded, and capacitor C4 is connected in parallel between the VCC pin and the GND pin of the control chip U4. The indicator circuit includes a light-emitting diode D3 and a resistor R2. The anode of the light-emitting diode D3 is connected to a 5V power supply, and the cathode is connected to the INDICATE pin of the control chip U4 after being connected in series with the resistor R2.

[0014] A control method for a solenoid valve single-wire communication control system employing the aforementioned automatic address code allocation, characterized in that: a computer program for implementing automatic address code allocation for the solenoid valve single-wire communication control runs within the control chip, performing the following processes: data reception, data verification, data parsing, data forwarding, communication link switching, address code storage, watchdog timer, status indication, and control output, wherein... Data reception involves processing the data input on the communication signal line of the input interface through the signal waveform shaping and driving circuit, and then inputting it into the control chip through the data receiving pin of the control chip. Data verification: After receiving a data frame with CRC checksum, the control chip executes a data verification program to calculate the CRC checksum of the actual received data frame and compare it with the received CRC checksum. Data parsing: After receiving a data frame that has been verified to be correct, the control chip executes corresponding instruction actions based on the frame header and data segment content of the data frame. The instruction actions include address clearing instructions, address allocation instructions, and / or output control instructions. Data forwarding: When the control chip receives a correct address clearing instruction, it preserves the instruction as is and forwards it out through the output interface; when the control chip receives a correct address allocation instruction, it parses the address code, increments the address code by 1, and forwards it out through the output interface. Communication link switching refers to the control chip controlling the communication switching circuit according to the received corresponding instructions to switch the connection mode of the communication signal lines of the output interface to serial or parallel mode. After the control chip is powered on and reset, it reads the address code in the local memory EEPROM. If a valid address code is read, the control chip controls the communication switching circuit to connect the communication signal lines of the output interface to the control chip's data input pin RXD. If the read address code is invalid, the control chip controls the communication switching circuit to connect the communication signal lines of the output interface to the control chip's data output pin TXD. If the control chip receives a correct address clear instruction, it controls the communication switching circuit to connect the communication signal lines of the output interface to the control chip's data output pin TXD. If the control chip receives a correct address allocation instruction, it saves the address code locally and, after the address code is incremented by 1 and forwarded, switches the communication signal lines of the output interface to the control chip's data input pin RXD. Address code storage refers to the process by which the control chip saves the parsed address code into the local EEPROM after receiving the correct address allocation instruction. A watchdog timer is a watchdog unit built into the control chip. The watchdog is fed periodically in the program. When the computer program running on the control chip crashes due to an abnormality, the control chip automatically resets. In this embodiment, the watchdog reset time is set to 32.75ms. The status indication refers to the following: after the control chip receives the correct address allocation instruction, that is, after the solenoid valve has been assigned an address, the control chip drive indicator light will be constantly lit, indicating that the address allocation is complete; after the control chip receives an invalid data frame, the control chip drive indicator light will flash, indicating that an invalid data frame has been received; after receiving a correct data frame again, the indicator light will return to its previous constant lit state. Control output refers to the output of the control coil drive circuit after the control chip receives the correct output control command and, based on the data parsing results, controls the solenoid valve coil to be energized or de-energized.

[0015] Furthermore, for each solenoid valve already connected in the valve group, address allocation only needs to be completed upon power-on. The solenoid valve control module (here, the control module refers to the entire control circuit board, including reading data from the EEPROM) only needs about 2.3ms from power-on reset and initialization to entering the main loop program; this time is a fixed time. Then, the bus controller sends an address clear command, and each solenoid valve is set as a cascaded link. The maximum time consumption for this process is calculated as follows: The processing of address clearing instructions takes the longest time when none of the solenoid valves have been assigned an address, and the shortest time when all the solenoid valves have been assigned an address.

[0016] When each solenoid valve is unassigned an address, i.e., all solenoid valves are in a cascaded state, the address clearing command sent by the bus controller needs to be forwarded level by level. When there are N solenoid valves, the address clearing command data frame contains 1 byte of frame header, 1 byte of data, and 2 bytes of checksum, for a total of 4 bytes. Each byte of data transmission also requires 1 start bit and 1 stop bit, for a total of 40 bits. The communication baud rate is 38400 Bd. The total time is: t1 = (((1÷38400)×4×10)+Δt)×N, in seconds, where Δt is the data parsing time, about 20us, and N is the number of solenoid valves (when N=24, t1≈0.0298s).

[0017] When all solenoid valves have been assigned addresses, meaning that the input interface signal lines of all solenoid valves are in parallel, the bus controller sends an address clear command to each solenoid valve. The total time taken is: t2 = ((1÷38400)×4×10) ≈0.001s. The address clear command has a fixed format, and it is the same regardless of the number of solenoid valves when broadcasting.

[0018] After the bus controller sends the address clear instruction, it only needs to delay for no less than the time of one address clear instruction before sending the address allocation instruction. The data frame format of the address allocation instruction is the same as that of the address clear instruction, only the frame header is different. Therefore, the maximum transmission processing time of the address allocation instruction is the same as that of the address clear instruction. So the time required to complete the entire address allocation is: t≥t1+t2.

[0019] The aforementioned bus controller can be described as the host computer that controls the system. Because the communication protocol of this system is custom-defined, in order to make it easier to apply in the industrial control industry, a bus protocol (standard protocols such as Modbus, CANopen, Profinet, Ethercat, etc.) converter is usually designed to bridge this system with host computers such as industrial control computers and PLCs.

[0020] Furthermore, when a solenoid valve that has already been assigned an address receives an address assignment command again, it first compares whether the already assigned address code is the same as the newly assigned address code. If they are different, the new address code is written into the local storage EEPROM; if they are the same, it is not stored again.

[0021] Furthermore, all solenoid valves in the valve group have completed address assignment, and the communication switching circuit is switched to a state where the communication signal lines of the input interface and the communication signal lines of the output interface are directly connected. The bus controller sends output control commands, which is the broadcast mode. The output response time of each solenoid valve is calculated as follows: When there are M solenoid valves in the valve group, the corresponding output control command requires 1 byte header, m bytes of data, and 2 bytes of checksum. With a communication baud rate of 38400 Bd, the total time T = (1 ÷ 38400) × (1 + m + 2) × 10 + ΔT, in seconds, where ΔT is the data verification and parsing time, approximately 20 µs; and m is the number of bytes required to control the M solenoid valves, m = ⌊ ⌋ + M mod 8 (When M = 32, m = 4; T≈0.0019s).

[0022] Furthermore, solenoid valves that have not been assigned an address will not respond to output control commands issued by the bus controller.

[0023] Furthermore, the control of the solenoid valves within the valve assembly also includes the following processes: The solenoid valve receives control commands from the bus controller or host computer and performs verification and validation. When the solenoid valve receives an address clear command from the bus controller or host computer, it clears the address code and switches to the serial path. Then, upon receiving an address allocation command, the solenoid valve parses its own address code, stores it, and then increments the address code by 1 before forwarding it to the next level to achieve automatic address code allocation. After the solenoid valve completes the address allocation, it switches to a parallel path; The input interface communication signal lines of each solenoid valve receive output control commands sent by the bus controller or the host computer in parallel. The data length of the output control command is designed according to the number of solenoid valves. The solenoid valve parses the data segment bit by bit according to its own address code to realize the energization or de-energization control of the solenoid valve coil. In this invention, the solenoid valves can be cascaded freely without a fixed number requirement. When the number of bits in the data segment of the output control command is greater than the number of solenoid valves, the extra data bits will not be responded to; when the number of bits in the data segment of the output control command is less than the number of solenoid valves, the solenoid valves that exceed the data sequence will not operate.

[0024] The beneficial effects of this invention are: (1) Each solenoid valve in this invention is equipped with a signal relay function, which is driven by relay at each level, thus achieving a longer transmission distance and better anti-interference performance.

[0025] (2) In this invention, a fixed format data frame is used for transmission. The data frame contains a CRC check code, which enhances the reliability of communication.

[0026] (3) The invention realizes the automatic allocation of the address code of the solenoid valve, so the solenoid valve can be added or removed flexibly, and there is no specific limit to the number.

[0027] (4) In this invention, the switching between serial and parallel links is achieved through a communication switching circuit. After the address allocation is completed, each electromagnetic device receives broadcast data from the bus controller or host computer in parallel. Only a low baud rate is needed to achieve high-speed response and no control time difference, which improves real-time performance and stability. Attached Figure Description

[0028] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0029] Figure 1 This is a schematic diagram of the principle of the single-line communication control system for the solenoid valve of the present invention.

[0030] Figure 2 This is a schematic diagram of the instruction receiving and communication circuit switching of the solenoid valve single-line communication control method of the present invention.

[0031] Figure 3 This is a circuit diagram of the single-wire communication control system for the solenoid valve of the present invention.

[0032] Figure 4 This is a schematic diagram illustrating the data frame format of the output control command of the present invention. Detailed Implementation

[0033] The present invention will now be described in detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, illustrating only the basic structure of the invention, and therefore only show the components relevant to the invention.

[0034] like Figure 1and Figure 2 As shown, the present invention discloses a single-wire communication control system and method for an electromagnetic valve with automatic address code allocation, comprising a valve group including a plurality of electromagnetic valves, each electromagnetic valve having an independent control circuit board. The control circuit board includes at least a control chip, an input interface, a signal waveform shaping and driving circuit, a communication switching circuit, an output interface, and a coil driving circuit. The input and output interfaces have the same wiring sequence, including a pair of power supply lines and a communication signal line. The communication switching circuit includes at least two input terminals and one output terminal. One end of the communication signal line of the input interface is connected to the output interface of the preceding adjacent electromagnetic valve or a host computer, and the other end is split into two paths after passing through the signal waveform shaping and driving circuit. One input pin (RXD) of the control chip is connected to the data input pin of the control chip, and the other input pin is connected to one input of the communication switching circuit. The data output pin (TXD) of the control chip is connected to the other input of the communication switching circuit. The communication switching circuit can switch between the two inputs and connect one input to the output of the communication switching circuit. The output of the communication switching circuit is connected to one end of the communication signal line of the output interface, and the other end of the communication signal line of the output interface is connected to the input interface of the next adjacent solenoid valve. The solenoid valves are cascaded through the input and output interfaces of the control circuit board. The control chip is also connected to a coil drive circuit to output a drive signal to drive the solenoid valve coil. The circuit also includes a voltage regulator circuit and an indicator light circuit. The voltage regulator circuit is connected between the power supply terminal of the input interface and the power supply terminal of the control chip to provide a suitable operating power for the control chip. The indicator light circuit is connected to the control chip to indicate the address allocation status and data reception status of the solenoid valve. Specifically, the communication switching circuit uses a single-pole double-throw multiplexer. Its common terminal serves as the output terminal, connected to the communication signal line of the output interface. The normally open terminal serves as an input terminal, connected to the data input pin RXD of the control chip. The normally closed terminal serves as another input terminal, connected to the data output pin TXD of the control chip. The control chip can control the switching of the multiplexer between the normally open and normally closed terminals according to the received instructions, so as to switch the connection mode of the output interface signal line.

[0035] like Figure 3As shown, the control circuit board includes a control chip U4, an input interface P1, a signal waveform shaping and driving circuit, a multiplexer U2, an output interface P2, a coil driving circuit, a voltage regulator circuit, and an indicator light circuit. The signal waveform shaping and driving circuit uses a Schmitt trigger buffer U3. The Din pin of the input interface P1 is connected to the input pin IN_A of the Schmitt trigger buffer U3. The output pin OUT_Y of the Schmitt trigger buffer U3 is divided into two paths: one path is connected to the RXD pin of the control chip U4 through a resistor R1, and the other path is connected to the NO pin of the multiplexer U2. The NC pin of the multiplexer U2 is connected to the TXD pin of the control chip U4, and the COM pin of the multiplexer U2 is connected to the input... The Dout pin of output interface P2 and the IN pin of multiplexer U2 are connected to the DIR pin of control chip U4; the communication signal line of input interface is connected to the input of Schmitt buffer U3, and the output of Schmitt buffer U3 is connected to the data receiving pin of control chip U4. Through the Schmitt threshold characteristic, noise signals generated by electromagnetic interference are filtered out; distorted and blurred digital signals are corrected into standard square wave signals; the data signal input on the communication signal line of each solenoid valve input interface first passes through the Schmitt input buffer before being output, realizing step-by-step relay drive, improving the signal load capacity, driving more subsequent circuits or long-distance transmission, avoiding signal attenuation, so as to achieve a longer transmission distance and better anti-interference performance.The coil drive circuit includes resistors R3, R4, and R5, a field-effect transistor Q1, a diode D4, and an LED D2. The solenoid valve coil has two terminals P3 and P4. The OUTPUT pin of the control chip U4 is connected to one end of resistor R4, and the other end of resistor R4 is connected to the gate of the field-effect transistor Q1. The drain of the field-effect transistor Q1 is grounded to GND. Resistor R5 is connected in parallel between the gate and drain of the field-effect transistor Q1. The source of the field-effect transistor Q1 is connected to the anode of the diode D4, and the cathode of the diode D4 is connected to the power supply VCC. The LED D2 and resistor R3 are connected in series and then in parallel between terminals P3 and P4, and the anode of the LED D2 and terminal P3 are both connected to the power supply VCC. The voltage regulator circuit includes a voltage regulator chip U1, a Zener diode D1, and capacitors C1, C2, and C3. The INPUT pin of chip 1 is connected to a 24V power supply, the OUTPUT pin outputs a 5V power supply, and the GND pin is grounded to GND. A Zener diode D1 and a capacitor C1 are connected in parallel between the INPUT pin and ground GND, with the cathode of the Zener diode D1 connected to the INPUT pin. Capacitors C1 and C2 are connected in parallel between the OUTPUT pin and ground GND. A fuse F1 is also connected in series between the 24V power supply and the VCC power supply. The VCC pin of control chip U4 is connected to a 5V power supply, the GND pin is grounded to GND, and capacitor C4 is connected in parallel between the VCC pin and the GND pin of control chip U4. The indicator circuit includes an LED D3 and a resistor R2. The anode of the LED D3 is connected to the 5V power supply, and the cathode is connected to the INDICATE pin of control chip U4 after being connected in series with resistor R2.

[0036] like Figure 2 As shown, a control method for a solenoid valve single-wire communication control system employing the aforementioned automatic address code allocation is described. The control chip runs a computer program that implements the automatic address code allocation for single-wire communication control of the solenoid valve, performing the following processes: data reception, data verification, data parsing, data forwarding, communication link switching, address code storage, watchdog timer, status indication, and control output. Data reception involves processing the data input on the communication signal line of the input interface through the signal waveform shaping and driving circuit, and then inputting it into the control chip through the data receiving pin of the control chip. Data verification: After receiving a data frame with CRC checksum, the control chip executes a data verification program to calculate the CRC checksum of the actual received data frame and compare it with the received CRC checksum. Data parsing: After receiving a correctly verified data frame, the control chip executes corresponding instructions based on the frame header and data segment content. These instructions include address clearing instructions, address allocation instructions, and / or output control instructions; for example... Figure 4As shown, the output control command data frame format is as follows: frame header, data segment: 3rd byte, data segment: 2nd byte, data segment: 1st byte, data segment: 0th byte, CRC check high byte, CRC check low byte, which are represented in hexadecimal and binary respectively. The solenoid valve address mapping and solenoid valve on / off status are also shown in the figure. As can be seen from the figure, 4 bytes of data can control a 32-bit solenoid valve.

[0037] Data forwarding: When the control chip receives a correct address clearing instruction, it preserves the instruction as is and forwards it out through the output interface; when the control chip receives a correct address allocation instruction, it parses the address code, increments the address code by 1, and forwards it out through the output interface. Communication link switching refers to the control chip controlling the communication switching circuit according to the received corresponding instructions to switch the connection mode of the communication signal lines of the output interface to serial or parallel mode. After the control chip is powered on and reset, it reads the address code in the local memory EEPROM. If a valid address code is read, the control chip controls the communication switching circuit to connect the communication signal lines of the output interface to the control chip's data input pin RXD. If the read address code is invalid, the control chip controls the communication switching circuit to connect the communication signal lines of the output interface to the control chip's data output pin TXD. If the control chip receives a correct address clear instruction, it controls the communication switching circuit to connect the communication signal lines of the output interface to the control chip's data output pin TXD. If the control chip receives a correct address allocation instruction, it saves the address code locally and, after the address code is incremented by 1 and forwarded, switches the communication signal lines of the output interface to the control chip's data input pin RXD. Address code storage refers to the process by which the control chip saves the parsed address code into the local EEPROM after receiving the correct address allocation instruction. A watchdog timer is a watchdog unit built into the control chip. The watchdog is fed periodically in the program. When the computer program running on the control chip crashes due to an abnormality, the control chip automatically resets. In this embodiment, the watchdog reset time is set to 32.75ms. The status indication refers to the following: after the control chip receives the correct address allocation instruction, that is, after the solenoid valve has been assigned an address, the control chip drive indicator light will be constantly lit, indicating that the address allocation is complete; after the control chip receives an invalid data frame, the control chip drive indicator light will flash, indicating that an invalid data frame has been received; after receiving a correct data frame again, the indicator light will return to its previous constant lit state. Control output refers to the output of the control coil drive circuit after the control chip receives the correct output control command and, based on the data parsing results, controls the solenoid valve coil to be energized or de-energized.

[0038] Each solenoid valve connected in the valve group only needs to complete address allocation upon power-on. The solenoid valve control module (here, the control module refers to the entire control circuit board, including reading data from the EEPROM) only needs about 2.3ms from power-on reset and initialization to entering the main loop program; this time is a fixed time. Then, the bus controller sends an address clear command, and each solenoid valve is set as a cascaded link. The maximum time for this process is calculated as follows: The processing of address clearing instructions takes the longest time when none of the solenoid valves have been assigned an address, and the shortest time when all the solenoid valves have been assigned an address.

[0039] When each solenoid valve is unassigned an address, i.e., all solenoid valves are in a cascaded state, the address clearing command sent by the bus controller needs to be forwarded level by level. When there are N solenoid valves, the address clearing command data frame contains 1 byte of frame header, 1 byte of data, and 2 bytes of checksum, for a total of 4 bytes. Each byte of data transmission also requires 1 start bit and 1 stop bit, for a total of 40 bits. The communication baud rate is 38400Bd. The total time is: t1=(((1÷38400)×4×10) +Δt)×N, in seconds, where Δt is the data parsing time, about 20us, and N is the number of solenoid valves (when N=24, t1≈0.0298s).

[0040] When all solenoid valves have been assigned addresses, meaning that the input interface signal lines of all solenoid valves are in parallel, the bus controller sends an address clear command to each solenoid valve. The total time taken is: t2 = ((1÷38400)×4×10) ≈0.001s. The address clear command has a fixed format, and it is the same regardless of the number of solenoid valves when broadcasting.

[0041] like Figure 2 As shown, after the bus controller sends the address clear instruction, it only needs to delay for no less than the time of one address clear instruction before it can send the address allocation instruction. The data frame format of the address allocation instruction is the same as that of the address clear instruction, only the frame header is different. Therefore, the maximum transmission processing time of the address allocation instruction is the same as that of the address clear instruction. So the time required to complete the entire address allocation is: t ≥ t1 + t2.

[0042] When a solenoid valve that has already been assigned an address receives an address assignment command again, it first compares the already assigned address code with the newly assigned address code. If they are different, the new address code is written into the local storage EEPROM; if they are the same, it is not stored again.

[0043] All solenoid valves in the valve group have been address-assigned. The communication switching circuit is switched to a direct connection state between the communication signal lines of the input interface and the communication signal lines of the output interface. The bus controller sends output control commands, which is the broadcast mode. The output response time of each solenoid valve is calculated as follows: When there are M solenoid valves in the valve group, the corresponding output control command requires 1 byte header, m bytes of data, and 2 bytes of checksum. With a communication baud rate of 38400Bd, the total time T = (1÷38400)×(1+m+2)×10+ΔT, in seconds, where ΔT is the data verification and parsing time, approximately 20µs; and m is the number of bytes required to control the M solenoid valves, m = ⌊ ⌋ + M mod 8 (When M = 32, m = 4; T≈0.0019s).

[0044] Solenoid valves that have not been assigned an address will not respond to output control commands issued by the bus controller.

[0045] The control of solenoid valves within the valve assembly also includes the following processes: The solenoid valve receives control commands from the bus controller or host computer and performs verification and validation.

[0046] The aforementioned bus controller can be described as the host computer that controls the system. Because the communication protocol of this system is custom-defined, in order to make it easier to apply in the industrial control industry, a bus protocol (standard protocols such as Modbus, CANopen, Profinet, Ethercat, etc.) converter is usually designed to bridge this system with host computers such as industrial control computers and PLCs.

[0047] like Figure 2 As shown in the diagram, bits 0, 1, ..., n represent the sequence of solenoid valves in the valve group, corresponding one-to-one. When a solenoid valve receives an address clear command from the bus controller or host computer, it clears its address code and switches to serial path. Immediately afterwards, upon receiving an address allocation command, the solenoid valve parses its own address code, stores it, and then increments the address code by 1 before forwarding it to the next level, thus achieving automatic address code allocation. Therefore, the address code allocation for a solenoid valve always starts from 0, with subsequent address codes incrementing by 1. After completing address allocation, the solenoid valve switches to parallel path. In parallel mode, the input interface communication signal lines of each solenoid valve receive output control commands sent by the bus controller or host computer.

[0048] The data length of the output control command can be designed according to the number of solenoid valves. The solenoid valves parse the data segment bit by bit based on their own address code to control the energization or de-energization of their coils. In this invention, solenoid valves can be freely cascaded without any specific number limit. When the number of bits in the data segment of the output control command is greater than the number of solenoid valves, the extra data bits will not be responded to; when the number of bits in the data segment of the output control command is less than the number of solenoid valves, the solenoid valves that exceed the data sequence will not operate.

[0049] Based on the above-described preferred embodiments of the present invention, and through the foregoing description, those skilled in the art can make various changes and modifications without departing from the scope of the present invention. The technical scope of this invention is not limited to the contents of the specification, but must be determined according to the scope of the claims.

Claims

1. A single-wire communication control system for an automatically assigned address code solenoid valve, characterized in that: The system includes a valve assembly comprising several solenoid valves, each with an independent control circuit board. The control circuit board includes at least a control chip, an input interface, a signal waveform shaping and driving circuit, a communication switching circuit, an output interface, and a coil driving circuit. The input and output interfaces have the same wiring sequence, including a pair of power supply lines and a communication signal line. The communication switching circuit includes at least two input terminals and one output terminal. One end of the input interface communication signal line is connected to the output interface of the preceding adjacent solenoid valve or the host computer. The other end is split into two paths after passing through the signal waveform shaping and driving circuit. One path is connected to the data input pin RXD of the control chip, and the other path is connected to one input terminal of the communication switching circuit. The data output pin TXD of the control chip is connected to the other input terminal of the communication switching circuit. The communication switching circuit can switch between the two input terminals and connect one of the input terminals to the output terminal of the communication switching circuit. The output terminal of the communication switching circuit is connected to one end of the output interface communication signal line, and the other end of the output interface communication signal line is connected to the input interface of the following adjacent solenoid valve. The solenoid valves are cascaded through the input and output interfaces of the control circuit board. The control chip is also connected to the coil driving circuit for outputting driving signals to drive the solenoid valve coil.

2. The solenoid valve single-wire communication control system with automatic address code allocation as described in claim 1, characterized in that: The communication switching circuit uses a single-pole double-throw multiplexer. Its common terminal serves as the output terminal and is connected to the communication signal line of the output interface. The normally open terminal serves as an input terminal and is connected to the data input pin RXD of the control chip. The normally closed terminal serves as another input terminal and is connected to the data output pin TXD of the control chip. The control chip can control the switching of the multiplexer between the normally open and normally closed terminals.

3. The solenoid valve single-wire communication control system with automatic address code allocation as described in claim 2, characterized in that: It also includes a voltage regulator circuit and an indicator light circuit. The voltage regulator circuit is connected between the power supply terminal of the input interface and the power supply terminal of the control chip to provide a suitable operating power for the control chip. The indicator light circuit is connected to the control chip and is used to indicate the address allocation status and data reception status of the solenoid valve.

4. The solenoid valve single-wire communication control system with automatic address code allocation as described in claim 3, characterized in that: The control circuit board includes a control chip U4, an input interface P1, a signal waveform shaping and driving circuit, a multiplexer U2, an output interface P2, a coil driving circuit, a voltage regulator circuit, and an indicator light circuit. The signal waveform shaping and driving circuit uses a Schmitt trigger buffer U3. The Din pin of the input interface P1 is connected to the input pin IN_A of the Schmitt trigger buffer U3. The output pin OUT_Y of the Schmitt trigger buffer U3 is divided into two paths. One path is connected to the RXD pin of the control chip U4 through resistor R1, and the other path is connected to the NO pin of the multiplexer U2. The NC pin of the multiplexer U2 is connected to the TXD pin of the control chip U4. The COM pin of the multiplexer U2 is connected to the Dout pin of the output interface P2. The IN pin of the multiplexer U2 is connected to the DIR pin of the control chip U4. The coil drive circuit includes resistors R3, R4, and R5, a field-effect transistor Q1, a diode D4, and a light-emitting diode D2. The solenoid valve coil has two terminals P3 and P4. The OUTPUT pin of the control chip U4 is connected to one end of resistor R4, and the other end of resistor R4 is connected to the gate of the field-effect transistor Q1. The drain of the field-effect transistor Q1 is grounded to GND. Resistor R5 is connected in parallel between the gate and drain of the field-effect transistor Q1. The source of the field-effect transistor Q1 is connected to the anode of the diode D4, and the cathode of the diode D4 is connected to the power supply VCC. The light-emitting diode D2 and resistor R3 are connected in series and then in parallel between terminals P3 and P4. The anode of the light-emitting diode D2 and terminal P3 are both connected to the power supply VCC. The voltage regulator circuit includes a voltage regulator chip U1, a Zener diode D1, and capacitors C1, C2, and C3. The INPUT pin of the voltage regulator chip U1 is connected to a 24V power supply, the OUTPUT pin outputs a 5V power supply, and the GND pin is grounded. The Zener diode D1 and capacitor C1 are connected in parallel between the INPUT pin and ground, with the cathode of the Zener diode D1 connected to the INPUT pin. Capacitors C1 and C2 are connected in parallel between the OUTPUT pin and ground. A fuse F1 is also connected in series between the 24V power supply and the VCC power supply. The VCC pin of the control chip U4 is connected to a 5V power supply, the GND pin is grounded, and capacitor C4 is connected in parallel between the VCC pin and the GND pin of the control chip U4. The indicator circuit includes a light-emitting diode D3 and a resistor R2. The anode of the light-emitting diode D3 is connected to a 5V power supply, and the cathode is connected to the INDICATE pin of the control chip U4 after being connected in series with the resistor R2.

5. A control method for a single-wire communication control system for a solenoid valve employing the automatic address code allocation as described in any one of claims 1-4, characterized in that: The control chip runs a computer program that automatically assigns address codes to the solenoid valve for single-wire communication control, performing the following processes: data reception, data verification, data parsing, data forwarding, communication link switching, address code storage, watchdog timer, status indication, and control output. Data reception involves processing the data input on the communication signal line of the input interface through the signal waveform shaping and driving circuit, and then inputting it into the control chip through the data receiving pin of the control chip. Data verification: After receiving a data frame with CRC checksum, the control chip executes a data verification program to calculate the CRC checksum of the actual received data frame and compare it with the received CRC checksum. Data parsing: After receiving a data frame that has been verified to be correct, the control chip executes corresponding instruction actions based on the frame header and data segment content of the data frame. The instruction actions include address clearing instructions, address allocation instructions, and / or output control instructions. Data forwarding: When the control chip receives a correct address clearing instruction, it preserves the instruction as is and forwards it out through the output interface; when the control chip receives a correct address allocation instruction, it parses the address code, increments the address code by 1, and forwards it out through the output interface. Communication link switching refers to the control chip controlling the communication switching circuit according to the received corresponding instructions to switch the connection mode of the communication signal lines of the output interface to serial or parallel mode. After the control chip is powered on and reset, it reads the address code in the local memory EEPROM. If a valid address code is read, the control chip controls the communication switching circuit to connect the communication signal lines of the output interface to the control chip's data input pin RXD. If the read address code is invalid, the control chip controls the communication switching circuit to connect the communication signal lines of the output interface to the control chip's data output pin TXD. If the control chip receives a correct address clear instruction, it controls the communication switching circuit to connect the communication signal lines of the output interface to the control chip's data output pin TXD. If the control chip receives a correct address allocation instruction, it saves the address code locally and, after the address code is incremented by 1 and forwarded, switches the communication signal lines of the output interface to the control chip's data input pin RXD. Address code storage refers to the process by which the control chip saves the parsed address code into the local EEPROM after receiving the correct address allocation instruction. A watchdog timer is a unit built into the control chip. The watchdog is fed periodically in the program, and the control chip automatically resets when the computer program running on the control chip malfunctions. The status indication refers to the following: after the control chip receives the correct address allocation instruction, that is, after the solenoid valve has been assigned an address, the control chip drive indicator light will be constantly lit, indicating that the address allocation is complete; after the control chip receives an invalid data frame, the control chip drive indicator light will flash, indicating that an invalid data frame has been received; after receiving a correct data frame again, the indicator light will return to its previous constant lit state. Control output refers to the output of the control coil drive circuit after the control chip receives the correct output control command and, based on the data parsing results, controls the solenoid valve coil to be energized or de-energized.

6. The single-wire communication control method for an electromagnetic valve with automatic address code allocation as described in claim 5, characterized in that: Each solenoid valve already connected in the valve group only needs to complete address allocation upon power-on. From power-on reset and initialization to entering the main loop program, the bus controller sends an address clear command, and each solenoid valve is set as a cascaded link. The maximum time consumption for this process is calculated as follows: The processing of address clearing instructions takes the longest time when none of the solenoid valves have been assigned an address, and the shortest time when none of the solenoid valves have been assigned an address. When each solenoid valve is unassigned an address, i.e., all solenoid valves are in a cascaded state, the address clearing command sent by the bus controller needs to be forwarded level by level; when the number of solenoid valves is N, the address clearing command data frame contains 1 byte of frame header, 1 byte of data, and 2 bytes of check code, totaling 4 bytes. Each byte of data transmission also requires 1 start bit and 1 stop bit, totaling 40 bits. The communication baud rate is 38400Bd, then the total time is: t1=(((1÷38400)×4×10) +Δt)×N, in seconds, where Δt is the data parsing time and N is the number of solenoid valves; When all solenoid valves have been assigned addresses, meaning that the input interface signal lines of all solenoid valves are in parallel, the address clearing command sent by the bus controller is regarded as a broadcast. The total time is: t2 = ((1÷38400)×4×10) ≈0.001s; After the bus controller sends an address clear instruction, it can send an address allocation instruction if the delay is not less than the time of one address clear instruction. The data frame format of the address allocation instruction is the same as that of the address clear instruction, only the frame header is different. Therefore, the maximum transmission processing time of the address allocation instruction is the same as that of the address clear instruction. So the time required to complete the entire address allocation is: t≥t1+t2.

7. The single-wire communication control method for an electromagnetic valve with automatic address code allocation as described in claim 5, characterized in that: When a solenoid valve that has already been assigned an address receives an address assignment command again, it first compares the already assigned address code with the newly assigned address code. If they are different, the new address code is written into the local storage EEPROM. If they are the same, they will not be stored again.

8. The single-wire communication control method for an electromagnetic valve with automatic address code allocation as described in claim 5, characterized in that: All solenoid valves in the valve group have been address-assigned. The communication switching circuit is switched to a direct connection state between the communication signal lines of the input interface and the communication signal lines of the output interface. The bus controller sends output control commands, which is the broadcast mode. The output response time of each solenoid valve is calculated as follows: When there are M solenoid valves in the valve group, the corresponding output control command requires 1 byte header, m bytes of data, and 2 bytes of checksum. With a communication baud rate of 38400 Bd, the total time T = (1 ÷ 38400) × (1 + m + 2) × 10 + ΔT, in seconds, where ΔT is the data verification and parsing time; and m is the number of bytes required to control the M solenoid valves, m = ⌊ ⌋+ M mod 8 .

9. The single-wire communication control method for an electromagnetic valve with automatic address code allocation as described in claim 5, characterized in that: Solenoid valves that have not been assigned an address will not respond to output control commands issued by the bus controller.

10. The single-wire communication control method for an electromagnetic valve with automatic address code allocation as described in claim 5, characterized in that: The control of the solenoid valves within the valve group also includes the following processes: The solenoid valve receives control commands from the bus controller or host computer and performs verification and validation. When the solenoid valve receives an address clear command from the bus controller or host computer, it clears the address code and switches to the serial path. Then, upon receiving an address allocation command, the solenoid valve parses its own address code, stores it, and then increments the address code by 1 before forwarding it to the next level to achieve automatic address code allocation. After the solenoid valve completes the address allocation, it switches to a parallel path; The input interface communication signal lines of each solenoid valve receive output control commands sent by the bus controller or the host computer in parallel. Based on the number of solenoid valves, the data length of the output control command is designed. The solenoid valve parses the data segment bit by bit according to its own address code to realize the energization or de-energization control of the solenoid valve coil. When the number of bits in the data segment of the output control command is greater than the number of solenoid valves, the extra data bits will not be responded to; when the number of bits in the data segment of the output control command is less than the number of solenoid valves, the solenoid valves that exceed the data sequence will not operate.

Images