Infrared movement circuit and infrared detector

Abstract

The invention provides an infrared machine core circuit and an infrared detector, and relates to the technical field of infrared detection, and the infrared machine core circuit comprises an interface board which comprises a low-speed IO interface; the digital board comprises an FPGA and a CPLD; the FPGA is used for executing system main control logic, receiving and processing data to be processed and sending processed data; the CPLD is used for receiving a control signal of the FPGA, driving the low-speed IO interface and sending a feedback signal to the FPGA; the analog-to-digital conversion board is connected with the digital board and is used for adapting to different types of infrared detectors and realizing detector driving and analog signal acquisition and digitization; the analog-to-digital conversion board can be modularly replaced according to different infrared detectors. According to the invention, full-localization components, miniaturization and light weight are realized, and the versatility is improved.

Description

Technical Field

[0001] This invention relates to the field of infrared detection technology, and in particular to an infrared core circuit and an infrared detector. Background Technology

[0002] Infrared detection technology plays a crucial role in fields such as security monitoring, car navigation, and temperature measurement. Infrared detection technology converts the infrared radiation received by an infrared detector into a signal that can be read by a circuit. Through a series of circuit processes, it ultimately outputs human-readable image information in analog or digital signal mode. The infrared core circuit, as the core component responsible for detector driving, signal acquisition, and processing, directly affects the final infrared image quality.

[0003] In related technologies, most core components of infrared sensor modules, such as signal processing chips (FPGAs), are imported, making it difficult to guarantee the security of the infrared sensor module supply chain, technological upgrades, and long-term supply stability. Furthermore, infrared sensor modules generally suffer from high customization and poor versatility. There are many types of infrared sensor modules; when applications require replacing infrared detectors or other changes in requirements, components must be replaced or new designs must be implemented. At the same time, to meet different functions, circuit boards often integrate a large number of interfaces and driver circuits with varying functions, increasing circuit design complexity and board size, and contradicting the growing miniaturization and lightweight requirements of current applications for infrared sensor modules. Summary of the Invention

[0004] This invention provides an infrared core circuit and an infrared detector, employing the following technical solution: Firstly, an infrared sensor circuit is provided, comprising: Interface board, including low-speed I / O interfaces; The digital board includes an FPGA and a CPLD; the FPGA is used to execute the system's main control logic, receive and process data to be processed, and send data indicating completion of processing; the CPLD is used to receive control signals from the FPGA, drive the low-speed I / O interface, and send feedback signals to the FPGA. An analog-to-digital converter board, connected to the digital board, is used to adapt to different models of infrared detectors, enabling detector driving and analog signal acquisition and digitization; the analog-to-digital converter board can be modularly replaced according to different infrared detectors.

[0005] Furthermore, the digital board and the interface board exchange data via high-speed serial communication through a high-speed LVDS interface, including: The FPGA and the CPLD communicate via differential signals; The FPGA converts the multiple parallel low-speed signals that need to be sent to the interface board from parallel to serial before sending them. The CPLD converts the received serial signal into a parallel signal and distributes it to the corresponding peripheral interface. Meanwhile, the CPLD converts the multiple parallel signals collected by the interface board into parallel signals and sends them back to the FPGA.

[0006] Furthermore, the interface board also includes at least one of the following: a power interface, an electromechanical interface, a communication interface, or a video interface.

[0007] Furthermore, the digital board, interface board, and analog-to-digital conversion board are configured in a stacked structure, and the digital board and interface board are connected by an inter-board high-speed connector; the inter-board high-speed connector is a domestically produced micro coaxial connector FMA-060-LD-A. The analog-to-digital converter board is connected to the digital board using a flexible circuit board structure.

[0008] Furthermore, the high-speed serial communication data frame includes a check bit to ensure the accuracy of data transmission; and / or includes a fixed-frequency heartbeat signal to monitor the connection and disconnection status of the communication link. If an anomaly is detected, an error bit is generated.

[0009] Furthermore, in the high-speed serial communication, some signals from multiple low-speed signals are address-encoded and data-packed, and then transmitted on the same set of differential lines.

[0010] Furthermore, N bits of parallel data are packaged, with K bits used to represent the address and M bits used to represent the data, thereby enabling the transmission of up to 2^K low-speed signals, each with a bit width of M bits, through a set of serial links, where N = K + M.

[0011] In a second aspect, an infrared detector is provided, including the infrared core circuit as described in the first aspect.

[0012] The infrared core circuit of the present invention has the following beneficial effects: This invention provides a domestically produced miniaturized infrared camera module component. The FPGA is responsible for all core image processing and algorithms, while the CPLD is responsible for all low-speed I / O and customized interfaces. It can realize multiple functions such as infrared imaging, image processing, and system communication. The component modules can be flexibly replaced according to application needs, and can be quickly adapted to various project requirements. At the same time, it adopts all domestically produced components, ensuring the independent controllability of the component and solving the problems of poor versatility, high change costs, and miniaturization and lightweighting.

[0013] The infrared detector corresponding to the infrared core circuit of this invention can achieve the same technical effect, and will not be described in detail here to avoid repetition. Attached Figure Description

[0014] Figure 1 A schematic diagram of the framework of an infrared core circuit provided in an embodiment of this application; Figure 2 A schematic diagram illustrating the principle of high-speed serial communication in an infrared core circuit provided in this application embodiment; Figure 3 This is a schematic diagram illustrating the principle of high-speed serial communication in another infrared core circuit provided in this application embodiment. Detailed Implementation

[0015] To further illustrate the technical means and effects adopted by the present invention to achieve its intended purpose, the technical solutions in the embodiments of this application are clearly described. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art are within the scope of protection of this application.

[0016] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0017] The steps described in the specification and the flowcharts in the accompanying drawings of this invention are not necessarily strictly executed according to the step numbers; the execution order of the method steps can be changed. Furthermore, certain steps can be omitted, multiple steps can be combined into one step, and / or one step can be broken down into multiple steps.

[0018] This specification provides an infrared core circuit and also relates to an infrared detector, which will be described in detail below with reference to the accompanying drawings and preferred embodiments.

[0019] Please see Figure 1 This application provides an infrared core circuit, including: Interface board, including low-speed I / O interfaces; The digital board includes an FPGA and a CPLD; the FPGA is used to execute the system's main control logic, receive and process data to be processed, and send data indicating completion of processing; the CPLD is used to receive control signals from the FPGA, drive the low-speed I / O interface, and send feedback signals to the FPGA. An analog-to-digital converter board, connected to the digital board, is used to adapt to different models of infrared detectors, enabling detector driving and analog signal acquisition and digitization; the analog-to-digital converter board can be modularly replaced according to different infrared detectors.

[0020] The digital board and the interface board interact via a high-speed serial communication through a high-speed LVDS interface, including: The FPGA and the CPLD communicate via differential signals; The FPGA converts the multiple parallel low-speed signals that need to be sent to the interface board from parallel to serial before sending them. The CPLD converts the received serial signal into a parallel signal and distributes it to the corresponding peripheral interface. Meanwhile, the CPLD converts the multiple parallel signals collected by the interface board into parallel signals and sends them back to the FPGA.

[0021] The interface board further includes at least one of the following: a power interface, an electromechanical interface, a communication interface, and / or a video interface.

[0022] In this application, reasonable circuit function partitioning is the foundation for modularization and generalization. The main approach is to lock in the core, modularize configuration items, and customize interfaces. Specifically: The core is defined as a digital board, a high-density pure digital circuit centered around an FPGA core processor, coupled with essential external resources such as memory and core power supply. It transmits and receives data to be processed and processed data through a unified interface. Currently, the design resources of this chassis meet the signal processing needs of a typical 4 / 8-channel standard thermal imager and can be used as the core processor, remaining unchanged in this system. Modular configuration items are defined as digital-to-analog converter circuits, with driver circuits configured individually based on detector differences. To ensure performance, the driver and ADC boards adopt an integrated flexible design, forming a series of designs based on detector type and chassis placement, without modification to meet specific user needs. Customized interfaces are defined as power, communication, video, and electromechanical interfaces, which can be customized according to project interface, layout, and functional requirements, generally without considering universality and compatibility.

[0023] In some possible implementations, the digital board, interface board, and analog-to-digital converter board are configured in a stacked structure, with the digital board and interface board connected via a high-speed inter-board connector. This high-speed inter-board connector is a domestically produced micro-coaxial connector, FMA-060-LD-A. High-speed, high-density, and high-reliability inter-board interconnection is fundamental to this solution, while also ensuring relatively low price and delivery time. Through extensive research, considering the market environment, the application foundation of microsystems, and the capabilities of domestic production lines, the AVIC Optoelectronics FMA-060-LD-A is selected as the preferred inter-board stacked connector. The domestically produced micro-coaxial connector is also preferred as the inter-board interconnect connector due to its extremely small size, high mechanical reliability, and electrical signal reliability, making it highly suitable for applications in high-speed, high-density signal transmission. The analog-to-digital converter board uses a flexible circuit board structure to connect to the digital board, adapting to different detector installation positions and spatial layouts.

[0024] In practical applications, the core signal processing module and analog-to-digital conversion module of this application are only 50mm x 50mm in size, ensuring the miniaturization of the components.

[0025] This application presents a low-speed I / O bus transmission and distribution scheme based on a high-speed serial interface, designed using an FPGA+CPLD architecture on a digital board. In practice, a large number of low-speed I / O peripherals are assigned to the interface board, totaling approximately 50 transmit / receive devices. Using a typical single-wire transmission scheme would result in an extremely redundant number of connectors and cables, hindering the use of small-package, low-I / O-count FPGAs to reduce circuit size. This solution reduces the number of cables through high-speed serial transmission.

[0026] Furthermore, the high-speed serial communication data frame includes a check bit to ensure the accuracy of data transmission; and / or includes a fixed-frequency heartbeat signal to monitor the connection and disconnection status of the communication link. If an anomaly is detected, an error bit is generated.

[0027] Preferably, the scheme uses a 10:1 parallel-to-serial converter for transmission in both the FPGA and CPLD (larger parallel-to-serial converters are incompatible due to the mismatch in the number of parallel lines). Considering the reliability and stability of the transmitted signal, two bits are used for communication verification. One line is designed as a heartbeat line, providing a fixed-frequency 0 / 1 signal, and the other line contains eight data lines and an odd parity bit for the heartbeat line. After receiving and restoring the signal, the parity bit is used to verify the correctness of the data packet, and the heartbeat line is used to check if the signal transmission channel is normal. If an anomaly is detected, an error bit is generated, and each module is protected to prevent uncontrolled hardware malfunctions on the interface board.

[0028] Furthermore, in the high-speed serial communication, some signals from multiple low-speed signals are address-encoded and data-packed, and then transmitted on the same set of differential lines.

[0029] Specifically, N bits of parallel data are packaged, with K bits used to represent the address and M bits used to represent the data, thereby enabling the transmission of up to 2^K low-speed signals, each with a width of M bits, through a set of serial links, where N = K + M.

[0030] In this step, analysis shows that, apart from the video signal which needs to be transmitted separately, the stepper motor control signal requires precise transmission of the duty cycle, thus necessitating a 40MHz transmission rate. The remaining signals are low-speed signals, and a 5MHz transmission rate is sufficient to ensure complete sampling and transmission without causing operational abnormalities due to duty cycle variations. Therefore, for low-speed signals, a packetized transmission method can be used: 3 address bits and 5 data bits out of 8 valid data bits, achieving 40 bits of parallel data transmission at a 5MHz frequency; or 2 address bits and 6 data bits, achieving 24 bits of parallel data transmission at a 10MHz frequency. (See also...) Figure 2-3 : In a typical system configuration, there are five pairs of differential lines: a transmit clock, a set of 8-bit high-speed signals for transmission, a set of 24 / 40-bit low-speed signals for transmission, a set of 8-bit high-speed signals for reception, and a set of 24 / 40-bit low-speed signals for reception. The CPLD passively operates using the data transmission clock transmitted by the FPGA, utilizing a simultaneous clock for data feedback. The FPGA directly receives the feedback data using its transmit clock, while the interface reserves a clock feedback channel. If timing assurance is difficult or reliability is poor, the CPLD's feedback clock is used for reception.

[0031] Based on the above solution, this application provides a domestically produced miniaturized infrared core component. The FPGA is responsible for all core image processing and algorithms, and the CPLD is responsible for all low-speed I / O and customized interfaces. It can realize multiple functions such as infrared imaging, image processing, and system communication. The component modules can be flexibly replaced according to application needs, and can be quickly adapted to various project requirements. At the same time, it adopts all domestically produced components, ensuring the independent control of the component and solving the problems of poor versatility, high change costs, and miniaturization and lightweighting.

[0032] Corresponding to the above-described infrared core circuit embodiment, this application embodiment provides an infrared detector, including the aforementioned infrared core circuit.

[0033] The infrared detector described above achieves the same technical effect as the infrared core circuit embodiment described above, and will not be repeated here to avoid repetition.

[0034] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0035] It is understood that the embodiments of this application have been described above in conjunction with the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. As those skilled in the art will know, various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of the invention. Furthermore, those skilled in the art, under the guidance or instruction of this application, can modify these features and embodiments to adapt to specific situations and materials without departing from the spirit and scope of the invention. Therefore, this invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the protection scope of this invention.

Claims

1. An infrared core circuit, characterized in that, include: Interface board, including low-speed I / O interfaces; Digital boards, including FPGAs and CPLDs; The FPGA is used to execute the system's main control logic, receive and process data to be processed, and send data that has been processed. The CPLD is used to receive control signals from the FPGA, drive the low-speed I / O interface, and send feedback signals to the FPGA. An analog-to-digital converter board, connected to the digital board, is used to adapt to different models of infrared detectors, enabling detector driving and analog signal acquisition and digitization; the analog-to-digital converter board can be modularly replaced according to different infrared detectors.

2. The infrared core circuit according to claim 1, characterized in that, The digital board and the interface board exchange data via high-speed serial communication through a high-speed LVDS interface, including: The FPGA and the CPLD communicate via differential signals; The FPGA converts the multiple parallel low-speed signals that need to be sent to the interface board from parallel to serial before sending them. The CPLD converts the received serial signal into a parallel signal and distributes it to the corresponding peripheral interface. Meanwhile, the CPLD converts the multiple parallel signals collected by the interface board into parallel signals and sends them back to the FPGA.

3. The infrared core circuit according to claim 1, characterized in that, The interface board further includes at least one of the following: a power interface, an electromechanical interface, a communication interface, or a video interface.

4. The infrared core circuit according to claim 1, characterized in that, The digital board, interface board, and analog-to-digital conversion board are configured in a stacked structure, and the digital board and interface board are connected by a high-speed inter-board connector; the high-speed inter-board connector is a domestically produced micro coaxial connector FMA-060-LD-A. The analog-to-digital converter board is connected to the digital board using a flexible circuit board structure.

5. The infrared core circuit according to claim 1, characterized in that, The high-speed serial communication data frame includes a check bit to ensure the accuracy of data transmission; and / or includes a fixed-frequency heartbeat signal to monitor the connection and disconnection status of the communication link. If an anomaly is detected, an error bit is generated.

6. The infrared core circuit according to claim 1, characterized in that, In the high-speed serial communication, some signals from multiple low-speed signals are address-encoded and data-packed, and then transmitted on the same set of differential lines.

7. The infrared core circuit according to claim 6, characterized in that, Pack N bits of parallel data, where K bits are used to represent the address and M bits are used to represent the data, thereby enabling the transmission of up to 2^K low-speed signals, each with a width of M bits, through a set of serial links, where N = K + M.

8. An infrared detector, characterized in that, Includes the infrared core circuit as described in claim 1.

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