Image sensor

Abstract

An image sensor comprises a photodiode, a conversion gain control tube, a first conversion gain path and a second conversion gain path, a drain electrode of the conversion gain control tube is coupled with the first conversion gain path, and a source electrode of the conversion gain control tube is coupled with the second conversion gain path; the first conversion gain path comprises a first reset tube, a first floating capacitor, a first sampling reset level storage array and a first sampling signal level storage array; the second conversion gain path comprises a second reset tube, a second floating capacitor, a second sampling reset level storage array and a second sampling signal level storage array; the grid electrode of the conversion gain control tube inputs a first control signal of a first level after the first reset tube and the second reset tube receive reset signals; the capacitance of the first floating capacitor is K times that of the second floating capacitor. According to the scheme, the data of the same group of photons can be read by different gain paths, so that high-dynamic-range imaging is realized.

Description

Technical Field

[0001] This invention relates to the field of image sensor technology, and more particularly to an image sensor. Background Technology

[0002] In frame-shift cameras, the image sensor needs to store multiple frames of image data in an extremely short time, with the time interval between adjacent frames potentially being only 20 nanoseconds (ns) or even shorter. Achieving high dynamic range (HDR) imaging under such extremely short frame intervals is extremely difficult.

[0003] Currently, methods such as global shutter cannot acquire data from the same cluster of photons within a very short time using paths with different gains, thus making it impossible to achieve high dynamic range imaging at extremely short frame intervals. Summary of the Invention

[0004] The purpose of this invention is at least to provide an image sensor that can read data of the same group of photons from different gain paths at extremely short frame intervals, thereby achieving high dynamic range imaging.

[0005] In a first aspect, the present invention provides an image sensor, comprising: a photodiode, a conversion gain control transistor, a first conversion gain path, and a second conversion gain path, wherein: the photodiode has its anode grounded and its cathode coupled to the source of the conversion gain control transistor; the conversion gain control transistor has its drain coupled to the first conversion gain path and its source coupled to the second conversion gain path; the first conversion gain path includes: a first reset transistor, a first floating capacitor, a first sampling reset level storage array, and a first sampling signal level storage array, wherein: the first sampling reset level storage array includes N sampling reset storage sub-units, the i-th sampling reset storage sub-unit being adapted to store the reset level corresponding to the i-th frame image; the reset level corresponding to the i-th frame image is the reset level in the first floating capacitor after the first reset transistor has been reset i times; the first sampling signal level storage array includes N sampling signal storage sub-units, the i-th sampling signal ... sampling signal storage sub-units; the first sampling signal level storage array includes N sampling signal storage sub-units, the first sampling signal storage sub-unit being adapted to store the sampling signal storage sub-units; the first sampling signal level storage array includes N sampling The signal level corresponding to the i-th frame image is stored. The second conversion gain path includes: a second reset transistor, a second floating capacitor, a second sampling reset level storage array, and a second sampling signal level storage array, wherein: the second sampling reset level storage array includes N sampling reset storage sub-units, and the i-th sampling reset storage sub-unit is adapted to store the reset level corresponding to the i-th frame image; the reset level corresponding to the i-th frame image is the reset level in the second floating capacitor after the second reset transistor is reset for the i-th time; the second sampling signal level storage array includes N sampling signal storage sub-units, and the i-th sampling signal storage sub-unit is adapted to store the signal level corresponding to the i-th frame image; the gate of the conversion gain control transistor receives a first control signal of the first level after the first reset transistor and the second reset transistor receive the reset signal; the capacitance of the first floating capacitor is K times the capacitance of the second floating capacitor, N is the total number of image frames, i, K, and N are all positive integers, and 1≤i≤N.

[0006] The image sensor includes a first conversion gain path and a second conversion gain path. The capacitance of the first floating capacitor in the first conversion gain path is K times the capacitance of the second floating capacitor in the second conversion gain path. The first and second conversion gain paths operate synchronously. When the first conversion gain path samples the reset level corresponding to the first frame image, the second conversion gain path can simultaneously sample the reset level corresponding to the first frame image; when the first conversion gain path samples the signal level corresponding to the first frame image, the second conversion gain path can simultaneously sample the signal level corresponding to the first frame image. Therefore, the first and second conversion gain paths can simultaneously acquire data corresponding to the same cluster of photons, thereby enabling high dynamic range imaging.

[0007] Optionally, the negative electrode voltage of the photodiode is not lower than the first level, and the charge generated by the photodiode is stored in the second floating capacitor; or the negative electrode voltage of the photodiode is lower than the first level, and the charge generated by the photodiode is stored in both the first floating capacitor and the second floating capacitor.

[0008] Optionally, the first conversion gain path further includes a first source follower transistor, a first pulse current transistor, and a first output unit, wherein: the first reset transistor has a power supply voltage input at its drain, a reset signal input at its gate, and its source is coupled to a first terminal of the first floating capacitor; the second terminal of the first floating capacitor is grounded; the first source follower transistor has a power supply voltage input at its drain, its gate is coupled to a first terminal of the first floating capacitor, and its source is coupled to the drain of the first pulse current transistor; the first pulse current transistor has its drain coupled to the first output unit, the first sampling reset level storage array, and the first sampling signal level storage array, and its source is grounded; the first pulse current transistor is turned on when a high-level signal is input to its gate to reset the first output unit; the first output unit is coupled to the first bit line and is adapted to output the reset level and signal level corresponding to each frame of image sequentially according to the readout order.

[0009] Optionally, the i-th sampling reset storage sub-unit includes: an i-th NMOS transistor and an i-th sampling reset capacitor, wherein: the source of the i-th NMOS transistor is coupled to the source of the first source follower transistor, and its drain is coupled to the first terminal of the i-th sampling reset capacitor; the i-th NMOS transistor is turned on when a high-level signal is input to its gate; and the second terminal of the i-th sampling reset capacitor is grounded.

[0010] Optionally, the i-th sampling signal storage sub-unit includes: an i-th NMOS transistor and an i-th sampling signal capacitor, wherein: the source of the i-th NMOS transistor is coupled to the source of the first source follower transistor, and its drain is coupled to the first terminal of the i-th sampling signal capacitor; the i-th NMOS transistor is turned on when a high-level signal is input to its gate; and the second terminal of the i-th sampling signal capacitor is grounded.

[0011] Optionally, the first conversion gain circuit further includes: a first analog memory switch transistor, the source of which is coupled to the source of the first source follower transistor, and the drain of which is coupled to the drain of the first pulse current transistor; the first analog memory switch transistor is turned on when a high-level signal is input to its gate, and the turn-on time of the first analog memory switch transistor is before the first reset transistor receives a reset signal for the first time.

[0012] Optionally, the first output unit includes a first NMOS transistor and a second NMOS transistor, wherein: the first NMOS transistor has a drain input power supply voltage, its gate is coupled to the drain of the first pulse current transistor, and its source is coupled to the drain of the second NMOS transistor; the second NMOS transistor has its source coupled to the first bit line; the second NMOS transistor is turned on when a high-level pixel readout command is input to its gate.

[0013] Optionally, the second conversion gain path further includes a second source follower transistor, a second pulse current transistor, and a second output unit, wherein: the second reset transistor has a power supply voltage input at its drain, a reset signal input at its gate, and its source is coupled to the first terminal of the second floating capacitor; the second floating capacitor has its second terminal grounded; the second source follower transistor has a power supply voltage input at its drain, its gate is coupled to the first terminal of the second floating capacitor, and its source is coupled to the drain of the second pulse current transistor; the second pulse current transistor has its drain coupled to the second output unit, the second sampling reset level storage array, and the second sampling signal level storage array, and its source is grounded; the second pulse current transistor is turned on when a high-level signal is input to its gate to reset the second output unit; the second output unit is coupled to the second bit line and is adapted to output the reset level and signal level corresponding to each frame of the image sequentially according to the readout order.

[0014] Optionally, the i-th sampling reset storage sub-unit includes: an i-th NMOS transistor and an i-th sampling reset capacitor, wherein: the source of the i-th NMOS transistor is coupled to the source of the second source follower transistor, and its drain is coupled to the first terminal of the i-th sampling reset capacitor; the i-th NMOS transistor is turned on when a high-level signal is input to its gate; and the second terminal of the i-th sampling reset capacitor is grounded.

[0015] Optionally, the i-th sampling signal storage sub-unit includes: an i-th NMOS transistor and an i-th sampling signal capacitor, wherein: the source of the i-th NMOS transistor is coupled to the source of the second source follower transistor, and its drain is coupled to the first terminal of the i-th sampling signal capacitor; the i-th NMOS transistor is turned on when a high-level signal is input to its gate; and the second terminal of the i-th sampling signal capacitor is grounded.

[0016] Optionally, the first conversion gain circuit further includes: a second analog storage switch transistor, the source of which is coupled to the source of the second source follower transistor, and the drain of which is coupled to the drain of the second pulse current transistor; the second analog storage switch transistor is turned on when a high-level signal is input to its gate, and the turn-on time of the second analog storage switch transistor is before the second reset transistor receives a reset signal for the first time.

[0017] Optionally, the second output unit includes a third NMOS transistor and a fourth NMOS transistor, wherein: the third NMOS transistor has a drain input power supply voltage, its gate is coupled to the drain of the second pulse current transistor, and its source is coupled to the drain of the fourth NMOS transistor; the fourth NMOS transistor has its source coupled to the second bit line; the fourth NMOS transistor is turned on when a high-level pixel readout command is input to its gate. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the structure of an image sensor according to an embodiment of the present invention;

[0019] Figure 2 This is a timing diagram of an exposure stage in an embodiment of the present invention;

[0020] Figure 3 This is a timing diagram of a readout stage in an embodiment of the present invention. Detailed Implementation

[0021] As described in the background section, it is currently impossible to acquire data from the same cluster of photons within a very short time using channels with different gains, thus making it impossible to achieve high dynamic range imaging at extremely short frame intervals.

[0022] In this embodiment of the invention, the first conversion gain path and the second conversion gain path operate synchronously. When the first conversion gain path samples the reset level corresponding to the first frame image, the second conversion gain path can simultaneously sample the reset level corresponding to the first frame image; when the first conversion gain path samples the signal level corresponding to the first frame image, the second conversion gain path can simultaneously sample the signal level corresponding to the first frame image. Therefore, the first and second conversion gain paths can simultaneously acquire data corresponding to the same cluster of photons, thereby achieving high dynamic range imaging.

[0023] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0024] This invention provides an image sensor, including a photodiode (PD), a conversion gain control transistor (SS1), a first conversion gain path, and a second conversion gain path. (Refer to...) Figure 1 A schematic diagram of the structure of an image sensor according to an embodiment of the present invention is provided.

[0025] In practice, the positive terminal of the photodiode PD is grounded, and the negative terminal of the photodiode PD is coupled to the source of the conversion gain control transistor SS1.

[0026] In a specific implementation, the drain of the conversion gain control transistor SS1 is coupled to the first conversion gain path, the source of the conversion gain control transistor SS1 is coupled to the second conversion gain path, and the gate of the conversion gain control transistor SS1 is input with a first control signal.

[0027] In this embodiment of the invention, the first conversion gain path includes: a first reset transistor RST1, a first floating capacitor Cfda, a first sampling reset level storage array, a first sampling signal level storage array, and a first output unit.

[0028] In a specific implementation, the drain of the first reset transistor RST1 is input with the power supply voltage VDDPIX, the gate of the first reset transistor RST1 is input with the reset signal, and the source of the first reset transistor RST1 is coupled to the first terminal of the first floating capacitor Cfda.

[0029] The second terminal of the first floating capacitor Cfda is grounded;

[0030] The drain of the first source follower transistor SF1a is input to the power supply voltage VDDPIX. The gate of the first source follower transistor SF1a is coupled to the first terminal of the first floating capacitor Cfda. The drain of the first source follower transistor SF1a is coupled to the drain of the first pulse current transistor PC1 and the first output unit.

[0031] The source of the first pulse current transistor PC1 is grounded; when a high-level control signal is input to the gate of the first pulse current transistor PC1, it is turned on, thereby resetting the first output unit.

[0032] In a specific implementation, the first sampling reset level storage array may include N sampling reset storage sub-units with the same structure.

[0033] The i-th sample-reset memory sub-cell may include the i-th NMOS transistor and the i-th sample-reset capacitor, wherein:

[0034] The source of the i-th NMOS transistor is coupled to the source of the first source follower transistor SF1a, and the drain of the i-th NMOS transistor is coupled to the first terminal of the i-th sampling reset capacitor; when a high-level control signal is input to the gate of the i-th NMOS transistor, the i-th NMOS transistor is turned on.

[0035] The second terminal of the i-th sampling reset capacitor is grounded.

[0036] The number of sampling reset capacitors is N. For example... Figure 1 As shown, the sampling reset capacitors include Cs1a1, Cs1a2, Cs1a3, ... Correspondingly, the number of NMOS transistors connected to each sampling reset capacitor is also N, and they are all grouped into group S1a.

[0037] In a specific implementation, the first sampling signal level storage array may include N sampling signal storage sub-units with the same structure.

[0038] The i-th sampled signal storage sub-unit may include the i-th NMOS transistor and the i-th sampled signal capacitor, wherein:

[0039] The source of the i-th NMOS transistor is coupled to the source of the first source follower transistor SF1a, and the drain of the i-th NMOS transistor is coupled to the first terminal of the i-th sampling signal capacitor; when a high-level control signal is input to the gate of the i-th NMOS transistor, the i-th NMOS transistor is turned on.

[0040] The second terminal of the capacitor for the i-th sampling signal is grounded.

[0041] The number of capacitors used for sampling the signal is N. For example... Figure 1 As shown, the sampling signal capacitors include Cs2a1, Cs2a2, Cs2a3, ... Correspondingly, the number of NMOS transistors connected to each sampling signal capacitor is also N, and they are all grouped into group S2a.

[0042] In a specific implementation, the first conversion gain path may further include a first analog memory switch transistor AMS1, wherein:

[0043] The source of the first analog memory switch AMS1 is coupled to the source of the first source follower transistor SF1a, and the drain of the first analog memory switch AMS1 is coupled to the drain of the first pulse current transistor PC1. When a high-level control signal is input to the gate of the first analog memory switch AMS1, the first analog memory switch AMS1 is turned on, thereby making the source of the first source follower transistor SF1a electrically connected to the drain of the first pulse current transistor PC1.

[0044] In a specific implementation, before the first reset signal is input to the gate of the first reset transistor RST1, a high level is input to the gate of the first analog storage switch transistor AMS1 and maintained at a high level until the acquisition of N frames of image data is completed.

[0045] In a specific implementation, the first output unit may include a first NMOS transistor MN1 and a second NMOS transistor MN2, wherein:

[0046] The gate of the first NMOS transistor MN1 is coupled to the source of the first source follower transistor SF1a. The drain of the first NMOS transistor MN1 is connected to the power supply voltage VDDPIX. The source of the first NMOS transistor MN1 is coupled to the drain of the second NMOS transistor MN2.

[0047] The source of the second NMOS transistor MN2 is connected to the first bit line; the second NMOS transistor MN2 is turned on when the pixel readout command is input at its gate, and outputs the reset level and signal level corresponding to each frame of image acquired by the first conversion gain path through its source.

[0048] In some embodiments, the first NMOS transistor MN1 can also be a source follower transistor.

[0049] In this embodiment of the invention, the second conversion gain path includes: a second reset transistor RST2, a second floating capacitor Cfdb, a second sampling reset level storage array, a second sampling signal level storage array, and a second output unit.

[0050] In a specific implementation, the drain of the second reset transistor RST2 is input with the power supply voltage VDDPIX, the gate of the second reset transistor RST2 is input with the reset signal, and the source of the second reset transistor RST2 is coupled to the first end of the second floating capacitor Cfdb.

[0051] The second terminal of the second floating capacitor Cfdb is grounded;

[0052] The drain of the second source follower transistor SF1b is input to the power supply voltage VDDPIX. The gate of the second source follower transistor SF1b is coupled to the first end of the second floating capacitor Cfdb. The drain of the second source follower transistor SF1b is coupled to the drain of the second pulse current transistor PC2 and the second output unit.

[0053] The source of the second pulse current transistor PC2 is grounded; when a high-level control signal is input to the gate of the second pulse current transistor PC2, it is turned on, thereby resetting the second output unit.

[0054] In a specific implementation, the second sampling reset level storage array may include N sampling reset storage sub-units with identical structures.

[0055] The i-th sample-reset memory sub-cell may include the i-th NMOS transistor and the i-th sample-reset capacitor, wherein:

[0056] The source of the i-th NMOS transistor is coupled to the source of the second source follower transistor SF1b, and the drain of the i-th NMOS transistor is coupled to the first terminal of the i-th sampling reset capacitor; when a high-level control signal is input to the gate of the i-th NMOS transistor, the i-th NMOS transistor is turned on.

[0057] The second terminal of the i-th sampling reset capacitor is grounded.

[0058] The number of sampling reset capacitors is N. For example... Figure 1As shown, the sampling reset capacitors include Cs1b1, Cs1b2, Cs1b3, ... Correspondingly, the number of NMOS transistors connected to each sampling reset capacitor is also N, and they are all grouped into group S1b.

[0059] In a specific implementation, the second sampling signal level storage array may include N sampling signal storage sub-units with the same structure.

[0060] The i-th sampled signal storage sub-unit may include the i-th NMOS transistor and the i-th sampled signal capacitor, wherein:

[0061] The source of the i-th NMOS transistor is coupled to the source of the second source follower transistor SF1b, and the drain of the i-th NMOS transistor is coupled to the first terminal of the i-th sampling signal capacitor; when a high-level control signal is input to the gate of the i-th NMOS transistor, the i-th NMOS transistor is turned on.

[0062] The second terminal of the capacitor for the i-th sampling signal is grounded.

[0063] The number of capacitors used for sampling the signal is N. For example... Figure 1 As shown, the sampling signal capacitors include Cs2b1, Cs2b2, Cs2b3, ... Correspondingly, the number of NMOS transistors connected to each sampling signal capacitor is also N, and they are all grouped into group S2b.

[0064] In a specific implementation, the second conversion gain path may further include a second analog memory switch AMS2, wherein:

[0065] The source of the second analog memory switch AMS2 is coupled to the source of the second source follower transistor SF1b, and the drain of the second analog memory switch AMS2 is coupled to the drain of the second pulse current transistor PC2. When a high-level control signal is input to the gate of the second analog memory switch AMS2, the second analog memory switch AMS2 is turned on, thereby making the source of the second source follower transistor SF1b electrically connected to the drain of the second pulse current transistor PC2.

[0066] In a specific implementation, before the gate of the second reset transistor RST2 is first input with a reset signal, a high level is input to the gate of the second analog storage switch transistor AMS2 and held at a high level until the acquisition of N frames of image data is completed.

[0067] In this embodiment of the invention, the turn-on time of the i-th NMOS transistor in group S1a is synchronized with the turn-on time of the i-th NMOS transistor in group S1b. The turn-on time of the i-th NMOS transistor in group S2a is synchronized with the turn-on time of the i-th NMOS transistor in group S2b.

[0068] In a specific implementation, in the first conversion gain path, the capacitance of the first floating capacitor Cfda can be K times that of the second floating capacitor Cfdb, where K is a positive integer and K>1.

[0069] In other words, the first conversion gain path is also the large floating capacitor conversion gain path, which has a relatively small conversion gain; the second conversion gain path is also the small floating capacitor conversion gain path, which has a relatively large conversion gain. In some embodiments, the first conversion gain path can also be called the small conversion gain path, and the second conversion gain path can also be called the large conversion gain path.

[0070] In practice, K can be a fixed value. The value of K can be determined based on the capacitance of the first floating capacitor Cfda and the capacitance of the second floating capacitor Cfdb selected in the actual application. For example, K=8, which means that the capacitance of the first floating capacitor Cfda is 8 times the capacitance of the second floating capacitor Cfdb.

[0071] The working process of the image sensor provided in the above embodiments of the present invention will be described below.

[0072] The operation of the aforementioned image sensor can include two stages: an exposure stage and a readout stage. (Refer to...) Figure 2 A timing diagram of the exposure stage is provided. (Refer to...) Figure 3 A timing diagram for the readout stage is given. The capacitance of the first floating capacitor Cfda is K times the capacitance of the second floating capacitor Cfdb.

[0073] During the exposure stage, a high-level control signal is first input to the gate of the first pulse current transistor PC1 and the gate of the second pulse current transistor PC2. Simultaneously, a high-level signal is output to the gates of all NMOS transistors in groups S1a, S1b, S2a, and S2b to control the conduction of all NMOS transistors in these groups. This resets all capacitors (sampling reset capacitor, sampling signal capacitor, and floating capacitor) in the first and second conversion gain paths, pulling the potential of the upper plate of all capacitors (i.e., the first terminal of the sampling capacitor) down to a lower level.

[0074] After resetting all capacitors, the exposure process for frames 1 through N is executed.

[0075] The exposure process for the first frame is as follows:

[0076] 1) Output a high-level reset signal to reset the photodiode PD, clear the residual charge in the photodiode PD, and start the exposure of the first frame.

[0077] 2) After the reset signal transitions from high to low, the first floating capacitor Cfda samples the level of the reset signal, and the second floating capacitor Cfdb samples the level of the reset signal.

[0078] In the first sampling reset level storage array, the NMOS transistor (s1a1) of the first sampling reset storage sub-unit is turned on after a high-level control signal is input to its gate, thereby storing the reset level in the first floating capacitor Cfda into the sampling reset capacitor (Cs1a1) of the first sampling reset storage sub-unit.

[0079] In the second sampling reset level storage array, the NMOS transistor (s1b1) of the first sampling reset storage sub-unit is turned on after a high-level control signal is input to its gate, thereby storing the reset level in the second floating capacitor Cfdb into the sampling reset capacitor (Cs1b1) of the first sampling reset storage sub-unit. The high-level control signals input to the gates of s1a1 and s1b1 are synchronized. That is, the gates of s1a1 and s1b1 simultaneously receive high-level control signals.

[0080] After the high-level control signal input to the gate of s1a1 and the gate of s1b1 transitions to a low level, step 2 is executed.

[0081] 3) The gate of the conversion gain control transistor SS1 is input with a first control signal of the first level.

[0082] The gate of the conversion gain control transistor SS1 is input with a first control signal of the first level. When the negative electrode voltage of the photodiode PD is not lower than the first level, the conversion gain control transistor SS1 is turned off, and the charge generated by the photodiode is stored in the second floating capacitor Cfdb. When the negative electrode voltage of the photodiode PD is higher than the first level, the conversion gain control transistor SS1 is turned on, and the charge generated by the photodiode PD is transferred. Part of the charge is stored in the first floating capacitor Cfda, and the other part of the charge is stored in the second floating capacitor Cfdb.

[0083] In some embodiments, when the conversion gain control transistor SS1 is turned on, the amount of charge stored in the first floating capacitor Cfda is referred to as the first charge, and the amount of charge stored in the second floating capacitor Cfdb is referred to as the second charge. The ratio of the first charge to the second charge is related to the ratio of the capacitance of the first floating capacitor Cfda to the capacitance of the second floating capacitor Cfdb. Typically, the ratio of the first charge to the second charge is approximately the same as the ratio of the capacitance of the first floating capacitor Cfda to the capacitance of the second floating capacitor Cfdb.

[0084] Step 4), the first control signal transitions from the first level to the low level.

[0085] Step 5), sample the signal.

[0086] In the first sampling signal level storage array, the NMOS transistor (s2a1) of the first sampling signal storage sub-unit is turned on after a high-level control signal is input to its gate, thereby storing the signal level in the first floating capacitor Cfda into the sampling signal capacitor (Cs2a1) of the first sampling signal storage sub-unit.

[0087] In the second sampling signal level storage array, the NMOS transistor (s2b1) of the first sampling signal storage sub-unit is turned on after a high-level control signal is input to its gate, thereby storing the signal level in the second floating capacitor Cfdb into the sampling signal capacitor (Cs2b1) of the first sampling signal storage sub-unit. The high-level control signals input to the gates of s2a1 and s2b1 are synchronized. That is, the gates of s2a1 and s2b1 simultaneously receive high-level control signals.

[0088] The exposure process for the first frame image is completed through steps 1) to 5) above.

[0089] Subsequently, the exposure process for the second to Nth frames can be referred to in steps 1) to 5) above for the exposure process of the first frame image, which will not be repeated here.

[0090] In this embodiment of the invention, after the exposure process of N frames of images is completed, the signals corresponding to the N frames of images are read from the image sensor. The first NMOS transistor MN1 and the third NMOS transistor MN3 are both source follower transistors. For distinction, the first NMOS transistor MN1 is also referred to as the third source follower transistor, and the third NMOS transistor MN3 is also referred to as the fourth source follower transistor.

[0091] The following explanation uses the process of reading the signal corresponding to the first frame of the image as an example.

[0092] Step 1) Output high-level signals to the gates of the first pulse current transistor PC1 and the second pulse current transistor PC2 respectively, turning on the first pulse current transistor PC1 and the second pulse current transistor PC2. Reset the gates of the third source follower transistor (i.e., the first NMOS transistor MN1) and the fourth source follower transistor (i.e., the second NMOS transistor MN2).

[0093] Step 2): After the signals input to the gates of the first pulse current transistor PC1 and the second pulse current transistor PC2 transition to low level signals, s1a1 in the first sampling reset level storage array and s1b1 in the second sampling reset level storage array are turned on respectively, thereby outputting the reset level stored in Cs1a1 to the gate of the third source follower transistor. The reset level stored in Cs1a1 is output through the first bit line BLa and quantized (denoted as Dra); and the reset level stored in Cs1b1 is output to the gate of the fourth source follower transistor. The reset level stored in Cs1b1 is output through the second bit line BLb and quantized (denoted as Drb).

[0094] Step 3): After reading the reset level stored in Cs1a1 and Cs1b1, a high-level signal is output to the gate of the pulse current transistor, turning it on. This resets the gates of the third and fourth source follower transistors.

[0095] Step 4): After the signal input to the gate of the pulse current transistor transitions to a low level, s2a1 in the first sampling signal level storage array and s2b1 in the second sampling signal level storage array are turned on respectively, thereby outputting the signal level stored in Cs2a1 to the gate of the third source follower transistor. The signal level stored in Cs2a1 is output through the first bit line BLa and quantized (denoted as Dsa); and the signal level stored in Cs2b1 is output to the gate of the fourth source follower transistor. The signal level stored in Cs2b1 is output through the second bit line BLb and quantized (denoted as Dsb).

[0096] Therefore, corresponding to the first frame image, the final light signal value obtained is:

[0097] Dl = (Dsa - Dra) × K + (Dsb - Drb), where K is the quotient obtained by dividing the capacitance of the first floating capacitor Cfda by the capacitance of the second floating capacitor Cfdb.

[0098] By following the same logic, using steps 1) to 4) above, the final optical signal value corresponding to each frame of the image can be obtained.

[0099] In summary, the image sensor provided by the embodiments of the present invention can perform reset operations and photocharge readout operations simultaneously, whether it is the first conversion gain path (small conversion gain path) or the second conversion gain path (large conversion gain path), exhibiting good synchronization. During the optical signal readout quantization process, correlated double sampling (CDS) readout is used, and all photocharges are quantized into optical signals, resulting in good noise characteristics.

[0100] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. An image sensor, characterized in that, include: A photodiode, a conversion gain control transistor, a first conversion gain path, and a second conversion gain path, wherein: The photodiode has its positive terminal grounded and its negative terminal coupled to the source of the conversion gain control transistor. The drain of the switching gain control transistor is coupled to the first switching gain path, and its source is coupled to the second switching gain path. The first conversion gain path includes: a first reset transistor, a first floating capacitor, a first sampled reset level storage array, and a first sampled signal level storage array, wherein: the first sampled reset level storage array includes N sampled reset storage sub-units, and the i-th sampled reset storage sub-unit is adapted to store the reset level corresponding to the i-th frame image; the reset level corresponding to the i-th frame image is the reset level in the first floating capacitor after the first reset transistor is reset for the i-th time; the first sampled signal level storage array includes N sampled signal storage sub-units, and the i-th sampled signal storage sub-unit is adapted to store the signal level corresponding to the i-th frame image; The second conversion gain path includes: a second reset transistor, a second floating capacitor, a second sampled reset level storage array, and a second sampled signal level storage array, wherein: the second sampled reset level storage array includes N sampled reset storage sub-units, and the i-th sampled reset storage sub-unit is adapted to store the reset level corresponding to the i-th frame image; the reset level corresponding to the i-th frame image is the reset level in the second floating capacitor after the second reset transistor is reset for the i-th time; the second sampled signal level storage array includes N sampled signal storage sub-units, and the i-th sampled signal storage sub-unit is adapted to store the signal level corresponding to the i-th frame image; After the first reset transistor and the second reset transistor receive the reset signal, the gate of the conversion gain control transistor receives a first control signal of the first level; the capacitance of the first floating capacitor is K times the capacitance of the second floating capacitor, N is the total number of image frames, i, K and N are all positive integers, 1≤i≤N.

2. The image sensor as described in claim 1, characterized in that, The negative electrode voltage of the photodiode is not lower than the first level, and the charge generated by the photodiode is stored in the second floating capacitor; The negative electrode voltage of the photodiode is lower than the first level, and the charge generated by the photodiode is stored in the first floating capacitor and the second floating capacitor.

3. The image sensor as described in claim 1 or 2, characterized in that, The first conversion gain path further includes a first source follower transistor, a first pulse current transistor, and a first output unit, wherein: The first reset transistor has a power supply voltage input at its drain, a reset signal input at its gate, and its source coupled to the first terminal of the first floating capacitor. The second terminal of the first floating capacitor is grounded. The first source follower transistor has its drain input power supply voltage, its gate coupled to the first terminal of the first floating capacitor, and its source coupled to the drain of the first pulse current transistor. The drain of the first pulse current transistor is coupled to the first output unit, the first sampling reset level storage array, and the first sampling signal level storage array, and its source is grounded; the first pulse current transistor is turned on when a high-level signal is input to its gate to reset the first output unit. The first output unit is coupled to the first bit line and is adapted to output the reset level and signal level corresponding to each frame of the image in the order of reading.

4. The image sensor as described in claim 3, characterized in that, The i-th sampling reset storage sub-unit includes: the i-th NMOS transistor and the i-th sampling reset capacitor, wherein: The i-th NMOS transistor has its source coupled to the source of the first source follower transistor, and its drain coupled to the first terminal of the i-th sampling reset capacitor; it is turned on when a high-level signal is input to the gate of the i-th NMOS transistor. The second terminal of the i-th sampling reset capacitor is grounded.

5. The image sensor as described in claim 3, characterized in that, The i-th sampling signal storage sub-unit includes: the i-th NMOS transistor and the i-th sampling signal capacitor, wherein: The i-th NMOS transistor has its source coupled to the source of the first source follower transistor, and its drain coupled to the first terminal of the i-th sampling signal capacitor; it is turned on when a high-level signal is input to the gate of the i-th NMOS transistor. The second terminal of the i-th sampling signal capacitor is grounded.

6. The image sensor as described in claim 3, characterized in that, The first conversion gain circuit further includes: a first analog storage switch transistor, the source of which is coupled to the source of the first source follower transistor, and the drain of which is coupled to the drain of the first pulse current transistor; the first analog storage switch transistor is turned on when a high-level signal is input to its gate, and the turn-on time of the first analog storage switch transistor is before the first reset transistor receives a reset signal for the first time.

7. The image sensor as described in claim 3, characterized in that, The first output unit includes: a first NMOS transistor and a second NMOS transistor, wherein: The first NMOS transistor has its drain connected to the power supply voltage, its gate coupled to the drain of the first pulse current transistor, and its source coupled to the drain of the second NMOS transistor. The source of the second NMOS transistor is coupled to the first bit line; the second NMOS transistor is turned on when a high-level pixel readout command is input to its gate.

8. The image sensor as described in claim 1 or 2, characterized in that, The second conversion gain path further includes a second source follower transistor, a second pulse current transistor, and a second output unit, wherein: The second reset transistor has a power supply voltage input at its drain, a reset signal input at its gate, and its source coupled to the first terminal of the second floating capacitor. The second floating capacitor has its second terminal grounded; The second source follower transistor has a drain input power supply voltage, its gate is coupled to the first terminal of the second floating capacitor, and its source is coupled to the drain of the second pulse current transistor. The drain of the second pulse current transistor is coupled to the second output unit, the second sampling reset level storage array, and the second sampling signal level storage array, and its source is grounded; the second pulse current transistor is turned on when a high-level signal is input to its gate to reset the second output unit. The second output unit, coupled to the second bit line, is adapted to output the reset level and signal level corresponding to each frame of the image in the order of readout.

9. The image sensor as claimed in claim 8, characterized in that, The i-th sampling reset storage sub-unit includes: the i-th NMOS transistor and the i-th sampling reset capacitor, wherein: The source of the i-th NMOS transistor is coupled to the source of the second source follower transistor, and its drain is coupled to the first terminal of the i-th sampling reset capacitor; the i-th NMOS transistor is turned on when a high-level signal is input to its gate. The second terminal of the i-th sampling reset capacitor is grounded.

10. The image sensor as claimed in claim 8, characterized in that, The i-th sampling signal storage sub-unit includes: the i-th NMOS transistor and the i-th sampling signal capacitor, wherein: The i-th NMOS transistor has its source coupled to the source of the second source follower transistor, and its drain coupled to the first terminal of the i-th sampling signal capacitor; it is turned on when a high-level signal is input to the gate of the i-th NMOS transistor. The second terminal of the i-th sampling signal capacitor is grounded.

11. The image sensor as claimed in claim 8, characterized in that, The first conversion gain circuit further includes: a second analog storage switch transistor, the source of which is coupled to the source of the second source follower transistor, and the drain of which is coupled to the drain of the second pulse current transistor; the second analog storage switch transistor is turned on when a high-level signal is input to its gate, and the turn-on time of the second analog storage switch transistor is before the second reset transistor receives a reset signal for the first time.

12. The image sensor as claimed in claim 8, characterized in that, The second output unit includes: a third NMOS transistor and a fourth NMOS transistor, wherein: The third NMOS transistor has a drain input power supply voltage, its gate is coupled to the drain of the second pulse current transistor, and its source is coupled to the drain of the fourth NMOS transistor. The source of the fourth NMOS transistor is coupled to the second bit line; the fourth NMOS transistor is turned on when a high-level pixel readout command is input to its gate.

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