SoC FPGA-based real-time spectrum analysis software implementation method

Abstract

The invention discloses a real-time spectrum analysis software implementation method based on an SoC FPGA, and the method comprises the following steps: connecting a PS end with a PL end through a BRAM interface, and forming the SoC FPGA; the PS end issues frequency sweeping control parameters to the PL end; the PL end analyzes the parameters and sends the parameters to the frequency sweep controller, and the frequency sweep controller controls the work of the signal processing link; the ADC module directly samples the radio frequency signal and outputs a real signal; obtaining an IQ signal with a specified signal rate by using a down-conversion module; the numerical control AGC amplifies a section of IQ signal subjected to frequency spectrum calculation to the maximum amplitude; the FFT module performs frequency spectrum calculation on the current IQ signal; and the PS splices the frequency spectrums uploaded by the PL end. According to the SoC FPGA platform disclosed by the invention, the ARM processor is fused with the FPGA programmable logic, and the ARM processor is responsible for realizing flexible configuration of a frequency spectrum measurement task; the FPGA is responsible for real-time preprocessing, parallel FFT calculation and feature parameter extraction of data collected by the radio frequency front end, so that the spectrum analysis function can be dynamically adjusted according to the service requirements of the SDR system.

Description

Technical Field

[0001] This invention relates to the field of measurement technology, and more specifically, to a method for implementing real-time spectrum analysis software based on SoC FPGA. Background Technology

[0002] The real-time spectrum analysis software implementation method based on SoC FPGA is an important technical path for current software-defined radio technology in the field of spectrum measurement and sensing, providing flexible and efficient dynamic spectrum analysis capabilities for wireless communication systems. 5G base stations need to monitor surrounding frequency band interference in real time to avoid co-channel collisions, and IoT gateways need to dynamically adjust their transmitter frequency points to avoid congested channels. These requirements all rely on real-time and accurate spectrum analysis capabilities. In existing technical solutions, professional spectrum analyzers are the mainstream tools for spectrum measurement, implementing fixed-function spectrum analysis, such as FFT calculation and power spectrum display, through dedicated ASICs or high-performance DSP chips, featuring high measurement accuracy and strong stability. In contrast, software-defined radio platforms based on general-purpose processors (CPUs) or embedded DSPs process signals acquired by the RF front-end through software algorithms, such as Fast Fourier Transform (FFT) and digital filtering, to achieve flexible customization of spectrum analysis logic. Building upon this foundation, SoC FPGA, as a heterogeneous computing platform that is "hardware reconfigurable and software programmable," integrates the ARM processor responsible for control and algorithm logic with the FPGA responsible for high-speed parallel data processing on a single chip. This provides a superior hardware foundation for real-time spectrum analysis. It can achieve high-speed signal acquisition, preprocessing, and FFT parallel acceleration through the FPGA, and can also run flexible spectrum analysis software through the ARM processor, thereby ensuring real-time performance while supporting flexible functional expansion.

[0003] Although professional spectrum analyzers and general-purpose software-defined radio platforms are widely used in spectrum measurement, they still struggle to adapt to complex wireless communication scenarios. Professional spectrum analyzers suffer from fixed functionality and insufficient flexibility. Their analytical functions, such as measurement modes, display formats, and trigger conditions, are typically implemented through hardware circuitry or fixed firmware. Users can only configure preset parameters via buttons or menus, making it difficult to set up special requirements, such as dynamic band sensing in cognitive radio or interference analysis of non-standard communication systems for functional expansion or algorithm adjustment. Software-defined radio platforms based on general-purpose processors (CPUs) or embedded DSPs have limitations in real-time performance and processing power. CPUs / DSPs typically employ serial or limited parallel architectures, resulting in poor performance in FFT calculations, spectrum data storage, and display when dealing with high sampling rate signals. Furthermore, the hardware resources of general-purpose platforms limit their ability to simultaneously process multi-channel, multi-band signals, making them unsuitable for complex communication scenarios, such as the joint spectrum analysis requirements of MIMO systems. Although some existing SoC FPGA-based solutions have attempted to combine the parallel acceleration of FPGA with the software flexibility of ARM, most implementations still suffer from problems such as low hardware-software co-operation efficiency and insufficient real-time optimization. In particular, their overall performance still needs to be improved when facing wireless communication systems with low power consumption, miniaturization, and high dynamic requirements. Summary of the Invention

[0004] The present invention aims to overcome at least one defect in the prior art and provide a real-time spectrum analysis software implementation method based on SoC FPGA to solve the problems of low hardware and software co-operation efficiency and insufficient real-time optimization of SoC FPGA platform.

[0005] The technical solution adopted in this invention is a method for implementing real-time spectrum analysis software based on SoC FPGA, comprising the following steps: S1. Connect the PS terminal and PL terminal using a BRAM interface to form a SoC FPGA. S2 and PS terminals send sweep frequency control parameters to PL terminal; The parameters parsed by S3 and PL are sent to the sweep frequency controller, which then controls the operation of the signal processing link. The signal processing link includes an analog AGC module, an ADC module, a down-conversion module, a numerical control AGC module, and a spectrum calculation module. S4, the ADC module receives externally input radio frequency signals, directly samples the radio frequency signals, and outputs real signals to the downconversion module and the analog AGC module; S5. The down-conversion module down-converts the signal to obtain an IQ signal with a specified signal rate, and sends the IQ signal to the CNC AGC module. S6. The numerical control AGC amplifies the current IQ signal to its maximum amplitude and inputs it into the spectrum calculation module; S7, the spectrum calculation module performs spectrum calculation on the current segment of IQ signal and uploads the calculated spectrum data to the PS terminal; S8 and PS splice the spectrum uploaded from the PL end.

[0006] SoC FPGA is a system-on-a-chip that integrates an ARM processor (PS side) and an FPGA (PL side). The data interaction between the PS side and the PL side is achieved through a BRAM interface, forming the SoC FPGA platform. The BRAM is a dual-port BRAM, and its depth can be flexibly set. By sampling, down-converting, mixing, spectrum shifting, filtering, amplifying, spectrum calculation, and splicing of RF signals, the analyzed spectrum is obtained.

[0007] In order to scan the signal, the PS terminal in step S2 sends the frequency sweep control parameters to the PL terminal, including the following steps: S21. Write the scan table from the PS terminal to the PL terminal. The scan table includes the number, center frequency, gain control mode, and gain control value. S22, PS end-to-end write scan dwell time; S23, PS terminal writes a command to control PL terminal to start scanning; S24. After the scan begins, the PL terminal scans according to the scan table and residence time, and outputs the power spectrum data of each frequency point in sequence. S25, PS end write command to stop scanning; S26, PS terminal write command to set center frequency, gain control mode and gain control value; S27. For the next scan, if the parameters remain unchanged, directly set the scan start.

[0008] The scanning table, scan dwell time, and command control are used on the PS terminal to control the PL terminal to perform scanning. The PS terminal sets the center frequency, gain control mode, and gain control value to avoid the PL terminal being in an uncertain working state. The gain control mode and gain control value control the analog AGC module and the digital AGC module.

[0009] The PL-end analytical parameters in step S3 include center frequency, real-time analysis bandwidth, number of FFT points, window function type, number of power spectrum integrations, FFT interval time, scan dwell time, scan status, and scan table.

[0010] The center frequency is the mixing frequency of the mixer in the downconverter module in fixed-frequency mode; the real-time analysis bandwidth determines the downconverted signal used to calculate the spectrum in the downconverter module; the FFT points are the length of the power spectrum output by the spectrum calculation module; the window function type is the windowing method of the spectrum calculation module; the power spectrum integration count is the cumulative summation count of the power spectrum in the spectrum calculation module; the FFT interval is the time interval between two calculations in the spectrum calculation module; the scan dwell time is the dwell time of each scan table; the scan state determines whether the current mode is scan mode or fixed-frequency mode.

[0011] The above parameters are sent to the sweep frequency controller, which then controls the operation of the signal processing link.

[0012] To obtain an IQ signal at a specified rate, step S5, which uses a down-conversion module to down-convert the signal to obtain an IQ signal at the specified rate, includes the following steps: S51, the downconverter module uses sampling and resampling technology to sample the signal, with a minimum sampling frequency of one signal bandwidth; S52. Mix the real signal and shift the spectrum of the specified frequency band to the zero frame point to obtain the IQ signal; S53. The IQ signal is downconverted step by step using decimation FIR filtering to obtain the IQ signal at the specified signal rate.

[0013] The signal is acquired by multiple sampling, then mixed and spectrum shifted to obtain the IQ signal, and then filtered stepwise to obtain the signal at the specified rate.

[0014] To obtain the IQ signal amplified to its maximum value, the numerical control AGC module in step S6 amplifies the current segment of the IQ signal to its maximum amplitude, specifically as follows: Obtain a fixed-length IQ signal, calculate the absolute value of the two signals, and obtain the maximum value of the two absolute values. Assume a coefficient such that the result of multiplying the maximum value by the coefficient is approximately equal to and not greater than a specified maximum positive value. Multiply the IQ signal by the coefficient to obtain the IQ signal amplified by the CNC AGC module.

[0015] The IQ signal is amplified to its maximum by using a numerical control AGC module, which facilitates subsequent spectrum calculation.

[0016] To calculate the spectrum of the IQ signal, step S7 involves performing spectrum calculation on the current segment of the IQ signal, which includes the following steps: S71. Window the current segment of the IQ signal; S72. Perform a Fast Fourier Transform on the current segment of the IQ signal; S73. Convert the results of the Fast Fourier Transform into a power spectrum; S74. Correct the power spectrum. Correction value = Simulated AGC attenuation value - CNC AGC gain value + Calibration value + Fixed value + Window function correction value. S75. Integrate and sort the power spectrum; S76. Based on the set number of FFT points, extract the power spectrum and output it. The extraction method is to extract the maximum value from each extraction group.

[0017] The IQ signal is converted into a power spectrum using window functions and Fast Fourier Transform (FFT). The power spectrum is then corrected, integrated, sorted, and decimated. The maximum value of each group is extracted and recorded as the spectrum calculation result. Window function types include Hanning, Hamming, Blackman, Chebyshev, and rectangular windows. Window functions improve the quality of frequency domain analysis, suppress spectral leakage, increase frequency resolution, and facilitate subsequent calculations.

[0018] To obtain the power spectrum, step S73, which converts the Fast Fourier Transform result into a power spectrum, specifically involves:

[0019] These are the real and imaginary parts of the Fast Fourier Transform result.

[0020] The power spectrum is integrated and sorted. The integration is performed by accumulating multiple power spectrum segments according to the number of integrations and then averaging them. The sorting is performed by arranging the power spectrum in reverse order into forward order.

[0021] By calculating the average of multiple power spectrum segments and sorting the power spectrum, it becomes easier to extract the maximum value later.

[0022] In order to obtain the frequency domain information of the signal more comprehensively and accurately, the PS end in step S8 splices the spectrum uploaded by the PL end. Specifically, if it is a fixed frequency mode, no splicing is required; if it is a frequency sweep mode, splicing is performed.

[0023] Because the scanning table, center frequency, gain control method, and gain control amount may differ in frequency sweep mode, calculation results under multiple spectra will appear, resulting in inconsistent spectra. In order to obtain more accurate frequency domain information, the spectra need to be stitched together.

[0024] Compared with the prior art, the beneficial effects of the present invention are as follows: The SoC FPGA platform, through the integration of a heterogeneous architecture (ARM processor + FPGA programmable logic), decomposes the spectrum analysis requirements of the SDR system into three functional modules: "control layer - computing layer - interface layer," and allocates hardware resources accordingly. The ARM processor runs an embedded operating system and high-level control software, responsible for the flexible configuration of spectrum measurement tasks, such as scanning bands, resolution bandwidth, and dynamic threshold adjustment. The FPGA logic resources are dedicated to a high-speed signal processing pipeline, undertaking real-time preprocessing of RF front-end acquired data, parallel FFT calculation, and feature parameter extraction. This collaborative model of "software-defined functions + hardware-accelerated execution" allows the spectrum analysis function to be dynamically adjusted according to the SDR system's service requirements. For example, the scanning frequency can be reduced to save power in low-interference scenarios, and a high-sensitivity narrowband detection mode can be switched in strong-interference environments, meeting the software-defined radio's requirements for "flexible configuration and on-demand sensing." Attached Figure Description

[0025] The accompanying drawings are for illustrative purposes only and should not be construed as limiting the invention. To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0026] Figure 1 This is a flowchart of a real-time spectrum analysis software implementation method based on SoC FPGA according to the present invention.

[0027] Figure 2 This is a flowchart illustrating the distribution of sweep frequency control parameters in a real-time spectrum analysis software implementation method based on SoC FPGA according to the present invention.

[0028] Figure 3 This is a flowchart illustrating the acquisition of IQ signals at a specified rate in a real-time spectrum analysis software implementation method based on SoC FPGA according to the present invention.

[0029] Figure 4 This is a flowchart illustrating the spectrum calculation of IQ signals in a real-time spectrum analysis software implementation method based on SoC FPGA according to the present invention.

[0030] Figure 5 This is an architecture diagram of a real-time spectrum analysis software based on SoC FPGA according to the present invention.

[0031] Figure 6 This is a simplified flowchart of a sweep FFT mode in the real-time spectrum analyzer of the present invention.

[0032] Figure 7 This is a downconversion flowchart of a real-time spectrum analysis software implementation method based on SoC FPGA according to the present invention.

[0033] like Figure 8 This diagram illustrates the process of amplifying IQ signals using a numerically controlled AGC module in a real-time spectrum analysis software implementation method based on a SoC FPGA, as described in this invention. Detailed Implementation

[0034] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0035] It should be noted that, unless otherwise defined, the technical or scientific terms used in this invention should have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in this invention do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0036] Example 1 like Figure 1-5 As shown in the figure, this embodiment provides a real-time spectrum analysis software implementation method based on SoC FPGA, which includes the following steps: S1. Connect the PS terminal and PL terminal using a BRAM interface to form a SoC FPGA. SoC FPGA is a system-on-a-chip that integrates an ARM processor as the PS end and an FPGA as the PL end. In this invention, the data interaction between the PS end and the PL end adopts a BRAM interface. The BRAM is a dual-port BRAM, and its depth can be flexibly set.

[0037] S2 and PS terminals send sweep frequency control parameters to PL terminal; The scanning mode process is as follows: S21, PS end writes scan table to PL end. Scan table includes number, center frequency, gain control mode and gain control value; Write one at a time, numbering from 1, until all are written.

[0038] S22, PS end-to-end write scan dwell time; S23, PS terminal writes a command to control PL terminal to start scanning; S24. After the scan starts, the PL terminal automatically scans according to the scan table and residence time, and outputs the power spectrum data of each frequency point in sequence. S25, PS end write command to stop scanning, switch to fixed frequency mode; S26, PS terminal write command to set center frequency, gain control mode and gain control value; Avoid placing the PL end in an uncertain working state.

[0039] S27. For the next scan, if the parameters remain unchanged, directly set the scan start.

[0040] S3 and PL terminals parse parameters and send them to the sweep frequency controller, which then controls the operation of the signal processing link. The parameters parsed by the PL end include center frequency, real-time analysis bandwidth, number of FFT points, window function type, number of power spectrum integrations, FFT interval time, scan dwell time, scan status, and scan table. These parameters are sent to the sweep frequency controller, which controls the operation of the signal processing link.

[0041] The control link includes an analog AGC module (AGC), an ADC module (ADC), a down-conversion module (DDC), a numerically controlled AGC module (DGC), and a frequency spectrum calculation module (FFT). The specific operating method is as follows: For example, the gain control method and gain control amount control the analog AGC module and the digital AGC module; the center frequency is the mixing frequency of the mixer in the downconverter module in fixed-frequency mode; the real-time analysis bandwidth determines which downconverted signal in the downconverter module is used to calculate the spectrum; the FFT points specify the length of the power spectrum output by the spectrum calculation module; the window function type determines the windowing method in the spectrum calculation module; the number of power spectrum integrations controls the number of power spectrum summations in the spectrum calculation module; the FFT interval time is the interval between two calculations in the spectrum calculation module; the scan dwell time is the dwell time of each scan table. For example, if the spectrum of the current scan table has been calculated, but the scan table dwell time has not yet been reached, then the spectrum of the current scan table will continue to be calculated; the scan state determines whether the current mode is scan mode or fixed-frequency mode.

[0042] S4, the ADC module receives externally input radio frequency signals, directly samples the radio frequency signals, and outputs real signals to the downconversion module and the analog AGC module; The analog AGC module controls the gain of the external amplifier chip and attenuator chip to keep the strength of the externally input RF signal within a suitable range and ensure the amplitude stability of the RF signal.

[0043] S5. Use the down-conversion module to down-convert the signal to obtain the IQ signal with the specified signal rate, and send the IQ signal to the CNC AGC module. like Figure 7 As shown, the S51 downconverter module uses sampling and resampling technology, with a minimum sampling frequency of one signal bandwidth. S52. Mix the real signal and shift the spectrum of the specified frequency band to the zero frame point to obtain the IQ signal; S53. The IQ signal is downconverted step by step using decimation FIR filtering to obtain the IQ signal at the specified signal rate.

[0044] like Figure 8 As shown, S6 and the numerical control AGC amplify the current segment IQ signal to its maximum amplitude and input it into the spectrum calculation module; If the number of points of the IQ signal to be calculated is L, the AGC will amplify each point of the IQ signal by the same factor, and maximize the amplitude of the IQ signal without overflowing, so as to ensure the accuracy of subsequent spectrum calculation.

[0045] For example, acquiring an IQ signal of length L. Calculate the absolute values ​​of the I and Q signals to obtain Obtain the maximum absolute value X of the IQ signals, multiply X by a coefficient g, where g is a power of 2, so that X is close to but not greater than the specified maximum positive value, and then process this segment of the IQ signal. Multiply by the coefficient g to obtain the amplified IQ signal of the numerical control AGC.

[0046] The numerical control AGC method in this embodiment requires no feedback and only needs to adjust the gain once. It has the characteristics of fast response and can be well adapted to spectrum calculation scenarios.

[0047] S7, the spectrum calculation module performs spectrum calculation on the current segment of IQ signal and uploads the calculated spectrum data to the PS terminal; S71. Window the current segment of the IQ signal; Window function types include Hanning, Heming, Blackman, Chebyshev, and rectangular windows.

[0048] S72. Perform a Fast Fourier Transform on the current segment of the IQ signal; The Fast Fourier Transform is implemented using the Xlinix IP core.

[0049] S73. Convert the results of the Fast Fourier Transform into a power spectrum; Specifically:

[0050] To obtain the real and imaginary parts of the Fast Fourier Transform result, in the PL terminal, It is implemented using a lookup table method, which consumes fewer resources compared to the CORDIC algorithm.

[0051] S74. Correct the power spectrum. Correction value = attenuation value of the analog AGC module - gain value of the numerical control AGC module + calibration amount + fixed amount + window function correction amount. S75. Integrate and sort the power spectrum; Integration involves accumulating multiple power spectrum segments based on the number of integrations of the power spectrum and then averaging them. Sorting involves converting the reversed power spectrum into the forward-ordered one. Integration and sorting are implemented using the same RAM to save BRAM resources on the PL side.

[0052] S76. Based on the set number of FFT points, extract the power spectrum and output it. The extraction method is to extract the maximum value from each extraction group.

[0053] S8 and PS splice the spectrum uploaded from the PL end.

[0054] If it is a fixed frequency mode, no splicing is required; if it is a frequency sweep mode, splicing is required. For example, if the real-time analysis bandwidth is set to 4 MHz, and the PS end sends three scan tables with center frequencies of 5, 9, and 13 MHz respectively, the PS end splices the three spectrum segments uploaded by the PL end together to obtain a spectrum segment of 3~15 MHz.

[0055] This embodiment uses a swept-frequency FFT mode, which is a combination of scanning mode and FFT mode. The result of a single scan is a combination of multiple FFT scans obtained at different center frequencies.

[0056] like Figure 6As shown, the parameters of the real-time spectrum analyzer are set to center frequency = 10 MHz, sweep width = 8 MHz, and real-time analysis bandwidth = 4 MHz. To obtain this spectrum, a sweep frequency FFT is performed using the corresponding real-time analysis bandwidth. The original 122.88 MHz RF signal of the first time period is mixed with the 8 MHz local oscillator signal. After down-conversion, a signal with a sampling rate of 5.12 MHz is obtained. The spectrum of this signal is calculated to obtain the power spectrum. Invalid data on both sides of the power spectrum is removed, and only the middle data is retained. The length of the middle data is equal to 1 / 1.28 of the original length, resulting in the spectrum of the original RF signal from 6 MHz to 10 MHz. The same operation is performed on the original RF signal of the adjacent second time period, replacing the 8 MHz local oscillator signal with a 12 MHz local oscillator signal, resulting in the spectrum of the original RF signal from 10 MHz to 14 MHz. The two spectra are then spliced ​​together to obtain the spectrum with center frequency = 10 MHz and sweep width = 8 MHz.

[0057] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0058] The preferred embodiments of the present invention disclosed above are merely illustrative of the invention. These preferred embodiments do not exhaustively describe all details, nor do they limit the invention to specific implementation methods. Clearly, many modifications and variations can be made based on the content of this specification. The selection and specific description of these embodiments in this specification are intended to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method for implementing real-time spectrum analysis software based on SoC FPGA, characterized in that, Includes the following steps: S1. Connect the PS terminal and PL terminal using a BRAM interface to form a SoC FPGA. S2 and PS terminals send sweep frequency control parameters to PL terminal; The parameters parsed by S3 and PL are sent to the sweep frequency controller, which then controls the operation of the signal processing link. The signal processing link includes an analog AGC module, an ADC module, a down-conversion module, a numerical control AGC module, and a spectrum calculation module. S4, the ADC module receives externally input radio frequency signals, directly samples the radio frequency signals, and outputs real signals to the downconversion module and the analog AGC module; S5. The down-conversion module down-converts the signal to obtain an IQ signal with a specified signal rate, and sends the IQ signal to the CNC AGC module. S6. The numerical control AGC amplifies the current segment IQ signal to its maximum amplitude and inputs it into the spectrum calculation module; S7, the spectrum calculation module performs spectrum calculation on the current segment of IQ signal and uploads the calculated spectrum data to the PS terminal; S8 and PS splice the spectrum uploaded from the PL end.

2. The method for implementing real-time spectrum analysis software based on SoC FPGA according to claim 1, characterized in that, The step S2, in which the PS terminal sends the frequency sweep control parameters to the PL terminal, includes the following steps: S21. Write the scan table from the PS terminal to the PL terminal. The scan table includes the number, center frequency, gain control mode, and gain control value. S22, PS end-to-end write scan dwell time; S23, PS terminal writes a command to control PL terminal to start scanning; S24. After the scan begins, the PL terminal scans according to the scan table and residence time, and outputs the power spectrum data of each frequency point in sequence. S25, PS end write command to stop scanning; S26, PS terminal write command to set center frequency, gain control mode and gain control value; S27. For the next scan, if the parameters remain unchanged, directly set the scan start.

3. The method for implementing real-time spectrum analysis software based on SoC FPGA according to claim 1, characterized in that, The PL-end analytical parameters in step S3 include center frequency, real-time analysis bandwidth, number of FFT points, window function type, power spectrum integration times, FFT interval, scan dwell time, scan status, and scan table. .

4. A method for implementing real-time spectrum analysis software based on SoC FPGA according to claim 3, characterized in that, The center frequency is the mixing frequency of the mixer in the downconverter module in fixed-frequency mode; the real-time analysis bandwidth determines the downconverted signal used to calculate the spectrum in the downconverter module; the FFT points are the length of the power spectrum output by the spectrum calculation module; the window function type is the windowing method of the spectrum calculation module; the power spectrum integration count is the cumulative summation count of the power spectrum in the spectrum calculation module; the FFT interval is the time interval between two calculations in the spectrum calculation module; the scan dwell time is the dwell time of each scan table; the scan state determines whether the current mode is scan mode or fixed-frequency mode.

5. A method for implementing real-time spectrum analysis software based on SoC FPGA according to claim 1, characterized in that, Step S5, which uses a down-conversion module to down-convert the signal to obtain an IQ signal with a specified signal rate, includes the following steps: S51, the downconverter module uses sampling and resampling technology to sample the signal, with a minimum sampling frequency of one signal bandwidth; S52. Mix the real signal and shift the spectrum of the specified frequency band to the zero frame point to obtain the IQ signal; S53. The IQ signal is downconverted step by step using decimation FIR filtering to obtain the IQ signal at the specified signal rate.

6. A method for implementing real-time spectrum analysis software based on SoC FPGA according to claim 1, characterized in that, In step S6, the numerical control AGC module amplifies the current segment IQ signal to its maximum amplitude, specifically as follows: Obtain a fixed-length IQ signal, calculate the absolute values ​​of the I and Q signals, and obtain the maximum value of the two absolute values. Assume a coefficient such that the result of multiplying the maximum value by the coefficient is approximately equal to and not greater than a specified maximum positive value. Multiplying the IQ signal by the coefficient yields the amplified IQ signal from the numerical control AGC module.

7. A method for implementing real-time spectrum analysis software based on SoC FPGA according to claim 1, characterized in that, The spectrum calculation module in step S7 performs spectrum calculation on the current segment of the IQ signal, including the following steps: S71. Window the current segment of the IQ signal; S72. Perform a Fast Fourier Transform on the current segment of the IQ signal; S73. Convert the results of the Fast Fourier Transform into a power spectrum; S74. Correct the power spectrum. Correction value = attenuation value of the analog AGC module - gain value of the numerical control AGC module + calibration amount + fixed amount + window function correction amount. S75. Integrate and sort the power spectrum; S76. Based on the set number of FFT points, extract the power spectrum and output it. The extraction method is to extract the maximum value from each extraction group.

8. The method for implementing real-time spectrum analysis software based on SoC FPGA according to claim 7, characterized in that, The step S73, which converts the Fast Fourier Transform result into a power spectrum, specifically involves: These are the real and imaginary parts of the Fast Fourier Transform result.

9. A method for implementing real-time spectrum analysis software based on SoC FPGA according to claim 7, characterized in that, In step S75, integrating the power spectrum involves accumulating multiple power spectrum segments based on the number of integrations and then averaging them; sorting the power spectrum involves arranging the reverse-order power spectrum into the forward-order sequence.

10. A method for implementing real-time spectrum analysis software based on SoC FPGA according to claim 1, characterized in that, In step S8, the PS end splices the spectrum uploaded by the PL end. Specifically, if it is a fixed frequency mode, no splicing is required; if it is a frequency sweep mode, splicing is performed.

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