Semiconductor device

Abstract

A semiconductor device includes: a memory cell array region including memory cells connected to word lines and bit lines; and a peripheral circuit region including the first semiconductor element and the second semiconductor element. Each of the first semiconductor element and the second semiconductor element includes: a fin structure extending in a first direction on the substrate; a gate structure extending on the fin structure in a second direction perpendicular to the first direction and including a gate insulating layer and a gate metal layer; and a source region and a drain region in the substrate at opposite sides of the fin structure. A thickness of the gate insulating layer in the first semiconductor element is greater than a thickness of the gate insulating layer in the second semiconductor element, and a source region and a drain region in the first semiconductor element are doped with a first conductivity type impurity and have different structures.

Description

Cross-references to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2024-0109381, filed with the Korean Intellectual Property Office on August 14, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates generally to semiconductor devices. Background Technology

[0003] Semiconductor devices are a crucial part of the electronics industry. Both storage devices for storing data and processors for processing data can be implemented using semiconductor devices. FinFET devices can be used to improve integration density, and research on FinFET devices capable of operating under high voltage conditions is actively underway. In high-voltage operating FinFET devices, it is necessary to improve characteristics affecting device reliability (such as hot carrier injection (HCI) and gate-induced drain leakage (GIDL)). Summary of the Invention

[0004] One aspect of this disclosure is to provide a semiconductor device with improved reliability, particularly when operating under high voltage conditions.

[0005] A semiconductor device according to an example embodiment of the present disclosure includes: a memory cell array region including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines; and a peripheral circuit region including a first semiconductor element in a first element region and a second semiconductor element in a second element region, wherein each of the first semiconductor element and the second semiconductor element includes: a substrate; a fin structure extending on the substrate along a first direction; a gate structure extending on the fin structure along a second direction perpendicular to the first direction and including a gate insulating layer and a gate metal layer; and a source region and a drain region located on either side of the fin structure in the substrate and spaced apart from each other. The thickness of the gate insulating layer included in the first semiconductor element is greater than the thickness of the gate insulating layer included in the second semiconductor element, and the source region and drain region included in the first semiconductor element are doped with impurities of a first conductivity type and have different structures.

[0006] The semiconductor device according to an example embodiment of the present disclosure includes: a substrate; a fin structure extending on the substrate in a first direction parallel to an upper surface of the substrate; a gate structure extending on the fin structure in a second direction parallel to an upper surface of the substrate and perpendicular to the first direction; and a source region and a drain region formed in the substrate at both ends of the fin structure and spaced apart from each other, wherein the size of the source region and the size of the drain region are substantially the same, and the source region and the drain region are located at different positions based on the gate structure in a third direction perpendicular to the first direction and the second direction, respectively.

[0007] The semiconductor device according to an example embodiment includes: a substrate; a fin structure extending on the substrate along a first direction; a gate structure extending on the fin structure along a second direction perpendicular to the first direction; a source region and a drain region formed on both sides of the fin structure in the substrate and spaced apart from each other, wherein the size of the drain region is larger than the size of the source region, and the shortest distance in a third direction perpendicular to the upper surface of the substrate between the lower surface of the gate structure and the lower surface of the drain region is less than the shortest distance in a third direction between the lower surface of the gate structure and the lower surface of the source region.

[0008] According to embodiments of this disclosure, the source and drain regions included in a semiconductor device can have different structures, thereby reducing the electric field around the region where the gate structure and drain regions overlap. Because the source and drain regions of the semiconductor device have different structures, a semiconductor device with improved HCI and GIDL characteristics can be provided, thereby improving the reliability of the semiconductor device.

[0009] The advantages and effects of this disclosure are not limited to the foregoing, and can be more easily understood in the process of describing specific exemplary embodiments of this disclosure. Attached Figure Description

[0010] The above and other aspects, features and advantages of this disclosure will become clearer from the following detailed description, taken in conjunction with the accompanying drawings, wherein the same reference numerals (when used) denote corresponding elements in multiple figures, wherein:

[0011] Figure 1 and Figure 2 This is a simplified schematic diagram of a semiconductor device according to an example embodiment of the present disclosure;

[0012] Figure 3 This is a simplified schematic diagram illustrating a subword line driver according to an exemplary embodiment of the present disclosure;

[0013] Figure 4 This is a schematic plan view illustrating the element regions according to an exemplary embodiment of the present disclosure;

[0014] Figure 5AIt shows along Figure 4 A schematic cross-sectional view of the section taken along line I-I'.

[0015] Figure 5B It shows along Figure 4 A schematic cross-sectional view of the section taken along line II-II'.

[0016] Figures 6 to 11 This is a schematic diagram showing a cross-section of the gate structure of a semiconductor device according to an exemplary embodiment of the present disclosure;

[0017] Figure 12 This is a schematic plan view illustrating the element regions according to an exemplary embodiment of the present disclosure;

[0018] Figures 13 to 16 It shows along Figure 12 A schematic cross-sectional view of the section taken along line III-III'; and

[0019] Figures 17A to 20B This is a schematic diagram illustrating an intermediate process in a method of manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0020] In the following description, exemplary embodiments of the present disclosure will be illustrated with reference to the accompanying drawings.

[0021] Figure 1 and Figure 2 This is a diagram that simply illustrates a semiconductor device according to an example embodiment of the present disclosure.

[0022] first, Figure 1 This is a block diagram illustrating the structure of a semiconductor device according to an exemplary embodiment of the present disclosure. The semiconductor device according to the exemplary embodiment of the present disclosure may be a dynamic random access memory (DRAM). Figure 1 In the example embodiment shown, semiconductor device 1 may include line decoder 20, PXI generator 22, connection circuit 42, word line drive circuit 32, cell array 10, and sense amplifier circuit 12.

[0023] The line decoder 20 can respond to the upper line addresses RA2 to RA8 (MRADD) received from the outside, decode the upper line address MRADD, and select the word line corresponding to the upper line address MRADD from the word lines WL.

[0024] In other words, the line decoder 20 can determine the selected word line from the word lines WL in response to the upper line address MRADD. For example, the line decoder 20 can output a word line enable signal NWEI to the corresponding word line driver circuit 32 (e.g., NWEI...). <0> The line decoder 20 includes logic gates, which can be formed from semiconductor elements. For example, the logic gates can be formed from p-channel metal-oxide-semiconductor (PMOS) transistors and / or n-channel metal-oxide-semiconductor (NMOS) transistors.

[0025] PXI generator 22 can output a pre-decoding signal PXI (e.g., PXI) in response to the lower row address LRADD (e.g., RA0 to RA1). <0> To PXI <3> For example, PXI generator 22 can decode the lower row address LRADD in the row address input from the outside and can generate a pre-decoding signal PXI corresponding to the selected word line. The pre-decoding signal PXI can be input to the drive signal generators 40 and 50 included in the connection circuit 42.

[0026] Drive signal generators 40 and 50 can generate a drive signal PXID (e.g., PXID) for driving word line WL in response to the pre-decoding signal PXI. <0> To PXID <3> ) and PXIB (e.g., PXIB <0> To PXIB <3> For example, drive signal generators 40 and 50 may include pull-up circuits that can raise drive signals PXID and PXIB to a predetermined voltage level. Drive signals PXID and PXIB can be output to the sub-word line driver SWD included in word line drive circuit 32.

[0027] Semiconductor device 1 may include a memory cell region and a peripheral circuit region surrounding (e.g., enclosing) the memory cell region. The memory cell region may be a region where memory cells for data storage are disposed. The peripheral circuit region may be a region where word line drivers, sense amplifiers, row decoders, column decoders, and control circuitry are disposed.

[0028] The sub-word line driver SWD can activate a selected word line in response to a word line enable signal NWEI and drive signals PXID and PXIB, and can perform a pre-charge operation. For example, drive signal generators 40 and 50 can increase the level of a first drive signal PXID input to the sub-word line driver SWD connected to the selected word line from a first voltage to a second voltage, the second voltage being higher than the first voltage, and can set the level of the second drive signal PXIB to the first voltage. The term “connection” (or “connected to” or similar terms such as “contact” or “in contact with”) as used herein is intended to refer to a physical and / or electrical connection between two or more elements and may include other intermediate elements. The term “and / or” as used herein includes any and all combinations of one or more of the associated listed items. A sub-word line driver SWD receiving a first drive signal PXID with a second voltage and a second drive signal PXIB with a first voltage can input the first drive signal PXID to the selected word line.

[0029] Simultaneously, the unselected word line driver SWD connected to one or more unselected word lines not selected by the word line enable signal NWEI can input a predetermined voltage to the unselected word line. In an example embodiment, the voltage input to the unselected word line can be lower than a second voltage. For example, the voltage input to the unselected word line can be a negative constant voltage below 0 volts (V).

[0030] In cell array 10, memory cells MC can be connected to word lines WL and bit lines BL. Each memory cell MC may include a storage capacitor and a switching element. This will be referred to below. Figure 2 To describe in more detail.

[0031] Reference Figure 2 It shows Figure 1 As a part of the semiconductor device 1 shown, each memory cell MC may include a storage capacitor CC and a switching element SW connected to the storage capacitor CC. The control terminal of the switching element SW may be connected to the corresponding word line among multiple word lines WL0 to WLn (where n is a natural number), and the first input terminal of the switching element SW may be connected to the corresponding bit lines among multiple bit lines BL0 to BLm and BL0B to BLmB (where m is a natural number). The second input terminal of the switching element SW may be connected to the storage capacitor CC. The word lines WL0 to WLn may be connected to the sub-word line driver SWD, and the bit lines BL0 to BLm and BL0B to BLmB may be connected to the sense amplifier BLSA.

[0032] Semiconductor devices are a crucial part of the electronics industry. Both storage devices for storing data and processors for processing data can be implemented using semiconductor devices. FinFET devices are used to improve integration, and research on FinFET devices capable of operating under high voltage conditions is actively underway. However, there are concerns about potential reliability degradation in FinFET devices operating under high voltage.

[0033] A semiconductor device according to an exemplary embodiment of this disclosure may include a plurality of semiconductor elements. In an exemplary embodiment, the plurality of semiconductor elements may be FINFET elements. Some of the plurality of semiconductor elements may be operable by receiving a relatively high voltage. A relatively high voltage may refer to a voltage of 3V or higher applied between the source and drain regions. For example, a sense amplifier may include semiconductor elements that operate by receiving a relatively low voltage, and a sub-word line driver may include semiconductor elements that operate by receiving a relatively high voltage.

[0034] A semiconductor device according to embodiments of the present disclosure may include at least one semiconductor element, wherein the source region and the drain region have different structures. Different structures may mean that the source region and the drain region do not have substantially the same structure. In embodiments, a semiconductor element receiving a relatively high voltage may have different structures in its source region and drain region.

[0035] The source and drain regions of a semiconductor device can be formed with different structures to reduce the electric field around the area where the gate structure and drain regions overlap in the vertical direction. As used herein, "element A and element B overlap in the X direction" (or similar language) means that there is at least one line extending along the X direction and intersecting both elements A and B. Specifically, the electric field can be reduced in the lateral (i.e., horizontal) direction. Because the source and drain regions have different structures, the peak value of the electric field formed in the path of charge moving from the source region to the drain region can be minimized. Accordingly, semiconductor devices with improved HCI and GIDL characteristics can be provided, and consequently, the reliability of the semiconductor device can be improved.

[0036] Figure 3 This is a simplified schematic diagram illustrating a subword line driver according to an exemplary embodiment of the present disclosure.

[0037] Reference Figure 3The sub-word line driver SWD may include a PMOS transistor 60, a first NMOS transistor 70, and a second NMOS transistor 80. The source of the PMOS transistor 60 can be connected to a first drive signal PXID, its gate can be connected to a word line enable signal NWEI, and its drain can be connected to the word line WL. The source of the first NMOS transistor 70 can be connected to a back bias voltage VBB, its gate can be connected to the word line enable signal NWEI, and its drain can be connected to the word line WL. The gate of the second NMOS transistor 80 can be connected to a second drive signal PXIB, its source can be connected to the back bias voltage VBB, and its drain can be connected to the word line WL.

[0038] The word line enable signal NWEI can be a signal generated at a ground voltage level in response to the word line enable signal NWEI activated at a boost voltage level. The sub-word line WL can have a boost voltage level in response to the sub-word line enable signal NWEI at a ground voltage level and the first drive signal PXID at a boost voltage level. During pre-charge operation, the sub-word line WL can have a back bias voltage VBB level in response to the sub-word line enable signal NWEI at a boost voltage level and the second drive signal PXIB.

[0039] In the exemplary embodiments of this disclosure, at least one of the PMOS transistor 60, the first NMOS transistor 70, and the second NMOS transistor 80, which are semiconductor elements included in the sub-word line driver SWD, may be a FINFET transistor. In this specification, the semiconductor element comprising a FINFET is used as an example, but this disclosure is not limited thereto. The structural and arrangement relationships of the source and drain regions described below can also be applied to planar elements or gate-all-around (GAA) elements, etc.

[0040] In the exemplary embodiments of this disclosure, the source and drain regions of a FINFET element can be formed with different structures. Forming different structures for the source and drain regions of a FINFET element reduces the peak electric field around the area where the gate structure and drain region overlap. Because the source and drain regions of the semiconductor element have different structures, semiconductor elements with improved HCI and GIDL characteristics can be provided, thereby improving the reliability of the semiconductor element.

[0041] Figure 4 This is a schematic plan view simply illustrating the element areas according to an example embodiment of the present disclosure.

[0042] Reference Figure 4The semiconductor device according to an example embodiment of the present disclosure may include a first element region 100a and a second element region 100b in a peripheral circuit region. The first element region 100a and the second element region 100b may respectively include an NMOS region and / or a PMOS region. In an embodiment, the first element region 100a may include a semiconductor element driven by receiving a relatively high voltage, and the second element region 100b may include a semiconductor element driven by receiving a relatively low voltage.

[0043] The first element region 100a may include a first semiconductor element 170a and a second semiconductor element 180a. In an embodiment, the first semiconductor element 170a and the second semiconductor element 180a may be included in a sub-word line driver. (See also...) Figure 3 As an example, the first semiconductor element 170a may be the first NMOS transistor 70 of the sub-word line driver SWD, and the second semiconductor element 180a may be the second NMOS transistor 80 of the sub-word line driver SWD. Each of the first semiconductor element 170a and the second semiconductor element 180a may include a source region 120a and may share a drain region 130a.

[0044] The second element region 100b may include a third semiconductor element 170b and a fourth semiconductor element 180b. In an example embodiment, the third semiconductor element 170b and the fourth semiconductor element 180b may be included in a sense amplifier. (See also...) Figure 2 As an example, a sensing amplifier BLSA that operates by receiving a relatively low voltage can be set in the second element region 100b.

[0045] The first element region 100a and the second element region 100b may include substrates 103a and 103b having multiple fin structures 105a and 105b, active regions disposed on substrates 103a and 103b to provide source regions 120a and 120b and drain regions 130a and 130b, and gate structures 110a and 110b disposed between the active regions and extending to intersect with the multiple fin structures 105a and 105b. The active regions may be formed of silicon (Si) and may be doped with, for example, N-type impurities such as phosphorus (P), nitrogen (N), arsenic (As), or antimony (Sb).

[0046] Substrates 103a and 103b may be substrates for fabricating semiconductor devices and may include well regions. Substrates 103a and 103b may have recessed regions partially removed from their upper surfaces. Substrates 103a and 103b may be provided, for example, as bulk wafers, epitaxial layers, silicon-on-insulator (SOI) layers, or semiconductor-on-insulator (SeOI) layers. Substrates 103a and 103b may include semiconductor materials, such as group IV semiconductors, group III-V compound semiconductors, or group II-VI compound semiconductors. For example, group IV semiconductors may include silicon, germanium, or silicon-germanium. Substrates 103a and 103b may include impurities of a first conductivity type, such as p-type impurities, but this disclosure is not limited thereto.

[0047] The first element region 100a and the second element region 100b may include a plurality of fin structures 105a and 105b extending along a first direction (X-axis direction) on substrates 103a and 103b, and gate structures 110a and 110b extending along a second direction (Y-axis direction) to intersect with the plurality of fin structures 105a and 105b. The plurality of fin structures 105a and 105b may be formed to protrude from the upper surface of substrates 103a and 103b and may have a fin shape.

[0048] The active region may include a substrate active region and multiple fin structures 105a and 105b. The multiple fin structures 105a and 105b may include impurities. The multiple fin structures 105a and 105b may be separated by corresponding device isolation films 107a and 107b in the substrate and may extend along a first direction (X-axis direction). The multiple fin structures 105a and 105b may be spaced apart from the device isolation films 107a and 107b in a second direction (Y-axis direction). Adjacent fin structures 105a may be spaced apart by device isolation films 107a in the second direction (Y-axis direction), and adjacent fin structures 105b may be spaced apart by device isolation films 107b in the second direction (Y-axis direction). The device isolation films 107a and 107b may include insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.

[0049] To form source regions 120a and 120b and drain regions 130a and 130b, portions of multiple fin structures 105a and 105b on both sides of gate structures 110a and 110b can be removed. Selective epitaxial growth (SEG) can be applied starting from the remaining portions of the multiple fin structures 105a and 105b to form source regions 120a and 120b and drain regions 130a and 130b.

[0050] Gate structures 110a and 110b may extend along a second direction (Y-axis direction) and may intersect with a plurality of fin structures 105a and 105b extending along a first direction (X-axis direction, intersecting the second direction). Each of gate structures 110a and 110b may respectively include gate metal layers 112a and 112b, and gate spacers 113a and 113b. Gate spacers 113a and 113b may be formed on each side surface of gate metal layers 112a and 112b.

[0051] Figure 5A It shows along Figure 4 A schematic cross-sectional view of the section intercepted by line I-I'.

[0052] Reference Figure 5A The first element region 100a may include a substrate 103a, a plurality of fin structures 105a extending on the substrate 103a along a first direction (X-axis direction), and a gate structure 110a extending on the plurality of fin structures 105a along a second direction (Y-axis direction). In an example embodiment, the first element region 100a may be included in a sub-word line driver. The gate structures 110a on the plurality of fin structures 105a may extend along the second direction (Y-axis direction). The gate structures 110a may be spaced apart from each other in the first direction (X-axis direction), with active regions interposed therebetween. For example, transistors may be formed in the regions where the gate structures 110a and the plurality of fin structures 105a intersect.

[0053] The gate structure 110a may include a gate insulating layer 111a, a gate metal layer 112a, and a gate spacer 113a. The gate insulating layer 111a may be disposed between the gate metal layer 112a and the plurality of fin structures 105a. The gate spacer 113a, formed of insulating material, may be disposed on the opposite side surface of the gate metal layer 112a, and an active region extending along a first direction (X-axis direction) may be disposed outside the gate spacer 113a.

[0054] The active region can provide a source region 120a and a drain region 130a for a semiconductor element, and can have an elevated source / drain configuration, wherein the upper surface of the substrate 103a, which serves as a reference layer, is higher than the lower surface of the gate structure 110a in a third direction (Z-axis direction) relative to the surface (e.g., the lower surface). Figures 5A to 11 In the example embodiment shown, the active region is depicted as having a rectangular shape, but the active region can have various shapes, including, for example, a polygonal shape and a circular shape. The active region can have a structure in which the active regions are connected to or merged onto three fin structures 105a. The number of fin structures 105a connected to each other in an active region can be varied.

[0055] When the semiconductor device is an NMOS transistor, the fin structure 105a and the active region may include silicon (Si). The active region may include a source region 120a and a drain region 130a. The source region 120a and the drain region 130a may be regions epitaxially grown from the fin structure 105a. According to an example embodiment, the source region 120a and the drain region 130a may be doped with a first conductivity type impurity and may have different doping concentrations. For example, the first conductivity type impurity may be an N-type impurity, and the doping concentration of the drain region 130a may be lower than that of the source region 120a.

[0056] As described above, the first element region 100a according to an exemplary embodiment of this disclosure may include a FINFET element to improve integration. However, due to concerns that the HCI and GIDL characteristics, which affect element reliability, may deteriorate in a FINFET element that operates by receiving relatively high voltages, the source region 120a and drain region 130a of the FINFET element may have different structures.

[0057] Different structures can indicate that the source region 120a and drain region 130a do not have essentially the same characteristics (e.g., size, shape, doping concentration, etc.). For example, refer to Figure 5A In the third direction (Z-axis direction), relative to the surface of the substrate 103a, the lower surface of the drain region 130a can be set higher than the lower surface of the source region 120a. In other words, the shortest distance between the lower surface of the gate structure 110a and the lower surface of the drain region 130a can be less than the shortest distance between the lower surface of the gate structure 110a and the lower surface of the source region 120a.

[0058] The source region 120a and drain region 130a of the semiconductor device can be formed with different structures, thereby reducing the peak electric field around the region where the gate structure 110a and drain region 130a overlap in the third direction (Z-axis direction). Accordingly, a semiconductor device with improved HCI and GIDL characteristics can be provided, thereby improving the reliability of the semiconductor device.

[0059] Figure 5B It shows along Figure 4 A schematic cross-sectional view of the section cut by line II-II'.

[0060] Reference Figure 5B The second element region 100b may include a substrate 103b, a plurality of fin structures 105b extending on the substrate 103b along a first direction (X-axis direction), and a gate structure 110b extending along a second direction (Y-axis direction). In an example embodiment, the second element region 100b may be included in a sense amplifier.

[0061] The gate structure 110b may include a gate insulating layer 111b, a gate metal layer 112b, and a gate spacer 113b. The gate insulating layer 111b may be disposed between the gate metal layer 112b and a plurality of fin structures 105b. The gate spacer 113b is formed of an insulating material and may be disposed on opposite side surfaces of the gate metal layer 112b, and an active region extending along a first direction (X-axis direction) may be disposed outside the gate spacer 113b. The active region may provide a source region 120b and a drain region 130b for a semiconductor element, and may have a raised source / drain configuration, wherein the upper surface of the substrate 103b, which serves as a reference layer, is higher than the lower surface of the gate structure 110b in a third direction (Z-axis direction).

[0062] Refer to together Figure 4 , Figure 5A and Figure 5B The first element region 100a may include a semiconductor element driven by receiving a relatively high voltage, and the second element region 100b may include a semiconductor element driven by receiving a relatively low voltage. For example, the first element region 100a may be included in a sub-word line driver, and the second element region 100b may be included in a sense amplifier.

[0063] The thickness of the gate insulating layer 111a included in the first element region 100a in the third direction (Z-axis direction) can be greater than the thickness of the gate insulating layer 111b included in the second element region 100b in the third direction. Since a semiconductor device operating by receiving a relatively high voltage may require a relatively high breakdown voltage, the semiconductor device may include a relatively thick gate insulating layer 111a. Conversely, since a semiconductor device operating by receiving a relatively low voltage may not require a relatively high breakdown voltage, the semiconductor device may include a relatively thin gate insulating layer 111b. Accordingly, the thickness of the gate insulating layer 111a included in the first element region 100a where a relatively high voltage is applied in the third direction (Z-axis direction) can be greater than the thickness of the gate insulating layer 111b included in the second element region 100b where a relatively low voltage is applied in the third direction.

[0064] Simultaneously refer to Figure 5A and Figure 5BThe source region 120a and drain region 130a included in the first element region 100a may have different characteristics (e.g., size, shape, doping concentration, etc.), and the source region 120b and drain region 130b included in the second element region 100b may have substantially the same characteristics. In an example embodiment, the different characteristics of the source region 120a and drain region 130a in the first element region 100a can be manifested in that the lower surface of the drain region 130a is higher than the lower surface of the source region 120a in the third direction (Z-axis direction).

[0065] In the first element region 100a, which operates by receiving a relatively high voltage, there may be concerns about the potential degradation of HCI and GIDL characteristics, which affect element reliability. Therefore, the first element region 100a can be intentionally formed such that the source region 120a and the drain region 130a have different structures. Meanwhile, in the second element region 100b, which operates by receiving a relatively low voltage, the source region 120b and the drain region 130b may not have different structures.

[0066] Figures 6 to 11 This is a schematic diagram simply illustrating a cross-section of at least a portion of a semiconductor device according to an exemplary embodiment of the present disclosure.

[0067] In exemplary embodiments of this disclosure, the semiconductor device may include a memory cell array region and a peripheral circuit region. The peripheral circuit region may include a first semiconductor element 200 and a second semiconductor element. Each of the first semiconductor element 200 and the second semiconductor element may include a substrate 203, a fin structure 205 extending on the substrate 203 along a first direction (X-axis direction), a gate structure 210 extending on the fin structure 205 along a second direction (Y-axis direction), a source region 220, and a drain region 230.

[0068] The first semiconductor element 200 can be an element that operates by receiving a relatively high voltage, and the second semiconductor element can be an element that operates by receiving a relatively low voltage. The source and drain regions included in the first semiconductor element 200 can have different structures. For example, refer to... Figures 6 to 8 The lower surface of the drain region 230 may be higher than the lower surface of the source region 220 in the third direction (Z-axis direction). Meanwhile, the source and drain regions included in the second semiconductor element may have substantially the same structure based on the gate structure.

[0069] Reference Figure 6In the first semiconductor element 200, active regions, including source region 220 and drain region 230, can be formed on opposite sides of the fin structure 205 centered on the gate structure 210. The active regions, including source region 220 and drain region 230, can be formed by removing the fin structure 205 and performing an epitaxial growth process. In an example embodiment, the etching process and the epitaxial growth process for forming the fin structure 205 of the source region 220 and drain region 230 can be performed separately.

[0070] The first semiconductor element 200 may include a source region 220. In a third direction (Z-axis direction), the source region 220 may include a region extending downward from the lower surface of the gate structure 210. The source region 220 may include a region protruding along a first direction (X-axis direction) into the region extending downward from the lower surface of the gate structure 210. In a third direction (Z-axis direction), the source region 220 may include a region extending upward from the lower surface of the gate structure 210, and may overlap with the gate structure 210 in that region.

[0071] The first semiconductor element 200 may include a drain region 230. In the third direction (Z-axis direction), the drain region 230 may include a region extending downward from the lower surface of the gate structure 210. In the third direction (Z-axis direction), the drain region 230 may have a region extending upward from the lower surface of the gate structure 210, and may overlap with the gate structure 210 in this region. The source region 220 and the drain region 230 may be included in a portion of the lower part of the gate structure 210, in which the source region 220 and the drain region 230 face each other, and the fin structure 205 is interposed therebetween.

[0072] Reference Figure 6 According to an exemplary embodiment of this disclosure, the shortest distances from the source region 220 and the drain region 230 in the first semiconductor element 200 to the gate structure 210 in the first direction (X-axis direction) may be different. The shortest distance p2 between the gate structure 210 and the drain region 230 in the first direction (X-axis direction) may be greater than the shortest distance p1 between the gate structure 210 and the source region 220 in the first direction (X-axis direction). By removing the fin structure 205 to form the source region 220 and the drain region 230, the source region 220 may be formed as a region protruding below the gate structure 210 along the first direction (X-axis direction), which is different from the drain region 230, and the shortest distance p1 between the gate structure 210 and the source region 220 in the first direction (X-axis direction) may be less than the shortest distance p2 between the gate structure 210 and the drain region 230 in the first direction (X-axis direction).

[0073] Reference Figure 6In the third direction (Z-axis direction), the lower surface of the drain region 230 may be higher than the lower surface of the source region 220 relative to the surface of the substrate 103 serving as the reference layer. The shortest distance d2 between the lower surface of the gate structure 210 and the lower surface of the drain region 230 in the third direction (Z-axis direction) may be less than the shortest distance d1 between the lower surface of the gate structure 210 and the lower surface of the source region 220 in the third direction (Z-axis direction). By removing each fin structure 205 to form the source region 220 and the drain region 230, the lower surface of the drain region 230 may be higher than the lower surface of the source region 220 in the third direction (Z-axis direction), and the shortest distance d1 between the lower surface of the gate structure 210 and the lower surface of the source region 220 and the shortest distance d2 between the lower surface of the gate structure 210 and the lower surface of the drain region 230 in the third direction may be different from each other.

[0074] In the exemplary embodiments of this disclosure, the epitaxial growth processes forming the source region 220 and the drain region 230 can be performed separately. By performing the epitaxial growth processes separately, the thickness h1 of the source region 220 and the thickness h2 of the drain region 230 in the third direction (Z-axis direction) can be different from each other. For example, the thickness h2 of the drain region 230 can be smaller than the thickness h1 of the source region 220. Since the removal process of the fin structure 205 and the epitaxial growth process are performed separately, the lower surface of the source region 220 can be lower than the lower surface of the drain region 230 in the third direction (Z-axis direction) relative to the surface of the substrate 103, and the positions of the upper surfaces of the source region 220 and the drain region 230 can be substantially the same, that is, the upper surfaces of the source region 220 and the drain region 230 can be horizontally coplanar.

[0075] In the exemplary embodiments of this disclosure, the source region 220 and drain region 230 included in the first semiconductor element 200 may have different structures in a first direction (X-axis direction) and a third direction (Z-axis direction). Compared to a second semiconductor element with substantially the same structure for its source and drain regions, the first semiconductor element 200, with its source and drain regions having different structures, can reduce the electric field around the region where the gate structure 210 and the drain region 230 overlap. Because the source and drain regions 220 and 230 of the first semiconductor element 200 form different structures, a first semiconductor element 200 with improved characteristics (such as HCI and GIDL) can be provided, thereby improving the reliability of the first semiconductor element 200 when a relatively high voltage is applied.

[0076] In exemplary embodiments of this disclosure, the semiconductor device may include a memory cell array region and a peripheral circuit region. The peripheral circuit region may include a first semiconductor element 200a and a second semiconductor element. The first semiconductor element 200a may be an element that operates by receiving a relatively high voltage, and the source region 220a and drain region 230a included in the first semiconductor element 200a may have different structures.

[0077] Reference Figure 7 The first semiconductor element 200a may include a substrate 203a, a fin structure 205a extending on the substrate 203a in a first direction (X-axis direction), a gate structure 210a extending on the fin structure 205a in a second direction (Y-axis direction), and a source region 220a and a drain region 230a formed on opposite sides of the fin structure 205a in the substrate 203a.

[0078] The source region 220a included in the first semiconductor element 200a can be formed by removing the fin structure 205a and performing an epitaxial growth process. In the third direction (Z-axis direction), the source region 220a may include a region extending downward from the lower surface of the gate structure 210a. The source region 220a may include a region protruding along a first direction (X-axis direction) into the region extending downward from the lower surface of the gate structure 210a (i.e., below the gate structure 210a). In the third direction (Z-axis direction), the source region 220a may have a region extending upward from the lower surface of the gate structure 210a, and may overlap with the gate structure 210a in this region.

[0079] The drain region 230a included in the first semiconductor element 200a can be formed by removing the fin structure 205a and performing an epitaxial growth process. In the third direction (Z-axis direction), the drain region 230a may include a region extending downward from the lower surface of the gate structure 210a. In the third direction (Z-axis direction), the drain region 230a has a region extending upward from the lower surface of the gate structure 210a, and may overlap with the gate structure 210a in this region. The source region 220a and the drain region 230a may be included in a portion of the lower part of the gate structure 210a, in which the source region 220a and the drain region 230a face each other, and the fin structure 205a is interposed therebetween.

[0080] Reference Figure 7According to an exemplary embodiment of this disclosure, the source region 220a and drain region 230a included in the first semiconductor element 200a may have different shortest distances from the gate structure 210a in the first direction (X-axis direction). The shortest distance p4 between the gate structure 210a and the drain region 230a in the first direction (X-axis direction) may be greater than the shortest distance p3 between the gate structure 210a and the source region 220a in the first direction (X-axis direction). By removing the fin structures 205a used to form the source region 220a and the drain region 230a respectively, the source region 220a may have a protruding region in the first direction (X-axis direction), and the shortest distance p4 between the drain region 230a and the gate structure 210a in the first direction (X-axis direction) may be greater than the shortest distance p3 between the source region 220a and the gate structure 210a.

[0081] Reference Figure 7 The lower surface of the drain region 230a can be higher than the lower surface of the source region 220a in the third direction (Z-axis direction). In other words, the shortest distance d4 between the lower surface of the gate structure 210a and the lower surface of the drain region 230a in the third direction (Z-axis direction) can be less than the shortest distance d3 between the lower surface of the gate structure 210a and the lower surface of the source region 220a.

[0082] Simultaneously, the epitaxial growth processes for forming the source region 220a and drain region 230a of the first semiconductor element 200a can be performed concurrently. Since the epitaxial growth processes are performed simultaneously, the thickness h3 of the source region 220a and the thickness h4 of the drain region 230a in the third direction (Z-axis direction) can be substantially the same. In this embodiment, when the widths of the source region 220a and the drain region 230a in the first direction (X-axis direction) are substantially the same, the sizes (i.e., areas) of the source region 220a and the drain region 230a can be substantially the same.

[0083] In the exemplary embodiments of this disclosure, the upper and lower surfaces of the source region 220a and drain region 230a of the first semiconductor element 200a may be positioned differently in the third direction (Z-axis direction). For example, the positions of the upper and lower surfaces of the drain region 230a may be further elevated in the third direction than the positions of the upper and lower surfaces of the source region 220a. The source region 220a and drain region 230a of the first semiconductor element 200a may have a structure in which the source region 220a and drain region 230a are positioned differently in the third direction (Z-axis direction) based on the gate structure 210a.

[0084] In the exemplary embodiments of this disclosure, the source region 220a and drain region 230a included in the first semiconductor element 200a may have different structures, thereby reducing the electric field around the region where the gate structure 210a and the drain region 230a overlap. Because the source region 220a and drain region 230a of the first semiconductor element 200a have different structures, the first semiconductor element 200a has improved characteristics (such as HCI and GIDL), thereby improving the reliability of the first semiconductor element 200a operating by receiving relatively high voltages.

[0085] In exemplary embodiments of this disclosure, the semiconductor device may include a memory cell array region and a peripheral circuit region. The peripheral circuit region may include a first semiconductor element 200b and a second semiconductor element. The first semiconductor element 200b may be an element that operates by receiving a relatively high voltage, and the source region 220b and drain region 230b included in the first semiconductor element 200b may have different structures.

[0086] Reference Figure 8 The first semiconductor element 200b may include a substrate 203b, a fin structure 205b extending on the substrate 203b in a first direction (X-axis direction), a gate structure 210b extending on the fin structure 205b in a second direction (Y-axis direction), and a source region 220b and a drain region 230b formed on opposite sides of the fin structure 205b in the substrate 203b.

[0087] Reference Figure 8 The first semiconductor element 200b may include a source region 220b. In a third direction (Z-axis direction), the source region 220b may include a region extending downward from the lower surface of the gate structure 210b. The source region 220b may include a region protruding along a first direction (X-axis direction) into the region extending downward from the lower surface of the gate structure 210b. In a third direction (Z-axis direction), the source region 220b may have a region extending upward from the lower surface of the gate structure 210b, and may overlap with the gate structure 210b in that region.

[0088] The first semiconductor element 200b may include a drain region 230b. In the third direction (Z-axis direction), the drain region 230b may include a region extending downward from the lower surface of the gate structure 210b. In the third direction (Z-axis direction), the drain region 230b may have a region extending upward from the lower surface of the gate structure 210b, and may overlap with the gate structure 210b in this region. The source region 220b and the drain region 230b may be included in a portion of the lower part of the gate structure 210b, in which the source region 220b and the drain region 230b face each other, and the fin structure 205b is interposed therebetween.

[0089] Reference Figure 8 The drain region may include a first drain region 230b and a second drain region 235b disposed between the first drain region 230b and the gate structure 210b. The second drain region 235b may be configured near the lower corner of the gate structure 210b and adjacent to the side of the first drain region 230b facing the gate structure 210b. The doping concentration of the second drain region 235b may be lower than that of the first drain region 230b. For example, the second drain region 235b may be a lightly doped drain (LDD) region. To form the second drain region 235b, a pad oxide pattern and a mask pattern may be formed on the source region 220b. According to an example embodiment, the pad oxide pattern may be a layer provided to protect the source region 220b and may be omitted. The mask pattern is a mask layer used for patterning semiconductor elements and may include silicon nitride and carbon-containing materials. The mask pattern may have multiple layers.

[0090] Reference Figure 8 The first drain region 230b and the second drain region 235b included in the first semiconductor element 200b may have a different structure than the source region 220b. The drain regions 230b and 235b may include the first drain region 230b and the second drain region 235b, and the source region 220b may include a region protruding along a first direction (X-axis direction) in the lower part of the gate structure 210b. Specifically, the drain region may include the second drain region 235b, thereby reducing the electric field around the region where the gate structure 210b and the drain regions 230b and 235b overlap. Because the source region 220b and the drain regions 230b and 235b of the first semiconductor element 200b have different structures, a semiconductor element with improved characteristics (such as HCI and GIDL) can be provided, thereby improving the reliability of the first semiconductor element 200b.

[0091] In exemplary embodiments of this disclosure, the semiconductor device may include a memory cell array region and a peripheral circuit region. The peripheral circuit region may include a first semiconductor element 300 and a second semiconductor element. The first semiconductor element 300 may be an element that operates by receiving a relatively high voltage, and the source region 320 and drain region 330 included in the first semiconductor element 300 may have different structures.

[0092] Reference Figure 9 The first semiconductor element 300 may include a substrate 303, a fin structure 305 extending on the substrate 303 along a first direction (X-axis direction), a gate structure 310 extending on the fin structure 305 along a second direction (Y-axis direction), and a source region 320 and a drain region 330 formed in the substrate 303 on opposite sides of the fin structure 305. The source region 320 and the drain region 330 may be doped with impurities of a first conductivity type.

[0093] The source region 320 included in the first semiconductor element 300 can be formed by removing the fin structure 305 and performing an epitaxial growth process thereon. In the third direction (Z-axis direction), the source region 320 may include a region extending downward from the lower surface of the gate structure 310. However, the source region 320 is not limited thereto; in some embodiments (not explicitly shown), the source region 320 may include a region protruding in the lower surface of the gate structure 310 along a first direction (X-axis direction). In the third direction (Z-axis direction), the source region 320 may have a region extending upward from the lower surface of the gate structure 310 and may overlap with the gate structure 310 in this region.

[0094] The drain region 330 included in the first semiconductor element 300 can be formed by implanting ions into the fin structure 305. For example, the drain region 330 can be formed by implanting a first conductivity type impurity into the fin structure 305. The drain region 330 may include a region extending downward from the lower surface of the gate structure 310 along a third direction (Z-axis direction). The source region 320 and the drain region 330 may be included in a portion of the lower part of the gate structure 310, in which the source region 320 and the drain region 330 face each other, and the fin structure 305 is interposed therebetween.

[0095] In this embodiment, the upper surfaces of the drain region 330 and the source region 320 may be located differently in the third direction. Since the source region 320 is epitaxially grown after the removal of the fin structure 305, its upper surface in the third direction (Z-axis direction) may be higher than the lower surface of the gate structure 310. Since the drain region 330 does not have the fin structure 305 removed, its upper surface may be substantially the same as the lower surface of the gate structure 310 relative to the surface of the substrate 303, which serves as the reference layer. Accordingly, its upper surface in the third direction (Z-axis direction) may be lower than the upper surface of the source region 320.

[0096] In this embodiment, the drain region 330 may be doped at least once with a first conductivity type impurity. The drain region 330 can be doped at least once by changing at least one of the energy, concentration, and angle of the injected first conductivity type impurity. The first conductivity type impurity can be injected into the drain region 330 multiple times with different energies, concentrations, and angles, thereby reducing the electric field around the area where the gate structure 310 and the drain region 330 overlap.

[0097] Reference Figure 9 The source region 320 and drain region 330 included in the first semiconductor element 300 can have different structures, such as whether the fin structure 305 is removed, and the position of its upper surface in the third direction (Z-axis direction). The source region 320 and drain region 330 can have different structures, thereby reducing the electric field around the area where the gate structure 310 and drain region 330 overlap. Because the source region 320 and drain region 330 of the first semiconductor element 300 have different structures, a semiconductor element with improved characteristics (such as HCI and GIDL) can be provided, thereby improving the reliability of the first semiconductor element 300.

[0098] In exemplary embodiments of this disclosure, the semiconductor device may include a memory cell array region and a peripheral circuit region. The peripheral circuit region may include a first semiconductor element 300a and a second semiconductor element. The first semiconductor element 300a may be an element that operates by receiving a relatively high voltage, and the source region 320a and drain region 330a included in the first semiconductor element 300a may have different structures.

[0099] Reference Figure 10The first semiconductor element 300a may include a substrate 303a, a fin structure 305a extending on the substrate 303a in a first direction (X-axis direction), a gate structure 310a extending on the fin structure 305a in a second direction (Y-axis direction), and a source region 320a and a drain region 330a formed on opposite sides of the fin structure 305a in the substrate 303a.

[0100] In the exemplary embodiments of this disclosure, a source region 320a and a drain region 330a may be formed in the first semiconductor element 300a. The source region 320a may be formed by performing an epitaxial growth process after removing the fin structure 305a. The drain region 330a may be formed by directly implanting a first conductivity type impurity into the fin structure 305a without removing the fin structure 305a.

[0101] The source region 320a included in the first semiconductor element 300a can be formed by removing the fin structure 305a and performing an epitaxial growth process thereon. In the third direction (Z-axis direction), the source region 320a may include a region extending downward from the lower surface of the gate structure 310a. However, the source region 320a is not limited thereto; in an example embodiment (not explicitly shown), the source region 320a may include a region protruding into the lower surface of the gate structure 310a along a first direction (X-axis direction). In the third direction (Z-axis direction), the source region 320a may have a region extending upward from the lower surface of the gate structure 310a and may overlap with the gate structure 310a in this region.

[0102] The drain region 330a included in the first semiconductor element 300a can be formed by implanting ions into the fin structure 305a. For example, the drain region 330a can be formed by implanting a first conductivity type impurity into the fin structure 305a. The drain region 330a may include a region extending downward from the lower surface of the gate structure 310a along a third direction (Z-axis direction). The source region 320a and the drain region 330a may be included in a portion of the lower part of the gate structure 310a, in which the source region 320a and the drain region 330a face each other, and the fin structure 305a is interposed therebetween.

[0103] Reference Figure 10The first semiconductor element 300a may include an anti-doped region 331a located between the gate structure 310a and the drain region 330a. This anti-doped region 331a is doped with impurities of a first conductivity type and impurities of a second conductivity type. Anti-doping refers to the deliberate doping of impurities during the fabrication of a semiconductor element to control its electrical characteristics, and the impurities may vary depending on the type of semiconductor. To prevent the overall characteristics of the semiconductor element from deteriorating due to anti-doping, the anti-doped region 331a may be formed only in the portion between the gate structure 310a and the drain region 330a (e.g., at the lower corner of the gate structure 310a adjacent to the drain region 330a).

[0104] In an exemplary embodiment of this disclosure, a first semiconductor element 300a may be formed with an anti-doped region 331a between the gate structure 310a and the drain region 330a, such that the drain region 330a and the source region 320a may have different structures. The formation of the anti-doped region 331a increases the breakdown voltage of the first semiconductor element 300a and reduces the electric field around the overlapping area of ​​the gate structure 310a and the drain region 330a. Because the source region 320a and the drain region 330a of the first semiconductor element 300a have different structures, the semiconductor element exhibits improved characteristics (such as HCI and GIDL), thereby improving the reliability of the first semiconductor element 300a.

[0105] In exemplary embodiments of this disclosure, the semiconductor device may include a memory cell array region and a peripheral circuit region. The peripheral circuit region may include a first semiconductor element 300b and a second semiconductor element. The first semiconductor element 300b may be an element that operates by receiving a relatively high voltage, and the source region 320b and drain region 330b included in the first semiconductor element 300b may have different structures.

[0106] Reference Figure 11 The first semiconductor element 300b may include a substrate 303b, a fin structure 305b extending on the substrate 303b along a first direction (X-axis direction), a gate structure 310b extending on the fin structure 305b along a second direction (Y-axis direction), and a source region 320b and a drain region 330b formed in the substrate 303b on opposite sides of the fin structure 305b. The source region 320b and the drain region 330b may be doped with impurities of a first conductivity type.

[0107] In the exemplary embodiments of this disclosure, the source region 320b and drain region 330b included in the semiconductor element 300b can be formed separately. The source region 320a can be formed by performing an epitaxial growth process after removing the fin structure 305b. The drain region 330b can be formed by directly implanting a first conductivity type impurity into the fin structure 305a without removing the fin structure 305b.

[0108] The drain region may include a first drain region 330b and a second drain region 335b disposed between the first drain region 330b and the gate structure 310b. The second drain region 335b may be doped with a first conductivity type impurity at a lower concentration than the first drain region 330b. For example, the second drain region 335b may be a lightly doped drain (LDD) region. Furthermore, the first drain region 330b may be doped with a first conductivity impurity at a higher concentration than the second drain region 335b. The first drain region 330b may be a heavily doped drain (HDD) region.

[0109] The first drain region 330b can be doped with a relatively high concentration of a first conductive impurity, and the second drain region 335b can be doped with a relatively low concentration of the first conductive impurity, thereby reducing the electric field around the area where the gate structure 310b and the first drain region 330b overlap. Since the source region 320b of the first semiconductor element 300b has a different structure from the drain regions 330b and 335b, a semiconductor element 300b with improved characteristics (such as HCI and GIDL) can be provided, thereby improving the reliability of the first semiconductor element 300b.

[0110] Figure 12 This is a schematic plan view simply illustrating the element areas according to an example embodiment of the present disclosure.

[0111] A semiconductor device according to an exemplary embodiment of this disclosure may include a component region 400 in a peripheral circuit region. Component region 400 may include an NMOS region and / or a PMOS region. In an embodiment, component region 400 may include a semiconductor element driven by receiving a relatively high voltage.

[0112] Component region 400 may include a first semiconductor element 470 and a second semiconductor element 480. In an embodiment, the sub-word line driver may include the first semiconductor element 470 and the second semiconductor element 480. (See also...) Figure 3 As an example and in combination Figure 12 The first semiconductor element 470 may be the first NMOS transistor 70 of the sub-word line driver SWD, and the second semiconductor element 480 may be the second NMOS transistor 80 of the sub-word line driver SWD.

[0113] The element region 400 may include a substrate 403 having a plurality of fin structures 405, an active region disposed on the substrate 403 to provide a source region 420 and a drain region 430, and a gate structure 410 disposed between the active regions and extending along a second direction (Y-axis direction) to intersect with the plurality of fin structures 405. The active regions may be formed of silicon (Si) and may be doped with, for example, N-type impurities such as phosphorus (P), nitrogen (N), arsenic (As), or antimony (Sb), but the embodiments are not limited thereto.

[0114] Substrate 403 may be a substrate for fabricating semiconductor devices and may include well regions. Substrate 403 may have recessed regions partially removed from its upper surface. Substrate 403 may be provided as a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, or a semiconductor-on-insulator (SeOI) layer. Substrate 403 may include semiconductor materials such as group IV semiconductors, group III-V compound semiconductors, or group II-VI compound semiconductors. For example, group IV semiconductors may include silicon, germanium, or silicon-germanium. Substrate 403 may include a first conductive impurity (such as a p-type impurity), but this disclosure is not limited thereto.

[0115] The element region 400 may include a plurality of fin structures 405 extending on the substrate 403 along a first direction (X-axis direction) and a gate structure 410 extending along a second direction (Y-axis direction) to intersect with the plurality of fin structures 405. The plurality of fin structures 405 may be formed to protrude from the upper surface of the substrate 403 along a third direction (Z-axis direction) and may have a fin-like structure.

[0116] The active region may include a substrate active region and a plurality of fin structures 405. The plurality of fin structures 405 may include impurities. The plurality of fin structures 405 may be separated by a device isolation film 407 in the substrate and may extend along a first direction (X-axis direction). Adjacent fin structures 405 may be spaced apart from each other in a second direction (Y-axis direction) by the device isolation film 407 therebetween. The plurality of fin structures 405 may be spaced apart from the device isolation film 407 in the second direction (Y-axis direction). The device isolation film 407 may include an insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride.

[0117] To form the source region 420 and the drain region 430, multiple fin structures 405 on both sides (i.e., opposite sides) of the gate structure 410 can be removed. The source region 420 and the drain region 430 can be formed by applying a selective epitaxial growth process to the multiple removed fin structures 405.

[0118] The gate structure 410 may include a gate insulating layer and a gate metal layer 412. The gate structure 410 may extend along a second direction (Y-axis direction) and intersect with a plurality of fin structures 405 extending along a first direction (X-axis direction), the first direction intersecting the second direction. Gate spacers 413 may be formed on each side surface of the gate metal layer 412.

[0119] Figures 13 to 16 An embodiment of the present invention illustrates the following: along Figure 12 A schematic cross-sectional view of the section cut by line III-III'.

[0120] Reference Figure 13 The element region 400 may include a substrate 403, a plurality of fin structures 405 extending on the substrate 403 along a first direction (X-axis direction), and a gate structure 410 extending on the plurality of fin structures 405 along a second direction (Y-axis direction). In an embodiment, the element region 400 may include a semiconductor element driven by a relatively high voltage and may be included in a word line driver. In an embodiment, the etching processes for forming the fin structures 405 of the source region 420 and the drain region 430 may be performed simultaneously, and their epitaxial growth processes may be performed separately.

[0121] In an exemplary embodiment of this disclosure, the source region 420 may include a region extending downward from the lower surface of the gate structure 410 along a third direction (Z-axis direction). Furthermore, the source region 420 may include a region extending upward from the lower surface of the gate structure 410 along a third direction, and may overlap with the gate structure 410 in this region.

[0122] In an exemplary embodiment of this disclosure, the drain region 430 may include a region extending downward from the lower surface of the gate structure 410 along a third direction (Z-axis direction). Furthermore, the drain region 430 may include a region extending upward from the lower surface of the gate structure 410, and may overlap with the gate structure 410 in this region. Simultaneously, the width W2 of the drain region 430 in the first direction (X-axis direction) may be greater than the width W1 of the source region 420 in the first direction (X-axis direction).

[0123] In the exemplary embodiments of this disclosure, multiple fin structures 405 used to form the source region 420 and the drain region 430 can be removed simultaneously. Because multiple fin structures 405 are removed simultaneously, the shortest distance P1 between the gate structure 410 and the source region 420 and the shortest distance P2 between the gate structure 410 and the drain region 430 in the first direction (X-axis direction) can be substantially the same as each other. Furthermore, the shortest distance D1 between the lower surface of the gate structure 410 and the lower surface of the source region 420 in the third direction (Z-axis direction) and the shortest distance D2 between the lower surface of the gate structure 410 and the lower surface of the drain region 430 can be substantially the same as each other. Additionally, the lower surfaces of the source region 420 and the drain region 430 can be substantially the same as each other in the third direction.

[0124] Simultaneously, epitaxial growth processes for forming the source region 420 and drain region 430 included in the component region 400 can be performed separately. The epitaxial growth processes can be performed separately such that the thickness H1 of the source region 420 and the thickness H2 of the drain region 430 are the same in the third direction (Z-axis direction). Furthermore, the upper surfaces of the source region 420 and the drain region 430 can be substantially the same in the third direction (Z-axis direction). However, since the width W2 of the drain region 430 in the first direction (X-axis direction) can be greater than the width W1 of the source region 420, the sizes of the source region 420 and the drain region 430 can be different. For example, the size of the drain region 430 can be larger than the size of the source region 420.

[0125] Reference Figure 13 The source region 420 and drain region 430 included in the element region 400 can have different structures with different widths and different region sizes in the first direction. Because the source region 420 and drain region 430 included in the element region 400 have different structures, the electric field around the region where the gate structure 410 and drain region 430 overlap can be reduced. Because the source region 420 and drain region 430 of the semiconductor element have different structures, a semiconductor element with improved characteristics (such as HCI and GIDL) can be provided, thereby improving the reliability of the semiconductor element.

[0126] Reference Figure 14The element region 400a may include a substrate 403a, a plurality of fin structures 405a extending on the substrate 403a along a first direction (X-axis direction), and a gate structure 410a extending on the respective plurality of fin structures 405a along a second direction (Y-axis direction). In an example embodiment, the element region 400a may include a semiconductor element driven by a relatively high voltage and may be included in a word line driver. The fin structures 405a may be removed separately to form the source region 420a and the drain region 430a, and their epitaxial growth processes may be performed simultaneously.

[0127] In an exemplary embodiment of this disclosure, the source region 420a may include a region extending downward from the lower surface of the gate structure 410a along a third direction (Z-axis direction). Within the lower surface of the gate structure 410a, the source region 420a may include a region protruding along a first direction (X-axis direction) (i.e., below the gate structure 410a). Additionally, the source region 420a may include a region extending upward from the lower surface of the gate structure 410a along a third direction (Z-axis direction), and may overlap with the gate structure 410a in this region.

[0128] In an exemplary embodiment of this disclosure, the drain region 430a may include a region extending downward from the lower surface of the gate structure 410a along a third direction (Z-axis direction). Additionally, the drain region 430a may include a region extending upward from the lower surface of the gate structure 410a, and may overlap with the gate structure 410a in this region. Furthermore, the width W4 of the drain region 430a in the first direction (X-axis direction) may be greater than the width W3 of the source region 420a in the first direction (X-axis direction).

[0129] Multiple fin structures 405a used to form the source region 420a and the drain region 430a can be removed separately. Since multiple fin structures 405a are removed separately, the shortest distance P4 between the gate structure 410a and the drain region 430a in the first direction (X-axis direction) can be greater than the shortest distance P3 between the gate structure 410a and the source region 420a. Furthermore, the shortest distance D4 between the lower surfaces of the gate structure 410a and the drain region 430a in the third direction (Z-axis direction) can be less than the shortest distance D3 between the gate structure 410a and the lower surfaces of the source region 420a.

[0130] Simultaneously, the epitaxial growth processes forming the source region 420a and the drain region 430a can be performed concurrently. Since the width W4 of the drain region 430a in the first direction (X-axis direction) is wider than the width W3 of the source region 420a, when the epitaxial growth processes of the source region 420a and the drain region 430a are performed simultaneously, the thickness H4 of the drain region 430a in the third direction (Z-axis direction) can be different from the thickness H3 of the source region 420a. For example, the thickness H4 of the drain region 430a in the third direction can be smaller than the thickness H3 of the source region 420a. Even if the thickness H4 of the drain region 430a is smaller than the thickness H3 of the source region 420a, since the width W4 of the drain region 430a is wider than the width W3 of the source region 420a, the size (i.e., area or volume) of the drain region 430a can still be larger than the size of the source region 420a. In the example embodiment, the upper surfaces of the source region 420a and the drain region 430a may be substantially the same in the third-order direction.

[0131] Reference Figure 14 The source region 420a and drain region 430a included in the element region 400a can have structures with different widths and sizes. Because the source region 420a and drain region 430a have different structures, the electric field around the area where the gate structure 410a and drain region 430a overlap can be reduced. Since the source region 420a and drain region 430a of the semiconductor element have different structures, semiconductor devices with improved characteristics (such as HCI and GIDL) can be provided, thereby improving the reliability of the semiconductor element.

[0132] Reference Figure 15 The element region 400b may include a substrate 403b, a plurality of fin structures 405b extending on the substrate 403b along a first direction (X-axis direction), and a gate structure 410b extending on the plurality of fin structures 405b along a second direction (Y-axis direction). In an exemplary embodiment of this disclosure, the width W6 of the drain region 430b in the first direction (X-axis direction) may be greater than the width W5 of the source region 420b. The etching process and epitaxial growth process for forming the source region 420b and the drain region 430b may be performed separately.

[0133] In an exemplary embodiment of this disclosure, the source region 420b may include a region extending downward from the lower surface of the gate structure 410b along a third direction (Z-axis direction). Within the lower surface of the gate structure 410b, the source region 420b may include a region protruding along a first direction (X-axis direction). Furthermore, the source region 420b may include a region extending upward from the lower surface of the gate structure 410b along a third direction (Z-axis direction), and may overlap with the gate structure 410b in this region.

[0134] In an exemplary embodiment of this disclosure, the drain region 430b may include a region extending downward from the lower surface of the gate structure 410b along a third direction (Z-axis direction). Furthermore, the drain region 430b may include a region extending upward from the lower surface of the gate structure 410b, and may overlap with the gate structure 410b in this region. Simultaneously, the width W6 of the drain region 430b in the first direction (X-axis direction) may be greater than the width W5 of the source region 420b.

[0135] Since the etching processes for forming the source region 420b and the drain region 430b are performed separately, the shortest distance P6 between the gate structure 410b and the drain region 430b in the first direction (X-axis direction) can be greater than the shortest distance P5 between the gate structure 410b and the source region 420b. Furthermore, the shortest distance D6 between the lower surfaces of the gate structure 410b and the drain region 430b in the third direction (Z-axis direction) can be less than the shortest distance D5 between the gate structure 410b and the lower surfaces of the source region 420b.

[0136] Since the epitaxial growth processes for forming the source region 420b and the drain region 430b are performed separately, the thickness H6 of the drain region 430b and the thickness H5 of the source region 420b can be different in the third direction (Z-axis). For example, the thickness H6 of the drain region 430b can be less than the thickness H5 of the source region 420b. Furthermore, the upper and lower surfaces of the source region 420b and the drain region 430b can be positioned differently in the third direction (Z-axis). For example, in the third direction, the upper surface of the drain region 430b can be lower than the upper surface of the source region 420b, and the lower surface of the drain region 430b can be higher than the lower surface of the source region 420b.

[0137] Reference Figure 15 The source region 420b and drain region 430b included in the element region 400b can have structures with different widths in a first direction (X-axis direction) and different thicknesses in a third direction (Z-axis direction). Because the source region 420b and drain region 430b have different structures, the electric field around the area where the gate structure 410b and drain region 430b overlap can be reduced. Since the source region 420b and drain region 430b of the semiconductor element have different structures, a semiconductor element with improved characteristics (such as HCI and GIDL) can be provided, thereby improving the reliability of the semiconductor element.

[0138] Reference Figure 16The element region 400c may include a substrate 403c, a plurality of fin structures 405c extending on the substrate 403c along a first direction (X-axis direction), and a gate structure 410c extending along a second direction (Y-axis direction). In an example embodiment, the width W8 of the drain region 430c in the first direction (X-axis direction) may be greater than the width W7 of the source region 420c in the first direction.

[0139] In an exemplary embodiment of this disclosure, the source region 420c may include a region extending downward from the lower surface of the gate structure 410c along a third direction (Z-axis direction). Within the lower surface of the gate structure 410c, the source region 420c may include a region protruding along a first direction (X-axis direction) (i.e., partially located below the gate structure 410c). Furthermore, the source region 420c may include a region extending upward from the lower surface of the gate structure 410c along a third direction (Z-axis direction), and may overlap with the gate structure 410c in this region.

[0140] In an exemplary embodiment of this disclosure, the drain region 430c may include a region extending downward from the lower surface of the gate structure 410c along a third direction. Furthermore, the drain region 430c may include a region extending upward from the lower surface of the gate structure 410c, and may overlap with the gate structure 410c in this region. Simultaneously, the width W8 of the drain region 430c in the first direction (X-axis direction) may be greater than the width W7 of the source region 420c.

[0141] Reference Figure 16 The drain region may include a first drain region 430c and a second drain region 435c disposed between the first drain region 430c and the lower surface of the gate structure 410c. The second drain region 435c may be doped at a relatively low concentration relative to the doping concentration of the first drain region 430c. The second drain region 435c may be an LDD region.

[0142] The source region 420c and drain regions 430c and 435c included in the element region 400c according to embodiments of this disclosure may have different structures with or without LDD regions. Because the source region 420c and drain regions 430c and 435c have different structures, the electric field around the region where the gate structure 410c and drain regions 430c and 435c overlap can be reduced. Since the source region 420c and drain regions 430c and 435c of the semiconductor element have different structures, a semiconductor element with improved characteristics (such as HCI, GIDL) can be provided, thereby improving the reliability of the semiconductor element.

[0143] Figures 17A to 20BThis is a schematic diagram illustrating an intermediate process in a method of manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure.

[0144] Refer to together Figure 17A and Figure 17B The semiconductor device may include a substrate 503, a plurality of fin structures 505 extending on the substrate 503 along a first direction (X-axis direction), and one or more dummy gate structures 510 extending along a second direction (Y-axis direction). In the first direction (X-axis direction), the dummy gate structures 510 and the active region may be spaced apart from each other. In the second direction (Y-axis direction), the plurality of fin structures 505 and the device isolation film 540 may be spaced apart from each other. The plurality of fin structures 505 can provide the active region of the semiconductor device.

[0145] The semiconductor device may include a substrate 503, a plurality of fin structures 505 on the substrate 503, and one or more dummy gate structures 510 on the respective plurality of fin structures 505. The upper surface of the plurality of fin structures 505 may be parallel to the lower surface of the dummy gate structure 510.

[0146] Each dummy gate structure 510 may include a dummy gate insulating layer 511, a dummy gate metal layer 512, and a mask pattern layer 514 on the fin structure 505. The dummy gate insulating layer 511 and the dummy gate metal layer 512 may be formed by an etching process using the mask pattern layer 514. The dummy gate insulating layer 511 may be formed of silicon oxide, and the dummy gate metal layer 512 may be formed of polysilicon.

[0147] The dummy gate structure 510 may also include a gate spacer 513, which can be formed by forming a film of insulating material on the top of the dummy gate structure 510, the plurality of fin structures 505 and the element isolation film 540, and then performing anisotropic etching on the film. The gate spacer 513 may include, for example, silicon oxide, silicon nitride or silicon oxynitride.

[0148] Refer to together Figure 18A and Figure 18B Multiple fin structures 505 can be selectively removed from the first side (520) of the dummy gate structure 510. This portion can be the source region of a semiconductor device. To remove only the first side (520) of the dummy gate structure 510, a mask pattern can be formed separately on the second side (530) of the dummy gate structure 510. The mask pattern can be a layer provided to protect the second side (530) of the dummy gate structure 510 and can include silicon nitride or a carbon-containing material.

[0149] The recess can be formed by removing the fin structure 505 from the first side (520) of the dummy gate structure 510. The recess can be formed by etching the fin structure 505 by forming a mask layer separately or by using the mask pattern layer 514 and the gate spacer 513 as a mask. In the example embodiment, the recess can be formed by sequentially applying a dry etching process and a wet etching process.

[0150] Optionally, after forming the recess, a curing process can be performed on the surface of the recessed fin structure 505 using a separate process. The upper surface of the recessed fin structure 505 may be lower than the lower surface of the dummy gate structure 510, but this disclosure is not necessarily limited to this. In another example embodiment, the upper surface of the recessed fin structure 505 may form a coplanar surface with the lower surface of the dummy gate structure 510.

[0151] Refer to together Figure 19A and Figure 19B Multiple fin structures 505 can be selectively removed from the second side (530) of the dummy gate structure 510. This portion can be the drain region of a semiconductor device. In order to remove only the second side (530) of the dummy gate structure 510, a mask pattern can be formed separately on the first side (520) of the dummy gate structure 510.

[0152] The recess can be formed by removing the fin structure 505 from the second side (530) of the dummy gate structure 510. The process of removing the fin structure 505 from the second side (530) of the dummy gate structure 510 can be the same as the process of removing the first side (520) of the dummy gate structure 510.

[0153] As described above, the process of removing the fin structure 505 in the portions of the source region 520 and drain region 530 that will become semiconductor elements can be performed separately. The fin structure 505 can be removed such that the shortest distance in the first direction between the portions that will become dummy gate structure 510 and drain region 530 can be greater than the shortest distance between the portions that will become dummy gate structure 510 and source region 520. Furthermore, the fin structure 505 can be removed such that the shortest distance in the third direction between the portions that will become dummy gate structure 510 and drain region 530 can be less than the shortest distance between the portions that will become dummy gate structure 510 and source region 520. Accordingly, the portions of the source region 520 and drain region 530 that will become semiconductor elements can have different structures.

[0154] Refer to together Figure 20A and 20BActive regions 525 and 535 can be formed using fin structure 505. Active regions 525 and 535 can be formed by applying a selective epitaxial growth process to the fin structure 505 included in the NMOS region. In the example embodiment, epitaxial growth processes forming source region 520 and drain region 530 can be performed simultaneously.

[0155] When an epitaxial growth process is performed on each of the source region 520 and drain region 530z, a capping layer can be formed to cover the active region. The capping layer may include an insulating material, such as silicon oxide or silicon nitride.

[0156] The active regions 525 and 535 formed in the NMOS region may comprise silicon (Si). When forming the active regions 525 and 535 in the NMOS region, N-type impurities may be doped in situ or through a separate ion implantation process. The N-type impurities doped in the active regions 525 and 535 may be phosphorus (P), nitrogen (N), arsenic (As), or antimony (Sb), but the embodiments are not limited thereto.

[0157] Reference Figure 20B The source region 520 and drain region 530 included in the semiconductor device can have different structures. The shortest distance between the dummy gate structure 510 and the source region 520 and drain region 530 in a first direction (X-axis direction), and the shortest distance between the dummy gate structure 510 and the source region 520 and drain region 530 in a third direction (Z-axis direction) can be different from each other. Because the source region 520 and drain region 530 of the semiconductor device have different structures, the electric field around the region where the gate structure and drain region 530 overlap can be reduced. Because the source region 520 and drain region 530 of the semiconductor device have different structures, semiconductor devices with improved characteristics (such as HCI and GIDL) can be provided, thereby improving the reliability of the semiconductor device.

[0158] The various advantages and effects of the present invention are not limited to those described above, and will become more readily understood in the process of explaining the specific embodiments.

[0159] While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and alterations may be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A semiconductor device, comprising: The memory cell array region includes multiple memory cells connected to multiple word lines and multiple bit lines; as well as The peripheral circuit area includes a first semiconductor element and a second semiconductor element. Each of the first semiconductor element and the second semiconductor element includes: Substrate; A fin structure extending on the substrate in a first direction parallel to the surface of the substrate; A gate structure extending on the fin structure along a second direction parallel to the surface of the substrate and perpendicular to the first direction, and comprising a gate insulating layer and a gate metal layer; and The source and drain regions are located in the substrate on opposite sides of the fin structure and are spaced apart from each other in the first direction. Wherein, in a third direction perpendicular to the surface of the substrate, the thickness of the gate insulating layer included in the first semiconductor element is greater than the thickness of the gate insulating layer included in the second semiconductor element, and The first semiconductor element includes a source region and a drain region doped with impurities of a first conductivity type and has different structures.

2. The semiconductor device according to claim 1, in, The peripheral circuit area includes a sub-word line driver and a sensing amplifier. The sub-word line driver includes the first semiconductor element, and The sensing amplifier includes the second semiconductor element.

3. The semiconductor device according to claim 1, in, In the first semiconductor element, the doping concentration of the drain region is lower than that of the source region.

4. The semiconductor device according to claim 1, in, The source region included in the first semiconductor element includes a region that protrudes along the first direction and at least partially overlaps with the lower surface of the gate structure in the third direction.

5. The semiconductor device according to claim 1, in, In the first semiconductor element, the shortest distance between the gate structure and the drain region in the first direction is greater than the shortest distance between the gate structure and the source region in the first direction.

6. The semiconductor device according to claim 5, in, In the first semiconductor element, the shortest distance between the lower surface of the gate structure and the drain region in the third direction is less than the shortest distance between the lower surface of the gate structure and the source region in the third direction.

7. The semiconductor device according to claim 5, in, In the first semiconductor element, the drain region and the source region have the same thickness in the third direction.

8. The semiconductor device according to claim 5, in, In the first semiconductor element, the thicknesses of the drain region and the source region in the third direction are different from each other.

9. The semiconductor device according to claim 5, in, In the first semiconductor element, the upper surface of the drain region and the upper surface of the source region are at the same position in the third direction.

10. The semiconductor device according to claim 5, in, In the first semiconductor element, the upper surface of the drain region is higher than the upper surface of the source region in the third direction.

11. The semiconductor device according to claim 1, in, The first semiconductor element includes a first drain region and a second drain region between the first drain region and the gate structure. The doping concentration of the second drain region is lower than that of the first drain region.

12. The semiconductor device according to claim 1, in, The width of the drain region in the first direction is greater than the width of the source region in the first direction, and the thickness of the drain region in the third direction is different from the thickness of the source region in the third direction.

13. The semiconductor device according to claim 12, in, In the first semiconductor element, the upper surface of the drain region and the upper surface of the source region are at the same position relative to the surface of the substrate in the third direction.

14. The semiconductor device according to claim 12, in, In the first semiconductor element, the upper surfaces of the drain region and the source region are located at different positions relative to the surface of the substrate in the third direction.

15. The semiconductor device according to claim 1, in, The drain region included in the first semiconductor element includes an anti-doped region, which is doped with a second conductivity type impurity that is different from the first conductivity type impurity.

16. The semiconductor device according to claim 1, in, By changing at least one of the energy, concentration, and angle used to inject the first type of conductivity impurity, the drain region included in the first semiconductor element is doped at least once or more times.

17. The semiconductor device according to claim 16, in, In the first semiconductor element, the upper surfaces of the drain region and the source region are located at different positions relative to the surface of the substrate in the third direction.

18. The semiconductor device according to claim 17, in, In the first semiconductor element, the upper surface of the drain region is lower than the upper surface of the source region in a third direction relative to the surface of the substrate.

19. A semiconductor device, comprising: Substrate; A fin structure extending on the substrate in a first direction parallel to the surface of the substrate; A gate structure extends on the fin structure along a second direction that is parallel to the surface of the substrate and perpendicular to the first direction; as well as The source and drain regions are located in the substrate on opposite sides of the fin structure and are spaced apart from each other in the first direction. Wherein, one or more of the source region and the drain region have the same size as each other, and The source region and the drain region are located at different positions relative to the gate structure in a third direction, which is perpendicular to the surface of the substrate and perpendicular to the first direction and the second direction, respectively.

20. A semiconductor device, comprising: Substrate; A fin structure extending on the substrate in a first direction parallel to the surface of the substrate; A gate structure extends on the fin structure along a second direction that is parallel to the surface of the substrate and perpendicular to the first direction; as well as The source and drain regions are located in the substrate on opposite sides of the fin structure and are spaced apart from each other in the first direction. Wherein, at least one dimension of the drain region is larger than at least one dimension of the source region, and In the third direction, the shortest distance between the lower surface of the gate structure and the drain region is less than the shortest distance between the lower surface of the gate structure and the source region. The third direction is perpendicular to the surface of the substrate and is perpendicular to the first direction and the second direction, respectively.

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