Semiconductor device

Abstract

A semiconductor device may include: a bit line extending in a first direction; a first semiconductor vertical portion on the bit line and extending in a vertical direction; a first word line adjacent to the first semiconductor vertical portion; a gate insulating pattern between the first semiconductor vertical portion and the first word line; and a contact pattern on an upper surface of the first semiconductor vertical portion. The vertical direction may be perpendicular to the uppermost surface of the bit line. An upper surface of the first semiconductor vertical portion may be located at a lower height than an upper surface of the first word line and an upper surface of the gate insulating pattern. The contact pattern may include a metal. The grain size of the metal may be greater than 10 nm and less than 40 nm.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0109224, filed with the Korean Intellectual Property Office on August 14, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a semiconductor device, and more specifically, to a semiconductor device including a vertical channel transistor and a method of manufacturing the semiconductor device. Background Technology

[0004] As the size of semiconductor devices shrinks, it can be advantageous to develop manufacturing technologies that can increase the integration density of semiconductor devices and improve operating speed and yield. Therefore, semiconductor devices with vertical channel transistors have been proposed to increase the integration density of semiconductor devices and improve the resistance and current drive characteristics of transistors. Summary of the Invention

[0005] One aspect of the present invention provides a semiconductor device with improved electrical characteristics and / or reliability.

[0006] The inventive concept is not limited to those mentioned above, and other aspects and / or advantages not mentioned will be clearly understood by those skilled in the art from the following description.

[0007] A semiconductor device according to some embodiments of the present invention may include: a bit line extending in a first direction; a first semiconductor vertical portion located on the bit line and extending in a vertical direction perpendicular to the uppermost surface of the bit line; a first word line adjacent to the first semiconductor vertical portion; a gate insulating pattern between the first semiconductor vertical portion and the first word line; and a contact pattern located on the upper surface of the first semiconductor vertical portion. The upper surface of the first semiconductor vertical portion may be located at a lower height than the upper surface of the first word line and the upper surface of the gate insulating pattern. The contact pattern may include a metal. The grain size of the metal may be greater than 10 nm and less than 40 nm.

[0008] A semiconductor device according to some embodiments of the present invention may include: a bit line extending in a first direction; a first semiconductor vertical portion located on the bit line and extending in a vertical direction perpendicular to the uppermost surface of the bit line; a first word line adjacent to the first semiconductor vertical portion; a gate insulating pattern between the first semiconductor vertical portion and the first word line; a contact pattern located on the upper surface of the first semiconductor vertical portion and extending to the upper surface of the gate insulating pattern; and a barrier pattern between the upper surface of the first semiconductor vertical portion and the contact pattern. The barrier pattern may extend between the gate insulating pattern and the contact pattern. The upper surface of the first semiconductor vertical portion may be located at a height higher than the upper surface of the first word line and at the same height as the upper surface of the gate insulating pattern. The barrier pattern may include an amorphous metal.

[0009] A semiconductor device according to some embodiments of the present invention may include: a bit line extending in a first direction; a semiconductor pattern located on the bit line, the semiconductor pattern including a first vertical portion and a second vertical portion spaced apart from each other in the first direction; a first word line and a second word line, the first word line and the second word line being spaced apart from each other in the first vertical portion and the second vertical portion, the first word line and the second word line being adjacent to the first vertical portion and the second vertical portion, respectively; a gate insulating pattern located between the first vertical portion and the first word line, and the gate insulating pattern between the second vertical portion and the second word line; and contact patterns located on the upper surfaces of the first vertical portion and the second vertical portion, respectively. The upper surfaces of the first vertical portion and the second vertical portion may be located at a height lower than the upper surfaces of the first word line, the second word line, and the gate insulating pattern. Each of the contact patterns may include a metal. The grain size of the metal may be greater than 10 nm and less than 40 nm. Attached Figure Description

[0010] The exemplary embodiments will become clearer from the following brief description taken in conjunction with the accompanying drawings. The drawings represent non-limiting exemplary embodiments as described herein.

[0011] Figure 1 This is a block diagram of a semiconductor memory device including a semiconductor device according to some embodiments of the present invention.

[0012] Figure 2 This is a perspective view of a semiconductor device that briefly illustrates some embodiments of the concept according to the present invention.

[0013] Figure 3 This is a plan view of a semiconductor device according to some embodiments of the present invention.

[0014] Figures 4 to 6These are cross-sectional views of semiconductor devices according to some embodiments of the present invention. Figures 4 to 6 They correspond to Figure 3 Cross-sectional views of lines A-A', B-B', and C-C'.

[0015] Figures 7A to 7D These are cross-sectional views of semiconductor devices according to some embodiments of the present invention. Figures 7A to 7D They correspond to Figure 3 A cross-sectional view of line D-D'.

[0016] Figure 8A yes Figure 7A and Figure 7B A magnified view of part "P1".

[0017] Figure 8B yes Figure 7C and Figure 7D A magnified view of part "P2".

[0018] Figures 9A to 16D It shows the manufacturing process. Figures 4 to 6 and Figure 7A A cross-sectional view of a method for constructing a semiconductor device.

[0019] Figure 16E yes Figure 16D A magnified view of part "P3".

[0020] Figures 17A to 17D These are cross-sectional views of semiconductor devices according to some embodiments of the present invention. Figures 17A to 17D Each corresponds to Figure 3 The line D-D'. Detailed Implementation

[0021] In the following, a semiconductor memory device and / or a method of manufacturing the semiconductor memory device according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

[0022] The concept of "substantially identical" components can indicate that components can be completely identical, and can also indicate that components can be determined to be identical, taking into account errors or deviations that occur during the manufacturing process.

[0023] When a phrase such as “at least one of…” follows a list of elements, the phrase modifies the entire list of elements, not individual elements within the list. For example, “at least one of A, B, and C” and similar language (e.g., “at least one selected from the group consisting of A, B, and C”) can be interpreted as only A, only B, only C, or any combination of two or more of A, B, and C, such as, for example, ABC, AB, BC, and AC.

[0024] When the terms “about” or “substantially” are used in conjunction with numerical values ​​in this specification, it is intended that the relevant numerical values ​​include manufacturing or operational tolerances (e.g., ±) around the stated values.

[0025] (10%). Furthermore, when the terms "generally" and "substantially" are used in conjunction with geometry, it is intended not to require precision in the geometry, but rather the degrees of freedom of the shape within the scope of this disclosure. Additionally, regardless of whether a value or shape is modified to "about" or "substantially," it will be understood that these values ​​and shapes should be interpreted as including manufacturing or operational tolerances (e.g., ±10%) around the stated values ​​or shapes. When a range is specified, the range includes all values ​​within it, such as increments of 0.1%.

[0026] Figure 1 This is a block diagram of a semiconductor memory device including a semiconductor device according to some embodiments of the present invention.

[0027] Reference Figure 1 The semiconductor memory device may include a memory cell array 1, a row decoder 2, a sense amplifier 3, a column decoder 4, and control logic 5.

[0028] The memory cell array 1 may include multiple memory cells MC arranged in two or three dimensions. Each memory cell MC may be positioned between and connected to intersecting word lines WL and bit lines BL.

[0029] Each memory cell MC may include a select element TR and a data storage element DS, which may be electrically connected in series. The select element TR may be disposed between and connected to the data storage element DS and the word line WL, and the data storage element DS may be connected to the bit line BL via the select element TR. The select element TR may be a field-effect transistor (FET), and the data storage element DS may be implemented by a capacitor, a magnetic tunnel junction pattern, or a variable resistor. As an example, the select element TR may include a transistor, the gate electrode of which may be connected to the word line WL, and the drain / source terminals of which may be connected to the bit line BL and the data storage element DS, respectively.

[0030] The row decoder 2 can be configured to decode address information that can be input from an external source, and select one of the word lines WL in the memory cell array 1 based on the decoded address information. The address information decoded by the row decoder 2 can be provided to the row driver (not shown), and in this case, the row driver can provide corresponding voltages to the selected word line and the unselected word line in the word line WL in response to the control of the control circuit.

[0031] The sensing amplifier 3 can be configured to sense, amplify, and output the voltage difference between a bit line selected by the address information decoded by the column decoder 4 and a reference bit line in the bit line BL.

[0032] The column decoder 4 can provide a data transfer path between the sense amplifier 3 and an external device (e.g., a memory controller). The column decoder 4 can be configured to decode address information input from an external source and select one bit line from the bit lines BL based on the decoded address information.

[0033] Control logic 5 can generate control signals that can be used to control write or read operations on memory cell array 1.

[0034] Figure 2 This is a perspective view of a semiconductor device that briefly illustrates some embodiments of the concept according to the present invention.

[0035] Reference Figure 2 A semiconductor device according to some embodiments of the present invention may include a substrate 100, a peripheral circuit structure PS on the substrate 100, and a cell array structure CS on the peripheral circuit structure PS.

[0036] The peripheral circuit structure PS may include core circuitry and peripheral circuitry formed on substrate 100. The core circuitry and peripheral circuitry may include reference circuitry. Figure 1 The row decoder 2 and column decoder 4, sensing amplifier 3 and control logic 5 are described. The peripheral circuit structure PS can be disposed between the substrate 100 and the cell array structure CS on a third direction D3 perpendicular to the upper surface of the substrate 100.

[0037] The cell array structure CS may include bit lines BL, word lines WL, and memory cells MC located between bit lines BL and word lines WL (see, for example, see...). Figure 1 ). Memory cell MC (for example, see Figure 1 The memory cell MC can be disposed in two or three dimensions on a plane parallel to the upper surface of the substrate 100 and extending in two different directions (e.g., a first direction D1 and a second direction D2). As described above, the memory cell MC (e.g., see...) Figure 1 Each of these can include a selection element TR and a data storage element DS.

[0038] According to some embodiments, the memory cell MC (e.g., see...) Figure 1 Each of these components may include a vertical channel transistor (VCT) that can be used as a selection element TR. The vertical channel transistor may be configured to include a channel region extending in a direction perpendicular to the upper surface of the substrate 100 (i.e., third direction D3). Furthermore, the memory cell MC (e.g., see...) Figure 1Each of these can include a capacitor that can be used as a data storage element DS.

[0039] Figure 3 This is a plan view of a semiconductor device according to some embodiments of the present invention. Figures 4 to 6 They correspond to Figure 3 Cross-sectional views of lines A-A', B-B', and C-C'. Figure 7A and Figure 7B They correspond to Figure 3 A cross-sectional view of line D-D'. Figure 8A yes Figure 7A and Figure 7B A magnified view of part "P1".

[0040] Reference Figures 3 to 6 , Figure 7A , Figure 7B and Figure 8A The semiconductor device may include a substrate 100, a peripheral circuit structure PS located on the substrate 100, and a cell array structure CS located on the peripheral circuit structure PS.

[0041] Substrate 100 may be a semiconductor substrate. Substrate 100 may be, for example, a silicon substrate, a germanium substrate, or a silicon-germanium substrate.

[0042] The peripheral circuit structure PS may include a peripheral gate structure PC, peripheral contact pads CP, peripheral contact plugs CPLG1, and a first interlayer insulating layer 102 covering them, all integrated on the substrate 100. The peripheral gate structure PC may include... Figure 1 The sensing amplifier 3. The cell array structure CS may include memory cells with vertical channel transistors.

[0043] The cell array structure CS may include multiple cell contact plugs CPLG2, multiple bit lines BL, multiple shielding structures SM, a second interlayer insulating layer 104, multiple semiconductor patterns SP, multiple word lines WL, multiple gate insulating patterns Gox, and a data storage pattern DSP. The second interlayer insulating layer 104 may cover the cell contact plugs CPLG2 and the shielding structures SM. The gate insulating pattern Gox may include a bottom surface Goxb, and the bottom surface Goxb may be located on the surface of the multiple semiconductor patterns SP.

[0044] For example, the peripheral gate structure PC of the peripheral circuit structure PS can be electrically connected to the bit line BL via peripheral contact plugs CPLG1, peripheral contact pads CP, and cell contact plugs CPLG2. Each of the first interlayer insulating layer 102 and the second interlayer insulating layer 104 may include multiple insulating layers and may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and low-k materials. In this specification, a low-k material refers to a material having a dielectric constant lower than that of silicon oxide. For example, a low-k material may include a dielectric material having a dielectric constant of 3.9 or less, and may include a material doped with fluorine (F) or carbon (C) in silicon oxide.

[0045] Bit lines BL can be disposed on the substrate 100 in the second interlayer insulating layer 104 and can extend in the first direction D1. Multiple bit lines BL can be provided, and they can be spaced apart from each other in the second direction D2. The bit lines BL can be electrically connected to the peripheral contact pads CP via cell contact plugs CPLG2. In this specification, the first direction D1 and the second direction D2 can be directions parallel to the upper surface of the substrate 100 and intersecting each other. The third direction D3 can be a vertical direction perpendicular to the upper surface of the substrate 100. The first, second, and third directions D1, D2, and D3 can be directions orthogonal to each other.

[0046] The bit line BL may include, but is not limited to, at least one of the following: doped polycrystalline silicon, metals (e.g., Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co), conductive metal nitrides (e.g., TiN, TaN, WN, NbN, TiAlN, TiSiN, TaSiN, RuTiN), conductive metal silicides, and conductive metal oxides (e.g., PtO, RuO2, IrO2, SrRuO3 (SRO), (Ba,Sr)RuO3 (BSRO), CaRuO3 (CRO), LaSrCoO (LSCo)). The bit line BL may comprise a single layer or multiple layers of the above materials. In some embodiments, the bit line BL may comprise a two-dimensional semiconductor material, for example, a two-dimensional semiconductor material may comprise graphene, carbon nanotubes, or combinations thereof.

[0047] The shielding structure SM can be disposed between the bit lines BL, and the shielding structure SM can extend in the first direction D1. The bit lines BL and the shielding structure SM can be spaced apart from each other in the second direction D2, and can be disposed alternately. The shielding structure SM can include, for example, a conductive material, such as a metal. The shielding structure SM can be disposed in the second interlayer insulating layer 104, and the upper surface of the shielding structure SM can be located at a height lower than the uppermost surface BLa of the bit line BL. In this specification, height can refer to the height in the third direction D3.

[0048] For example, the shielding structure SM can be formed of a conductive material and may include air gaps or voids. In another example, although not shown, air gaps may be provided in the second interlayer insulation layer 104 instead of the shielding structure SM.

[0049] Semiconductor patterns SP can be set on bit lines BL. Multiple semiconductor patterns SP can be set. Semiconductor patterns SP can be spaced apart from each other in the first direction D1 and the second direction D2.

[0050] The semiconductor pattern SP may include a first vertical portion V1 and a second vertical portion V2 spaced apart from each other in a first direction D1. The semiconductor pattern SP may include a first horizontal portion H1 extending from the lower part of the first vertical portion V1 toward the second vertical portion V2. The semiconductor pattern SP may include a second horizontal portion H2 extending from the lower part of the second vertical portion V2 toward the first vertical portion V1. The first horizontal portion H1 and the second horizontal portion H2 may be spaced apart from each other in the first direction D1. The first vertical portion V1 and the first horizontal portion H1 may be integral with each other, and the second vertical portion V2 and the second horizontal portion H2 may be integral with each other. That is, the first vertical portion V1 and the first horizontal portion H1 may be connected to each other to have an "L" shape, and the second vertical portion V2 and the second horizontal portion H2 may be connected to each other to have a mirror-symmetrical "L" shape. The first vertical portion V1 and the second vertical portion V2 may be referred to as the first semiconductor vertical portion V1 and the second semiconductor vertical portion V2, respectively. The first horizontal portion H1 and the second horizontal portion H2 may be referred to as the first semiconductor horizontal portion H1 and the second semiconductor horizontal portion H2, respectively.

[0051] According to some embodiments, such as Figure 7A As shown, the upper surface of bit line BL can extend in a straight line in the first direction D1. The height of the upper surface of bit line BL can remain the same in the first direction D1. Therefore, the upper surface of bit line BL can be the uppermost surface BLa of bit line BL.

[0052] According to another embodiment, such as Figure 7B As shown, the upper surface of bit line BL can have a rough structure. The upper surface of bit line BL below the semiconductor pattern SP can be located at a lower height than the uppermost surface BLa of bit line BL. The uppermost surface BLa of bit line BL can be the upper surface of bit line BL located at the highest height. The uppermost surface BLa of bit line BL may not be located between the first vertical portion V1 and the second vertical portion V2 of semiconductor pattern SP. The uppermost surface BLa of bit line BL can be located between adjacent semiconductor patterns SP.

[0053] According to some embodiments, such as Figure 7AAs shown, the lower surfaces Hb of the first horizontal portion H1 and the second horizontal portion H2 can be located at the same height as the uppermost surface BLa of the bit line BL. The lower surfaces Vb of the first vertical portion V1 and the second vertical portion V2 can be located at the same height as the uppermost surface BLa of the bit line BL. The first horizontal portion H1 and the second horizontal portion H2 may not be embedded in the bit line BL. The first vertical portion V1 and the second vertical portion V2 may not be embedded in the bit line BL. That is, the semiconductor pattern SP can have a form that is not embedded in the bit line BL.

[0054] In another embodiment, such as Figure 7B As shown, the lower surfaces Hb of the first horizontal portion H1 and the second horizontal portion H2 can be located at a height lower than the uppermost surface BLa of the bit line BL. At least a portion of the first horizontal portion H1 and the second horizontal portion H2 can be embedded in the upper part of the bit line BL. As an example, the upper surfaces of the first horizontal portion H1 and the second horizontal portion H2 can be located at a height lower than the uppermost surface BLa of the bit line BL, but are not limited thereto. As another example, although not shown, the upper surfaces of the first horizontal portion H1 and the second horizontal portion H2 can be located at a height higher than the uppermost surface BLa of the bit line BL or at the same height as the uppermost surface BLa of the bit line BL. The lower surfaces of the first vertical portion V1 and the second vertical portion V2 can be embedded in the upper part of the bit line BL. The lower surfaces Vb of the first vertical portion V1 and the second vertical portion V2 can be coplanar with the lower surfaces Hb of the first horizontal portion H1 and the second horizontal portion H2, and can be located at a height lower than the uppermost surface BLa of the bit line BL.

[0055] The first horizontal portion H1 and the second horizontal portion H2 of the semiconductor pattern SP may include a common source / drain region, and the upper surfaces of the first vertical portion V1 and the second vertical portion V2 may respectively include a first source / drain region and a second source / drain region. The first vertical portion V1 may include a first channel region located between the common source / drain region and the first source / drain region, and the second vertical portion V2 may include a second channel region located between the common source / drain region and the second source / drain region. Each of the first vertical portion V1 and the second vertical portion V2 may be electrically connected to a bit line BL. That is, the semiconductor device conceived according to the present invention can have a structure in which a pair of vertical channel transistors share a bit line BL.

[0056] The semiconductor pattern SP may include an oxide semiconductor, and for example, the oxide semiconductor may include In... x Ga y Zn z O、In x Ga y Si z O、In xSn y Zn z O、In x Zn y O, Zn x O, Zn x Sn y O, Zn x O y N, Zr x Zn y Sn z O、Sn x O、Hf x In y Zn z O.Ga x Zn y Sn z O, Al x Zn y Sn z O、Yb x Ga y Zn z O, and In x Ga y The semiconductor pattern SP may contain at least one of the following, but is not limited to: Indium gallium zinc oxide (IGZO). The semiconductor pattern SP may comprise a single layer or multiple layers of oxide semiconductor. The semiconductor pattern SP may comprise amorphous oxide semiconductor, crystalline oxide semiconductor, or polycrystalline oxide semiconductor. In some embodiments, the semiconductor pattern SP may have a bandgap energy greater than that of silicon. For example, the semiconductor pattern SP may have a bandgap energy of about 1.5 eV to 5.6 eV. For example, the semiconductor pattern SP may have optimal channel performance when it has a bandgap energy of about 2.0 eV to 4.0 eV. For example, the semiconductor pattern SP may be polycrystalline or amorphous, but is not limited to. In embodiments, the semiconductor pattern SP may comprise a two-dimensional semiconductor material, such as graphene, carbon nanotubes, or a combination thereof.

[0057] The character line WL can be set between the first vertical portion V1 and the second vertical portion V2. Multiple character lines WL can be set. The character lines WL can extend in the second direction D2 and can be spaced apart from each other in the first direction D1.

[0058] Each of the word lines WL may include a first word line WL1 and a second word line WL2, and the first word line WL1 and the second word line WL2 may be spaced apart from each other in a first direction D1. The first word line WL1 may be disposed on the inner surface of the first vertical portion V1. The inner surface of the first vertical portion V1 may be the side surface of the first vertical portion V1 facing the second vertical portion V2. The second word line WL2 may be disposed on the inner surface of the second vertical portion V2. The inner surface of the second vertical portion V2 may be the side surface of the second vertical portion V2 facing the first vertical portion V1.

[0059] The first character line WL1 can be adjacent to the first channel area of ​​the first vertical portion V1, and can control the first channel area. The second character line WL2 can be adjacent to the second channel area of ​​the second vertical portion V2, and can control the second channel area.

[0060] According to some embodiments, such as Figure 7A As shown, word line WL and bit line BL can overlap non-horizontally.

[0061] According to another embodiment, such as Figure 7B As shown, due to the non-flatness of the bit line BL, a portion of the word line WL can be embedded in the upper part of the bit line BL. Consequently, the embedded portion of the word line WL can horizontally overlap with the bit line BL. Therefore, the word line WL can be more effectively controlled to the lower part of each of the first and second channel regions (e.g., controlled to the lower part of each of the first and second channel regions at a height lower than the uppermost surface BLa of the bit line BL), and as a result, the electrical characteristics and / or reliability of the semiconductor device can be improved.

[0062] The word line (WL) may include, but is not limited to, at least one of the following: doped polycrystalline silicon, metals (e.g., Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co), conductive metal nitrides (e.g., TiN, TaN, WN, NbN, TiAlN, TiSiN, TaSiN, RuTiN), conductive metal silicides, and conductive metal oxides (e.g., PtO, RuO2, IrO2, SrRuO3 (SRO), (Ba,Sr)RuO3 (BSRO), CaRuO3 (CRO), LaSrCoO (LSCo)). The word line WL may comprise a single layer or multiple layers of the aforementioned materials. In some embodiments, the word line WL may comprise a two-dimensional semiconductor material, such as graphene, carbon nanotubes, or combinations thereof.

[0063] A gate insulating pattern Gox can be interposed between the semiconductor pattern SP and the word line WL. Specifically, the gate insulating pattern Gox can be interposed between the inner surface of the first vertical portion V1 and the first word line WL1, and between the inner surface of the second vertical portion V2 and the second word line WL2, respectively. The gate insulating pattern Gox can also extend between the first horizontal portion H1 and the first word line WL1, and between the second horizontal portion H2 and the second word line WL2, respectively. The word line WL can be separated from the semiconductor pattern SP by the gate insulating pattern Gox. The gate insulating pattern Gox can cover the semiconductor pattern SP with a uniform thickness.

[0064] The gate insulating pattern Gox may include at least one of silicon oxide, silicon oxynitride, and a high-k dielectric material with a dielectric constant higher than that of silicon oxide. The high-k dielectric material may include metal oxides or metal oxynitrides. For example, high-k dielectric materials that can be used as the gate insulating pattern Gox may include at least one of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, and Al2O3, but are not limited thereto.

[0065] A first insulating pattern 120 may be interposed between adjacent semiconductor patterns SP along a first direction D1. Multiple first insulating patterns 120 may be provided. The first insulating patterns 120 may extend across the bit line BL in a second direction D2 and may be spaced apart from each other in the first direction D1. The first insulating pattern 120 may cover at least a portion of the outer surface of the first vertical portion V1 and the second vertical portion V2. For example, the first insulating pattern 120 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k material. For example, the first insulating pattern 120 may be formed of a single layer or multiple layers.

[0066] According to some embodiments, such as Figure 7A As shown, the first insulating pattern 120 can cover the outer surfaces of the first vertical portion V1 and the second vertical portion V2. The lower surfaces Hb of the first horizontal portion H1 and the second horizontal portion H2 of the semiconductor pattern SP can be located at the same height as the lower surface of the first insulating pattern 120, and can be coplanar with the lower surface of the first insulating pattern 120.

[0067] According to another embodiment, such as Figure 7B As shown, the first insulating pattern 120 can contact the uppermost surface BLa of the bit line BL. The first insulating pattern 120 can cover the portion of the outer surface of the first vertical portion V1 and the second vertical portion V2 that is not embedded in the bit line BL. The lower surfaces Hb of the first horizontal portion H1 and the second horizontal portion H2 of the semiconductor pattern SP can be located at a height lower than the lowermost surface of the first insulating pattern 120.

[0068] The second insulating pattern 130 can be disposed between the first word line WL1 and the second word line WL2 of the word line WL. Multiple second insulating patterns 130 can be disposed. The second insulating patterns 130 can extend across the bit line BL in the second direction D2 and can be spaced apart from each other in the first direction D1. The first insulating pattern 120 and the second insulating pattern 130 can be disposed alternately relative to the first direction D1. The second insulating pattern 130 can include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and low-k materials.

[0069] A protective pattern 110 may be inserted between the word line WL and the second insulating pattern 130. The protective pattern 110 may cover the inner surface of the word line WL. The protective pattern 110 may include at least one of, for example, silicon oxide, silicon nitride, and silicon oxynitride.

[0070] A capping pattern 220 may be disposed on the upper surface WLa of the word line WL. The capping pattern 220 may cover the upper surface of the protective pattern 110 and the second insulating pattern 130. The capping pattern 220 may extend in the second direction D2. The upper surface of the capping pattern 220 may be coplanar with the upper surface Goxa of the gate insulating pattern Gox. The capping pattern 220 may include at least one of, for example, silicon oxide, silicon nitride, and silicon oxynitride.

[0071] Landing pads LP can be respectively disposed on the first vertical portion V1 and the second vertical portion V2 of the semiconductor pattern SP. Landing pads LP can be in direct contact with and electrically connected to the upper surfaces Vb of the first vertical portion V1 and the second vertical portion V2. When viewed in a planar view, the landing pads LP can be spaced apart from each other in the first direction D1 and the second direction D2, and can be arranged in various shapes (such as matrix shapes, zigzag shapes, honeycomb shapes, etc.). When viewed in a planar view, each of the landing pads LP can have various shapes, such as circular, elliptical, rectangular, square, rhomboid, hexagonal, etc.

[0072] For example, refer to Figure 8A The upper surfaces Va of the first vertical portion V1 and the second vertical portion V2 can be positioned at a height lower than the upper surface Goxa of the gate insulating pattern Gox. Additionally, the upper surfaces Va of the first vertical portion V1 and the second vertical portion V2 can be positioned at a height lower than the upper surface WLa of the word line WL. The upper surface Goxa of the gate insulating pattern Gox, the upper surface of the first insulating pattern 120, and the upper surface of the capping pattern 220 can be located at the same height and can be coplanar with each other.

[0073] The landing pad LP may include a substrate pattern 300, a barrier pattern 310, a blocking pattern 320, and a contact pattern 330. The substrate pattern 300 may be disposed on the upper surface Va of each of the first vertical portion V1 and the second vertical portion V2. The substrate pattern 300 may extend onto the side surface and upper surface Goxa of the gate insulating pattern Gox. The substrate pattern 300 may extend onto the side surface and upper surface of the first insulating pattern 120. The substrate pattern 300 may extend onto the upper surface of the capping pattern 220. That is, the substrate pattern 300 may conformally cover the upper surface Va of each of the first vertical portion V1 and the second vertical portion V2, the side and upper surfaces of the gate insulating pattern Gox, the side and upper surfaces of the first insulating pattern 120, and the upper surface of the capping pattern 220. The substrate pattern 300 may be interposed between the upper surface Va of each of the gate insulating pattern Gox, the first vertical portion V1, and the second vertical portion V2, and between the first insulating pattern 120 and the contact pattern 330 described below. The substrate pattern 300 may include a first metal, and the first metal may be, for example, Mo, Ni, Au, Pt, Ru, or combinations thereof, but is not limited thereto.

[0074] A barrier pattern 310 may be disposed on a substrate pattern 300. The barrier pattern 310 may conformally cover the substrate pattern 300. The barrier pattern 310 may vertically overlap the substrate pattern 300. The barrier pattern 310 may be interposed between the substrate pattern 300 and the contact pattern 330 described below. The barrier pattern 310 may comprise an amorphous metal, and may comprise, for example, amorphous Ti.

[0075] A barrier pattern 320 may be disposed on a barrier pattern 310. The barrier pattern 320 may conformally cover the barrier pattern 310. The barrier pattern 320 may vertically overlap the barrier pattern 310. The barrier pattern 320 may be interposed between the barrier pattern 310 and the contact pattern 330 described below. The barrier pattern 320 may include a conductive metal nitride and may include the same metal element as the barrier pattern 310. The barrier pattern 320 may include, for example, TiN, TiSiN, etc., but is not limited thereto.

[0076] Contact pattern 330 may be disposed on barrier pattern 320. Contact pattern 330 may cover the upper surface and side surface of barrier pattern 320. The lowermost surface 330b of contact pattern 330 may be the lowest surface among the lower surfaces of contact pattern 330 located at the lowest height. For example, the lowermost surface 330b of contact pattern 330 may be located at a height lower than the upper surface WLa of word line WL, but is not limited thereto. When viewed in a plan view, the lowermost surface 330b of contact pattern 330 may be located in the region that vertically overlaps with the first vertical portion V1 and the second vertical portion V2. Contact pattern 330 may include a second metal, and the second metal may be different from the first metal. Contact pattern 330 may include metal elements different from barrier pattern 310 and barrier pattern 320. The grain size of the second metal of contact pattern 330 may be greater than 10 nm and less than 40 nm. For example, the second metal may include W, and the grain size of W in contact pattern 330 may be greater than 10 nm and less than 40 nm.

[0077] Therefore, a portion of the landing pad LP can overlap horizontally with the word line WL.

[0078] Refer again Figures 3 to 6 , Figure 7A and Figure 7B The third interlayer insulating layer 240 can fill the space between the landing pads LP on the first insulating pattern 120 and the second insulating pattern 130. The third interlayer insulating layer 240 can include at least one of silicon oxide, silicon nitride and silicon oxynitride, and can include a single layer or multiple layers.

[0079] The data storage pattern DSP can be disposed on each of the landing pads LP. The data storage pattern DSP can be electrically connected to the first vertical portion V1 and the second vertical portion V2 of the semiconductor pattern SP via the landing pads LP, respectively.

[0080] In one example, the data storage pattern DSP can be a capacitor and can include a lower electrode and an upper electrode, as well as a capacitor dielectric layer interposed between the lower electrode and the upper electrode. In this case, the lower electrode can contact the landing pad LP, and the lower electrode can have various shapes in the planar view, such as circular, elliptical, rectangular, square, rhomboid, or hexagonal.

[0081] Alternatively, the data storage pattern DSP can be a variable resistance pattern that can switch between two resistive states by an electrical pulse applied to the memory element. For example, the data storage pattern DSP may include phase change materials, perovskite compounds, transition metal oxides, magnetic materials, ferromagnetic materials, or antiferromagnetic materials whose crystal states change according to the amount of current.

[0082] Figure 7C and Figure 7D They correspond to Figure 3 A cross-sectional view of line D-D'. Figure 8B yes Figure 7C and Figure 7D A magnified view of part "P2". For simplicity, the repeated content has been omitted.

[0083] Reference Figure 7C , Figure 7D and Figure 8B The upper surfaces Va of the first vertical portion V1 and the second vertical portion V2 can be located at the same height as the upper surface Goxa of the gate insulating pattern Gox, and can be coplanar with the upper surface Goxa of the gate insulating pattern Gox. Additionally, the upper surfaces Va of the first vertical portion V1 and the second vertical portion V2 can be located at a height higher than the upper surface WLa of the word line WL.

[0084] The landing pad LP may include a substrate pattern 300, a barrier pattern 310, a barrier pattern 320, and a contact pattern 330 stacked sequentially. The substrate pattern 300 may be disposed on the upper surface Va of each of the first vertical portion V1 and the second vertical portion V2, and may extend to the upper surface of the gate insulating pattern Gox, the upper surface of the first insulating pattern 120, and the upper surface of the capping pattern 220.

[0085] The blocking pattern 310 can be disposed on the base pattern 300 and can conformally cover the base pattern 300. The blocking pattern 320 can be disposed on the blocking pattern 310 and can conformally cover the blocking pattern 310.

[0086] The contact pattern 330 can be disposed on the barrier pattern 320. Even when moving in the first direction D1 and the second direction D2, the height of the lower surface of the contact pattern 330 can remain the same. That is, the lower surface of the contact pattern 330 can be the lowermost surface 330b of the contact pattern 330.

[0087] Therefore, the landing pad LP does not need to overlap horizontally with the word line WL.

[0088] The substrate pattern 300, barrier pattern 310, barrier pattern 320, and contact pattern 330 may include references Figure 8A The materials described are substantially the same. In particular, the contact pattern 330 may include W with a grain size greater than 10 nm and less than 40 nm.

[0089] According to the present invention, the contact pattern 330 may include a second metal with a small grain size, thereby limiting and / or suppressing hydrogen diffusion. Additionally, the amorphous metal included in the barrier pattern can have high solubility in hydrogen, and thus can increase the hydrogen capture effect. The solubility of the amorphous metal in the barrier pattern 310 in hydrogen can be higher than that of the metal nitride in the barrier pattern 320. Specifically, since the conductive metal nitride included in the barrier pattern 320 has a columnar structure, hydrogen can diffuse, but since the barrier pattern 310 includes an amorphous metal, hydrogen diffusion can be limited and / or suppressed due to the blocking effect on the columnar structure of the barrier pattern 320. Furthermore, as an example, when the barrier pattern 320 includes TiSiN, the hydrogen blocking effect can be more significant due to the relatively higher Si ratio. Additionally, the substrate pattern 300 can reduce the contact resistance with the channel. As a result, hydrogen diffusion into the channel region can be limited and / or suppressed, and the contact resistance with the channel can be reduced, thereby improving the electrical characteristics and / or reliability of the semiconductor device.

[0090] Figures 9A to 16D It shows the manufacturing process. Figures 3 to 6 and Figure 7A A cross-sectional view of a method for constructing a semiconductor device. Specifically, Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A and Figure 16A Is with Figure 3 The cross-sectional view corresponding to line A-A'. Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B and Figure 16B Is with Figure 3 The cross-sectional view corresponding to line B-B'. Figure 9C , Figure 10C , Figure 11C , Figure 12C , Figure 13C , Figure 14C , Figure 15C and Figure 16C Is with Figure 3 The cross-sectional view corresponding to line C-C'. Figure 9D , Figure 10D , Figure 11D , Figure 12D , Figure 13D , Figure 14D , Figure 15D and Figure 16D Is with Figure 3The cross-sectional view corresponding to line D-D'. Figure 16E yes Figure 16D A magnified image of part "P3". Refer to the following text. Figure 3 and Figures 9A to 16D Description for manufacturing Figure 7A Methods for developing semiconductor devices. For simplicity, descriptions of content repeated above will be omitted.

[0091] Reference Figure 3 as well as Figures 9A to 9D A peripheral circuit structure PS can be formed on the substrate 100. Forming the peripheral circuit structure PS may include forming a peripheral gate structure PC, peripheral contact pads CP, peripheral contact plugs CPLG1, and a first interlayer insulating layer 102 covering them. A second interlayer insulating layer 104 can be formed on the peripheral circuit structure PS. Bit lines BL can be formed in the second interlayer insulating layer 104. Multiple bit lines BL can be formed. Bit lines BL can be formed to extend in a first direction D1 and spaced apart from each other in a second direction D2. Bit lines BL can be formed to be electrically connected to wiring below them and wiring in the peripheral circuit structure PS. Forming bit lines BL may include depositing a bit line layer (not shown) and patterning the bit line layer to form the bit lines BL. A shielding structure SM can be formed in the second interlayer insulating layer 104. Multiple shielding structures SM can be formed. Forming shielding structures SM may include depositing a shielding layer (not shown) and patterning the shielding layer to form the shielding structure SM.

[0092] A first insulating layer 120L can be formed on the second interlayer insulating layer 104 and the bit line BL. The first insulating layer 120L can completely cover the second interlayer insulating layer 104 and the bit line BL. That is, the first insulating layer 120L can cover the entire front surface of the substrate 100. The first insulating layer 120L can include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and low-k materials.

[0093] Reference Figure 3 and Figures 10A to 10D A first insulating pattern 120 can be formed. Forming the first insulating pattern 120 may include forming a mask pattern (not shown) on the first insulating layer 120L, using the mask pattern as an etching mask to etch the first insulating layer 120L, and removing the mask pattern. In the etching process, the bit line BL and the second interlayer insulating layer 104 may not be etched. Multiple first insulating patterns 120 can be formed. The first insulating patterns 120 may extend in the second direction D2 and be spaced apart from each other in the first direction D1.

[0094] Reference Figure 3 and Figures 11A to 11DA semiconductor layer SL and a first molding layer 122 can be sequentially formed on the entire surface of substrate 100. Layer formation techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD) can be used to form the semiconductor layer SL and the first molding layer 122. The semiconductor layer SL can conformally cover the first insulating pattern 120 and can extend to the upper surface of the second interlayer insulating layer 104. The first molding layer 122 can completely cover the semiconductor layer SL.

[0095] The first molding layer 122 may include a carbon-containing material. For example, the first molding layer 122 may include a spin-coated hard mask (SOH) and an amorphous carbon layer (ACL).

[0096] Reference Figure 3 and Figures 12A to 12D A first trench TR1 can be formed. Forming the first trench TR1 may include forming a mask pattern (not shown) on the first molding layer 122, sequentially etching the first molding layer 122 and the semiconductor layer SL using the mask pattern as an etching mask, and removing the mask pattern. The etching process may include anisotropic etching. In the etching process, the second interlayer insulating layer 104 and the first insulating pattern 120 may not be etched. When viewed in a plan view, the first trench TR1 can be formed in a region that does not vertically overlap with the bit line BL. A plurality of first trenches TR1 may be formed. The first trenches TR1 may extend in a first direction D1 and may be spaced apart from each other in a second direction D2.

[0097] Reference Figure 3 and Figures 13A to 13D A semiconductor pattern SP can be formed. Forming the semiconductor pattern SP may include filling the first trench TR1 with a second molding layer (not shown), removing the upper portion of the first molding layer 122 and the second molding layer to expose the semiconductor layer SL formed on the first insulating pattern 120, removing a portion of the exposed semiconductor layer SL, and removing the remaining portion of the first molding layer 122 and the second molding layer.

[0098] The removal of the first molding layer 122 and the upper portion of the second molding layer, as well as a portion of the semiconductor layer SL, can be performed using a planarization process. For example, planarization can be performed using a chemical mechanical polishing (CMP) process or an etch-back process. The planarization process can be performed until the upper surface of the first insulating pattern 120 is exposed.

[0099] Multiple semiconductor patterns SP can be formed by partially removing the semiconductor layer SL.

[0100] The second molding layer may include a carbon-containing material. For example, the second molding layer may include a spin-coated hard mask (SOH) and an amorphous carbon layer (ACL).

[0101] Reference Figure 3 and Figures 14A to 14D A gate insulating layer (GIL) and a conductive layer (CL) can be formed sequentially. Layer formation techniques with excellent step-coating characteristics (such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc.) can be used to form the gate insulating layer (GIL) and the conductive layer (CL). The gate insulating layer (GIL) can conformally cover the side and top surfaces of the first insulating pattern 120, the exposed top surface of the second interlayer insulating layer 104, and the top and side surfaces of the semiconductor pattern SP. The conductive layer (CL) can conformally cover the gate insulating layer (GIL). By conformally forming the gate insulating layer (GIL) and the conductive layer (CL), a second trench (TR2) can be formed. The second trench (TR2) can extend in the second direction D2 and be spaced apart from each other in the first direction D1.

[0102] Reference Figure 3 and Figures 15A to 15D Word lines WL and gate insulating patterns Gox can be formed. Word lines WL can be formed as a first word line WL1 on a first vertical portion V1 and a second word line WL2 on a second vertical portion V2. Forming word lines WL can include, for example, removing the conductive layer CL on the first insulating pattern 120. Furthermore, portions of the conductive layer CL that vertically overlap with the second trench TR2 can be further removed to separate the conductive layer CL into multiple word lines WL.

[0103] When forming the word line WL, a portion of the gate insulating layer GIL can be removed to separate the gate insulating layer GIL into multiple gate insulating patterns Gox. That is, the gate insulating layer GIL on the first insulating pattern 120 and the portion of the gate insulating layer GIL that vertically overlaps with the second trench TR2 can be removed.

[0104] A portion of the semiconductor pattern SP can be removed to separate the portion between the first vertical portion V1 and the second vertical portion V2 into a first horizontal portion H1 and a second horizontal portion H2. Forming the first horizontal portion H1 and the second horizontal portion H2 may include, for example, removing the portion of the semiconductor pattern SP that vertically overlaps with the second trench TR2.

[0105] A protective pattern 110 may be formed along the inner surface of the word line WL. Forming the protective pattern 110 may include forming a protective layer (not shown) that conformally covers the inner surface of the word line WL and removing a portion of the protective layer.

[0106] Subsequently, a second insulating pattern 130 can be formed between the first word line WL1 and the second word line WL2. Forming the second insulating pattern 130 may include forming a second insulating layer (not shown) on the entire surface of the substrate 100, and removing the upper portion of the second insulating layer to separate the second insulating layer into a plurality of second insulating patterns 130. The upper surface of the second insulating pattern 130 may be formed at a height lower than the upper surface Goxa of the gate insulating pattern Gox and the upper surface of the first insulating pattern 120, and at the same height as the upper surface WLa of the word line WL.

[0107] A capping pattern 220 can be formed on the upper surface WLa of the letter line WL, the upper surface of the protective pattern 110, and the upper surface of the second insulating pattern 130. When the capping pattern 220 is formed, the upper surface of the first insulating pattern 120 and the upper surface Va of the first vertical portion V1 and the second vertical portion V2 can be exposed to the outside.

[0108] Then, a recess RS can be formed on the upper portion of each of the first vertical portion V1 and the second vertical portion V2. Forming the recess RS may include, for example, selectively etching the upper portion of each of the first vertical portion V1 and the second vertical portion V2. Due to the recess RS, the upper surface Va of the first vertical portion V1 and the second vertical portion V2 can be located at a height lower than the upper surface WLa of the word line WL.

[0109] Reference Figure 3 and Figures 16A to 16E A landing conductive layer LCL can be formed on the entire surface of the semiconductor device being manufactured. The landing conductive layer LCL can fill the recess RS on the upper part of the first vertical portion V1 and the second vertical portion V2. The landing conductive layer LCL may include a substrate layer 300L, a barrier layer 310L, a barrier layer 320L, and a contact layer 330L. The substrate layer 300L, the barrier layer 310L, the barrier layer 320L, and the contact layer 330L can be formed sequentially on the entire surface of the substrate 100. The substrate layer 300L can conformally cover the lower surface and side surface of the recess RS, and can extend to the upper surface of the gate insulating pattern Gox, the capping pattern 220, and the first insulating pattern 120. The barrier layer 310L can conformally cover the substrate layer 300L. The barrier layer 320L can conformally cover the barrier layer 310L.

[0110] The contact layer 330L can conformally cover the barrier layer 320L. Forming the contact layer 330L can include, for example, chemical vapor deposition (CVD) using a precursor WF6 and a reducing gas SiH4 or B2H6. The contact layer 330L can be formed using the precursor WF6 and the reducing gas SiH4. When using SiH4, the grain size of the tungsten (W) forming the contact layer 330L can be reduced. Furthermore, nitrogen treatment (N treatment) can be performed intermittently during the process of forming the contact layer 330L. When nitrogen treatment (N treatment) is added, the tungsten (W) forming the contact layer 330L can be deposited more effectively, and the grain size of the tungsten (W) can also be reduced. Therefore, the contact layer 330L can include tungsten (W) with a grain size greater than 10 nm and less than 40 nm. However, the material forming the contact layer 330L is not limited to tungsten (W).

[0111] Refer again Figures 3 to 6 and Figure 7A Landing pads LP can be formed on the first vertical portion V1 and the second vertical portion V2, respectively. Forming landing pads LP may include, for example, removing a portion of the landing conductive layer LCL to separate the landing conductive layer LCL into multiple landing pads LP.

[0112] A third interlayer insulating layer 240 can be formed to fill the space between landing pads LP on the first insulating pattern 120 and the second insulating pattern 130. Data storage patterns DSP can be formed on the landing pads LP respectively. The data storage patterns DSP can be electrically connected to the first vertical portion V1 and the second vertical portion V2 of the semiconductor pattern SP respectively through the landing pads LP.

[0113] Figures 17A to 17D These are cross-sectional views of semiconductor devices according to some embodiments of the present invention. Figures 17A to 17D Each corresponds to Figure 3 The line D-D'. For simplicity, any content that is repeated in the above description will be omitted.

[0114] Reference Figures 17A to 17D The semiconductor pattern SP may include a first vertical portion V1 and a second vertical portion V2 spaced apart from each other in a first direction D1. Furthermore, the semiconductor pattern SP may include a horizontal portion H connecting the first vertical portion V1 and the second vertical portion V2. The horizontal portion H may be adjacent to the lower portion of the first vertical portion V1 and the second vertical portion V2 to connect them. Figures 7A to 7D In contrast, the horizontal portion H can be a first horizontal portion H1 and a second horizontal portion H2 extending toward each other and forming a single unit.

[0115] The horizontal portion H of the semiconductor pattern SP can be disposed on the upper surface of the bit line BL. For example, refer to... Figure 17A and Figure 17C The lower surface Hb of the horizontal portion H can contact the uppermost surface BLa of the bit line BL, and can be located at the same height as the uppermost surface BLa of the bit line BL. The lower surfaces Vb of the first vertical portion V1 and the second vertical portion V2 can contact the uppermost surface BLa of the bit line BL, and can be located at the same height as the uppermost surface BLa of the bit line BL. The lower surfaces Vb of the first vertical portion V1 and the second vertical portion V2 can be coplanar with the lower surface Hb of the horizontal portion H.

[0116] As another example, see Figure 17B and Figure 17D The lower surface Hb of the horizontal portion H of the semiconductor pattern SP can be located at a height lower than the uppermost surface BLa of the bit line BL. At least a portion of the horizontal portion H can be embedded in the upper part of the bit line BL. The upper surface of the horizontal portion H can be located at a height lower than the uppermost surface BLa of the bit line BL, but is not limited thereto. Although not shown, the upper surface of the horizontal portion H can be set at a height higher than or at the same height as the uppermost surface BLa of the bit line BL. The lower surfaces of the first vertical portion V1 and the second vertical portion V2 can be embedded in the upper part of the bit line BL. The lower surfaces Vb of the first vertical portion V1 and the second vertical portion V2 can be substantially coplanar with the lower surface Hb of the horizontal portion H, and can be set at a height lower than the uppermost surface BLa of the bit line BL.

[0117] As an example, such as Figures 17A to 17D As shown, the gate insulating pattern Gox can be inserted between the first vertical portion V1 and the first word line WL1, and between the second vertical portion V2 and the second word line WL2, respectively, and can be separated on the horizontal portion H without being connected to each other. That is, the gate insulating patterns Gox can be spaced apart from each other on the horizontal portion H.

[0118] As another example, although not shown, the gate insulating pattern Gox can be inserted between the first vertical portion V1 and the first word line WL1 and between the second vertical portion V2 and the second word line WL2, and can extend as a connection on the horizontal portion H.

[0119] Figure 17A and Figure 17B A magnified view of part "P1" in Figure 8A As shown in the image. Figure 17C and Figure 17D A magnified view of part "P2" in Figure 8B As shown in the image. That is to say, Figure 17A and Figure 17BPart of "P1" can have the same Figure 7A and Figure 7B The structure of the part “P1” is basically the same. Figure 17C and Figure 17D Part of "P2" can have the same Figure 7C and Figure 7D The structure of part “P2” is basically the same.

[0120] According to embodiments of the present invention, hydrogen diffusion into the channel can be limited and / or prevented, and as a result, the electrical characteristics and / or reliability of the semiconductor device according to embodiments of the present invention can be improved.

[0121] One or more of the elements disclosed above may include or be implemented in a processing circuit system, such as hardware including logic circuitry, a hardware / software combination such as a processor executing software, or a combination thereof. For example, the processing circuit system may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0122] While embodiments have been described above, those skilled in the art will understand that many modifications and variations can be made without departing from the spirit and scope of the inventive concept as defined in the appended claims. Therefore, the exemplary embodiments of the inventive concept should be considered illustrative rather than restrictive in all respects, wherein the spirit and scope of the inventive concept are indicated by the appended claims.

Claims

1. A semiconductor device, comprising: Bit lines that extend in the first direction; A first semiconductor vertical portion is located on the bit line and extends in a vertical direction, the vertical direction being perpendicular to the uppermost surface of the bit line; The first word line is adjacent to the vertical portion of the first semiconductor; A gate insulating pattern is located between the vertical portion of the first semiconductor and the first word line; as well as A contact pattern is located on the upper surface of the vertical portion of the first semiconductor, wherein, The upper surface of the first vertical portion of the semiconductor is located at a height lower than the upper surface of the first word line and the upper surface of the gate insulating pattern. The contact pattern includes metal, and The grain size of the metal is greater than 10 nm and less than 40 nm.

2. The semiconductor device according to claim 1, further comprising: A substrate pattern is located between the upper surface of the vertical portion of the first semiconductor and the contact pattern, wherein, The contact pattern extends to the upper surface of the gate insulating pattern, and The substrate pattern extends between the gate insulating pattern and the contact pattern.

3. The semiconductor device according to claim 2, further comprising: A barrier pattern is located between the contact pattern and the substrate pattern.

4. The semiconductor device according to claim 3, further comprising: A blocking pattern is located between the substrate pattern and the barrier pattern.

5. The semiconductor device according to claim 4, wherein, The blocking pattern comprises amorphous metal.

6. The semiconductor device according to claim 1, further comprising: The horizontal portion of the first semiconductor extends from the lower portion of the vertical portion of the first semiconductor toward the lower portion of the first letter line in the first direction. The vertical portion and the horizontal portion of the first semiconductor are connected to each other to form a single unit.

7. The semiconductor device according to claim 6, wherein, The lower surface of the first semiconductor horizontal portion is located at the same height as the uppermost surface of the bit line.

8. The semiconductor device according to claim 6, wherein, The lower surface of the first semiconductor horizontal portion is located at a height lower than the uppermost surface of the bit line.

9. A semiconductor device, comprising: Bit lines that extend in the first direction; A first semiconductor vertical portion is located on the bit line and extends in a vertical direction, the vertical direction being perpendicular to the uppermost surface of the bit line; The first word line is adjacent to the vertical portion of the first semiconductor; A gate insulating pattern is located between the vertical portion of the first semiconductor and the first word line; A contact pattern located on the upper surface of the vertical portion of the first semiconductor and extending to the upper surface of the gate insulating pattern; as well as A blocking pattern is located between the upper surface of the vertical portion of the first semiconductor and the contact pattern, wherein... The blocking pattern extends between the gate insulating pattern and the contact pattern. The upper surface of the first vertical portion of the semiconductor is located at a height higher than the upper surface of the first word line and at the same height as the upper surface of the gate insulating pattern. The blocking pattern comprises amorphous metal.

10. The semiconductor device according to claim 9, wherein, The contact pattern includes metal, and The grain size of the metal is greater than 10 nm and less than 40 nm.

11. The semiconductor device of claim 9, further comprising: A substrate pattern is located between the upper surface of the vertical portion of the first semiconductor and the barrier pattern, wherein... The substrate pattern extends between the gate insulating pattern and the barrier pattern.

12. The semiconductor device of claim 10, further comprising: A barrier pattern is located between the contact pattern and the blocking pattern.

13. A semiconductor device, comprising: Bit lines that extend in the first direction; A semiconductor pattern located on the bit line, the semiconductor pattern comprising a first vertical portion and a second vertical portion spaced apart from each other in the first direction; The first character line and the second character line are spaced apart from each other in the first direction between the first vertical portion and the second vertical portion, and the first character line and the second character line are respectively adjacent to the first vertical portion and the second vertical portion; A gate insulating pattern is located between the first vertical portion and the first word line, and the gate insulating pattern is located between the second vertical portion and the second word line; as well as Contact patterns are located on the upper surfaces of the first vertical portion and the second vertical portion, respectively. Wherein, the upper surfaces of the first vertical portion and the second vertical portion are located at a height lower than the upper surfaces of the first word line, the second word line, and the gate insulating pattern, and Each of the contact patterns includes metal, and The grain size of the metal is greater than 10 nm and less than 40 nm.

14. The semiconductor device of claim 13, further comprising: A substrate pattern, located between the contact pattern and the gate insulating pattern, The substrate pattern extends between the contact pattern and the upper surface of the first vertical portion, and between the contact pattern and the upper surface of the second vertical portion, respectively. The contact patterns extend to the upper surface of the gate insulating pattern.

15. The semiconductor device of claim 14, further comprising: Barrier patterns are respectively located between the contact pattern and the substrate pattern.

16. The semiconductor device of claim 15, further comprising: The blocking patterns are located between the base pattern and the barrier pattern. Each of the blocking patterns comprises an amorphous metal.

17. The semiconductor device according to claim 13, wherein, The semiconductor pattern also includes a first horizontal portion and a second horizontal portion. The first horizontal portion extends from the lower part of the first vertical portion toward the second vertical portion, and The second horizontal portion extends from the lower part of the second vertical portion toward the first vertical portion.

18. The semiconductor device according to claim 17, wherein, The lower surfaces of the first horizontal portion and the second horizontal portion are each located at the same height as the uppermost surface of the bit line.

19. The semiconductor device according to claim 17, wherein, The lower surfaces of the first horizontal portion and the second horizontal portion are each located at a height lower than the uppermost surface of the bit line.

20. The semiconductor device according to claim 17, wherein, The first horizontal portion and the second horizontal portion extend toward each other and form a single unit.

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