Semiconductor device

Abstract

A semiconductor device may include: a plurality of channels on a first region of a substrate, the plurality of channels being spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate, and the substrate including the first region and a second region; a gate structure at least partially surrounding each of the plurality of channels; a bit line in contact with a first end portion of each of the plurality of channels, the bit line extending in a vertical direction; a first capacitor on a second end portion of each of the plurality of channels; a plurality of semiconductor patterns disposed on the second region of the substrate in a vertical direction, each of the plurality of semiconductor patterns at least partially overlapping a corresponding channel of the plurality of channels in a horizontal direction parallel to an upper surface of the substrate; and a plurality of second capacitors on the plurality of semiconductor patterns, respectively.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2024-0112640, filed on August 22, 2024, with the Korean Intellectual Property Office (KIPO), the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] Example embodiments of the inventive concept relate to semiconductor devices. More specifically, example embodiments of the inventive concept relate to three-dimensional (3D) semiconductor memory devices. Background Technology

[0003] Dynamic random access memory (DRAM) devices may include word lines, bit lines, channels, and capacitors. Efficiently arranging word lines, bit lines, channels, and capacitors is helpful in increasing the integration density of DRAM devices. Summary of the Invention

[0004] Example embodiments of the inventive concept provide a semiconductor device with enhanced electrical properties.

[0005] According to an exemplary embodiment of the inventive concept, a semiconductor device is provided. The semiconductor device may include: a plurality of channels on a first region of a substrate, the plurality of channels being spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate, and the substrate including a first region and a second region; a gate structure at least partially surrounding each of the plurality of channels; a bit line contacting a first end of each of the plurality of channels, the bit line extending in a vertical direction; a first capacitor on a second end of each of the plurality of channels; a plurality of semiconductor patterns arranged in a vertical direction on a second region of the substrate, each of the plurality of semiconductor patterns at least partially overlapping a corresponding channel of the plurality of channels in a horizontal direction parallel to the upper surface of the substrate; and a plurality of second capacitors, respectively on the plurality of semiconductor patterns.

[0006] According to an exemplary embodiment of the inventive concept, a semiconductor device is provided. The semiconductor device may include: a plurality of channels on a first region of a substrate, the plurality of channels being spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate, the substrate including a first region and a second region; a gate structure at least partially surrounding each of the plurality of channels; a bit line contacting a first end of each of the plurality of channels, the bit line extending in a vertical direction; a first capacitor on a second end of each of the plurality of channels; a first plate electrode structure extending in a vertical direction on a second region of the substrate; and a plurality of semiconductor patterns on opposite sidewalls of the first plate electrode structure in a first direction parallel to the upper surface of the substrate. At least two of the semiconductor patterns are vertically spaced apart from each other; a plurality of second capacitors, each contacting a corresponding sidewall of an opposing sidewall of a first plate electrode structure and on the upper and lower surfaces and sidewalls of at least one of the plurality of semiconductor patterns, each of the plurality of second capacitors extending in the vertical direction and including a first capacitor electrode, a dielectric pattern, and a second capacitor electrode; and a plurality of second plate electrode structures, respectively on opposing sidewalls of the first plate electrode structure and on a second region of the substrate, each of the plurality of second plate electrode structures extending in the vertical direction and contacting a corresponding second capacitor of the plurality of second capacitors.

[0007] According to an exemplary embodiment of the inventive concept, a semiconductor device is provided. The semiconductor device may include: a plurality of channels on a memory cell region of a substrate, the plurality of channels being spaced apart from each other in a vertical direction perpendicular to the upper surface of the substrate, and the substrate including the memory cell region and a peripheral circuit region; a gate structure at least partially surrounding each of the plurality of channels; a bit line contacting a first end of each of the plurality of channels, the bit line extending in a vertical direction; a cell capacitor on a second end of each of the plurality of channels; a first plate electrode structure extending in a vertical direction on the peripheral circuit region of the substrate; and a plurality of semiconductor patterns on opposite sidewalls of the first plate electrode structure in a first horizontal direction parallel to the upper surface of the substrate, the plurality of semiconductor patterns... The at least two of the plurality of semiconductor patterns are spaced apart from each other in the vertical direction, and each of the plurality of semiconductor patterns is at least partially superimposed with a corresponding channel of the plurality of channels in the second horizontal direction; a power capacitor, in contact with at least one of the opposing sidewalls of the first plate electrode structure, and extending in the vertical direction on the upper and lower surfaces and sidewalls of at least one of the plurality of semiconductor patterns, and including a first capacitor electrode, a dielectric pattern and a second capacitor electrode; and a second plate electrode structure, extending in the vertical direction and contacting the second capacitor electrode of the power capacitor on the sidewall of the opposing sidewall of the first plate electrode structure and on the peripheral circuit region of the substrate.

[0008] The semiconductor device according to the example embodiment may include a memory cell region, and a power capacitor may be disposed in the peripheral circuit region using a stacked structure of the memory cell region. Therefore, a power capacitor with sufficient capacitance can be disposed in the semiconductor device while using existing processes, which enhances the electrical characteristics of the semiconductor device. Attached Figure Description

[0009] Figures 1 to 7 These are plan views, cross-sectional views, and perspective views of a semiconductor device according to an example embodiment.

[0010] Figure 8 It is shown Figure 7 A schematic diagram of the electrical connections of the second capacitor structure shown.

[0011] Figures 9 to 45 These are vertical and horizontal sectional views illustrating a method of manufacturing a semiconductor device according to an example embodiment.

[0012] Figures 46 to 52 This is a schematic diagram illustrating the electrical connections of a second capacitor structure included in a semiconductor device according to an example embodiment. Detailed Implementation

[0013] The above and other aspects and features of the semiconductor device and method of manufacturing the semiconductor device according to the example embodiments will become readily apparent from the following detailed description with reference to the accompanying drawings. It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various materials, layers, regions, pads (or solder pads), electrodes, patterns, structures, and / or processes, these various materials, layers, regions, pads, electrodes, patterns, structures, and / or processes should not be limited by these terms. Rather, these terms are used only to distinguish one material, layer, region, pad, electrode, pattern, structure, or process from another. Therefore, “first,” “second,” “third,” etc., may be used selectively or interchangeably for each material, layer, region, pad, electrode, pattern, structure, or process.

[0014] Two intersecting (or crossing) directions among the horizontal directions substantially parallel to the upper surface of the substrate may be referred to as the first direction D1 and the second direction D2, respectively, and the direction substantially vertical (i.e., perpendicular) to the upper surface of the substrate may be referred to as the third direction D3. In an example embodiment, the first direction D1 and the second direction D2 may be substantially perpendicular to each other. Each of the first to third directions D1, D2, and D3 may include not only the directions shown in the figures, but also directions opposite to those shown in the figures.

[0015] Figures 1 to 7These are plan views, cross-sectional views, and perspective views illustrating a semiconductor device according to an example embodiment. Specifically, Figure 1 It's a floor plan. Figure 2 It is a vertical sectional view. Figure 3 It is a horizontal sectional view. Figures 4 to 6 It is a vertical sectional view, and Figure 7 It's a 3D image.

[0016] Figure 1 It is a plan view showing the regions included in the semiconductor device. Figure 2 yes Figure 1 A vertical sectional view of region X, which is a schematic diagram showing the main components of the semiconductor device. Figure 3 yes Figure 1 Region Y in Figure 4 and Figure 5 Horizontal section view at height H1 Figure 4 and Figure 5 They are respectively along Figure 3 The lines A-A' and C-C' intercept the Figure 1 A cross-sectional view of region Y. Figure 6 yes Figure 1 A vertical sectional view of region Z, and Figure 7 yes Figure 2 A perspective view of region P, which is a schematic diagram showing the main element of a second capacitor structure included in a semiconductor device.

[0017] Figure 8 It is shown Figure 7 A schematic diagram of the electrical connections of the second capacitor structure shown.

[0018] Reference Figures 1 to 6 The semiconductor device may include a first region I and a second region II.

[0019] In an example embodiment, the first region I may be a memory cell region in which memory cells are disposed, and the second region II may be a peripheral circuit region in which circuit patterns for applying electrical signals to memory cells are disposed. The first region I may include memory cell block regions, each of which may include a memory cell, and the memory cell block regions may be arranged in each of the first direction D1 and the second direction D2, and may be separated from each other by the first partition structure 180.

[0020] The first segmentation structure 180 may contact the upper surface of the first region I of the first substrate 100 and may have a grid shape in a plan view. In an example embodiment, the first segmentation structure 180 may include a first segmentation pattern 160 and a second segmentation pattern 170 on the sidewalls and lower surface of the first segmentation pattern 160 (e.g., covering the sidewalls and lower surface of the first segmentation pattern 160 and / or overlapping with the sidewalls and lower surface of the first segmentation pattern 160). The first segmentation pattern 160 may include an insulating nitride (e.g., silicon nitride), and the second segmentation pattern 170 may include an oxide (e.g., silicon oxide).

[0021] Each of the memory cell block regions may include a third region III and a fourth region IV. The third region III may be a memory cell array region in which a memory cell array including memory cells is disposed, and the fourth region IV may be a pad region or extension region in which a contact plug for transmitting electrical signals to the memory cell array or a conductive pad in contact with the contact plug is disposed.

[0022] In an example embodiment, the fourth region IV may be located on one side or the opposite side of the third region III in the first direction D1. Figure 3 This shows a portion of the memory cell block region (i.e., a portion of each of the third region III and the fourth region IV).

[0023] In this specification, each of the first to fourth regions I, II, III and IV may be defined within the interior of the first substrate 100 and / or the second substrate 700 on which the semiconductor device is disposed, or may be defined in the space above and below the first substrate 100 and / or the second substrate 700.

[0024] In example embodiments, the semiconductor device may have a periphery-on-cell (POC) structure or a cell-on-periphery (COP) structure. Therefore, some of the circuit patterns may be located not only in the peripheral circuit region but also above or below the memory cells in the memory cell region. Figures 1 to 6 The diagram shows a semiconductor device having some POC structures positioned above memory cells in a circuit pattern.

[0025] In some cases, the upper part of the memory cell region (i.e., the area in which some of the circuit patterns are disposed) may be referred to as the core region, and the lower part of the memory cell region (i.e., the area in which memory cells are disposed) may be referred to as the memory cell region.

[0026] When a semiconductor device has a POC (Proof-of-Concept) structure, the peripheral circuit region may have an upper portion and a lower portion, which may be referred to as a first peripheral circuit region and a second peripheral circuit region, respectively. In an example embodiment, a circuit pattern may be disposed in the first peripheral circuit region, and a second capacitor structure may be disposed in the second peripheral circuit region. The second capacitor structure is discussed in more detail below.

[0027] The memory cell region and the core region can be separated from each other by a bonding layer structure including a first bonding layer 640 and a second bonding layer 830, and the first peripheral circuit region and the second peripheral circuit region can also be separated from each other by a bonding layer structure including a first bonding layer 640 and a second bonding layer 830.

[0028] The semiconductor device may include a channel 125, a first gate structure, a bit line 440, a first capacitor structure, a conductive pad 430, first contact plugs to third contact plugs 612, 614 and 616 and first wiring structures to third wiring structures 622, 624 and 626 on a first region I of the first substrate 100, and a second capacitor structure, a fourth contact plug 618 and a fifth contact plug 619 and a fourth wiring structure 628 and a fifth wiring structure 629 on a second region II of the first substrate 100.

[0029] Additionally, the semiconductor device may include a dummy bit line 445, a barrier structure 490, a first segmentation structure 180, a third segmentation structure, a fourth segmentation structure 415, a support pattern 210, a semiconductor layer 120, a first semiconductor pattern 123, a second mask 320, an eighth segmentation pattern 340, an eleventh segmentation pattern 450, a second insulating interlayer 435, and a first capping layer 500 on a first region I of the first substrate 100.

[0030] Additionally, the semiconductor device may include a third sacrificial pattern 850, a second semiconductor pattern 860, a fifth insulating pattern 918, a pad 920, and a twelfth slit pattern 870 (see reference) on a second region II of the first substrate 100. Figure 40 ), the thirteenth segment pattern 932 and the fifteenth segment pattern 936, the insulating pad layer 130, the first mask layer 140 and the second cover layer 950.

[0031] In addition, the semiconductor device may include a transistor, a sixth contact plug 750, a sixth wiring structure 800, and a seventh wiring structure 810 located beneath a first region I and a second region II of the second substrate 700.

[0032] The semiconductor device may further include a third insulating layer 600 and a fourth insulating layer 630 on a first region I and a second region II of a first substrate 100, a fifth insulating layer 740 and a sixth insulating layer 820 below the first region and the second region of a second substrate 700, and a bonding layer structure may be disposed between the fourth insulating layer 630 and the sixth insulating layer 820.

[0033] Each of the first substrate 100 and the second substrate 700 may include a semiconductor material (e.g., silicon, germanium, silicon-germanium, etc., or III-V compound semiconductors (such as GaP, GaAs, GaSb, etc.)). In an example embodiment, each of the first substrate 100 and the second substrate 700 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0034] The channels 125 may extend a given length in a second direction D2 on a third region III of the first substrate 100, and the plurality of channels 125 may be spaced apart from each other in the first direction D1 at the same level from the upper surface of the first substrate 100 to form a channel column. As used herein, the term "level" may mean the height or distance from the upper surface of the first substrate 100 in a third direction D3 (e.g., a vertical direction). In an example embodiment, the plurality of channel columns may be spaced apart from each other in the second direction D2 to form a channel array. Additionally, the plurality of channels 125 may be spaced apart from each other in the third direction D3, such that the plurality of channel columns may be spaced apart from each other in the third direction D3 and the plurality of channel arrays may be spaced apart from each other in the third direction D3.

[0035] Semiconductor layer 120 may extend in the first direction D1 on each of the opposing lateral portions of the third region III of the first substrate 100 in the second direction D2. Additionally, first semiconductor pattern 123 may extend in the first direction D1 on each of the opposing lateral portions of the fourth region IV of the first substrate 100 in the second direction D2, and the first semiconductor pattern 123 may contact and connect to semiconductor layer 120. In an example embodiment, each of semiconductor layer 120 and first semiconductor pattern 123 may be disposed at the same height from the upper surface of the first substrate 100 as the corresponding channel in channel 125 (e.g., in the third direction D3).

[0036] The second semiconductor pattern 860 may extend a given length in the second direction D2 on the second region II of the first substrate 100, and a plurality of second semiconductor patterns 860 may be spaced apart from each other in the first direction D1 to form a second semiconductor pattern column. In an example embodiment, the plurality of second semiconductor pattern columns may be spaced apart from each other in the second direction D2 to form a second semiconductor pattern array. Additionally, the plurality of second semiconductor patterns 860 may be spaced apart from each other in the third direction D3, such that the plurality of second semiconductor pattern columns may be spaced apart from each other in the third direction D3 and the plurality of second semiconductor pattern arrays may be spaced apart from each other in the third direction D3. In an example embodiment, each of the second semiconductor patterns 860 may be positioned at the same height from the upper surface of the first substrate 100 as the corresponding channel in the channel 125 (i.e., the corresponding channel) (e.g., in the third direction D3). For example, the second semiconductor pattern in the second semiconductor pattern 860 may be disposed (i.e., arranged) on the second region II of the first substrate 100 in the third direction D3, and the second semiconductor pattern in the second semiconductor pattern 860 may be superimposed (e.g., at least partially superimposed) with the corresponding channel in the channel 125 in the horizontal direction (e.g., see...). Figure 2 For example, the second semiconductor pattern 860 may be on the opposite sidewall of the second plate electrode structure 945 (e.g., in the second direction D2).

[0037] Each of the channel 125, the semiconductor layer 120, the first semiconductor pattern 123, and the second semiconductor pattern 860 may include the same material (e.g., a semiconductor material such as silicon).

[0038] The first gate structure may surround an end of the channel 125 in the second direction D2 and may include a first gate electrode 370, a first gate insulating pattern 360, and a gate mask 380. In an example embodiment, the first gate structure may extend in the first direction D1 and surround an end of the channel 125 in each of the channel columns on a third region III of the first substrate 100, and a plurality of first gate structures may be spaced apart from each other in the second direction D2. For example, the first gate structure may at least partially surround a channel in the channel 125 disposed on a third direction D3. Each of the first gate structures may serve as a word line of a semiconductor device. As used herein, “element A surrounds element B” (or similar language) means that element A is at least partially around element B, but does not necessarily mean that element A completely surrounds element B.

[0039] The first gate insulating pattern 360 may be on the lower and upper surfaces of the end of the channel 125 and on the opposite sidewalls in the first direction D1 (e.g., it may cover the lower and upper surfaces of the end of the channel 125 and the opposite sidewalls in the first direction D1 and / or overlap with the lower and upper surfaces of the end of the channel 125 and the opposite sidewalls in the first direction D1). The first gate insulating pattern 360 may include an oxide (e.g., silicon oxide).

[0040] The first gate electrode 370 may be located on the lower and upper surfaces of a portion of the first gate insulating pattern 360 and on opposite sidewalls in the first direction D1 (e.g., it may cover the lower and upper surfaces of a portion of the first gate insulating pattern 360 and on opposite sidewalls in the first direction D1 and / or overlap with the lower and upper surfaces of a portion of the first gate insulating pattern 360 and on opposite sidewalls in the first direction D1). In an example embodiment, the first gate electrode 370 may extend in the first direction D1 and may be located on a portion of the first gate insulating pattern in the first gate insulating pattern 360 that is disposed in the first direction D1 (e.g., it may cover the portion of the first gate insulating pattern in the first gate insulating pattern 360 that is disposed in the first direction D1 and / or overlap with the portion of the first gate insulating pattern in the first gate insulating pattern 360 that is disposed in the first direction D1). The first gate electrode 370 may include a conductive material (e.g., a metal, a metal nitride, a metal silicide, etc.).

[0041] The gate mask 380 may be located on the lower and upper surfaces of a portion of the first gate insulating pattern 360 and on opposing sidewalls in the first direction D1 (e.g., it may cover the lower and upper surfaces of a portion of the first gate insulating pattern 360 and the opposing sidewalls in the first direction D1 and / or overlap with the lower and upper surfaces of a portion of the first gate insulating pattern 360 and the opposing sidewalls in the first direction D1), and may contact the sidewalls of the first gate electrode 370 in the second direction D2. The gate mask 380 may include an insulating nitride (e.g., silicon nitride).

[0042] Conductive pads 430 may extend in a first direction D1 on a fourth region IV of the first substrate 100, and a plurality of conductive pads 430 may be spaced apart from each other in a second direction D2. In an example embodiment, at least a portion of the conductive pads 430 may (e.g., in a third direction D3) be disposed at the same height as the first gate electrode 370 and may contact the sidewalls of the first gate electrode 370 in the first direction D1 for electrical connection with the first gate electrode 370. In an example embodiment, the conductive pads 430 may be stacked with the first gate structure and the channel 125 in the first direction D1. As used herein, “element A is stacked with element B in direction X” (or similar language) means that there is at least one straight line extending in direction X and intersecting both element A and element B.

[0043] In the example embodiment, the plurality of conductive pads 430 may be spaced apart from each other in the third direction D3, and the length of the conductive pads 430 in the first direction D1 may decrease in a stepped manner from the lowest conductive pad to the highest conductive pad. Therefore, the conductive pads 430 disposed in the third direction D3 can form a stepped structure.

[0044] The conductive pad 430 may include a conductive material (e.g., a metal, a metal nitride, a metal silicide, doped polysilicon, etc.).

[0045] In an example embodiment, the third segmentation structure may include a first insulating pattern 290, a second insulating pattern 300, and a seventh segmentation pattern 310.

[0046] The third segmentation structure can be disposed on the first region I of the first substrate 100, and can be located in the space between the first gate structures stacked along the third direction D3, in the space between the channels 125 stacked along the third direction D3, in the space between the semiconductor layers 120 stacked along the third direction D3, in the space between the upper surface of the first substrate 100 and the lowest first gate structure in the first gate structure, in the space between the upper surface of the first substrate 100 and each of the lowest channel in the channel 125 and the lowest semiconductor layer in the semiconductor layer 120, and in the space between the second mask 320 and the uppermost first gate structure in the first gate structure, the uppermost channel in the channel 125 and the uppermost semiconductor layer in the semiconductor layer 120. The spaces between each of the body layers (e.g., the spaces between first gate structures stacked on third-direction D3, the spaces between channels 125 stacked on third-direction D3, the spaces between semiconductor layers 120 stacked on third-direction D3, the spaces between the upper surface of the first substrate 100 and the lowermost first gate structure in the first gate structure, the spaces between the upper surface of the first substrate 100 and each of the lowermost channel in the channel 125 and the lowermost semiconductor layer in the semiconductor layer 120, and the spaces between the second mask 320 and the uppermost first gate structure in the first gate structure, the uppermost channel in the channel 125 and each of the uppermost semiconductor layer in the semiconductor layer 120). Additionally, the third segmentation structure may be located in the space between channels in adjacent (i.e., adjacent) channels 125 in the second direction D2, and in the space between channel 125 and semiconductor layer 120 (e.g., it may fill the space between channels in adjacent (i.e., adjacent) channels 125 in the second direction D2, and the space between channel 125 and semiconductor layer 120). Furthermore, the third segmentation structure may be disposed on a first region I of the first substrate 100 between channels in adjacent channels 125 in the first direction D1.

[0047] The first insulating pattern 290 and the second insulating pattern 300 may be stacked sequentially on the surface of the channel 125, and the seventh dividing pattern 310 may be disposed on the second insulating pattern 300 and may be in other parts of the space (e.g., may fill other parts of the space).

[0048] The first insulating pattern 290 and the seventh dividing pattern 310 may include oxides (e.g., silicon oxide), and the second insulating pattern 300 may include insulating nitrides (e.g., silicon nitride).

[0049] The eighth segmentation pattern 340 may be disposed on the fourth region IV of the first substrate 100, and may be disposed in the space between the conductive pads 430 and the first semiconductor patterns 123 stacked on the third direction D3, the space between the upper surface of the first substrate 100 and each of the lowermost conductive pads of the conductive pads 430 and the lowermost first semiconductor patterns of the first semiconductor patterns 123, and the space between the second mask 320 and each of the uppermost conductive pads of the conductive pads 430 and the uppermost semiconductor patterns of the semiconductor patterns 123 (e.g., may be filled in the space between the conductive pads 430 and the first semiconductor patterns 123 stacked on the third direction D3, the space between the upper surface of the first substrate 100 and each of the lowermost conductive pads of the conductive pads 430 and the lowermost first semiconductor patterns of the first semiconductor patterns 123, and the space between the second mask 320 and each of the uppermost conductive pads of the conductive pads 430 and the uppermost semiconductor patterns of the semiconductor patterns 123).

[0050] Additionally, the eighth segmentation pattern 340 may be disposed on the fourth region IV of the first substrate 100 between conductive pads adjacent to each other on the third direction D3 in the conductive pad 430 and between the semiconductor pattern 123 and the conductive pad 430.

[0051] In an example embodiment, the length of the eighth segmented pattern 340 disposed on the third direction D3 in the first direction D1 may decrease in a stepped manner from the lowermost eighth segmented pattern to the uppermost eighth segmented pattern, and therefore the stacked structure including the eighth segmented pattern 340 may be a stepped structure. In an example embodiment, the eighth segmented pattern on the corresponding conductive pad at each level in the conductive pad 430 and the corresponding conductive pad in the conductive pad 430 may jointly form a stepped layer, and the sidewall of each of the eighth segmented patterns 340 in the first direction D1 may be aligned with the sidewall of the corresponding conductive pad in the third direction D3 in the conductive pad 430 in the first direction D1 (e.g., may be collinear with the sidewall of the corresponding conductive pad in the third direction D3 in the conductive pad 430 in the first direction D1).

[0052] The eighth segmentation pattern 340 may include an insulating nitride (e.g., silicon nitride).

[0053] The support pattern 210 may be disposed on a first region I of the first substrate 100 and may extend through the semiconductor layer 120, the third segmentation structure, the eighth segmentation pattern 340, and the conductive pad 430 to contact the upper surface of the first substrate 100. A plurality of support patterns 210 may be spaced apart from each other in a first direction D1 in each of the opposing lateral portions in a second direction D2 of a third region III of the first substrate 100, and a plurality of support patterns 210 may be spaced apart from each other in a first direction D1 and a second direction D2 in a fourth region IV of the first substrate 100.

[0054] The support pattern 210 may include an insulating nitride (e.g., silicon nitride) and may be merged with the eighth segmentation pattern 340.

[0055] The second mask 320 may be disposed on the third segmentation structure and the eighth segmentation pattern 340 on the first region I of the first substrate 100. However, the eighth segmentation pattern 340 may be on the sidewall of the second mask 320 (e.g., may cover the sidewall of the second mask 320 and / or overlap with the sidewall of the second mask 320), and therefore the upper surface of the second mask 320 may be coplanar with the upper surface of the eighth segmentation pattern 340. The second mask 320 may include an insulating nitride (e.g., silicon nitride).

[0056] The second insulating interlayer 435 may be disposed on the eighth segmentation pattern 340 on the fourth region IV of the first substrate 100. In an example embodiment, the upper surface of the second insulating interlayer 435 may be coplanar with the upper surface of the second mask 320. The second insulating interlayer 435 may include an oxide (e.g., silicon oxide).

[0057] A fourth segmentation structure 415 may be disposed on a first region I of the first substrate 100 between adjacent channels in the channel 125 in the second direction D2. In an example embodiment, the fourth segmentation structure 415 may extend in the first direction D1 on each of the second regions II and the third regions III of the first substrate 100, and a plurality of fourth segmentation structures 415 may be spaced apart from each other in the second direction D2. In an example embodiment, the upper surface of the fourth segmentation structure 415 may be coplanar with the upper surface of the second mask 320.

[0058] The fourth segmentation structure 415 may include the ninth segmentation pattern 410 and a fourth insulating pattern 400 on the sidewalls and lower surface of the ninth segmentation pattern 410 (e.g., covering the sidewalls and lower surface of the ninth segmentation pattern 410 and / or overlapping with the sidewalls and lower surface of the ninth segmentation pattern 410). The fourth insulating pattern 400 may include an insulating nitride (e.g., silicon nitride), and the ninth segmentation pattern 410 may include an oxide (e.g., silicon oxide).

[0059] Bit lines 440 may extend partially in the third region III of the first substrate 100 in the third direction D3 through a fourth segment structure 415 extending in the first direction D1, and multiple bit lines 440 may be spaced apart from each other in the first direction D1. An eleventh segment pattern 450 comprising an oxide (e.g., silicon oxide) may extend partially through the fourth segment structure 415 between adjacent bit lines in the first direction D1, such that the bit lines 440 may be separated from each other by the eleventh segment pattern 450. Dummy bit lines 445 may be disposed on the portion of the third region III adjacent to the fourth region IV of the first substrate 100.

[0060] In an example embodiment, each of bit line 440 and dummy bit line 445 may contact a channel in channel 125 disposed on a third direction D3 at each of the opposite sides of bit line 440 and dummy bit line 445 in a second direction D2. For example, each of bit line 440 and dummy bit line 445 may contact an end of a channel in channel 125 disposed on a third direction D3. Each of bit line 440 and dummy bit line 445 may contact the sidewalls of the first gate insulating pattern 360 and gate mask 380 in the second direction D2, the first gate insulating pattern 360 and gate mask 380 surrounding an end of each of the channels 125.

[0061] In an example embodiment, each of bit line 440 and dummy bit line 445 may include, for example, polysilicon doped with n-type impurities. In other example embodiments, each of bit line 440 and dummy bit line 445 may include, for example, a metal, a metal nitride, a metal silicide, etc.

[0062] The blocking structure 490 may extend through a third segmentation structure in the channel 125 between adjacent channels in the second direction D2 on the portion of the third region III adjacent to the fourth region IV of the first substrate 100, and may contact the upper surface of the first substrate 100. The blocking structure 490 may be disposed on the opposite side of the bit line 440 in the second direction D2 relative to the channel 125. In an exemplary embodiment, the blocking structure 490 may have a polygonal (such as rectangular) shape in a plan view; however, the inventive concept is not limited thereto.

[0063] In an example embodiment, the blocking structure 490 may include a second blocking pattern 480 extending in the third direction D3 and a first blocking pattern 470 on the sidewalls and lower surface of the second blocking pattern 480 (e.g., covering the sidewalls and lower surface of the second blocking pattern 480 and / or overlapping with the sidewalls and lower surface of the second blocking pattern 480). The first blocking pattern 470 may include an insulating nitride (e.g., silicon nitride), and the second blocking pattern 480 may include an oxide (e.g., silicon oxide).

[0064] The first capacitor structure may include a first capacitor 550 and a first plate electrode 560, and the first capacitor 550 may include a first capacitor electrode 520 and a second capacitor electrode 540 and a first dielectric pattern 530.

[0065] In an example embodiment, the first capacitor electrode 520, the first dielectric pattern 530, and the second capacitor electrode 540 may be sequentially stacked on the third region III of the first substrate 100 in the space between the channels stacked in the third direction D3 in the channel 125, the space between the lowermost channel in the channel 125 and the upper surface of the first substrate 100, and the space between the uppermost channel in the channel 125 and the second mask 320, and the first plate electrode 560 may be in the remaining portion of the space and the space between the adjacent channels in the second direction D2 in the channel 125 (e.g., the remaining portion of the space and the space between the adjacent channels in the second direction D2 in the channel 125 may be filled).

[0066] Therefore, the first plate electrode 560 may include a first vertical extension extending in a third direction D3 and a first horizontal extension extending in a second direction D2 from each of the opposing sidewalls of the first vertical extension. A plurality of first horizontal extensions may be spaced apart from each of the opposing sidewalls of the first vertical extension in the third direction D3. Each of the first capacitor 550 and the first plate electrode 560 may extend in a first direction D1 on a third region III of the first substrate 100. The first plate electrode 560 may include, for example, silicon germanium doped with impurities or undoped silicon germanium.

[0067] In an example embodiment, the first capacitor structure may extend through the first capping layer 500 and the third segmentation structure, and may contact the sidewall of the blocking structure 490 in the first direction D1. Therefore, the first capacitor structure may be arranged relative to the channel 125 on the opposite side of the bit line 440 in the second direction D2.

[0068] A first metal silicide pattern 580 may be disposed at the portion of each of the channels 125 that contacts the first capacitor electrode 520. For example, the first metal silicide pattern 580 may be disposed between each of the channels 125 and the first capacitor 550. The first metal silicide pattern 580 may include a metal silicide (e.g., titanium silicide, tantalum silicide, etc.).

[0069] Word lines (e.g., first gate structures) and bit lines 440 extending in the first direction D1 and the second direction D2 respectively on the third region III of the first substrate 100, a channel 125 that can be surrounded by word lines and contacted and electrically connected to the bit lines 440, and a first capacitor 550 electrically connected to the channel 125 can jointly form a memory cell, and a plurality of memory cells can be disposed on each of the first direction to the third direction D1, D2 and D3 on the third region III of the first substrate 100.

[0070] The first capping layer 500 may be disposed on the first region I of the first substrate 100 on the second mask 320, the second insulating interlayer 435, and the fourth segmentation structure 415, and may be on the upper sidewall of the first capacitor structure (e.g., covering the upper sidewall of the first capacitor structure and / or overlapping with the upper sidewall of the first capacitor structure). The first capping layer 500 may include an insulating nitride (e.g., silicon nitride).

[0071] The third sacrificial pattern 850 and the fifth insulating pattern 918 may be disposed between adjacent second semiconductor patterns in the second semiconductor pattern 860 on the second region II of the first substrate 100, on the upper surface of the uppermost second semiconductor pattern in the second semiconductor pattern 860, and between the upper surface of the first substrate 100 and the lower surface of the lowermost second semiconductor pattern in the second semiconductor pattern 860. The sidewalls of the third sacrificial pattern 850 and the fifth insulating pattern 918 in the second direction D2 may contact each other. The third sacrificial pattern 850 and the fifth insulating pattern 918 may be superimposed on the second semiconductor pattern 860 disposed at each of the opposite edges in the second direction D2 of the semiconductor pattern 860 disposed in each of the first direction D1 and the second direction D2 in the third direction D3.

[0072] The third sacrificial pattern 850 may include a material (e.g., silicon-germanium) that is etch-selective relative to the second semiconductor pattern 860, and the fifth insulating pattern 918 may include an oxide (e.g., silicon oxide).

[0073] Insulating pad 130 and first mask layer 140 may be sequentially stacked on the upper surfaces of the uppermost third sacrificial pattern in the third sacrificial pattern 850 and the uppermost fifth insulating pattern in the fifth insulating pattern 918 in the third direction D3. A plurality of first mask layers 140 may be spaced apart from each other in each of the first direction D1 and the second direction D2, and may be stacked with the second semiconductor pattern 860 in the third direction D3.

[0074] The insulating pad 130 may include an oxide (e.g., silicon oxide), and the first mask layer 140 may include an insulating nitride (e.g., silicon nitride).

[0075] Reference Figure 40 Multiple twelfth segment patterns 870 may be spaced apart from each other on the second region II of the first substrate 100 in each of the first direction D1 and the second direction D2.

[0076] The twelfth segment pattern 870 may extend in the third direction D3, and some of the twelfth segment patterns 870 (e.g., the twelfth segment patterns in the twelfth segment pattern 870 disposed at each of the opposite edges in the second direction D2) may contact the sidewalls of each of the third sacrificial pattern 850, the fifth insulating pattern 918, the second semiconductor pattern 860, the insulating pad layer 130 and the first mask layer 140 in the first direction D1.

[0077] The twelfth dividing pattern 870 may include a material (e.g., an insulating nitride (such as silicon nitride)) that has etch selectivity relative to the fifth insulating pattern 918.

[0078] Return to reference Figures 1 to 6 and Figure 40 The fifteenth dividing pattern 936 may extend in the first direction D1 on the second region II of the first base 100, and the plurality of fifteenth dividing patterns 936 may be spaced apart from each other in the second direction D2. The sidewalls and lower surfaces of the fifteenth dividing pattern 936 may have pads 920 thereon (e.g., the sidewalls and lower surfaces of the fifteenth dividing pattern 936 may be covered and / or stacked by pads 920).

[0079] The fifteenth segment pattern 936 may extend in the third direction D3, and the pad 920 on the sidewall of the fifteenth segment pattern 936 may contact the sidewalls of the fifth insulating pattern 918, the second semiconductor pattern 860, the insulating pad layer 130 and the first mask layer 140 stacked in the third direction D3 in the second direction D2, and the sidewall of the twelfth segment pattern 870 in the second direction D2.

[0080] The fifteenth dividing pattern 936 may include oxides (e.g., silicon oxide), and the pad 920 may include insulating nitrides (e.g., silicon nitride).

[0081] The second capacitor structure may include a second capacitor 960 on a second region II of the first substrate 100, as well as a second plate electrode structure 945 and a third plate electrode structure 970. In other words, the second plate electrode structure 945, the third plate electrode structure 970, and the second capacitor 960 on the second region II of the first substrate 100 may be included in the second capacitor structure. For example, a plurality of second capacitor structures may be arranged on the second region II of the first substrate 100 in a second direction D2.

[0082] The second capacitor 960 may include a third capacitor electrode 962, a second dielectric pattern 964, and a fourth capacitor electrode 966 stacked sequentially. The second plate electrode structure 945 may include a first conductive pattern to a third conductive pattern 942, 944, and 946 stacked sequentially on a third direction D3. The third plate electrode structure 970 may include a fourth conductive pattern to a sixth conductive pattern 965, 967, and 969 stacked sequentially on a third direction D3.

[0083] The first conductive pattern 942 included in the second plate electrode structure 945 may extend in the second region II of the first substrate 100 in the first direction D1 and the third direction D3. A plurality of first conductive patterns 942 may be spaced apart from each other in the second direction D2 between adjacent fifteenth segmented patterns in the fifteenth segmented pattern 936. In an exemplary embodiment, the upper surface of the first conductive pattern 942 may be higher than the lower surface of the first mask layer 140 (e.g., relative to the upper surface of the first substrate 100 in the third direction D3); however, the inventive concept is not limited thereto.

[0084] The thirteenth segment pattern 932 and the pad 920 may be stacked on the sidewall of the first conductive pattern 942 in the second direction D2, specifically on the sidewall of the first conductive pattern 942 facing the first portion of the twelfth segment pattern 870 and on the sidewall of the second portion of the first conductive pattern 942 that overlaps with the second semiconductor pattern 860 in the second direction D2. Therefore, the structure including the thirteenth segment pattern 932 and the pad 920 on the sidewall of the first portion of the first conductive pattern 942 may extend in the third direction D3, and multiple structures including the thirteenth segment pattern 932 and the pad 920 on the sidewall of the second portion of the first conductive pattern 942 may be spaced apart from each other in the third direction D3. For example, the structure including the thirteenth segment pattern 932 and the pad 920 may be between (e.g., in the second direction D2) the sidewall of the second plate electrode structure 945 (e.g., the sidewall of the first conductive pattern 942) and the sidewall of each of the second semiconductor patterns 860, and may contact the sidewall of the second plate electrode structure 945 (e.g., the sidewall of the first conductive pattern 942) and the sidewall of each of the second semiconductor patterns 860. For example, the thirteenth segment pattern 932 and the pad 920 may be sequentially stacked on the sidewall of the second plate electrode structure 945 (e.g., the sidewall of the first conductive pattern 942) in the second direction D2.

[0085] The thirteenth dividing pattern 932 and the pad 920 may also be disposed on the sidewall of the third portion of the first conductive pattern 942 facing the first mask layer 140, and may contact the sidewall of the first mask layer 140 in the second direction D2. Additionally, the thirteenth dividing pattern 932 and the pad 920 may be disposed on the lower surface and lower sidewall of the first conductive pattern 942, and may contact the upper surface of the first substrate 100.

[0086] The thirteenth dividing pattern 932 may include an oxide (e.g., silicon oxide), and the pad 920 may include an insulating nitride (e.g., silicon nitride). Thus, the sequentially stacked thirteenth dividing pattern 932 and pad 920 can collectively form an insulating layer structure. As used herein, the thirteenth dividing pattern 932 and pad 920 may also be referred to as the first insulating layer and the second insulating layer of the insulating layer structure, respectively.

[0087] In an example embodiment, the first conductive pattern 942 may include, for example, polycrystalline silicon doped with impurities, the second conductive pattern 944 may include metal silicides (e.g., tungsten silicide, titanium silicide, etc.), and the third conductive pattern 946 may include metal (e.g., tungsten). In other example embodiments, the first to third conductive patterns 942, 944, and 946 may include metal (e.g., tungsten) and may be merged together, and the second plate electrode structure 945 may have a monolayer structure.

[0088] The third capacitor electrode 962, included in the second capacitor 960, can contact a portion of the sidewall of the first conductive pattern 942 in the second direction D2 on the second region II of the first substrate 100 (specifically, the sidewall of the portion of the first conductive pattern 942 overlapping with the fifth insulating pattern 918 in the second direction D2, the upper and lower surfaces of the second semiconductor pattern 860 and its sidewall in the second direction D2, and the opposing sidewall of the twelfth segmented pattern 870 in the first direction D1 and its sidewall in the second direction D2). Additionally, the third capacitor electrode 962 can contact the thirteenth segmented pattern 932 on the sidewall of the first conductive pattern 942 in the second direction D2 and the upper and lower surfaces of the pad 920.

[0089] A second metal silicide pattern 865 may be disposed on the portion of the second semiconductor pattern 860 that contacts the third capacitor electrode 962. For example, the second metal silicide pattern 865 may be between each of the second semiconductor patterns 860 and a corresponding second capacitor (i.e., a respective second capacitor) in the second capacitor 960. The second metal silicide pattern 865 may include a metal silicide (e.g., titanium silicide, tantalum silicide, etc.).

[0090] In an example embodiment, the second capacitor 960 may extend in a first direction D1 between second plate electrode structures that are adjacent to each other in a second direction D2 in the second plate electrode structure 945, and may extend in a third direction D3.

[0091] Each of the first to fourth capacitor electrodes 520, 540, 962, and 966 may include a metal (e.g., titanium, tantalum, etc.) or a metal nitride (e.g., titanium nitride, tantalum nitride, etc.). Each of the first dielectric pattern 530 and the second dielectric pattern 964 may include a high-k metal oxide (e.g., hafnium oxide, zirconium oxide, etc.).

[0092] The third plate electrode structure 970 may be located within the space defined by the second capacitor 960 (e.g., may fill the space defined by the second capacitor 960) and may extend in the first direction D1 over the second region II of the first substrate 100. Therefore, the third plate electrode structure 970 may contact the fourth capacitor electrode 966 included in the second capacitor 960. For example, a pair of third plate electrode structures 970 may be located on opposite sidewalls of the second plate electrode structure 945 (e.g., in the second direction D2) and on the second region II of the first substrate 100.

[0093] In an example embodiment, the fourth conductive pattern 965 included in the third plate electrode structure 970 may include a second vertical extension and a second horizontal extension. The second vertical extension extends in a third direction D3, and the second horizontal extension extends from each of the opposing sidewalls of the second vertical extension in a second direction D2. A plurality of second horizontal extensions of the fourth conductive pattern 965 may be spaced apart from each of the opposing sidewalls of the second vertical extensions in the third direction D3. In other words, the third plate electrode structure 970 (e.g., the fourth conductive pattern 965) may include a second vertical extension and a second horizontal extension, the second vertical extension extending in the third direction D3, and the second horizontal extensions spaced apart from each other in the third direction D3 and extending in the second direction D2.

[0094] In an example embodiment, portions of the second capacitor 960 on the sidewalls of each of the second horizontal extensions of the fourth conductive pattern 965 are accessible to the sidewalls of the first conductive pattern 942 included in the second plate electrode structure 945 and are electrically connected to the first conductive pattern 942.

[0095] In an example embodiment, each of the second horizontal extensions of the fourth conductive pattern 965 may be disposed between second semiconductor patterns in the second semiconductor pattern 860 that are adjacent to each other in the third direction D3. Therefore, each of the second horizontal extensions of the fourth conductive pattern 965 may at least partially overlap with a corresponding second semiconductor pattern in the second semiconductor pattern 860 in the third direction D3.

[0096] The fifth conductive pattern 967 and the sixth conductive pattern 969 may be stacked on the upper surface of the fourth conductive pattern 965 on the third direction D3. In an example embodiment, the upper surface of the fifth conductive pattern 967 may be lower than the lower surface of the first mask layer 140 (e.g., on the third direction D3 relative to the upper surface of the first substrate 100); however, the inventive concept is not limited thereto.

[0097] The fourth conductive pattern 965 may include, for example, impurity-doped polycrystalline silicon or impurity-doped silicon-germanium, the fifth conductive pattern 967 may include metal silicides (e.g., tungsten silicide, titanium silicide, etc.), or compounds of metal and silicon-germanium (e.g., tungsten-silicon-germanium, titanium-silicon-germanium, etc.), and the sixth conductive pattern 969 may include metals (e.g., tungsten).

[0098] The second capping layer 950 may be disposed on the upper surface of the first mask layer 140, the uppermost surface of the pad 920 and the thirteenth dividing pattern 932, and the upper surface of the twelfth dividing pattern 870 and the fifteenth dividing pattern 936 in the second region II of the first substrate 100, and may be on the upper sidewall of the second capacitor 960 (e.g., covering the upper sidewall of the second capacitor 960 and / or stacked with the upper sidewall of the second capacitor 960). The second capping layer 950 may include an insulating nitride (e.g., silicon nitride).

[0099] The third insulating interlayer 600 and the fourth insulating interlayer 630, the first bonding layer 640 and the second bonding layer 830, the sixth insulating interlayer 820 and the fifth insulating interlayer 740, and the second substrate 700 may be sequentially stacked on the first region I and the second region II of the first substrate 100 in a third direction D3 on the first capping layer 500 and the second capping layer 950, as well as the first capacitor structure and the second capacitor structure.

[0100] The first contact plug 612 can extend through the third insulating interlayer 600 and the first cover layer 500 and can contact the upper surface of the bit line 440. The second contact plug 614 can extend through the third insulating interlayer 600 and can contact the upper surface of the first plate electrode 560 included in the first capacitor structure. The third contact plug 616 can extend through the third insulating interlayer 600, the first cover layer 500, the second mask 320 and the eighth dividing pattern 340 or the third insulating interlayer 600, the first cover layer 500 and the second insulating interlayer 435 and can contact the upper surface of the conductive pad 430.

[0101] The fourth contact plug 618 extends through the third insulating interlayer 600 and the second cover layer 950 and is accessible to the upper surface of the third conductive pattern 946 included in the second plate electrode structure 945, and the fifth contact plug 619 extends through the third insulating interlayer 600 and is accessible to the upper surface of the sixth conductive pattern 969 included in the third plate electrode structure 970.

[0102] The first to fifth wiring structures 622, 624, 626, 628, and 629 may be disposed in the fourth insulating interlayer 630 and may respectively contact the upper surfaces of the first to fifth contact plugs 612, 614, 616, 618, and 619. A first bonding layer 640 may include a first bonding pad 645, and a second bonding layer 830 may include a second bonding pad 835. The first bonding pad 645 and the second bonding pad 835 may contact each other. Each of the first bonding pads 645 may contact and be electrically connected to the corresponding wiring structure in the first to fifth wiring structures 622, 624, 626, 628, and 629.

[0103] The sixth wiring structure 800 and the seventh wiring structure 810 may be disposed on the first region I and the second region II of the first substrate 100, respectively, and may have a sixth insulating interlayer 820 thereon (e.g., the sixth wiring structure 800 and the seventh wiring structure 810 may be covered and / or stacked by the sixth insulating interlayer 820). The sixth wiring structure 800 and the seventh wiring structure 810 may contact and be electrically connected to the corresponding second bonding pads in the second bonding pads 835. The sixth contact plug 750 may be disposed in the fifth insulating interlayer 740 and may contact the corresponding wiring structures in the sixth wiring structure 800 and the seventh wiring structure 810, respectively.

[0104] A second gate structure 730, including a second gate insulating pattern 710 and a second gate electrode 720, may be disposed below the first region I of the second substrate 700, and an impurity region 705 may be disposed in the lower portion of the second substrate 700 adjacent to the second gate structure 730. The second gate structure 730 and the impurity region 705 may jointly form a transistor.

[0105] In a semiconductor device, a memory cell may be disposed in the memory cell region, and a second capacitor structure having a structure similar to the first capacitor structure may be disposed in the lower part of the peripheral circuit region.

[0106] That is, the first capacitor 550 included in the first capacitor structure on the first region I of the first substrate 100 may include a first capacitor electrode 520, a first dielectric pattern 530, and a second capacitor electrode 540 stacked on the surface of the channel 125 at each horizontal level, and a first metal silicide pattern 580 may be disposed on the portion of the channel 125 that contacts the first capacitor electrode 520. For example, a bit line 440 may be on a first end of the channel 125 disposed in a third direction D3, and the first capacitor 550 may be on a second end of the channel 125 opposite to the corresponding first end (e.g., opposite in a second direction D2). The second capacitor 960 included in the second capacitor structure on the second region II of the first substrate 100 may include a third capacitor electrode 962, a second dielectric pattern 964, and a fourth capacitor electrode 966, and a second metal silicide pattern 865 may be disposed on the portion of the second semiconductor pattern 860 that contacts the third capacitor electrode 962. Therefore, the first capacitor 550 and the second capacitor 960 may be at least partially stacked on each other in the horizontal direction.

[0107] The portions of the first capacitor 550 on the surfaces of the first capacitor 550 at various levels of the channel 125 may be connected to each other at the sidewalls of the seventh segment pattern 310, and thus the first capacitor 550 may extend in the third direction D3. Similarly, the portions of the second capacitor 960 on the surfaces of the second semiconductor pattern 860 at various levels may be connected to each other at the sidewalls of the first conductive pattern 942, and thus the second capacitor 960 may extend in the third direction D3. In other words, as used herein, it can be interpreted that the second capacitor 960 extends in the third direction D3 along the second semiconductor pattern 860 disposed in the third direction D3. For example, when interpreted as the second capacitor 960 extending in the third direction D3 along the second semiconductor pattern 860 disposed in the third direction D3, a pair of second capacitors 960 may be on opposite sidewalls of the second plate electrode structure 945 (e.g., in the second direction D2). A pair of second capacitors 960 may each contact a corresponding sidewall in the opposite sidewall of the second plate electrode structure 945, and may be on the upper and lower surfaces and sidewalls of each of the second semiconductor patterns in the second semiconductor pattern 860.

[0108] However, as used herein, it can also be interpreted that at the first capacitor 550 extending in the third direction D3, a portion of the surface of each of the channels 125 may be referred to as the first capacitor 550, and a plurality of first capacitors 550 may be connected to each other in the third direction D3. Similarly, as used herein, it can also be interpreted that at the second capacitor 960 extending in the third direction D3, a portion of the surface of each of the second semiconductor patterns 860 may be referred to as the second capacitor 960, and a plurality of second capacitors 960 may be connected to each other in the third direction D3. In other words, as used herein, it can be interpreted that a plurality of second capacitors 960 are arranged in the third direction D3 and respectively on the second semiconductor patterns of the second semiconductor patterns 860 disposed in the third direction D3. In other words, as used herein, it can be interpreted as the second capacitor 960 extending along the second semiconductor pattern 860 disposed on the third direction D3, or it can be interpreted as a plurality of second capacitors 960 arranged on the third direction D3 and respectively on the second semiconductor pattern 860 disposed on the third direction D3. For example, when interpreted as a plurality of second capacitors 960 arranged on the third direction D3, the plurality of second capacitors 960 arranged on the third direction D3 may be physically and / or electrically connected to each other, the first second capacitor of the plurality of second capacitors 960 may be on the first sidewall of the second plate electrode structure 945, and the second second capacitor of the plurality of second capacitors 960 may be on the second sidewall of the second plate electrode structure 945 opposite to the first sidewall (e.g., in the second direction D2).

[0109] The portions of the second capacitor 960 on the surfaces of the horizontal extensions of the third plate electrode structure 970, which respectively extend in the first direction D1, can be connected to each other at the sidewalls of the twelfth dividing pattern 870, and thus the second capacitor 960 can extend in the first direction D1. However, as used herein, it can also be interpreted that only the portions of the second capacitor 960 on the surfaces of each of the horizontal extensions of the third plate electrode structure 970 can be referred to as the second capacitor 960, and a plurality of second capacitors 960 can be connected to each other in the first direction D1. For example, the second capacitors among the second capacitors 960 can be arranged in the first direction D1 and can be connected to each other in the first direction D1 (e.g., physically and / or electrically connected to each other).

[0110] In an example embodiment, the first capacitor 550 included in the first capacitor structure may be a cell capacitor for data storage, and the second capacitor 960 included in the second capacitor structure may be a power capacitor. The second capacitor 960 may include, for example, a decoupling capacitor for noise cancellation, or a pump capacitor included in a pump circuit.

[0111] Reference Figure 7 and Figure 8 The second capacitor structure may include a unit capacitor structure UC, which includes a second plate electrode structure 945 extending in a first direction D1, a third plate electrode structure 970 extending in the first direction D1 at opposite sides (i.e., opposite sidewalls) of the second plate electrode structure 945 in the second direction D2, and a second capacitor 960 disposed in the first direction D1 between each of the second plate electrode structure 945 and the third plate electrode structure 970. Multiple unit capacitor structures UC may be disposed in the second direction D2 and electrically connected to each other. The unit capacitor structure UC may have a symmetrical shape in the second direction D2 relative to the second plate electrode structure 945. For example, the second capacitor 960 and the third plate electrode structure 970 included in the unit capacitor structure UC may be symmetrical in the second direction D2 relative to the second plate electrode structure 945 included in the unit capacitor structure UC (e.g., see...). Figure 8 ).

[0112] Figure 7 and Figure 8 The diagram shows three unit capacitor structures connected to each other, arranged in the second direction D2. Each of the second plate electrode structure 945 and the third plate electrode structure 970 may extend in the third direction D3, and a plurality of second capacitors 960 may be spaced apart from each other in the first direction D1 and the third direction D3 between the second plate electrode structure 945 and the third plate electrode structure 970.

[0113] In an example embodiment, a third capacitor electrode 962 (see [reference needed]) is included in each of the second capacitors 960. Figure 6 The second plate electrode structure 945 is accessible and electrically connected to the second plate electrode structure 945, and the fourth capacitor electrode 966 (see...) Figure 6 The second plate electrode structure 945 may be in contact with and electrically connected to the third plate electrode structure 970. For example, the second plate electrode structure 945 may extend on the first substrate 100 in a third direction D3 and may be in common contact with the second capacitor in the second capacitor 960 (e.g., may be physically and / or electrically connected to the second capacitor in the second capacitor 960).

[0114] In an example embodiment, the source voltage V can be transmitted via, for example, a fourth contact plug 618. SS The voltage V is applied to each of the second plate electrode structures 945 included in the second capacitor structure, and the drain voltage V can be transmitted via, for example, the fifth contact plug 619. DD It is applied to each of the third plate electrode structures 970 included in the second capacitor structure. Therefore, it is related to the source voltage V. SS and drain voltage V DDThe same voltage corresponding to the difference between them can be jointly applied to the second capacitor 960 included in each of the unit capacitor structures UC, such that the second capacitors 960 can be connected in parallel. Therefore, the capacitance of the second capacitor structure can be the sum of the capacitances of the second capacitors 960 included in the second capacitor structure.

[0115] However, the inventive concept is not limited thereto, and the second capacitor structure may include unit capacitor structures electrically connected to each other in various ways, as will be referred to below. Figures 46 to 52 Let's discuss this in more detail.

[0116] The semiconductor device may include a second capacitor structure at the lower part of the peripheral circuit region, and the second capacitor structure may be used as a decoupling capacitor or a pump capacitor to enhance the electrical characteristics of the semiconductor device.

[0117] Figures 9 to 45 These are vertical and horizontal sectional views illustrating a method of manufacturing a semiconductor device according to an example embodiment.

[0118] Figures 10 to 31 as well as Figure 43 and Figure 44 This is a diagram of the first region I of the first substrate 100. Specifically, Figure 10 , Figure 12 , Figure 14 , Figure 16 , Figure 18 , Figure 20 , Figure 22 , Figure 24 , Figure 26 , Figure 28 and Figure 30 These are the horizontal sectional views at the first height H1 of the corresponding vertical sectional view. Figure 11 , Figure 25 and Figure 43 These are the vertical sectional views taken along line A-A' of the corresponding horizontal sectional view. Figure 13 , Figure 15 , Figure 19 and Figure 23 These are the vertical sectional views taken along line B-B' of the corresponding horizontal sectional view. Figure 17 , Figure 21 , Figure 27 , Figure 31 and Figure 44 These are vertical sectional views taken along line C-C' of the corresponding horizontal sectional view, and... Figure 29 It is a vertical sectional view taken along the line E-E' of the corresponding horizontal sectional view.

[0119] Figures 32 to 42 and Figure 45 This is a diagram of the second region II of the first substrate 100. Specifically, Figure 32 , Figure 34 , Figure 36 , Figure 38 and Figure 40 These are horizontal sectional views taken at the second height H2 of the corresponding vertical sectional view, and... Figure 33 , Figure 35 , Figure 37 , Figure 39 , Figure 41 , Figure 42 and Figure 45 These are the vertical sectional views taken along line F-F' of the corresponding horizontal sectional view.

[0120] Figure 9 It is a vertical sectional view of the first region I and the second region II of the first base 100.

[0121] Reference Figure 9 The sacrificial layer 110 and the semiconductor layer 120 may be alternately and repeatedly stacked on the first substrate 100 including the first region I and the second region II (see reference). Figure 1 and Figure 2 To form a molded layer.

[0122] Figure 9 The diagram shows that the sacrificial layer 110 and the semiconductor layer 120 are stacked on the first substrate 100 at four and three levels, respectively, but this disclosure is not limited thereto, and the sacrificial layer 110 and the semiconductor layer 120 may be stacked at more than four levels and less than three levels, respectively.

[0123] In an example embodiment, the molding layer can be formed by an epitaxial growth process that uses the upper surface of the first substrate 100 as a seed.

[0124] In an example embodiment, semiconductor layer 120 may include, for example, silicon, and sacrificial layer 110 may include a material (e.g., silicon-germanium) that has etch selectivity relative to semiconductor layer 120.

[0125] The insulating pad 130 and the first mask layer 140 may be sequentially stacked on the molding layer in a third direction D3. The insulating pad 130 may include an oxide (e.g., silicon oxide), and the first mask layer 140 may include an insulating nitride (e.g., silicon nitride).

[0126] Reference Figure 10 and Figure 11 For example, a dry etching process can be performed on the first mask layer 140, the insulating pad layer 130 and the molding layer to form a first opening 150 on a first region I of the first substrate 100 that extends through the first mask layer 140, the insulating pad layer 130 and the molding layer and exposes the upper surface of the first substrate 100, and a first segmentation structure 180 can be formed in the first opening 150.

[0127] In an example embodiment, the first segmentation structure 180 may have a grid shape in a plan view, and thus a plurality of memory block regions may be defined on a first region I of the first substrate 100 in each of the first direction D1 and the second direction D2, each of the memory block regions may have, for example, a rectangular shape in a plan view. However, the inventive concept is not limited thereto, and each of the memory block regions may have other shapes in a plan view. Figure 10 This shows a portion of the first segmentation structure 180.

[0128] In an example embodiment, each of the memory block regions may include a third region III and a fourth region IV arranged in the first direction D1.

[0129] In an example embodiment, the first segmentation structure 180 may include a first segmentation pattern 160 on the sidewalls and bottom of the first opening 150 and a second segmentation pattern 170 in the remaining portion of the first opening 150 (e.g., filling the remaining portion of the first opening 150). The sidewalls and lower surface of the second segmentation pattern 170 may have the first segmentation pattern 160 thereon (e.g., may be covered and / or superimposed by the first segmentation pattern 160). The first segmentation pattern 160 may include an insulating nitride (e.g., silicon nitride), and the second segmentation pattern 170 may include an oxide (e.g., silicon oxide).

[0130] For example, a dry etching process can be performed on the first mask layer 140, the insulating pad layer 130 and the molding layer to form a second opening 190 on a first region I of the first substrate 100 that extends through the first mask layer 140, the insulating pad layer 130 and the molding layer and exposes the upper surface of the first substrate 100, and a third segmentation pattern 200 can be formed in the second opening 190.

[0131] In an example embodiment, the third segmentation pattern 200 may have stripes extending in the second direction D2 in a plan view, and a plurality of third segmentation patterns 200 may be spaced apart from each other in each of the first direction D1 and the second direction D2. The third segmentation pattern 200 may include an oxide (e.g., silicon oxide).

[0132] Reference Figure 12 and Figure 13 For example, a dry etching process can be performed on the first mask layer 140, the insulating pad layer 130 and the molding layer to form a third opening on the first region I of the first substrate 100 that extends through the first mask layer 140, the insulating pad layer 130 and the molding layer and exposes the upper surface of the first substrate 100, and a support pattern 210 can be formed in the third opening.

[0133] In an example embodiment, the support pattern 210 may have a shape in a plan view such as a circle, ellipse, polygon, or polygon with rounded corners, and a plurality of support patterns 210 may be spaced apart from each other in each of the first direction D1 and the second direction D2. The support pattern 210 may include an insulating nitride (e.g., silicon nitride).

[0134] A first insulating interlayer 220 may be formed on a first region I of the first substrate 100 on the first mask layer 140, the first segmentation structure 180, the third segmentation pattern 200, and the support pattern 210. The first insulating interlayer 220 may include oxides (e.g., silicon oxide).

[0135] Reference Figure 14 and Figure 15 For example, a dry etching process can be performed on the first insulating interlayer 220, the first mask layer 140, the insulating pad layer 130 and the molding layer to form a fourth opening 230 that extends through the first insulating interlayer 220, the first mask layer 140, the insulating pad layer 130 and the molding layer and exposes the upper surface of the first substrate 100, and a second segmentation structure 270 can be formed in the fourth opening 230.

[0136] In an example embodiment, the second segmentation structure 270 may have a stripe extending in the first direction D1 in a plan view, and a plurality of second segmentation structures 270 may be spaced apart from each other in the fourth region IV in the second direction D2. In an example embodiment, each of the second segmentation structures 270 may overlap in the first direction D1 with a portion of the molding layer between the adjacent third segmentation pattern in the third segmentation pattern 200 in the second direction D2.

[0137] In an example embodiment, the second segmentation structure 270 may include fourth to sixth segmentation patterns 240, 250, and 260 sequentially stacked from the sidewalls and bottom of the fourth opening 230. Each of the fourth segmentation pattern 240 and the sixth segmentation pattern 260 may include an oxide (e.g., silicon oxide), and the fifth segmentation pattern 250 may include an insulating nitride (e.g., silicon nitride).

[0138] When forming the second segmentation structure 270, portions of the sacrificial layer 110 and the semiconductor layer 120, which are part of the molded layer in the fourth region IV, can be transformed into the first sacrificial pattern 115 and the first semiconductor pattern 123, respectively.

[0139] Reference Figure 16 and Figure 17For example, a dry etching process can be performed on the first insulating interlayer 220, the first mask layer 140, the insulating pad layer 130 and the molding layer to form a fifth opening 280 that extends through the first insulating interlayer 220, the first mask layer 140, the insulating pad layer 130 and the molding layer and exposes the upper surface of the first substrate 100.

[0140] In an example embodiment, the fifth opening 280 may extend in the first direction D1 between adjacent third segmentation patterns in the second direction D2 of the third segmentation pattern 200, and a plurality of fifth openings 280 may be spaced apart from each other in the second direction D2 in the third region III. Each of the fifth openings 280 may be aligned in the first direction D1 with a corresponding second segmentation structure in the second segmentation structure 270, and may expose the sidewall of the fourth segmentation pattern 240 at the end of the second segmentation structure 270 in the first direction D1.

[0141] When the fifth opening 280 is formed, the portions of the third segmentation pattern 200 of the sacrificial layer 110 and the semiconductor layer 120 in the first region I of the first substrate 100 between adjacent third segmentation patterns in the first direction D1 and between the fifth opening 280 can be transformed into the second sacrificial pattern and the channel 125, respectively, and the portions of the insulating pad layer 130 and the first mask layer 140 on the second sacrificial pattern can be retained as the insulating pad and the first mask 145, respectively.

[0142] For example, a wet etching process can be performed through the fifth opening 280 to remove a portion of the second sacrificial pattern in the third region III, and also to remove most of the third segmented pattern 200 in the third region III adjacent to the fifth opening 280 and the insulating pad.

[0143] Therefore, the first gap can be formed in the third region III between adjacent channels in the third direction D3, between the uppermost channel in the channel 125 and the first mask 145, and between the lowermost channel in the channel 125 and the upper surface of the first substrate 100. Additionally, the first gap can be widened in the first direction D1 such that portions of the third segmentation pattern 200 at the same level as each of the channels 125 can be retained, and other portions of the third segmentation pattern 200 can be removed.

[0144] A first insulating layer and a second insulating layer may be sequentially stacked on the inner wall of the first gap, the sidewalls and bottom of the fifth opening 280, and the upper surface of the first insulating interlayer 220. A seventh dividing layer may be formed on the second insulating layer to fill the first gap and the fifth opening 280 (e.g., to fill the first gap and the fifth opening 280). The seventh dividing layer, the first insulating layer, the second insulating layer, the first insulating interlayer 220, and the second dividing structure 270 may be planarized until the upper surface of the first mask 145 is exposed. Therefore, a third dividing structure including a first insulating pattern 290, a second insulating pattern 300, and a seventh dividing pattern 310 may be formed in the first gap and the fifth opening 280, and the first insulating interlayer 220 may be removed. The planarization process may include, for example, a chemical mechanical polishing (CMP) process and / or an etch-back process.

[0145] The first insulating pattern 290 and the seventh dividing pattern 310 may comprise oxides (e.g., silicon oxide), and the second insulating pattern 300 may comprise insulating nitrides (e.g., silicon nitride). A third dividing pattern 200 retained between channels 125 may merge with the first insulating pattern 290, and hereinafter, the merged structure may be referred to as the first insulating pattern 290. In some embodiments, portions of the first insulating pattern 290 and the fourth dividing pattern 240 exposed through the fifth opening 280 may contact each other to merge.

[0146] Reference Figure 18 and Figure 19 A second mask 320 can be formed on the first mask layer 140, the first mask 145, and the third segmentation structure. For example, a dry etching process using the second mask 320 as an etching mask can be performed to remove the second segmentation structure 270, thereby forming a sixth opening 330 that exposes the upper surface of the first substrate 100. The portion of the first sacrificial pattern 115 adjacent to the sixth opening 330 can be removed through the sixth opening 330, and the insulating pad layer 130 can also be removed.

[0147] Therefore, the second gap can be formed between adjacent first semiconductor patterns in the third direction D3 of the first semiconductor pattern 123, between the uppermost first semiconductor pattern in the first semiconductor pattern 123 and the first mask layer 140, and between the lowermost first semiconductor pattern in the first semiconductor pattern 123 and the first substrate 100.

[0148] The second mask 320 may include an insulating nitride (e.g., silicon nitride), and the first mask layer 140 and the first mask 145 may be incorporated into the second mask 320. Hereinafter, the incorporated structure may be referred to as the second mask 320.

[0149] An eighth segmentation layer may be formed on the first substrate 100 and the second mask 320 to fill the second gap and the sixth opening 330 (e.g., to fill the second gap and the sixth opening 330), and the eighth segmentation layer may be subjected to a planarization process until the upper surface of the second mask 320 is exposed to form an eighth segmentation pattern 340 in the second gap and the sixth opening 330. The eighth segmentation pattern 340 may include an insulating nitride (e.g., silicon nitride), and therefore, in some embodiments, the support pattern 210 may be incorporated into the eighth segmentation pattern 340.

[0150] Reference Figure 20 and Figure 21 The second mask 320 and the third segmentation structure can be partially removed, for example, by a dry etching process, to form a seventh opening 350 on the first region I of the first substrate 100 that exposes the upper surface of the first substrate 100.

[0151] In an example embodiment, the lower and upper surfaces of the end of the channel 125 in the second direction D2, as well as the sidewalls, can be exposed through the seventh opening 350.

[0152] For example, a thermal oxidation process can be performed to form a first gate insulating pattern 360 on the lower and upper surfaces and sidewalls of the end of the channel 125 exposed through the seventh opening 350 (e.g., a first gate insulating pattern 360 covering the lower and upper surfaces and sidewalls of the end of the channel 125 exposed through the seventh opening 350 and / or a first gate insulating pattern 360 superimposed on the lower and upper surfaces and sidewalls of the end of the channel 125 exposed through the seventh opening 350).

[0153] A first gate electrode layer may be formed on the sidewalls and bottom of the seventh opening 350 and on the first gate insulating pattern 360, and a wet etching process or a dry etching process may be performed on the first gate electrode layer to form a first gate electrode 370 surrounding a portion of the first gate insulating pattern 360.

[0154] A gate mask layer may be formed on the sidewalls and bottom of the seventh opening 350, the first gate insulating pattern 360, and the first gate electrode 370. A wet etching process or a dry etching process may be performed on the gate mask layer to form a gate mask 380. The gate mask 380 surrounds a portion of the first gate insulating pattern 360 and contacts the sidewall of the first gate electrode 370 in the second direction D2.

[0155] The first gate electrode 370, the first gate insulating pattern 360, and the gate mask 380 may collectively form a first gate structure and may extend in the first direction D1 to surround the end of each of the channels 125 in the second direction D2 in the third region III. Therefore, a plurality of first gate structures may be spaced apart from each other in the third direction D3 at each of the opposite sides of the seventh opening 350 in the second direction D2. Each of the first gate structures may serve as a word line of a semiconductor device.

[0156] The fill pattern can be formed in the space between the first gate structures spaced apart on the third direction D3 (e.g., filling the space between the first gate structures spaced apart on the third direction D3). The third insulating layer and the fourth insulating layer can be sequentially stacked on the sidewalls of each of the first gate structures adjacent to the seventh opening 350 in the second direction D2, the sidewalls of the fill pattern, and the upper surface of the first substrate 100 exposed through the seventh opening 350. The ninth dividing layer can be formed in the seventh opening 350 (e.g., filling the seventh opening 350). The ninth dividing layer, the third insulating layer, and the fourth insulating layer can be subjected to a planarization process until the upper surface of the second mask 320 is exposed to form the ninth dividing pattern 410, the third insulating pattern, and the fourth insulating pattern 400, respectively.

[0157] The fill pattern, the third insulating pattern, and the ninth dividing pattern 410 may include oxides (e.g., silicon oxide), and the fourth insulating pattern 400 may include insulating nitrides (e.g., silicon nitride). The fill pattern and the third insulating pattern may be combined to form a seventh dividing pattern 310, and the combined structure may be referred to as the seventh dividing pattern 310 hereinafter.

[0158] The fourth insulating pattern 400 and the ninth dividing pattern 410 together form the fourth dividing structure 415.

[0159] Reference Figure 22 and Figure 23 The eighth segmented pattern 340 can be partially removed by, for example, a dry etching process to form an eighth opening 420 that exposes the upper surface of the first substrate 100, and the first semiconductor pattern 123 can be removed by, for example, a wet etching process through the eighth opening 420 to form a third gap. A conductive pad layer can be formed in the eighth opening 420 to fill the third gap, and the conductive pad layer can be formed by, for example, a wet etching process to form a conductive pad 430 in the third gap on the first region I of the first substrate 100.

[0160] In an example embodiment, the conductive pad 430 may extend in the fourth region IV in the first direction D1, and the plurality of conductive pads 430 may be spaced apart from each other in the second direction D2. Additionally, the plurality of conductive pads 430 may be spaced apart from each other in the third direction D3.

[0161] A tenth dividing layer may be formed in the eighth opening 420 (e.g., to fill the eighth opening 420), and the tenth dividing layer may be subjected to a planarization process until the upper surface of the second mask 320 is exposed to form a tenth dividing pattern in the eighth opening 420. The tenth dividing pattern may include an insulating nitride (e.g., silicon nitride) and may contact the eighth dividing pattern 340 between conductive pads 430 spaced apart from each other on a third-direction D3 to merge into the eighth dividing pattern 340. Hereinafter, the eighth dividing pattern 340 together with the tenth dividing pattern merged into the eighth dividing pattern 340 may be referred to as the eighth dividing pattern 340.

[0162] Reference Figure 24 and Figure 25 The second mask 320, the eighth segmentation pattern 340 and the conductive pad 430 in the first region I of the first substrate 100 can be partially removed by, for example, a dry etching process to form a ninth opening that exposes the upper surface of the eighth segmentation pattern 340.

[0163] In an example embodiment, after the dry etching process, each of the conductive pads 430 and a portion of the eighth segmented pattern 340 thereon may collectively form a stepped layer extending in the first direction D1, and the stacked structure including the conductive pads 430 and the eighth segmented pattern 340 may have a stepped structure having a length that decreases in a stepped manner from its bottom to its top. During the dry etching process, the upper portions of the first segmented pattern 160 and the second segmented pattern 170 that contact the ends of the conductive pads 430 in the first direction D1 may also be removed.

[0164] The second insulating interlayer 435 may be formed in the ninth opening (e.g., to fill the ninth opening). The second insulating interlayer 435 may include an oxide (e.g., silicon oxide) and may contact the second slit pattern 170. In some embodiments, the second insulating interlayer 435 may be incorporated into the second slit pattern 170.

[0165] Reference Figures 26 to 27 The fourth segment structure 415 and the seventh segment pattern 310 can be partially etched on the first region I of the first substrate 100 by, for example, a dry etching process to form a first trench. A bit line layer can be formed in the first trench, and the bit line layer can be patterned to form a bit line 440.

[0166] When the first trench is formed, the ends of the channel 125, the first gate insulating pattern 360, and the gate mask 380 disposed at each of the opposite sides of the fourth split structure 415 in the second direction D2 on the third direction D3 can be exposed, and thus the bit line 440 extending in the third direction D3 in the first trench can contact the channel 125, the first gate insulating pattern 360, and the gate mask 380.

[0167] In the example embodiment, multiple bit lines 440 may be spaced apart from each other in the third region III along the first direction D1, and the multiple bit lines 440 may each contact a channel 125 disposed in the first direction D1 to be electrically connected to the channel 125. However, the bit line 440 disposed in the first direction D1 that is adjacent to the fourth region IV may be a dummy bit line 445.

[0168] In an example embodiment, bit line 440 may comprise polysilicon doped with n-type impurities. In other example embodiments, bit line 440 may comprise, for example, a metal, a metal nitride, a metal silicide, etc.

[0169] The eleventh segmentation pattern 450 may be formed in the space between the bit lines 440 disposed in the first direction D1 (e.g., to fill the space between the bit lines 440 disposed in the first direction D1). The eleventh segmentation pattern 450 may include an oxide (e.g., silicon oxide).

[0170] Reference Figure 28 and Figure 29 The seventh dividing pattern 310 can be partially removed by, for example, a dry etching process to form a tenth opening on the first region I of the first substrate 100 that exposes the upper surface of the first substrate 100, and a blocking structure 490 can be formed in the tenth opening.

[0171] In an example embodiment, the blocking structure 490 may be formed in the portion of the third region III adjacent to the fourth region IV, and may be formed between adjacent channels in the second direction D2 at the location of the in-situ line 440 in the channel 125 relative to the opposite side of the channel 125 in the second direction D2.

[0172] In an example embodiment, the blocking structure 490 may include a first blocking pattern 470 on the sidewalls and bottom of the tenth opening and a second blocking pattern 480 in the remaining portion of the tenth opening (e.g., filling the remaining portion of the tenth opening). The sidewalls and lower surface of the second blocking pattern 480 may have the first blocking pattern 470 thereon (e.g., may be covered and / or superimposed by the first blocking pattern 470). The first blocking pattern 470 may include an insulating nitride (e.g., silicon nitride), and the second blocking pattern 480 may include an oxide (e.g., silicon oxide).

[0173] In the example embodiment, the blocking structure 490 may have a polygonal shape (e.g., a rectangle) in a plan view; however, the inventive concept is not limited thereto.

[0174] A first capping layer 500 may be formed on the barrier structure 490, bit line 440, dummy bit line 445, second insulating interlayer 435, second mask 320, seventh dividing pattern 310, fourth dividing structure 415 and eleventh dividing pattern 450. The first capping layer 500 may include an insulating nitride (e.g., silicon nitride).

[0175] Reference Figure 30 and Figure 31 The first capping layer 500, the second mask 320 and the third segmentation structure can be partially removed by, for example, a dry etching process to form an eleventh opening 510 on the first region I of the first substrate 100, exposing the upper surface of the first substrate 100.

[0176] In an example embodiment, the eleventh opening 510 may expose the sidewall of the blocking structure 490 in the first direction D1.

[0177] For example, a wet etching process can be performed through the eleventh opening 510 to remove a portion of the seventh dividing pattern 310 in the channel 125 that is adjacent to and adjacent to the channel in the third direction D3, to form a fourth gap. During the wet etching process, portions of the first insulating pattern 290 and the second insulating pattern 300 on the lower and upper surfaces and sidewalls of the portion of the channel 125 can also be removed to expose that portion of the channel 125.

[0178] A first capacitor electrode layer, a first dielectric layer, and a second capacitor electrode layer may be sequentially stacked on the inner wall of the fourth gap, the inner wall of the eleventh opening 510, and the upper surface of the first capping layer 500. A first plate electrode layer may be formed on the second capacitor electrode layer to fill the fourth gap and the eleventh opening 510. The first plate electrode layer, the first capacitor electrode layer, the second capacitor electrode layer, and the first dielectric layer may be planarized until the upper surface of the first capping layer 500 is exposed to form a first plate electrode 560, a first capacitor electrode 520, a second capacitor electrode 540, and a first dielectric pattern 530, respectively, in the fourth gap and the eleventh opening 510.

[0179] When forming the first capacitor electrode layer, a first metal silicide pattern 580 may be formed at the portion of the channel 125 that contacts the first capacitor electrode layer.

[0180] The first capacitor electrode 520, the second capacitor electrode 540, and the first dielectric pattern 530 can jointly form the first capacitor 550, and the first capacitor 550 together with the first plate electrode 560 can jointly form the first capacitor structure.

[0181] Reference Figure 32 and Figure 33 For example, a dry etching process can be performed on the first mask layer 140, the insulating pad layer 130 and the molding layer to form a twelfth opening that extends through the first mask layer 140, the insulating pad layer 130 and the molding layer and exposes the upper surface of the first substrate 100, and a twelfth segment layer can be formed in the twelfth opening on the second region II of the first substrate 100.

[0182] In an example embodiment, the twelfth segment layer may extend on the second region II of the first substrate 100 in the second direction D2, and the plurality of twelfth segment layers may be spaced apart from each other in the first direction D1. The twelfth segment layer may comprise an insulating nitride (e.g., silicon nitride).

[0183] For example, a dry etching process can be performed on the first mask layer 140, the insulating pad layer 130, the molding layer and the twelfth dividing layer to form thirteenth to fifteenth openings 902, 904 and 906 on the second region II of the first substrate 100, extending through the first mask layer 140, the insulating pad layer 130, the molding layer and the twelfth dividing layer and exposing the upper surface of the first substrate 100.

[0184] In an example embodiment, each of the thirteenth to fifteenth openings 902, 904, and 906 may extend in a first direction D1 on a second region II of the first substrate 100, and the thirteenth to fifteenth openings 902, 904, and 906 may be spaced apart from each other in a second direction D2. In an example embodiment, the fourteenth opening 904 and the thirteenth opening 902 may be alternately and repeatedly disposed in the second direction D2 between the fifteenth openings 906 that are spaced apart from each other in the second direction D2, and spaced apart from each other in the second direction D2 between the fifteenth openings 906 that are spaced apart from each other in the second direction D2. When forming the thirteenth to fifteenth openings 902, 904, and 906, the twelfth segment layer extending in the second direction D2 may be separated into a plurality of twelfth segment patterns 870 spaced apart from each other in the second direction D2.

[0185] When forming the twelfth dividing layer and the thirteenth to fifteenth openings 902, 904 and 906, the sacrificial layer 110 and the semiconductor layer 120 on the second region II of the first substrate 100 can be separated into a third sacrificial pattern 850 and a second semiconductor pattern 860, respectively. A plurality of third sacrificial patterns 850 may be spaced apart from each other in each of the first direction D1 and the second direction D2, and a plurality of semiconductor patterns 860 may be spaced apart from each other in each of the first direction D1 and the second direction D2.

[0186] For example, a wet etching process can be performed to remove the portion of the third sacrificial pattern 850 adjacent to each of the thirteenth to fifteenth openings 902, 904, and 906 in the second direction D2 to form a fifth gap 908. Thus, the third sacrificial pattern 850 between the thirteenth to fifteenth openings 902, 904, and 906 can be removed, and the portion of each of the third sacrificial patterns 850 at one side of the fifteenth opening 906 in the second direction D2 can be retained.

[0187] The fifth gap 908 may be formed between adjacent second semiconductor patterns in the second semiconductor pattern 860 in the third direction D3, between the uppermost second semiconductor pattern in the second semiconductor pattern 860 and the lower surface of the insulating pad layer 130, and between the lowermost second semiconductor pattern in the second semiconductor pattern 860 and the upper surface of the first substrate 100. Therefore, a plurality of fifth gaps 908 may be spaced apart from each other in each of the first direction D1 and the second direction D2.

[0188] Reference Figure 34 and Figure 35 A fifth insulating layer can be formed in the thirteenth to fifteenth openings 902, 904 and 906 and the fifth gap 908. The fifth insulating layer in the thirteenth to fifteenth openings 902, 904 and 906 can be removed by, for example, a wet etching process, and thus a fifth insulating pattern 918 can be formed in the fifth gap 908.

[0189] Multiple fifth insulating patterns 918 may be spaced apart from each other in each of the first direction D1 and the second direction D2, and may include oxides (e.g., silicon oxide).

[0190] A padding layer may be formed on the inner walls of the thirteenth to fifteenth openings 902, 904 and 906 and on the upper surface of the first mask layer 140. A thirteenth segmentation layer may be formed on the padding layer to fill the thirteenth to fifteenth openings 902, 904 and 906 (e.g., to fill the thirteenth to fifteenth openings 902, 904 and 906). The thirteenth segmentation layer and the padding layer may be subjected to a planarization process until the upper surface of the first mask layer 140 is exposed to form thirteenth to fifteenth segmentation patterns 932, 934 and 936 and padding 920, respectively.

[0191] Thirteenth to fifteenth segment patterns 932, 934 and 936 may be formed in thirteenth to fifteenth segment openings 902, 904 and 906, respectively. Each of the thirteenth to fifteenth segment patterns 932, 934 and 936 may extend in a first direction D1 on a second region II of the first base 100, and the sidewalls and lower surfaces of each of the thirteenth to fifteenth segment patterns 932, 934 and 936 may have a pad 920 thereon (e.g., may be covered and / or stacked by the pad 920).

[0192] Reference Figure 36 and Figure 37 The thirteenth segment pattern 932 can be partially removed by, for example, a dry etching process to form a second trench 940 on the second region II of the first substrate 100, and a second plate electrode structure 945 can be formed in the second trench 940.

[0193] In an example embodiment, the second plate electrode structure 945 may extend in a first direction D1 on a second region II of the first substrate 100, and the sidewalls and lower surface of the second plate electrode structure 945 may have a thirteenth segmentation pattern 932 thereon (e.g., may be covered and / or stacked by the thirteenth segmentation pattern 932). In an example embodiment, the second plate electrode structure 945 may include a first conductive pattern to a third conductive pattern 942, 944 and 946 sequentially stacked in a third direction D3.

[0194] Reference Figure 38 and Figure 39 A second capping layer 950 can be formed on the second region II of the first substrate 100 on the first mask layer 140, the thirteenth to fifteenth segmented patterns 932, 934 and 936, the pad 920 and the second plate electrode structure 945, and the second capping layer 950 and the fourteenth segmented pattern 934 can be partially removed by, for example, a dry etching process to form a third trench 954.

[0195] The second capping layer 950 may include an insulating nitride (e.g., silicon nitride) and, in some embodiments, may be incorporated into the first mask layer 140.

[0196] In an example embodiment, the third trench 954 may extend in the first direction D1 on the second region II of the first substrate 100.

[0197] Reference Figure 40 and Figure 41 The fourteenth dividing pattern 934, the pad 920 and the fifth insulating pattern 918 adjacent to the third trench 954 can be partially removed by, for example, a wet etching process to form a sixth gap on the second region II of the first substrate 100.

[0198] During the wet etching process, portions of the insulating pad 130 adjacent to the third trench 954, as well as portions of the thirteenth segment pattern 934 and the pad 920 on the sidewalls of the second plate electrode structure 945, can also be partially removed.

[0199] The third capacitor electrode layer, the second dielectric layer, and the fourth capacitor electrode layer may be sequentially stacked on the inner wall of the sixth gap, the sidewall of the first mask layer 140, the sidewall and upper surface of the second capping layer 950, the surface of the second semiconductor pattern 860, the upper surface of the first substrate 100, and the sidewall of the fifteenth segmentation pattern 936. The fourth conductive layer may be formed on the fourth capacitor electrode layer to fill the third trench 954. The fourth conductive layer, the fourth capacitor electrode layer, the second dielectric layer, and the third capacitor electrode layer may be subjected to a planarization process until the upper surface of the second capping layer 950 is exposed.

[0200] Therefore, a fourth conductive pattern 965 can be formed in the third trench 954, and a fourth capacitor electrode 966, a second dielectric pattern 964, and a third capacitor electrode 962 can be sequentially stacked on the sidewalls and lower surface of the fourth conductive pattern 965. The third capacitor electrode 962, the fourth capacitor electrode 966, and the second dielectric pattern 964 can together form a second capacitor 960.

[0201] A second metal silicide pattern 865 may be formed on the portion of the second semiconductor pattern 860 that contacts the third capacitor electrode 962.

[0202] In an example embodiment, the fourth conductive pattern 965 may include a second vertical extension and a second horizontal extension on a second region II of the first substrate 100. The second vertical extension extends in a third direction D3, and the second horizontal extension extends from each of the opposing sidewalls of the second vertical extension in a second direction D2. A plurality of second horizontal extensions of the fourth conductive pattern 965 may be spaced apart from each of the opposing sidewalls of the second vertical extensions of the fourth conductive pattern 965 in a third direction D3. Each of the second capacitor 960 and the fourth conductive pattern 965 may also extend in a first direction D1.

[0203] Reference Figure 42 The upper part of the fourth conductive pattern 965 can be removed to form the fourth trench, and the fifth conductive pattern 967 and the sixth conductive pattern 969 can be formed in the fourth trench.

[0204] The fourth to sixth conductive patterns 965, 967 and 969, which are sequentially stacked on the third-direction D3, can collectively form the third plate electrode structure 970.

[0205] The second capacitor 960, the second plate electrode structure 945, and the third plate electrode structure 970 can together form the second capacitor structure.

[0206] Reference Figures 43 to 45 A third insulating interlayer 600 may be formed on the first capping layer 500 and the second capping layer 950, as well as the first capacitor structure and the second capacitor structure, in the first region I and the second region II of the first substrate 100.

[0207] On the first region I of the first substrate 100, a first contact plug 612 may be formed to pass through the third insulating interlayer 600 and the first cover layer 500 to contact the upper surface of the bit line 440, a second contact plug 614 may be formed to pass through the third insulating interlayer 600 to contact the upper surface of the first plate electrode 560, and a third contact plug 616 may be formed to pass through the first cover layer 500, the second mask 320 and the eighth dividing pattern 340 or the third insulating interlayer 600, the first cover layer 500 and the second insulating interlayer 435 to contact the upper surface of the conductive pad 430.

[0208] On the second region II of the first substrate 100, a fourth contact plug 618 may be formed to pass through the third insulating interlayer 600 and the second cover layer 950 to contact the upper surface of the second plate electrode structure 945, and a fifth contact plug 619 may be formed to pass through the third insulating interlayer 600 to contact the upper surface of the third plate electrode structure 970.

[0209] The first to fifth wiring structures 622, 624, 626, 628, and 629 may be formed on the third insulating interlayer 600 and the first to fifth contact plugs 612, 614, 616, 618, and 619. The fourth insulating interlayer 630 may be formed on the first to fifth wiring structures 622, 624, 626, 628, and 629 (e.g., covering the first to fifth wiring structures 622, 624, 626, 628, and 629 and / or overlapping with the first to fifth wiring structures 622, 624, 626, 628, and 629), and a first bonding layer 640 including a first bonding pad 645 may be formed on the fourth insulating interlayer 630.

[0210] Return to reference Figures 1 to 8Transistors can be formed on the first region I and the second region II of the second substrate 700, respectively.

[0211] Each of the transistors may include a second gate structure 730 and an impurity region 705. The second gate structure 730 includes a second gate insulating pattern 710 and a second gate electrode 720. The impurity region 705 is located at a corresponding portion of the second substrate 700 adjacent to the second gate structure 730.

[0212] The fifth insulating interlayer 740 may be formed on the transistor (e.g., covering the transistor and / or stacked with the transistor), and the sixth contact plug 750 may be formed through the fifth insulating interlayer 740 to contact each of the impurity regions 705.

[0213] The sixth wiring structure 800 and the seventh wiring structure 810 may be formed on the fifth insulating layer 740, and the sixth insulating layer 820 may be formed on the fifth insulating layer 740 to cover the sixth wiring structure 800 and the seventh wiring structure 810 (e.g., cover the sixth wiring structure 800 and the seventh wiring structure 810 and / or overlap with the sixth wiring structure 800 and the seventh wiring structure 810), and a second bonding layer 830 including a second bonding pad 835 may be formed on the sixth insulating layer 820.

[0214] The second substrate 700 is flip-up, and the second bonding layer 830 is accessible to the first bonding layer 640, such that the first substrate 100 and the second substrate 700 can be bonded to each other. The first bonding pad 645 and the second bonding pad 835 are accessible to each other.

[0215] Semiconductor devices can be manufactured using the above processes.

[0216] Figures 46 to 52 This is a schematic diagram illustrating the electrical connections of a second capacitor structure included in a semiconductor device according to an example embodiment. The second capacitor structure may be similar to... Figure 8 For ease of description, the following description will focus primarily on the references above. Figure 8 The differences in description.

[0217] Reference Figure 46 Each of the third plate electrode structures 970 included in the second capacitor structure can be in a floating state (e.g., electrically floating state), and the source voltage V SS It can be applied to some of the second plate electrode structures 945 included in the second capacitor structure (e.g., odd-numbered second plate electrode structures in the second plate electrode structure 945 (e.g., the first second plate electrode structure)), and the drain voltage V DDOther second plate electrode structures (e.g., even-numbered second plate electrode structures in the second plate electrode structure 945 included in the second capacitor structure) can be applied to the second plate electrode structure 945.

[0218] Therefore, the first second capacitor connected to the second capacitor 960 of the odd-numbered second plate electrode structures in the second plate electrode structure 945 and the second second capacitor connected to the second capacitor 960 of the even-numbered second plate electrode structures in the second plate electrode structure 945 can be electrically connected to each other through the third plate electrode structure 970 between the first second capacitor and the second second capacitor, and are connected to the source voltage V. SS and drain voltage V DD The voltage corresponding to the difference between them can be applied to the first and second capacitors in the second capacitor 960.

[0219] therefore, Figure 46 The capacitance of the second capacitor structure can be Figure 8 The capacitance of the second capacitor structure is half of that of the second capacitor structure.

[0220] Reference Figure 47 Each of the second plate electrode structures 945 included in the second capacitor structure can be in a floating state (e.g., electrically floating state), and the source voltage V SS It can be applied to some of the third plate electrode structures 970 included in the second capacitor structure (e.g., even-numbered third plate electrode structures in the third plate electrode structure 970 (e.g., the second and third plate electrode structures)), and the drain voltage V DD Other third plate electrode structures (e.g., odd-numbered third plate electrode structures in the third plate electrode structure 970, such as the first third plate electrode structure) may be applied to the third plate electrode structure 970 included in the second capacitor structure.

[0221] Therefore, the first second capacitor connected to the even-numbered second capacitors of the third plate electrode structures 960 in the third plate electrode structure 970 and the second second capacitor connected to the odd-numbered second capacitors of the third plate electrode structures 960 in the third plate electrode structure 970 can be electrically connected to each other through the second plate electrode structure 945 between the first second capacitor and the second second capacitor, and are connected to the source voltage V. SS and drain voltage V DD The voltage corresponding to the difference between them can be applied to the first and second capacitors in the second capacitor 960.

[0222] therefore, Figure 47 The capacitance of the second capacitor structure can be Figure 8The capacitance of the second capacitor structure is half of that of the second capacitor structure.

[0223] Reference Figure 48 Each of the second plate electrode structures 945 included in the second capacitor structure and some of the third plate electrode structures 970 included in the second capacitor structure (e.g., even-numbered third plate electrode structures in the third plate electrode structures 970 (e.g., second and third plate electrode structures)) may be in a floating state (e.g., electrically floating state). Source voltage V SS It can be applied to other third plate electrode structures (e.g., the (4n-1)th (n is a natural number) third plate electrode structure in the third plate electrode structure 970 included in the second capacitor structure), and the drain voltage V DD Other third plate electrode structures (e.g., the (4n-3)th (n is a natural number) third plate electrode structure in the third plate electrode structure 970 included in the second capacitor structure) can be applied to the third plate electrode structure 970.

[0224] Therefore, the four second capacitors 960 between the (4n-1)th (n is a natural number) and (4n-3)th (n is a natural number)th third plate electrode structures in the third plate electrode structure 970 can be electrically connected to each other through the two second plate electrode structures 945 and one third plate electrode structure 970 between the (4n-1)th and (4n-3)th third plate electrode structures, and are connected to the source voltage V. SS and drain voltage V DD The voltage corresponding to the difference between them can be applied to the four second capacitors 960.

[0225] therefore, Figure 48 The capacitance of the second capacitor structure can have Figure 8 The capacitance of the second capacitor structure is one-quarter of that of the second capacitor structure.

[0226] Reference Figure 49 Each of the third plate electrode structures 970 included in the second capacitor structure and some of the second plate electrode structures 945 included in the second capacitor structure (e.g., even-numbered second plate electrode structures in the second plate electrode structures 945 (e.g., second second plate electrode structures)) may be in a floating state (e.g., electrically floating state). Source voltage V SS It can be applied to other second plate electrode structures included in the second plate electrode structure 945 of the second capacitor structure (e.g., the (4n-1)th (n is a natural number) second plate electrode structure in the second plate electrode structure 945), and the drain voltage V DDOther second plate electrode structures (e.g., the (4n-3)th (n is a natural number) second plate electrode structure in the second plate electrode structure 945 included in the second capacitor structure) can be applied.

[0227] Therefore, the four second capacitors 960 between the (4n-1)th (n is a natural number) second plate electrode structure and the (4n-3)th (n is a natural number) second plate electrode structure in the second plate electrode structure 945 can be electrically connected to each other through one second plate electrode structure 945 and two third plate electrode structures 970 between the (4n-1)th and (4n-3)th second plate electrode structures, and are connected to the source voltage V. SS and drain voltage V DD The voltage corresponding to the difference between them can be applied to the four second capacitors 960.

[0228] therefore, Figure 49 The capacitance of the second capacitor structure can have Figure 8 The capacitance of the second capacitor structure is one-quarter of that of the second capacitor structure.

[0229] Reference Figure 50 The second plate electrode structure 945 included in the second capacitor structure may extend in the first direction D1, while the plurality of third plate electrode structures 970 included in the second capacitor structure may be spaced apart from each other in the first direction D1.

[0230] Therefore, only the corresponding second capacitor in the second capacitor 960, and not all the second capacitors 960 provided in the first direction D1, can be electrically connected to the third plate electrode structure 970.

[0231] Reference Figure 51 The third plate electrode structure 970 included in the second capacitor structure may extend in the first direction D1, and the plurality of second plate electrode structures 945 included in the second capacitor structure may be spaced apart from each other in the first direction D1.

[0232] Therefore, only the corresponding second capacitor in the second capacitor 960, and not all the second capacitors 960 provided in the first direction D1, can be electrically connected to the second plate electrode structure 945.

[0233] Reference Figure 52 The plurality of second plate electrode structures 945 included in the second capacitor structure are spaced apart from each other in the first direction D1, and the plurality of third plate electrode structures 970 included in the second capacitor structure are spaced apart from each other in the first direction D1.

[0234] Therefore, only the corresponding second capacitor in the second capacitor 960, and not all the second capacitors 960 disposed in the first direction D1, can be electrically connected to each of the second plate electrode structure 945 and the third plate electrode structure 970.

[0235] As shown above (refer to the reference) Figures 46 to 52 As shown, the voltage applied to the second plate electrode structure 945 and the third plate electrode structure 970 included in the second capacitor structure, or the number of second capacitors 960 electrically connected to the second plate electrode structure 945 and the third plate electrode structure 970, can be adjusted so that the capacitance of the second capacitor structure can have a desired value.

[0236] As used herein, the terms “comprising,” “including,” “having,” and any other variations thereof specify the presence of the stated feature, step, operation, element, component, and / or group, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. Furthermore, as used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0237] The foregoing is illustrative of exemplary embodiments and should not be construed as limiting the exemplary embodiments. Although some exemplary embodiments have been described, those skilled in the art will readily understand that many modifications can be made to the exemplary embodiments without substantially departing from the scope of this disclosure. Therefore, all such modifications are intended to be included within the scope of this disclosure as defined in the claims. It should be understood that the foregoing is illustrative of various exemplary embodiments and should not be construed as limiting to the specific exemplary embodiments disclosed, and modifications to the disclosed exemplary embodiments and other exemplary embodiments are intended to be included within the scope of the appended claims.

Claims

1. A semiconductor device, comprising: Multiple channels are spaced apart from each other in a vertical direction perpendicular to the upper surface of the substrate, and the substrate includes a first region and a second region. A gate structure, at least partially surrounding each of the plurality of channels; Bit lines contact a first end of each of the plurality of channels, and the bit lines extend in a vertical direction; A first capacitor is located at the second end of each of the plurality of channels; Multiple semiconductor patterns are arranged vertically on a second region of a substrate, each of the multiple semiconductor patterns being at least partially superimposed with a corresponding channel of the multiple channels in a first horizontal direction parallel to the upper surface of the substrate; as well as Multiple second capacitors are respectively located on the multiple semiconductor patterns.

2. The semiconductor device according to claim 1, wherein, At least two of the plurality of second capacitors are electrically connected to each other.

3. The semiconductor device according to claim 2, further comprising: The plate electrode structure extends vertically on the substrate and is in common contact with the second capacitors of the plurality of second capacitors.

4. The semiconductor device according to claim 3, wherein, The plate electrode structure includes a first conductive pattern, a second conductive pattern, and a third conductive pattern sequentially stacked in the vertical direction, and The first conductive pattern comprises polycrystalline silicon doped with impurities, the second conductive pattern comprises metal silicide, and the third conductive pattern comprises metal.

5. The semiconductor device according to claim 3, further comprising: An insulating layer structure is located between the sidewall of the plate electrode structure and the sidewall of each of the plurality of semiconductor patterns, and contacts the sidewall of the plate electrode structure and the sidewall of each of the plurality of semiconductor patterns.

6. The semiconductor device according to claim 5, wherein, The insulating layer structure includes a first insulating layer and a second insulating layer sequentially stacked on the sidewalls of the plate electrode structure in a second horizontal direction, and The first insulating layer comprises an oxide, and the second insulating layer comprises a nitride.

7. The semiconductor device according to claim 2, further comprising: The plate electrode structure extends vertically on the substrate, and the plate electrode structure is located in the space defined by the second capacitor of the plurality of second capacitors.

8. The semiconductor device according to claim 7, wherein, The plate electrode structure includes a first conductive pattern, a second conductive pattern, and a third conductive pattern sequentially stacked in the vertical direction, and The first conductive pattern includes silicon germanium doped with impurities, the second conductive pattern includes at least one of a metal and a silicon germanium compound and a metal silicide, and the third conductive pattern includes a metal.

9. The semiconductor device according to claim 7, wherein, The plate electrode structure includes: The vertical extension extends in the vertical direction; and Multiple horizontal extensions are spaced apart from each other in the vertical direction, and each of the multiple horizontal extensions extends in a second horizontal direction.

10. The semiconductor device according to claim 9, wherein, Each of the plurality of horizontal extensions of the plate electrode structure is at least partially superimposed in the vertical direction on a corresponding semiconductor pattern of the plurality of semiconductor patterns.

11. The semiconductor device according to any one of claims 1 to 10, wherein the semiconductor device further comprises: A first metal silicide pattern is present between each of the plurality of channels and a first capacitor. as well as A second metal silicide pattern is positioned between each of the plurality of semiconductor patterns and a corresponding second capacitor among the plurality of second capacitors.

12. The semiconductor device according to any one of claims 1 to 10, wherein, The first region of the substrate is the memory cell region, and the second region of the substrate is the peripheral circuit region.

13. The semiconductor device according to any one of claims 1 to 10, wherein, The first capacitor is a unit capacitor, and at least one of the plurality of second capacitors is a power capacitor.

14. A semiconductor device, comprising: Multiple channels are spaced apart from each other in a vertical direction perpendicular to the upper surface of the substrate, the substrate including a first region and a second region. A gate structure, at least partially surrounding each of the plurality of channels; Bit lines contact a first end of each of the plurality of channels, and the bit lines extend in a vertical direction; A first capacitor is located at the second end of each of the plurality of channels; The first plate electrode structure extends vertically in the second region of the substrate; Multiple semiconductor patterns are located on opposite sidewalls of a first plate electrode structure in a first direction parallel to the upper surface of the substrate, with at least two of the multiple semiconductor patterns being spaced apart from each other in a vertical direction. A plurality of second capacitors, each contacting a corresponding sidewall in an opposing sidewall of a first plate electrode structure and on the upper and lower surfaces and sidewalls of at least one of the plurality of semiconductor patterns, each of the plurality of second capacitors extending in a vertical direction and including a first capacitor electrode, a dielectric pattern and a second capacitor electrode; as well as A plurality of second plate electrode structures are respectively located on opposite sidewalls of the first plate electrode structure and on a second region of the substrate, each of the plurality of second plate electrode structures extending in a vertical direction and contacting a corresponding second capacitor among the plurality of second capacitors.

15. The semiconductor device of claim 14, wherein, The plurality of second capacitors and the plurality of second plate electrode structures are symmetrical with respect to the first plate electrode structure in a first direction.

16. The semiconductor device according to claim 14, wherein, The first plate electrode structure is configured to receive the source voltage, and Each of the plurality of second plate electrode structures is configured to receive a drain voltage.

17. The semiconductor device according to claim 14, wherein, The first plate electrode structure, the first second plate electrode structure among the plurality of second plate electrode structures, and the first second capacitor among the plurality of second capacitors are included in the second capacitor structure, and The second capacitor structure is a second capacitor structure among a plurality of second capacitor structures arranged on a second region of the substrate in a first direction, and the first plate electrode structure is a first plate electrode structure among a plurality of first plate electrode structures.

18. The semiconductor device according to claim 17, wherein, Each of the plurality of second plate electrode structures is in an electrically levitated state. Among the plurality of first plate electrode structures, the first first plate electrode structure is configured to receive the source voltage, and The second first plate electrode structure among the plurality of first plate electrode structures is configured to receive the drain voltage.

19. The semiconductor device according to claim 14, wherein, The first plate electrode structure extends in a second direction that is parallel to the upper surface of the substrate and intersects with the first direction. Each of the plurality of second capacitors is a second capacitor among a plurality of second capacitors spaced apart from each other in a second direction, and the plurality of second capacitors contact corresponding sidewalls of opposite sidewalls of the first plate electrode structure. Each of the plurality of second plate electrode structures is a second plate electrode structure among a plurality of second plate electrode structures spaced apart from each other in a second direction, and the plurality of second plate electrode structures contact a corresponding second capacitor among the plurality of second capacitors.

20. A semiconductor device, comprising: Multiple channels are spaced apart from each other in a vertical direction perpendicular to the upper surface of the substrate, and the substrate includes a memory cell region and a peripheral circuit region. A gate structure, at least partially surrounding each of the plurality of channels; Bit lines contact a first end of each of the plurality of channels, and the bit lines extend in a vertical direction; A unit capacitor, at the second end of each of the plurality of channels; The first plate electrode structure extends vertically in the peripheral circuit region of the substrate; Multiple semiconductor patterns are located on opposite sidewalls of a first plate electrode structure in a first horizontal direction parallel to the upper surface of the substrate. At least two of the multiple semiconductor patterns are spaced apart from each other in a vertical direction, and each of the multiple semiconductor patterns is at least partially superimposed on a corresponding channel of the multiple channels in a second horizontal direction. A power capacitor is in contact with at least one of the opposing sidewalls of the first plate electrode structure, and extends vertically on the upper and lower surfaces and sidewalls of at least one of the plurality of semiconductor patterns, and includes a first capacitor electrode, a dielectric pattern and a second capacitor electrode. as well as The second plate electrode structure extends vertically and contacts the second capacitor electrode of the power capacitor on the sidewall opposite to the first plate electrode structure and on the peripheral circuit region of the substrate.

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