Semiconductor device and method of manufacturing the same

Abstract

Embodiments provide a semiconductor device capable of reducing variations in memory hole width and a method of manufacturing the same. According to one embodiment, a semiconductor device includes a substrate, a laminated film, and a columnar portion. The laminated film is provided above the substrate, and has a plurality of insulating layers and a plurality of electrode layers alternately laminated in a first direction intersecting an upper surface of the substrate. The columnar portion passes through the laminated film in the first direction. At least one first insulating layer on the lower end side among the plurality of insulating layers has a higher concentration of the group V element than a second insulating layer other than the first insulating layer among the plurality of insulating layers.

Description

Related applications

[0001] This application claims priority to Japanese Patent Application No. 2024-144437 (filed on August 26, 2024). This application incorporates the entire contents of that basic application by reference. Technical Field

[0002] This embodiment of the present invention relates to a semiconductor device and a method for manufacturing the same. Background Technology

[0003] If the width deviation of the memory hole (i.e., the columnar portion) is large between the upper and lower ends of the memory hole, the deviation of the threshold voltage of the memory cell between the upper and lower ends of the memory cell will also increase. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a semiconductor device and a method thereof that can reduce the deviation of memory hole width.

[0005] According to one embodiment, a semiconductor device includes a substrate, a multilayer film, and a pillar-shaped portion. The multilayer film is disposed above the substrate and has a plurality of insulating layers and a plurality of electrode layers alternately stacked in a first direction intersecting the upper surface of the substrate. The pillar-shaped portion penetrates the multilayer film along the first direction. At least one first insulating layer on the lower end side of the plurality of insulating layers has a higher concentration of group V elements compared to a second insulating layer other than the first insulating layer among the plurality of insulating layers. Attached Figure Description

[0006] Figure 1 This is a cross-sectional view showing an example of the configuration of the semiconductor device according to the first embodiment. Figure 2 This is a cross-sectional view showing the columnar portion of the semiconductor device according to the first embodiment. Figure 3 This illustrates the columnar portion of the semiconductor device according to the first embodiment. Figure 2 Section III-III view. Figure 4 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment. Figure 5 This is a cross-sectional view showing a detailed manufacturing method of the semiconductor device according to the first embodiment. Figure 6 It is shown Figure 5 The following is a cross-sectional view of the manufacturing method of the semiconductor device according to the first embodiment. Figure 7 This is a cross-sectional view showing a manufacturing method of a semiconductor device for a comparative example. Figure 8 yes Figure 6 The diagram shows a detailed cross-sectional view of the laminated membrane. Figure 9 It is shown Figure 6 The following is a cross-sectional view of the manufacturing method of the semiconductor device according to the first embodiment. Figure 10 This is a cross-sectional view showing the insulating layer on the lower end side of the semiconductor device according to the second embodiment. Figure 11 This is a cross-sectional view showing the suppression of leakage current by the semiconductor device of the second embodiment. Figure 12 This is a cross-sectional view showing the semiconductor device according to the third embodiment. Detailed Implementation

[0007] Embodiments of the present invention will now be described with reference to the accompanying drawings. Figures 1 to 12 In the accompanying drawings, identical or similar components are marked with the same reference numerals, and repeated descriptions are omitted. (First Implementation) Figure 1 This is a cross-sectional view showing an example of the configuration of the semiconductor device according to the first embodiment. Figure 1 The semiconductor device 1 shown is a three-dimensional memory formed by bonding an array chip C1 and a circuit chip C2. The semiconductor device 1 has a CBA (CMOS directly bonded to array) structure.

[0008] The array chip C1 includes a memory cell array 11 comprising multiple memory cells arranged in three dimensions, an insulating film 12 on the memory cell array 11, and an interlayer insulating film 13 below the memory cell array 11. The insulating film 12 is, for example, a silicon oxide film or a silicon nitride film. The interlayer insulating film 13 is, for example, a silicon oxide film, or a laminated film comprising a silicon oxide film and other insulating films.

[0009] Circuit chip C2 is disposed beneath array chip C1. Circuit chip C2 functions as a control circuit (logic circuit) that controls the operation of array chip C1. Circuit chip C2 includes an interlayer insulating film 14 and a substrate 15 beneath the interlayer insulating film 14. The interlayer insulating film 14 is, for example, a silicon oxide film, or a laminate containing a silicon oxide film and other insulating films. The substrate 15 is, for example, a semiconductor substrate such as a silicon substrate. Figure 1 The X and Y directions, which are parallel to and perpendicular to the surface of substrate 15 (i.e., the upper surface), and the Z direction, which is orthogonal to the upper surface of substrate 15, are shown. The Z direction is an example of the first direction. The X and Y directions are examples of the second direction that intersect the first direction.

[0010] The array chip C1 includes multiple word lines WL, multiple pillars CL, and source lines SL as multiple electrode layers within the memory cell array 11. The word lines WL are examples of conductive layers. A stepped structure 21 is provided at the end of the memory cell array 11 in the X direction. Each word line WL is electrically connected to the wiring layer 23 via a contact plug 22. Multiple pillars CL extend through the multiple word lines WL in the Z direction. Each pillar CL is electrically connected to the bit line BL, which is on the same layer as the wiring layer 23, via a via plug 24. Additionally, each pillar CL is electrically connected to the source line SL. The source line SL comprises a first layer SL1, which is a semiconductor layer, and a second layer SL2, which is a metal layer. A wiring layer 43, including a via plug V, is provided below the bit line BL. A via plug 42 is provided below the wiring layer 43. Multiple metal pads 41 are provided below the via plug 42. The metal pads 41 are, for example, a Cu (copper) layer or an Al (aluminum) layer.

[0011] The array chip C1 also includes multiple through-hole plugs 45, metal pads 46, and a passivation film 47. The multiple through-hole plugs 45 are disposed on the wiring layer 23, the metal pads 46 are disposed on the through-hole plugs 45 and the insulating film 12, and the passivation film 47 is disposed on the metal pads 46 and the insulating film 12. The metal pads 46 are, for example, a Cu layer or an Al layer, serving as... Figure 1 The external connection pads (bonding pads) of the semiconductor device function as bonding pads. The passivation film 47 is, for example, an insulating film such as silicon oxide. The passivation film 47 has an opening P that exposes the upper surface of the metal pad 46. The metal pad 46 can be connected to the mounting substrate or other devices via the opening P through bonding wires, solder balls, metal bumps, etc.

[0012] The circuit chip C2 includes multiple transistors 31. Each transistor 31 has a gate electrode 32 disposed on a substrate 15 separated by a gate insulating film, and a source diffusion layer and a drain diffusion layer (not shown) disposed within the substrate 15. Additionally, the circuit chip C2 includes multiple contact plugs 33, a wiring layer 34, and a wiring layer 35. The multiple contact plugs 33 are disposed on the source diffusion layer or the drain diffusion layer of the transistor 31. The wiring layer 34 is disposed on the contact plugs 33 and includes multiple wirings. The wiring layer 35 is disposed on the wiring layer 34 and includes multiple wirings.

[0013] The circuit chip C2 also includes a wiring layer 36, multiple via plugs 37, and multiple metal pads 38. The wiring layer 36 is disposed on the wiring layer 35 and includes multiple wirings. The multiple via plugs 37 are disposed on the wiring layer 36, and the multiple metal pads 38 are disposed on the via plugs 37. The metal pads 38 are disposed below the metal pads 41 of the array chip C1.

[0014] Circuit chip C2 is bonded to array chip C1 at bonding surface S. Specifically, the interlayer insulating film 13 of array chip C1 and the interlayer insulating film 14 of circuit chip C2 are bonded at bonding surface S. Furthermore, the metal pads 41 of array chip C1 and 38 of circuit chip C2 are bonded at bonding surface S. Thus, array chip C1 and circuit chip C2 are electrically connected via metal pads 38 and 41.

[0015] Figure 2 This is a cross-sectional view showing the structure of the columnar portion CL in the semiconductor device of the first embodiment. Figure 3 This illustrates the structure of the columnar portion CL in the semiconductor device according to the first embodiment. Figure 2 Section III-III view.

[0016] like Figure 2 As shown, the memory cell array 11 includes an interlayer insulating film 13 ( Figure 1 The memory cell array 11 comprises a multilayer film 7 consisting of alternating layers of word lines WL and insulating layers 51 and 51A. The word lines WL may contain tungsten (W) as a primary component. The word lines WL may also contain transition elements other than tungsten, such as molybdenum (Mo), titanium (Ti), and niobium (Nb). The insulating layers 51 and 51A are primarily composed of silicon oxide (SiO2). However, as described later, the lower insulating layer 51A and the upper insulating layer 51 differ in their concentrations of Group V elements.

[0017] The columnar portion CL is disposed in the laminated film 7 in a manner that extends through the Z-direction. That is, the columnar portion CL is disposed inside the memory hole MH that extends through the laminated film 7 in the Z-direction. Figure 3 In the example shown, the columnar portion CL has a circular cross-section. The columnar portion CL sequentially comprises a barrier insulating film 52, a charge storage film 53, a tunnel insulating film 54, a channel semiconductor film 55, and a core insulating film 56. The charge storage film 53 is, for example, a silicon nitride film. The charge storage film 53 is formed, for example, on the side of the word line WL and the insulating layer 51, separated by the barrier insulating film 52. The charge storage film 53 can also be a semiconductor layer such as a polysilicon layer. The channel semiconductor film 55 is, for example, a polysilicon layer. The channel semiconductor film 55 is formed, for example, on the side of the charge storage film 53, separated by the tunnel insulating film 54. The barrier insulating film 52, the tunnel insulating film 54, and the core insulating film 56 are, for example, silicon oxide films or metal insulating films.

[0018] In order to even on substrate 16 (reference) Figure 4The heat treatment also ensures a sufficient etching rate for wet etching used to widen the memory aperture MH. The lower (bottom) side of the multiple insulating layers 51, 51A has a higher concentration of Group V elements compared to the upper insulating layers 51 other than the lower side insulating layers 51A. Insulating layer 51A is an example of a first insulating layer. Insulating layer 51 is an example of a second insulating layer. Group V elements are also called Group 15 elements. Phosphorus (P) is a preferred Group V element, for example.

[0019] The lower insulating layer 51A is, for example, an insulating layer that is 10 to 15 layers from the bottommost insulating layer. The lower insulating layer 51A may also be an insulating layer that is about 1 / 10 of the lower insulating layer among multiple insulating layers 51, 51A.

[0020] exist Figure 2 In the example shown, group V elements are contained (i.e., doped) in the lower insulating layer 51A, but not in the upper insulating layer 51. That is, in Figure 2 In the example shown, the concentration of Group V elements in the upper insulating layer 51 is 0%. By including Group V elements in the lower insulating layer 51A, the etching rate of wet etching can be locally increased at the lower end (i.e., the bottom) of the memory hole MH. This increases the diameter (i.e., the bottom diameter) of the memory hole MH at its lower end. Increasing the diameter of the memory hole MH at its lower end reduces the taper of the memory hole MH's tip. That is, it reduces the width deviation of the memory hole MH between its upper and lower ends.

[0021] The concentration of Group V elements in the lower insulating layer 51A can be 1.9% or higher. Here, the higher the concentration of phosphorus (P) in the silicon oxide film (SiO2), the higher the etching rate of the silicon oxide film using diluted fluoric acid. By setting the concentration of Group V elements to 1.9% or higher, the lower insulating layer 51A can maintain a sufficient etching rate for wet etching even after heat treatments such as annealing to reduce warpage of the substrate 16. Specifically, by setting the concentration of Group V elements to 1.9% or higher, the etching rate of the lower insulating layer 51A can be increased to an etching rate equivalent to that of the lower sacrificial layer 57A (i.e., the oxygen-containing SiN film) described later. This not only reduces the width deviation of the memory hole MH between the upper and lower insulating layers 51 and 51A, but also reduces the width deviation of the memory hole MH between the insulating layer 51A and the sacrificial layer 57A (i.e., the word line WL). Therefore, the tip taper of the memory hole MH can be further reduced.

[0022] The concentration of group V elements in the lower insulating layer 51A can be 3.5% or less. By keeping the concentration of group V elements at 3.5% or less, the leakage current between word lines WL caused by group V elements can be reduced. Specifically, by keeping the concentration of group V elements at 3.5% or less, the leakage current between word lines WL can be reduced compared to the leakage current when using the low-density silicon oxide film (SiO2) as the insulating layer 51A, as described later.

[0023] Next, the manufacturing method of the semiconductor device 1 having the above configuration will be described. Figure 4 This is a cross-sectional view showing a method for manufacturing the semiconductor device 1 according to the first embodiment. Figure 4 The diagram shows an array wafer W1 containing multiple array chips C1 before dicing and a circuit wafer W2 containing multiple circuit chips C2 before dicing. The array wafer W1 is also called a memory wafer, and the circuit wafer W2 is also called a CMOS wafer.

[0024] Figure 4 The orientation of the memory wafer W1 and Figure 1 The array chip C1 is facing in the opposite direction. Figure 4 The image shows a memory wafer W1 that has been reversed for bonding. The array wafer W1 is manufactured by bonding and dicing the circuit wafer W2. Figure 1 Semiconductor device 1. That is, Figure 1 The image shows the array chip C1 after it has been reversed for bonding, bonded, and cut.

[0025] exist Figure 4 In the accompanying drawings, reference numeral S1 indicates the upper surface of the memory wafer W1. Reference numeral S2 indicates the upper surface of the circuit wafer W2. The memory wafer W1 includes a substrate 16 disposed under an insulating film 12. The substrate 16 is, for example, a semiconductor substrate such as a silicon substrate. The substrate 16 is an example of a second substrate.

[0026] In the first embodiment, firstly, as Figure 4As shown, a memory cell array 11, an insulating film 12, an interlayer insulating film 13, a stepped structure 21, and metal pads 41 are formed on the substrate 16 of the memory wafer W1. Meanwhile, an interlayer insulating film 14, transistors 31, and metal pads 38 are formed on the substrate 15 of the circuit wafer W2. At this time, via plugs 45, wiring layers 44 and 43, via plugs 42, and metal pads 41 are sequentially formed on the substrate 16. Meanwhile, contact plugs 33, wiring layers 34, 35, and 36, via plugs 37, and metal pads 38 are sequentially formed on the substrate 15. Next, the array wafer W1 and the circuit wafer W2 are bonded together using mechanical pressure. As a result, the interlayer insulating film 13 and the interlayer insulating film 14 are bonded. Next, the array wafer W1 and the circuit wafer W2 are annealed, for example, at 400°C. As a result, the metal pads 41 and 38 are bonded together.

[0027] Then, substrate 15 is thinned using CMP, and substrate 16 is removed using CMP. The array wafer W1 and circuit wafer W2 are then diced into multiple chips. This process manufactures a... Figure 1 The semiconductor device 1 shown. Additionally... Figure 1 The metal pads 46 and passivation film 47 shown are formed on the insulating film 12, for example, after the thin film formation of the substrate 15 and the removal of the substrate 16.

[0028] Although Figure 1 The boundary surfaces of interlayer insulating film 13 and interlayer insulating film 14, and the boundary surfaces of metal pad 41 and metal pad 38 are shown, but these boundary surfaces are usually not visible after the above-described annealing. However, the location of these boundary surfaces can be estimated, for example, by detecting the side of metal pad 41, the tilt of the side of metal pad 38, or the positional offset between the side of metal pad 41 and metal pad 38.

[0029] Figure 5 This is a cross-sectional view showing a detailed manufacturing method of the semiconductor device 1 according to the first embodiment. More specifically, firstly, as... Figure 5 As shown in (a), multiple insulating layers 51, 51A and multiple sacrificial layers 57, 57A are alternately stacked on the substrate 16 (refer to...). Figure 4 A laminated film 70 is formed on top of the first laminated film. The laminated film 70 is an example of a second laminated film. Figure 5 In the example shown, the lower insulating layer 51A is, for example, a silicon oxide film (SiO2) containing phosphorus (P), a group V element. The upper insulating layer 51 is, for example, a silicon oxide film (SiO2) without phosphorus (P).

[0030] The lower insulating layer 51A is formed, for example, by plasma CVD (Chemical Vapor Deposition) using silane (SiH4) gas and helium-diluted phosphine gas (PH3 / He) in a phosphorus-containing manner. Here, the higher the flow rate of PH3 / He gas, the higher the concentration of phosphorus (P) in the silicon oxide film (SiO2). Therefore, by adjusting the flow rate of PH3 / He gas, the concentration of phosphorus (P) in the lower insulating layer 51A can be appropriately adjusted. On the other hand, the upper insulating layer 51 is formed, for example, by plasma CVD using silane (SiH4) gas in a phosphorus-free manner.

[0031] The sacrificial layer 57 is a layer replaced by word lines WL. The lower-side sacrificial layer 57A is, for example, an oxygen-containing silicon nitride (SiN) film. The upper-side sacrificial layer 57 is, for example, an oxygen-free silicon nitride (SiN) film. The lower-side sacrificial layer 57A is formed, for example, by plasma CVD using SiH2Cl2 gas, NH3 gas, and N2O gas in an oxygen-containing manner. By forming the sacrificial layer 57 in an oxygen-containing manner, the wet etching rate of the lower-side sacrificial layer 57A can be increased. The upper-side sacrificial layer 57 is formed, for example, by plasma CVD using SiH2Cl2 gas and NH3 gas in an oxygen-free manner.

[0032] After the formation of the laminated film 70, as Figure 5 As shown in (b), a memory aperture MH is formed in a manner that penetrates the laminated film 70. Figure 5 In the example shown in (b), the memory hole MH is formed using photolithography and RIE (Reactive Ion Etching) using a CF (fluorocarbon) based etching gas. Regarding the formation of the memory hole MH using the RIE method, the sidewalls of the insulating layers 51, 51A and the sacrificial layers 57, 57A are protected by a protective film 8 containing a CF-based polymer generated by the CF-based etching gas, while the process proceeds in the depth direction (-Z direction) of the memory hole MH. By protecting the sidewalls of the insulating layers 51, 51A and the sacrificial layers 57, 57A, the damage layers 51a, 57a generated on the sidewalls due to the RIE method can be reduced.

[0033] Figure 6 It is shown Figure 5 The following is a cross-sectional view of the manufacturing method of the semiconductor device 1 according to the first embodiment. After forming the memory hole MH, as... Figure 6 As shown in (a), the protective film 8 is removed by ashing. After removing the protective film 8, as... Figure 6As shown in (b), the damaged layers 51a and 57a were removed and the memory hole MH was widened by wet etching using diluted fluoric acid (DHF) as the solution.

[0034] Figure 7 This is a detailed cross-sectional view of the manufacturing method of the comparative example semiconductor device 1. Here, when the RIE method is implemented, a thinning of the tip of the memory aperture MH occurs towards the lower layer side of the laminated film 70, resulting in a smaller width (i.e., diameter). The more the depth of the memory aperture MH is increased to increase the storage capacity of the memory cell array 11, the more significant the thinning of the tip of the memory aperture MH becomes. To reduce the thinning of the tip of the memory aperture MH, it is preferable to increase the etching rate of the wet etching used to widen the memory aperture MH on the lower layer side of the laminated film 70. However, if... Figure 7 When the lower insulating layer 51B does not contain phosphorus (P), it is difficult to sufficiently increase the etching rate of the lower insulating layer 51B. Even if the lower insulating layer 51B is a silicon oxide film (SiO2) with low density achieved by adjusting the pressure and weight balance of the process gas, it is still difficult to sufficiently increase the etching rate.

[0035] More specifically, during the period from the formation of the laminated film 70 to the widening of the memory hole MH by wet etching, heat treatment (i.e., annealing) of the substrate 16 is sometimes performed to reduce warpage of the substrate 16. During heat treatment, the insulating layer 51B is heated together with the substrate 16, thereby reducing the etching rate of the insulating layer 51B for wet etching. Therefore, even when using a low-density silicon oxide film (SiO2), it is difficult to sufficiently reduce the tip taper of the memory hole MH. That is, in an insulating layer 51B that does not contain phosphorus (P), it is difficult to sufficiently reduce the width deviation of the memory hole MH between the upper and lower ends.

[0036] Figure 8 yes Figure 6 (b) shows a detailed cross-sectional view of the manufacturing method of semiconductor device 1. On the other hand, as... Figure 8 As shown, in the first embodiment, the lower-side insulating layer 51A contains phosphorus (P). By containing phosphorus (P) in the lower-side insulating layer 51A, the etching rate of wet etching of the lower-side insulating layer 51A can be sufficiently increased. That is, even if the phosphorus (P)-containing insulating layer 51A is heat-treated, the etching rate is difficult to reduce. Therefore, the thinning of the tip of the memory hole MH, which is widened by wet etching, is sufficiently reduced. In other words, according to the phosphorus (P)-containing insulating layer 51A, the deviation in the width of the memory hole MH between the upper and lower ends can be sufficiently reduced.

[0037] exist Figure 8In the example shown, the width (i.e., diameter) of the memory hole MH in the radial direction orthogonal to the Z direction (i.e., the X and Y directions) is largest at the position of the uppermost insulating layer 51A among the plurality of insulating layers 51A on the lower end side containing group V elements. In other words, the inner perimeter of the memory hole MH is largest at the position of the uppermost insulating layer 51A among the plurality of insulating layers 51A on the lower end side. Thus, the memory hole MH of the first embodiment has a portion where the width locally increases between the upper and lower ends, but as a whole, the memory hole MH has a larger width compared to the memory hole MH of the comparative example (see reference). Figure 7 A more uniform width. Reflecting the shape of the memory hole MH, the width (i.e., diameter) of the columnar portion CL in the radial direction orthogonal to the Z direction is greatest at the position of the uppermost insulating layer 51A among the multiple insulating layers 51A on the lower end side.

[0038] Figure 9 It is shown Figure 6 The following is a cross-sectional view of the manufacturing method of the semiconductor device 1 according to the first embodiment. After widening the memory hole MH, as... Figure 9 As shown in (a), a columnar portion CL is embedded in the memory hole MH.

[0039] That is, firstly, a barrier insulating film 52 is formed on the sides of each of the insulating layers 51, 51A and the sacrificial layers 57, 57A. The barrier insulating film 52 is, for example, a silicon oxide film (SiO2). The barrier insulating film 52 is formed, for example, by ALD (Atomic Layer Deposition) using TDMAS (tris(dimethylamino)silane) gas. The barrier insulating film 52 can also be formed on the sides of the sacrificial layer 57 by directly oxidizing the sides of the sacrificial layer 57 using free radical oxidation.

[0040] After the barrier insulating film 52 is formed, a charge storage film 53 is formed on the side opposite to the insulating layers 51, 51A and the sacrificial layers 57, 57A of the barrier insulating film 52. The charge storage film 53 is, for example, a silicon nitride film (SiN). The charge storage film 53 is formed, for example, by the ALD method in a reduced pressure environment (2000 Pa or less) at a temperature above 300°C and below 800°C using dichlorosilane (SiH2Cl2) gas and ammonia (NH3) gas.

[0041] After the charge storage film 53 is formed, a tunnel insulating film 54 is formed on the side of the charge storage film 53 opposite to the blocking insulating film 52. The tunnel insulating film 54 is, for example, a silicon oxynitride (SiON) film. The tunnel insulating film 54 is formed, for example, by the ALD method in a reduced pressure environment (2000 Pa or less) at a temperature above 400°C and below 800°C using hexachlorodisilazane (HCD) gas, ammonia, and oxygen.

[0042] After forming the tunnel insulating film 54, a channel semiconductor film 55 is formed on the side of the tunnel insulating film 54 opposite to the charge storage film 53. The channel semiconductor film 55 is, for example, a silicon (Si) film. The channel semiconductor film 55 is formed, for example, by CVD in a reduced pressure environment (2000 Pa or less) at a temperature above 400°C and below 800°C using silane gas, and then crystallized by annealing. Thus, the silicon film changes from amorphous silicon to polycrystalline silicon.

[0043] After the channel semiconductor film 55 is formed, a core insulating film 56 is formed on the side of the channel semiconductor film 55 opposite to the tunnel insulating film 54. The core insulating film 56 is, for example, a silicon oxide film. The core insulating film 56 is formed, for example, using tetraethyl orthosilicate (TEOS) by CVD.

[0044] After embedding the columnar portion CL within the memory hole MH as described above, a trench (not shown) is formed on the laminated film 70. Following trench formation, the sacrificial layers 57 and 57A are removed by wet etching using the formed trench. The wet etching may employ a solution such as hot phosphoric acid. By removing the sacrificial layers 57 and 57A, as... Figure 9 As shown in (b), a void C is formed between adjacent insulating layers 51 and 51A. Within the void C, the Z-direction surface of insulating layer 51 and the side of the blocking insulating film 52 are exposed.

[0045] After the formation of cavity C, as Figure 2 As shown, the word line WL is formed by filling the hole C.

[0046] As described above, the semiconductor device 1 of the first embodiment includes a substrate 15, a laminated film 7, and a columnar portion CL. The laminated film 7 is disposed above the substrate 15 and has a plurality of insulating layers 51, 51A and a plurality of word lines WL alternately laminated in the Z direction intersecting the upper surface of the substrate 15. The columnar portion CL penetrates the laminated film 7 in the Z direction. The lower insulating layer 51A (i.e., the first insulating layer) of the plurality of insulating layers 51, 51A has a higher concentration of group V elements than the upper insulating layer 51 (i.e., the second insulating layer) of the plurality of insulating layers 51, 51A.

[0047] Furthermore, the method for manufacturing the semiconductor device 1 according to the first embodiment includes forming a laminated film 70 above a substrate 16, the laminated film 70 having a plurality of insulating layers 51, 51A and a plurality of sacrificial layers 57, 57A alternately laminated in a Z direction intersecting the upper surface of the substrate 16. The method also includes forming a memory hole MH penetrating the laminated film 70 in the Z direction. The method further includes processing the memory hole MH in a manner that increases the width (i.e., diameter) in a radial direction orthogonal to the Z direction. The lower insulating layer 51A is formed in a manner that makes the concentration of group V elements higher than that of the upper insulating layer 51.

[0048] Therefore, even after heat treatment, the insulating layer 51A on the lower end side can maintain a high etching rate for wet etching of the widened memory hole MH. This reduces the tip taper of the memory hole MH. Therefore, according to the first embodiment, the width deviation of the memory hole MH (i.e., the columnar portion CL) between the upper and lower ends of the memory hole MH can be reduced. By reducing the width deviation of the memory hole MH, the threshold voltage of the memory cell array 11 can be made more uniform. That is, the electrical characteristics of the semiconductor device 1 can be improved. Furthermore, the columnar portion CL can be appropriately embedded within the memory hole MH.

[0049] In addition, in the first embodiment, the group V element can be phosphorus (P).

[0050] Therefore, since the insulating layer 51A can contain phosphorus (P), it can maintain a high etching rate for wet etching even after heat treatment. Furthermore, by using phosphorus (P) instead of nitrogen (N), the same element contained in the sacrificial layers 57 and 57A, as a Group V element, it is possible to prevent the insulating layer 51A from being removed along with the sacrificial layers 57 and 57A due to the etching solution during the replacement of the sacrificial layers 57 and 57A.

[0051] In addition, in the first embodiment, the concentration of group V elements in the lower end insulating layer 51A can be 1.9% or more.

[0052] This allows for a further increase in the etching rate of the wet-etched insulating layer 51A. Specifically, the etching rate of the insulating layer 51A can be increased to the same level as the etching rate of the sacrificial layer 57A, which is composed of an oxygen-containing silicon oxide film.

[0053] In addition, in the first embodiment, the concentration of group V elements in the lower end insulating layer 51A can be 3.5% or less.

[0054] This improves the withstand voltage of the lower insulating layer 51A, thereby reducing the leakage current between adjacent word lines WL. Specifically, the withstand voltage of the insulating layer 51A can be improved compared to the withstand voltage of the insulating layer composed of a low-density silicon oxide film.

[0055] In addition, in the first embodiment, the V group elements are included in the lower end insulating layer 51A, but not in the upper end insulating layer 51.

[0056] This allows for a localized increase in the etching rate of the insulating layer 51A on the lower side, thereby effectively reducing the tip thinning of the memory hole MH.

[0057] In addition, in the first embodiment, the memory hole MH can be formed using reactive ion etching, and the memory hole MH can be fabricated using wet etching.

[0058] Therefore, it is possible to widen the memory hole MH while removing the damage layer formed on the sidewall of the memory hole MH through RIE.

[0059] Alternatively, in the first embodiment, the sacrificial layer 55A on the lower end side may be formed in an oxygen-containing manner.

[0060] This allows for an increased etch rate of the sacrificial layer 55A on the lower side for wet etching, thus more effectively reducing the tip thinning of the memory hole MH.

[0061] In addition, in the first embodiment, the formation of the memory hole MH can also be carried out while the sidewall of the memory hole MH is protected by a protective film 8 formed on the sidewall of the memory hole MH by the etching gas.

[0062] This reduces the damage layer on the sidewalls of the memory hole MH caused by RIE.

[0063] (Second Implementation) Next, a second embodiment that further improves the withstand voltage of the lower end insulating layer 51A will be described, focusing on the differences from the embodiment described above. Figure 10 This is a cross-sectional view showing the semiconductor device according to the second embodiment.

[0064] This concludes the explanation of an example where the lower insulating layer 51A entirely contains group V elements. In contrast, in... Figure 10In the example shown, the lower insulating layer 51A partially contains group V elements. Specifically, the lower insulating layer 51A includes: a first insulating portion 511 containing group V elements, a second insulating portion 512 disposed on the first insulating portion 511 and not containing group V elements, and a third insulating portion 513 disposed below the first insulating portion 511 and not containing group V elements.

[0065] The first insulating portion 511 is, for example, the phosphorus (P)-containing silicon oxide film (SiO2) described above. The second insulating portion 512 and the third insulating portion 513 are, for example, existing silicon oxide films (SiO2) that do not contain phosphorus (P). By providing the second insulating portion 512, the withstand voltage of the lower end insulating layer 51A can be improved. In addition, by providing the third insulating portion 513, the withstand voltage of the lower end insulating layer 51A can be further improved.

[0066] The second insulating portion 512 and the third insulating portion 513 are thinner than the first insulating portion 511 in the Z direction. For example, the thickness of the second insulating portion 512 and the third insulating portion 513 is less than 1 / 3 of the thickness of the first insulating portion 511. By making the thickness of the second insulating portion 512 and the third insulating portion 513 thinner than the thickness of the first insulating portion 511, it is possible to maintain the voltage resistance of the insulating layer 51A on the lower end side while suppressing the reduction of the etching rate of wet etching.

[0067] Figure 11 This is a cross-sectional view showing the suppression of leakage current in the semiconductor device 1 according to the second embodiment. When the lower insulating layer 51A contains group V elements throughout, it is sometimes difficult to sufficiently ensure the withstand voltage of the lower insulating layer 51A unless special measures are taken to suppress the concentration of group V elements to, for example, below 3.5%. In this case, such as... Figure 11 As shown by arrow A1 in (a), the leakage current flowing between the upper and lower word lines WL may increase.

[0068] In contrast, according to the second embodiment, since group V elements are contained only in the first insulating portion 511 of the insulating layer 51A on the lower end side, the withstand voltage of the insulating layer 51A on the lower end side can be ensured. Therefore, as... Figure 11 As shown by arrow A2 in (b), leakage current can be significantly reduced.

[0069] Furthermore, by providing a second insulating portion 512 and a third insulating portion 513 of the same material above and below the first insulating portion 511, the etch resistance of the insulating layer 51A when replacing the sacrificial layer 57A can be made consistent between the upper and lower ends of the insulating layer 51A. This improves the shape stability of the insulating layer 51A.

[0070] (Third Implementation) Next, an example will be given in which all layers of insulating layer 51 contain group V elements. Figure 12 This is a cross-sectional view showing the semiconductor device 1 according to the third embodiment. Up to this point, an example in which only the insulating layer 51A on the lower end side contains group V elements has been described. In contrast, in... Figure 12 In the example shown, all insulating layers 51-51A from the top to the bottom contain group V elements. The concentration of group V elements can also be increased by a predetermined amount towards the lower layers. According to the third embodiment, since the concentration of group V elements can be adjusted for each of the insulating layers 51-51A, the shape of the memory hole MH can be further improved.

[0071] While several embodiments have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. The novel apparatus and methods described herein can be implemented in various other ways. Furthermore, various omissions, substitutions, and modifications can be made to the manner of the apparatus and methods described herein without departing from the spirit of the invention. The scope of the appended claims and their equivalents is intended to cover such manner and variations falling within the scope and spirit of the invention. [Explanation of reference numerals in the attached figures]

[0072] 1: Semiconductor device; 7: Laminated film; 15: Substrate; 51, 51A: Insulating layer; WL: Word line; CL: Pillar portion; 57, 57A: Sacrificial layer; 70: Laminated film; 511: First insulating portion; 512: Second insulating portion; 513: Third insulating portion.

Claims

1. A semiconductor device comprising: substrate; A laminated film disposed above the substrate, having a plurality of insulating layers and a plurality of electrode layers alternately laminated in a first direction intersecting the upper surface of the substrate; and The columnar portion extends through the laminated film along the first direction. The concentration of group V elements is higher in at least one first insulating layer on the lower end side of the plurality of insulating layers compared to the concentration of group V elements in the second insulating layer other than the first insulating layer among the plurality of insulating layers.

2. The semiconductor device according to claim 1, wherein, The group V element is phosphorus.

3. The semiconductor device according to claim 1, wherein, The concentration of the group V element in the first insulating layer is 1.9% or higher.

4. The semiconductor device according to claim 3, wherein, The concentration of the group V element in the first insulating layer is less than 3.5%.

5. The semiconductor device according to claim 1, wherein, The group V elements are contained in the first insulating layer but not in the second insulating layer.

6. The semiconductor device according to claim 1, wherein, The group V elements are contained in both the first insulating layer and the second insulating layer.

7. The semiconductor device according to claim 1, wherein, The laminated film has two or more of the first insulating layers. The width of the columnar portion in the second direction intersecting the first direction is greatest at the position of the uppermost first insulating layer among the two or more first insulating layers.

8. The semiconductor device according to any one of claims 1 to 7, wherein, The first insulating layer comprises: A first insulating portion, comprising the group V element; and The second insulating portion, disposed on the first insulating portion, does not contain the group V elements.

9. The semiconductor device according to claim 8, wherein, The first insulating layer also includes a third insulating portion disposed below the first insulating portion, which does not contain the group V elements.

10. The semiconductor device according to claim 8, wherein, The second insulating portion is thinner than the first insulating portion in the first direction.

11. The semiconductor device according to claim 9, wherein, The thickness of the third insulating portion in the first direction is thinner than that of the first insulating portion.

12. A method for manufacturing a semiconductor device, include: A second laminated film is formed above the second substrate, the second laminated film having a plurality of insulating layers and a plurality of sacrificial layers alternately laminated in a first direction intersecting the upper surface of the second substrate; Forming a pore that penetrates the second layer of the film along the first direction; as well as The hole is machined in a manner that increases the width of the hole in a second direction intersecting the first direction. At least one first insulating layer on the lower end side of the plurality of insulating layers is formed in such a manner that the concentration of group V elements is higher than that of the second insulating layer other than the first insulating layer among the plurality of insulating layers.

13. The method for manufacturing a semiconductor device according to claim 12, wherein, The holes were formed using reactive ion etching.

14. The method of manufacturing a semiconductor device according to claim 12, wherein, The holes were machined using a wet etching method.

15. The method of manufacturing a semiconductor device according to claim 12, wherein, At least one first sacrificial layer on the lower end side of the plurality of sacrificial layers is formed in an oxygen-containing manner.

16. The method of manufacturing a semiconductor device according to claim 13, wherein, The hole is formed while the sidewalls of the hole are protected by a protective film formed on the sidewalls of the hole by the etching gas.

17. The method of manufacturing a semiconductor device according to claim 16, wherein, It also includes: removing the protective film after the pores are formed. The holes are machined after the protective film is removed.

18. A method for manufacturing a semiconductor device according to any one of claims 12 to 17, wherein, Also includes: After machining the hole, a columnar portion is formed within the hole; and After the columnar portion is formed, the sacrificial layer is replaced with an electrode layer.

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