Semiconductor structure, manufacturing method thereof and memory system

Abstract

The embodiment of the invention provides a semiconductor structure, a manufacturing method thereof and a memory system, and relates to the technical field of semiconductors. The semiconductor structure includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure comprises a memory cell array and a first interconnection layer, and the first interconnection layer comprises a first metal interconnection. The second semiconductor structure comprises a peripheral circuit and a second interconnection layer, the second interconnection layer comprises a second metal interconnection, and the second metal interconnection is connected with a transistor in the peripheral circuit. The first metal interconnection and / or the second metal interconnection are / is covered with an anti-oxidation layer, and the anti-oxidation layer is covered with an oxide layer. According to the scheme provided by the embodiment of the invention, the first metal interconnection and / or the second metal interconnection are / is covered with the anti-oxide layer, so that the first metal interconnection and / or the second metal interconnection in the semiconductor structure can be prevented from being oxidized.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a semiconductor structure, a method for manufacturing the same, and a memory system. Background Technology

[0002] With the continuous rise and development of artificial intelligence (AI), big data, the Internet of Things, mobile devices and communications, and cloud storage, the demand for storage capacity is growing exponentially.

[0003] Planar memory cells have been scaled down to smaller sizes through improvements in process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches its lower limit, planar processes and manufacturing technologies become challenging and costly. Therefore, the storage density of planar memory cells is nearing its upper limit.

[0004] Three-dimensional (3D) memory architecture can solve the density limitations of planar memory cells. Summary of the Invention

[0005] The purpose of this disclosure is to provide a semiconductor structure, a method for manufacturing the same, and a memory system that can prevent oxidation of the first metal interconnect and / or the second metal interconnect in the semiconductor structure.

[0006] This disclosure provides a semiconductor structure, including: a first semiconductor structure comprising a memory cell array and a first interconnect layer, the first interconnect layer including a first metal interconnect; and a second semiconductor structure comprising a peripheral circuit and a second interconnect layer, the second interconnect layer including a second metal interconnect connected to a transistor in the peripheral circuit. The first metal interconnect and / or the second metal interconnect are covered with an anti-oxidation layer, the anti-oxidation layer being covered with an oxide layer.

[0007] In some exemplary embodiments of this disclosure, the first metal interconnect includes spaced-apart first metal contact structures covered with the anti-oxidation layer; the oxide layer is filled between different first metal contact structures; and the first metal contact structures are connected to memory cells within the memory cell array.

[0008] In some exemplary embodiments of this disclosure, the first metal interconnect includes second metal contact structures spaced apart, the second metal contact structures being covered with the anti-oxidation layer; and the oxide layer is filled between different first metal contact structures.

[0009] The first semiconductor structure further includes a first bonding layer, and the second semiconductor structure further includes a second bonding layer bonded to the first bonding layer; the peripheral circuit is coupled to the memory cell array through the first bonding layer and the second bonding layer; the second metal contact structure is connected to the first bonding layer.

[0010] In some exemplary embodiments of this disclosure, the thickness of the anti-oxidation layer is greater than or equal to 0.5 nanometers and less than or equal to 5 nanometers.

[0011] In some exemplary embodiments of this disclosure, the anti-oxidation layer is insulating.

[0012] In some exemplary embodiments of this disclosure, the anti-oxidation layer includes a silicon metal bonding material layer and a silicon dioxide layer; the silicon dioxide layer covers the silicon metal bonding material layer.

[0013] In some exemplary embodiments of this disclosure, the anti-oxidation layer comprises a nitride.

[0014] In some exemplary embodiments of this disclosure, the anti-oxidation layer comprises an oxygen-doped silicon carbide material.

[0015] In some exemplary embodiments of this disclosure, the first metal interconnect and / or the second metal interconnect comprises tungsten.

[0016] In some exemplary embodiments of this disclosure, the oxide layer comprises silicon dioxide.

[0017] This disclosure provides a method for manufacturing a semiconductor structure, comprising: forming a first semiconductor structure, the first semiconductor structure including a memory cell array and a first interconnect layer, the first interconnect layer including a first metal interconnect; and forming a second semiconductor structure, the second semiconductor structure including a peripheral circuit and a second interconnect layer, the second interconnect layer including a second metal interconnect, the second metal interconnect being connected to a transistor in the peripheral circuit. Wherein, the first metal interconnect and / or the second metal interconnect are covered with an anti-oxidation layer, the anti-oxidation layer being covered with an oxide layer.

[0018] In some exemplary embodiments of this disclosure, forming a first semiconductor structure includes: providing a first substrate; forming the memory cell array on the first substrate; forming a first interconnect layer on the memory cell array, the first interconnect layer including the first metal interconnect; forming an anti-oxidation layer on the first metal interconnect, such that the anti-oxidation layer covers the first metal interconnect; and forming an oxide layer on the anti-oxidation layer.

[0019] In some exemplary embodiments of this disclosure, forming the anti-oxidation layer on the first metal interconnect includes: depositing polysilicon on the first metal interconnect; and oxidizing the polysilicon to obtain the anti-oxidation layer.

[0020] In some exemplary embodiments of this disclosure, forming the anti-oxidation layer on the first metal interconnect includes: depositing a nitride or oxygen-doped silicon carbide material on the first metal interconnect to form the anti-oxidation layer.

[0021] In some exemplary embodiments of this disclosure, forming the first interconnect layer on the memory cell array includes: generating the first metal interconnects spaced apart on the memory cell array using a multiple exposure technique.

[0022] In some exemplary embodiments of this disclosure, forming a second semiconductor structure includes: providing a second substrate; forming the peripheral circuit on the second substrate; forming a second interconnect layer on the peripheral circuit, the second interconnect layer including the second metal interconnect; forming an anti-oxidation layer on the second metal interconnect, such that the anti-oxidation layer covers the second metal interconnect; and forming an oxide layer on the anti-oxidation layer.

[0023] In some exemplary embodiments of this disclosure, forming the anti-oxidation layer on the second metal interconnect includes: depositing polysilicon on the second metal interconnect; and oxidizing the polysilicon to obtain the anti-oxidation layer.

[0024] In some exemplary embodiments of this disclosure, forming the anti-oxidation layer on the second metal interconnect includes: depositing a nitride or oxygen-doped silicon carbide material on the second metal interconnect to form the anti-oxidation layer.

[0025] In some exemplary embodiments of this disclosure, forming the second interconnect layer on the peripheral circuit includes: generating spaced second metal interconnects on the peripheral circuit using a multiple exposure technique.

[0026] This disclosure provides a memory system, including: a memory; and a memory controller coupled to the memory and configured to control the memory. The memory includes: a first semiconductor structure including a memory cell array and a first interconnect layer, the first interconnect layer including a first metal interconnect; and a second semiconductor structure including peripheral circuitry and a second interconnect layer, the second interconnect layer including a second metal interconnect connected to a transistor within the peripheral circuitry. The first metal interconnect and / or the second metal interconnect are covered with an anti-oxidation layer, the anti-oxidation layer being covered with an oxide layer. Attached Figure Description

[0027] Figure 1 A cross-sectional view of a semiconductor structure according to an embodiment of the present disclosure is shown.

[0028] Figure 2 A schematic diagram illustrating the fabrication of a second semiconductor structure according to an embodiment of this disclosure is shown.

[0029] Figure 3 A cross-sectional view of another second semiconductor structure in an embodiment of this disclosure is shown.

[0030] Figure 4 A cross-sectional view of yet another second semiconductor structure in an embodiment of this disclosure is shown.

[0031] Figure 5 A cross-sectional view of another semiconductor structure in an embodiment of this disclosure is shown.

[0032] Figure 6 A flowchart illustrating a method for manufacturing a semiconductor structure according to an embodiment of this disclosure is shown.

[0033] Figure 7 A schematic diagram of a method for manufacturing a first semiconductor structure according to an embodiment of the present disclosure is shown.

[0034] Figure 8 A schematic diagram illustrating another method for manufacturing a first semiconductor structure according to an embodiment of this disclosure is shown.

[0035] Figure 9 A block diagram of an exemplary system with a memory is shown in an embodiment of this disclosure.

[0036] Figure 10 A block diagram of a memory system is shown as an example.

[0037] Figure 11 A block diagram of another memory system is shown as an example.

[0038] Figure 12 A schematic circuit diagram of a memory including peripheral circuitry provided for embodiments of this disclosure.

[0039] Figure 13 This is a schematic diagram of a peripheral circuit provided in an embodiment of the present disclosure. Detailed Implementation

[0040] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted.

[0041] The terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this disclosure, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. The symbol " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0042] In this disclosure, unless otherwise expressly specified and limited, terms such as "connection" and "coupled" should be interpreted broadly, for example, referring to electrical connections or the ability to communicate with each other; they can be direct connections or indirect connections through an intermediate medium. Those skilled in the art can understand the specific meaning of these terms in this disclosure according to the specific circumstances.

[0043] It should be readily understood that, for ease of description, spatially relative terms such as “below,” “under,” “down,” “below,” “above,” and “above” may be used herein to describe the relationship between one element or feature as shown in the accompanying drawings and another element or feature (or other elements or features). This disclosure should be interpreted in the broadest possible sense; for example, “above” means not only “directly on something,” but also includes the meaning of “on something” with an intermediate feature or layer in between. Furthermore, “above” or “on top of” means not only “on something” or “above something,” but also includes the meaning of “above something” or “above something” without an intermediate feature or layer in between (i.e., directly on something).

[0044] In addition to the orientations shown in the accompanying drawings, spatially relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatially related descriptive terms used herein may be interpreted accordingly. Furthermore, if the device is flipped, one layer or region will be "below" or "under" another layer or region.

[0045] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafers.

[0046] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entire lower or upper layer structure, or may have a range smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes somewhere. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where interconnect lines and / or via contacts are formed) and one or more dielectric layers.

[0047] In this disclosure, the term "semiconductor structure" refers to the collective term for the entire semiconductor structure formed in the various steps of manufacturing a memory device, including all layers or regions that have been formed. Hereinafter, unless otherwise specified, "semiconductor structure" refers to the intermediate structure including the wafer / wafer and the gate stack structure formed therein.

[0048] As used in this text, the term "3D storage device" refers to a device in a lateral orientation (e.g., Figure 1 On a substrate (shown as X-axis), a vertical orientation (e.g.) is formed. Figure 1 The Z-axis shown is represented as a string of memory transistors (referred to herein as a "memory string," such as a NAND string), which is a semiconductor device that extends vertically relative to the substrate. As used in the text, the term "vertical" refers to a lateral surface nominally perpendicular to the substrate.

[0049] Figure 1 A cross-sectional view of a semiconductor structure according to an embodiment of this disclosure is shown. Figure 1 As shown, the semiconductor structure 10 provided in this embodiment includes a first semiconductor structure 40 and a second semiconductor structure 20.

[0050] The first semiconductor structure 40 includes a memory cell array 42 and a first interconnect layer 41. The first interconnect layer 41 includes a first metal interconnect 411.

[0051] The second semiconductor structure 20 includes a peripheral circuit 22 and a second interconnect layer 21. The second interconnect layer 21 includes a second metal interconnect 211. The peripheral circuit 22 includes a transistor 231. The second metal interconnect 211 is connected to the transistor 231 in the peripheral circuit 22.

[0052] In this disclosure, metal interconnects (including first metal interconnects and second metal interconnects) refer to interconnects (e.g., interconnect lines and / or via contacts) in the interconnect layer that are made of a conductive metal material. For example, at least one of tungsten (W), copper (Cu), etc. W is used as an example in the following embodiments, but this disclosure is not limited thereto.

[0053] In some embodiments, the first metal interconnect 411 is covered with an anti-oxidation layer 412, and the anti-oxidation layer 412 is covered with an oxide layer 413.

[0054] In this embodiment of the disclosure, the anti-oxidation layer refers to a layer that can be used to prevent the metal interconnect from being oxidized. An oxide layer refers to a layer containing oxygen (O) and / or a layer in which oxygen is required in its fabrication process. In the following embodiments, SiO2 (silicon dioxide) layers are used as examples, but this disclosure is not limited thereto.

[0055] In this embodiment of the disclosure, covering the first metal interconnect 411 with an anti-oxidation layer 412 means that the first metal interconnect 411 will not be in direct contact with the oxide layer 413 thereon, and at least the anti-oxidation layer 412 is spaced between the first metal interconnect 411 and the oxide layer 413. By covering the first metal interconnect in the first interconnect layer with an anti-oxidation layer, the oxide layer 413 located on the first metal interconnect in subsequent processes can be prevented from being oxidized by oxygen or oxygen elements in the process.

[0056] In other embodiments, the second metal interconnect 211 is covered with an anti-oxidation layer 212, and the anti-oxidation layer 212 is covered with an oxide layer 213.

[0057] In this embodiment of the disclosure, covering the second metal interconnect 211 with an anti-oxidation layer 212 means that the second metal interconnect 211 will not be in direct contact with the oxide layer 213 thereon, and at least the anti-oxidation layer 212 is spaced between the second metal interconnect 211 and the oxide layer 213. By covering the second metal interconnect in the second interconnect layer with an anti-oxidation layer, the oxide layer 213 located on the second metal interconnect in subsequent processes can be prevented from being oxidized by oxygen or oxygen elements in the process.

[0058] In some other embodiments, the first metal interconnect 411 is covered with an anti-oxidation layer 412, and the anti-oxidation layer 412 is covered with an oxide layer 413; and the second metal interconnect 211 is covered with an anti-oxidation layer 212, and the anti-oxidation layer 212 is covered with an oxide layer 213.

[0059] The semiconductor structure provided in this disclosure covers an anti-oxidation layer between a first metal interconnect in a first interconnect layer of a first semiconductor structure and an oxide layer thereon, and / or covers an anti-oxidation layer between a second metal interconnect in a second interconnect layer of a second semiconductor structure and an oxide layer thereon. On the one hand, oxidation of the metal interconnect can be avoided, thereby preventing an increase in resistance (Rs) after oxidation of the metal interconnect; on the other hand, the effect of oxidation of the metal interconnect on the performance of the oxide layer can be avoided, for example, preventing the TDDB (Time-dependent dielectric breakdown) that affects the oxide layer.

[0060] The oxide layer in this embodiment is a dielectric material. TDDB is a parameter measuring the stability of a dielectric material under long-term voltage stress. If there is no anti-oxidation layer between the metal interconnect and the oxide layer thereon, the surface of the metal interconnect may react with the surrounding oxidizing environment (e.g., oxygen in the oxide layer) when exposed to subsequent process steps. The interface properties between the oxidized metal interconnect and the oxide layer may change, thus affecting the TDDB performance. Furthermore, as a conductive material, the resistance of the metal interconnect is crucial to the overall performance of the semiconductor structure. Oxidation of the metal interconnect leads to the formation of a high-resistivity metal oxide layer on its surface, thereby increasing the resistance of the metal interconnect. This increase in resistance may reduce the conductivity of the semiconductor structure, affecting indicators such as signal transmission speed and power loss.

[0061] In an exemplary embodiment, the thickness of the anti-oxidation layer is greater than or equal to 0.5 nanometers and less than or equal to 5 nanometers.

[0062] In this embodiment, a thin and dense anti-oxidation layer is deposited on the surface of the metal interconnect. This anti-oxidation layer has good anti-oxidation properties and can effectively isolate the metal interconnect from the oxidizing environment in subsequent processes. The thickness of the anti-oxidation layer is set between [0.5, 5] nm, which ensures effective isolation from oxidation without affecting the electrical performance of the metal interconnect. For example, any value such as 1 nm, 1.2 nm, 2 nm, 2.5 nm, 3 nm, 4 nm, 4.1 nm can be used.

[0063] In this embodiment, the thickness of the anti-oxidation layer can be controlled within the aforementioned range in various ways. For example, during the deposition of the anti-oxidation layer, the deposition time and / or deposition rate can be controlled. The deposition time directly affects the amount of material deposited on the metal interconnect, thus determining the thickness of the anti-oxidation layer. The deposition rate refers to the thickness of material deposited on the metal interconnect per unit time. By adjusting the deposition rate, the thickness of the anti-oxidation layer can be controlled more precisely. The deposition rate is affected by various factors, including the concentration, flow rate, temperature, pressure, and geometry of the precursor during the deposition of the anti-oxidation layer. By adjusting these parameters, precise control of the deposition rate can be achieved. For example, in the chemical vapor deposition (CVD) process, the deposition rate can be controlled by adjusting the flow rate and temperature of the precursor during the deposition of the anti-oxidation layer. Furthermore, after the anti-oxidation layer deposition is completed, the thickness of the anti-oxidation layer can be corrected and optimized through post-processing (such as annealing, etching, etc.). For example, chemical mechanical polishing (CMP) technology can be used to thin out excessively thick anti-oxidation layers; or etching technology can be used to remove part of the anti-oxidation layer to adjust its thickness.

[0064] In an exemplary embodiment, the anti-oxidation layer is insulating. In this embodiment, using an insulating material as the anti-oxidation layer prevents it from affecting the performance of conductive metal interconnects, while simultaneously enabling it to function as a dielectric material along with the oxide layer.

[0065] Figure 1 The semiconductor structure 10 shown may be, for example, a 3D memory device. However, it should be understood that the semiconductor structure 10 is not limited to a 3D memory device and may include any suitable semiconductor device. The semiconductor structure 10 disclosed herein is not limited to... Figure 1 The examples shown may include any other suitable semiconductor devices with 2D, 2.5D, or 3D architectures, such as logic devices, volatile memory devices (e.g., Dynamic Random Access Memory (DRAM) and Static Random-Access Memory (SRAM)) and non-volatile memory devices (e.g., flash memory).

[0066] Continue to refer to Figure 1 The second semiconductor structure 20 may include a substrate 23, on which peripheral circuitry 22 is located. The substrate 23 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material.

[0067] Note that in Figure 1The X and Z axes are included to further illustrate the spatial relationships of components in the semiconductor structure 10 having substrate 23. Substrate 23 includes two lateral surfaces (e.g., a top surface and a bottom surface) extending laterally in the X direction (i.e., the lateral direction). As used herein, when the substrate is located in the lowest plane of the semiconductor structure 10 in the Z direction (i.e., the vertical direction), a component (e.g., a layer or device) is determined in the Z direction relative to the substrate of the semiconductor structure 10 (e.g., substrate 23) to be "above," "on top of," or "below" another component (e.g., a layer or device) of the semiconductor structure 10. The same concepts used to describe spatial relationships are applied throughout this disclosure.

[0068] It should be understood that, despite Figure 1 In this configuration, the first semiconductor structure 40 is disposed above the second semiconductor structure 20, but in some embodiments, their relative positions may be reversed. For example, in another semiconductor structure, the first semiconductor structure 40 may be disposed below the second semiconductor structure 20.

[0069] The second semiconductor structure 20 may include peripheral circuitry 22 on substrate 23. Peripheral circuitry 22 may include a plurality of transistors 231 formed on substrate 23. Transistors 231 may be formed "on" substrate 23, wherein all or part of each transistor 231 is formed in substrate 23 (e.g., below the top surface of substrate 23) and / or directly on substrate 23. Isolation regions (e.g., shallow trench isolation (STI), not shown) and doped regions (e.g., source and drain regions of transistor 231, not shown) may be formed in substrate 23.

[0070] In some embodiments, peripheral circuitry 22 may include any suitable digital, analog, and / or mixed-signal peripheral circuitry for facilitating the operation of semiconductor structure 10. For example, peripheral circuitry 22 may include one or more of page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers, charge pumps, current or voltage references, or any active or passive components of circuitry (e.g., transistors, diodes, resistors, or capacitors). In some embodiments, peripheral circuitry 22 is formed on substrate 23 using complementary metal-oxide-semiconductor (CMOS) technology.

[0071] The second semiconductor structure 20 may include a second interconnect layer 21 above the peripheral circuitry 22 for transmitting electrical signals to and from the peripheral circuitry 22. The second interconnect layer 21 may include a plurality of second metal interconnects 211, including lateral interconnects and / or vertical interconnect access (via) contacts (or via contacts). As used herein, the term “interconnect” may broadly include any suitable type of interconnect, such as middle end of line (MEOL) interconnects and back end of line (BEOL) interconnects. As described in detail below, the second metal interconnects 211 in the second interconnect layer 21 may include functional interconnects electrically connected to the peripheral circuitry 22 (e.g., transistor 231), and optionally, dummy interconnects not electrically connected to any device in the peripheral circuitry 22. The second interconnect layer 21 also includes one or more interlayer dielectric (ILD) layers (also referred to as “intermetal dielectric (IMD) layers”) in which interconnects and via contacts / via contacts may be formed. That is, the second interconnect layer 21 may include a second metal interconnect 211 among multiple ILD layers. The ILD layers in the second interconnect layer 21 may, for example, include an oxide layer 213. The second metal interconnect 211 in the second interconnect layer 21 may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), silicides, or any combination thereof. The ILDs in the second interconnect layer 21 may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low k) dielectrics, or any combination thereof.

[0072] exist Figure 1 In this embodiment, the second interconnect layer 21 includes a plurality of second metal interconnects 211, which are spaced apart. For example, the spaced-apart second metal interconnects 211 can be a plurality of vertical via contacts in the second interconnect layer 21. At least a portion (described here as all) of the plurality of second metal interconnects 211 are covered with an anti-oxidation layer 212, and the oxide layer 213 is filled between two adjacent second metal interconnects covered with the anti-oxidation layer 212.

[0073] In some embodiments, the semiconductor structure 10 is a NAND flash memory device, wherein the memory cells in the memory cell array 42 are provided in the form of an array of NAND memory strings, each memory string extending vertically above the peripheral circuitry 22. The memory cell array 42 may include NAND memory strings that extend vertically through multiple pairs (referred to herein as “conductor / dielectric layer pairs”), each comprising a conductor layer and a dielectric layer. The stacked conductor / dielectric layer pairs are also referred to herein as “memory stack layers”. The conductor layers and dielectric layers in the memory may be stacked alternately in the vertical direction.

[0074] like Figure 1 As shown, each NAND flash memory string may include a semiconductor channel 4211 and a dielectric layer 421 (also referred to as a "memory film"). In some embodiments, the semiconductor channel 4211 includes silicon, such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon. In some embodiments, the memory film is a composite layer including a tunneling layer 4212, a memory layer 4213 (also referred to as a "charge trapping / memory layer"), and a barrier layer (not shown). Each NAND flash memory string may have a cylindrical shape (e.g., a column). According to some embodiments, the semiconductor channel 4211, tunneling layer 4212, memory layer 4213, and barrier layer are arranged radially from the center of the column outwards. The tunneling layer 4212 may include silicon oxide, silicon oxynitride, or any combination thereof. The memory layer 4213 may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high-k dielectric, or any combination thereof.

[0075] In some embodiments, the NAND memory string also includes a plurality of control gates (each control gate being part of a word line). Each conductor layer in the memory stack can serve as a control gate for a memory cell of each NAND memory string. Each NAND memory string may include a source select gate at its upper end and a drain select gate at its lower end. As used herein, the “upper end” of a component (e.g., a NAND memory string) is the end located away from the substrate 23 in the Z direction, and the “lower end” of a component (e.g., a NAND memory string) is the end located closer to the substrate 23 in the Z direction.

[0076] In some embodiments, the first semiconductor structure 40 further includes a semiconductor layer 43 disposed above and in contact with the NAND memory string. The memory cell array 42 may be disposed below the semiconductor layer 43. In some embodiments, the semiconductor layer 43 includes a plurality of semiconductor plugs 49 electrically isolated by isolation regions. In some embodiments, each semiconductor plug 49 is disposed at the upper end of a corresponding NAND memory string and serves as the drain of the corresponding NAND memory string, and thus can be considered part of the corresponding NAND memory string. The semiconductor plug 49 may comprise monocrystalline silicon. The semiconductor plug 49 may be undoped, partially doped (in the thickness and / or width direction) by p-type or n-type dopants, or fully doped.

[0077] In some embodiments, the first semiconductor structure 40 includes local interconnects formed in one or more ILD layers and in contact with components such as word lines (e.g., conductor layers) and NAND memory strings in the memory cell array 42. The local interconnects may include word line via contacts 46, source line via contacts 45, and bit line via contacts 48. Each local interconnect may include a conductive material, including but not limited to W / Co, Cu, Al, silicides, or any combination thereof. Word line via contacts 46 may extend vertically through one or more ILD layers. Each word line via contact may contact a corresponding conductor layer to individually address a corresponding word line. Each source line via contact 45 may contact the source of a corresponding NAND memory string. Bit line via contacts 48 may extend vertically through one or more ILD layers. Each bit line via contact 48 may be electrically connected to a corresponding semiconductor plug 49 (e.g., drain) of a NAND memory string to individually address the corresponding NAND memory string.

[0078] Similar to the second semiconductor structure 20, the first semiconductor structure 40 may also include an interconnect layer for transmitting electrical signals to and from the NAND memory string. For example... Figure 1 As shown, the first semiconductor structure 40 may include a first interconnect layer 41 beneath the memory cell array 42. The first interconnect layer 41 may include a plurality of first metal interconnects 411, including interconnects and via contacts / via contacts in one or more ILD layers. The first metal interconnects 411 may be connected to memory cells within the memory cell array 42. For example, the first metal interconnects 411 in the first interconnect layer 41 may include functional interconnects electrically connected to NAND memory strings (each NAND memory string may include multiple memory cells), and optionally, may also include dummy interconnects not electrically connected to any NAND memory string in the memory cell array 42.

[0079] exist Figure 1In this embodiment, the first interconnect layer 41 includes a plurality of first metal interconnects 411, which are spaced apart. For example, the spaced first metal interconnects 411 can be a plurality of vertical via contacts in the first interconnect layer 41. At least a portion (to exemplify all) of the plurality of first metal interconnects 411 are covered with an anti-oxidation layer 412, and the oxide layer 413 is filled between two adjacent first metal interconnects 411 covered with the anti-oxidation layer 412.

[0080] For example, a self-aligned quadruple patterning (SAQP) process can be used to form the aforementioned spaced first metal interconnect 411 and / or second metal interconnect 211. For instance, by etching W, the desired pattern can be transferred onto W using SAQP, followed by covering with an anti-oxidation layer, and then filling with an oxide layer (also known as a dielectric layer), such as SiO2.

[0081] SAQP achieves denser and more precise patterning on the same semiconductor structure by breaking down the patterning process into multiple steps and precisely controlling pattern formation at each step. This disclosure, through the use of SAQP for precise etching of W, can form conductive channels and interconnect structures with excellent electrical performance and reliability, while reducing reliance on advanced lithography machines such as Extreme Ultraviolet (EUV) to some extent, thus lowering manufacturing costs. This helps reduce parasitic effects such as resistance and capacitance, improves signal transmission speed and stability, and thereby enhances the overall performance and reliability of the semiconductor structure.

[0082] It is understood that other processes can also be used to form metal interconnects in the embodiments of this disclosure, such as self-aligned quadruple patterning (SADP), but this disclosure is not limited thereto.

[0083] Figure 1 In the semiconductor structure 10 shown, the first interconnect layer 41 may include 1, 2, 3 or more layers, and the number of layers in the second interconnect layer 21 may be any one from 1 to 7 or more layers.

[0084] like Figure 1As shown, another interconnect layer (referred to herein as the "BEOL interconnect layer") may be disposed above the memory cell array 42 and may include interconnects, such as interconnects 441 and via contacts 442 in one or more ILD layers. The BEOL interconnect layer 44 may also include contact pads 443 and a redistribution layer (not shown) at the top of the semiconductor structure 10 for wire bonding and / or intercalation bonding. The BEOL interconnect layer 44 and the first interconnect layer 41 may be formed on opposite sides of the memory cell array 42. In some embodiments, the interconnects 441, via contacts 442, and contact pads 443 in the BEOL interconnect layer 44 may transmit electrical signals between the semiconductor structure 10 and external circuitry. In some embodiments, the solutions provided in this disclosure may also be applied to the BEOL interconnect layer 44, i.e., covering the interconnects (which may include metal interconnects) in the BEOL interconnect layer 44 with an anti-oxidation layer, and then covering the anti-oxidation layer with an oxide layer.

[0085] Figure 2 A schematic diagram illustrating the fabrication of a second semiconductor structure according to an embodiment of this disclosure is shown. Figure 2 The embodiment uses the manufacturing process of the second semiconductor structure as an example for illustration; the manufacturing process of the first semiconductor structure can be referred to. For example... Figure 2 As shown, a peripheral circuit 22 is formed on a substrate 23, and then a second metal interconnect 211 spaced apart is formed on the peripheral circuit 22. The second metal interconnect 211 may be, for example, W.

[0086] When the pattern is transferred onto W via SAQP, and then SiO2 is filled to form SiO2 on the surface of W, the use of O2 in the SiO2 manufacturing process causes W to come into direct contact with O2, resulting in oxidation of W, for example, forming... Figure 2 The metal oxides shown (e.g., WO3) x Layer 212'. This may affect the electrical properties of the semiconductor structure, such as TDDB and Rs.

[0087] In some embodiments, the degree of oxidation of W can be reduced by lowering the temperature during the SiO2 manufacturing process. For example, low-temperature deposition techniques, such as low-temperature chemical vapor deposition (LTCVD) or atomic layer deposition (ALD), can be used to reduce the oxidation of W during deposition. On the one hand, lowering the temperature still makes it difficult to completely prevent W oxidation; oxidation of W is still inevitable. On the other hand, lowering the temperature can cause shrinkage of the semiconductor structure, and when the shrinkage is significant, it can lead to cracks in the semiconductor structure.

[0088] In other embodiments, an inert gas (such as nitrogen or argon) can be introduced as a protective atmosphere during the SiO2 manufacturing process to isolate oxygen during heat treatment and reduce the degree of oxidation of W. However, this may lead to the release of outgassing gases such as C / H / N in subsequent processes, thereby affecting the performance of the semiconductor structure.

[0089] In an exemplary embodiment, the anti-oxidation layer includes a silicon metal bonding material layer and a silicon dioxide layer; the silicon dioxide layer covers the silicon metal bonding material layer.

[0090] Figure 3 Taking the second semiconductor structure 20 as an example. Figure 3 As shown, the anti-oxidation layer 212 covering the second metal interconnect 211 of the second semiconductor structure 20 includes a silicon metal bonding material layer 2121 and a silicon dioxide layer 2122, with the silicon dioxide layer 2122 covering the silicon metal bonding material layer 2121.

[0091] Figure 3 In this embodiment, after forming spaced second metal interconnects 211 on the peripheral circuit 22, polysilicon (polycrystalline silicon) can be deposited on the second metal interconnects 211. The precursor used for poly deposition is a silicon-containing compound (e.g., silicon-containing compounds such as silane (SiH4), disilane (Si2H6), and trisilane (Si3H8), organosilicon compounds, or silicon alkoxides, etc.). These compounds can decompose or react during deposition to form a polycrystalline silicon thin film. The silicon deposited on the exposed surface of the second metal interconnects 211 may react with a metal (e.g., W) in the second metal interconnects 211 to generate a silicon metal bonding material layer (e.g., W). x Si y The polycrystalline silicon covering the surface of this silicon metal bonding material layer reacts with oxygen in subsequent processes, such as the manufacturing process of oxide layer 213 (which could also be SiO2), to generate silicon dioxide layer 2122 in anti-oxidation layer 212. Here, x and y are both positive integers greater than or equal to 1.

[0092] In an exemplary embodiment, during the poly deposition process, W-Si bonds can form between poly and W. Unlike simple elemental W and Si, these bonds can be detected by electron energy loss spectroscopy (EELS). The formation of W-Si bonds results in specific energy loss characteristic peaks appearing in the EELS spectrum. EELS can also indirectly prove the existence of W-Si bonds by identifying W and Si elements in the anti-oxidation layer. By analyzing the energy loss edges (such as K-absorption edges, L-absorption edges, etc.) of W and Si elements and their interactions, it can be inferred whether W and Si are chemically bonded. EELS can also be combined with other characterization techniques (such as X-ray photoelectron spectroscopy (XPS), Auger electron spectroscopy (AES), etc.) to further analyze the type (such as covalent, ionic, or metallic) and properties of W-Si bonds. During EELS testing, the anti-oxidation layer or semiconductor structure is placed in a transmission electron microscope (TEM) and tested using an EELS accessory.

[0093] This embodiment employs poly deposition to generate an anti-oxidation layer. On one hand, both the silicon metal bonding material layer and the silicon dioxide layer in the anti-oxidation layer are non-conductive, thus not affecting the conductivity of the metal interconnects or the non-conductivity of the oxide layer. On the other hand, during poly deposition, a silicon metal bonding material layer that is not easily oxidized is first formed on the metal interconnects. Furthermore, during the subsequent fabrication of the oxide layer, oxygen reacts with the poly surface to generate a silicon dioxide layer, thereby preventing direct contact between the metal interconnects and oxygen in the oxide layer. This effectively prevents or mitigates oxidation of the metal in the metal interconnects, reducing the impact on the TDDB performance and Rs of the semiconductor structure and increasing the process window. Simultaneously, polysilicon is easy to deposit and reacts with oxygen to generate SiO2. This ensures that both the silicon dioxide layer in the anti-oxidation layer and the silicon dioxide layer in the oxide layer contain SiO2, reducing the impact on the oxide layer. SiO2 not only possesses excellent insulating properties but also exhibits good chemical and thermal stability. This contributes to improving the stability and reliability of the entire semiconductor structure. However, it is understood that other suitable materials besides polysilicon can be selected to form the anti-oxidation layer.

[0094] In an exemplary embodiment, the deposition of poly can employ chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable thin film deposition techniques. This allows for precise control of the film thickness and uniformity, forming a continuous, dense anti-oxidation layer and ensuring its quality.

[0095] In an exemplary embodiment, during the deposition of poly, the deposition time, content, deposition rate, etc., can be controlled to deposit a thin layer of poly on the metal interconnect, so as to form a thin, uniform, dense and continuous anti-oxidation layer on the metal interconnect, which isolates the metal interconnect from direct contact with the oxidizing environment. This achieves the effect of preventing the metal interconnect from being oxidized and not affecting the conductivity of the metal interconnect.

[0096] In an exemplary embodiment, to detect the silica layer in the anti-oxidation layer and distinguish it from the oxide layer, chlorine (Cl) can be added to the precursor during poly deposition. This Cl may not completely volatilize or be removed during oxidation, but may partially remain in the formed silica layer. Therefore, the silica layer has a different chemical composition than the oxide layer formed by direct thermal oxidation of silicon. Thus, the silica layer formed when the poly is oxidized will contain Cl. The Cl in the silica layer can be detected using energy-dispersive X-ray spectroscopy (EDX).

[0097] In an exemplary embodiment, when manufacturing the oxide layer (SiO2 as an example here), a thermal oxidation method can be used, whereby the oxide layer is generated by a chemical reaction between silicon and an oxidant (e.g., oxygen or water vapor) at a high temperature (e.g., 900–1200°C). That is, in the solution provided in this disclosure, by first covering the metal interconnect with an anti-oxidation layer, it is not necessary to lower the temperature during the oxide layer manufacturing process, nor is it necessary to reduce the content of the oxidant (e.g., reduce oxygen plasma), nor is it necessary to introduce a protective gas. This achieves the effect of preventing the metal interconnect from being oxidized, thereby not affecting the quality of the oxide layer and improving the breakdown resistance of W. Simultaneously, it avoids the release of byproduct gases such as C / H / N in subsequent processes, avoids shrinkage caused by temperature reduction, and prevents problems such as cracking.

[0098] In other embodiments, the anti-oxidation layer 412 covering the first metal interconnect 411 of the first semiconductor structure 40 includes a silicon metal bonding material layer and a silicon dioxide layer, wherein the silicon dioxide layer in the anti-oxidation layer 412 covers the silicon metal bonding material layer.

[0099] In an exemplary embodiment, the anti-oxidation layer comprises a nitride.

[0100] In an exemplary embodiment, the anti-oxidation layer comprises an oxygen-doped silicon carbide material.

[0101] In an exemplary embodiment, the anti-oxidation layer comprises silicon carbide (e.g., SiC).

[0102] Figure 4 Taking the second semiconductor structure 20 as an example. Figure 4 As shown, the anti-oxidation layer 212 covering the second metal interconnect 211 of the second semiconductor structure 20 includes SiN (silicon nitride, a type of nitride) or SiCO (oxygen-doped silicon carbide material).

[0103] Figure 4 In this embodiment, SiN / SiCO can be deposited on the second metal interconnects 211 after forming spaced-apart second metal interconnects 211 on the peripheral circuit 22. SiN / SiCO is stable and does not react with the metal (e.g., W) in the second metal interconnects 211. In subsequent processes, such as the fabrication of the oxide layer 213 (which could also be SiO2), SiN / SiCO also does not react with the oxygen therein.

[0104] In an exemplary embodiment, the N / C elements in SiN / SiCO can be detected on the W surface by EDX.

[0105] In other embodiments, when SiN / SiCO is used as a liner layer (i.e., an anti-oxidation layer), it may interact with the W surface or form an interface layer. The N and C elements in these interface layers may be chemically bonded to W or exist as impurity elements near the W surface. The presence and distribution of these elements on the W surface can be detected by EDX analysis.

[0106] This embodiment employs SiN / SiCO deposition to generate an anti-oxidation layer. On one hand, SiN / SiCO possesses excellent thermal stability, ensuring it does not affect the conductivity of the metal interconnects or the non-conductive properties of the oxide layer. On the other hand, the SiN / SiCO deposition process forms a layer on the metal interconnects that is resistant to oxidation. During subsequent oxide layer fabrication, direct contact between the metal interconnects and oxygen in the oxide layer is avoided, effectively preventing or mitigating oxidation of the metal in the metal interconnects. This reduces the impact on the TDDB performance and Rs of the semiconductor structure, and increases the process window. Ultimately, this contributes to improving the stability and reliability of the entire semiconductor structure.

[0107] In other embodiments, the anti-oxidation layer 412 covering the first metal interconnect 411 of the first semiconductor structure 40 includes a nitride or oxygen-doped silicon carbide material or silicon carbide.

[0108] In an exemplary embodiment, the first semiconductor structure further includes a first bonding layer, and the second semiconductor structure further includes a second bonding layer bonded to the first bonding layer; the peripheral circuit is coupled to the memory cell array through the first bonding layer and the second bonding layer.

[0109] The following is for reference. Figure 5 Examples are provided, but this disclosure is not limited thereto. For example... Figure 5 As shown, the second semiconductor structure 20 includes a substrate 23 (which may also be referred to as the second substrate for distinction), and peripheral circuitry 22, a second interconnect layer 21, and a second bonding layer 50 sequentially stacked on the substrate 23. The second interconnect layer 21 may include an IDL layer 213' (which may contain an oxide layer 213), in which a second metal interconnect 211-1 (functional interconnect) and a second metal interconnect 211-2 (dummy interconnect) are disposed. The second bonding layer 50 may include a second dielectric layer 51, in which a first bonding contact 52 and a second bonding contact 53 are disposed. The first bonding contact 52 (functional bonding contact) is connected to the second metal interconnect 211-1 in the second interconnect layer 21 through a first conductive channel 54 to achieve coupling with devices (e.g., transistors) in the peripheral circuitry 22. The second bonding contact 53 (dummy bonding contact) has no conductive channel connected to the second metal interconnect 211-2, and is therefore not coupled to devices in the peripheral circuitry 22.

[0110] Figure 5 In this embodiment, the first bonding contact 52 and the first conductive channel 54 employ a dual damascene process, which involves two patterning processes (e.g., two photolithography and development processes) to increase bonding yield. Simultaneously, by achieving a proper distribution of the first bonding contact 52 and the second bonding contact 53 within the bonding layer, the required uniformity of metal and dielectric distribution can be achieved, avoiding inhomogeneities in device corrosion control and pitting control during subsequent chemical mechanical polishing (CMP) processes.

[0111] The first semiconductor structure 40 includes a second substrate 43, and a memory cell array 42, a first interconnect layer 41, and a first bonding layer 60 sequentially stacked under the second substrate 43. The first interconnect layer 41 may include an IDL layer 413' (which may include an oxide layer 413), in which a second metal interconnect 411-1 (functional interconnect) and a second metal interconnect 411-2 (dummy interconnect) are disposed. The first bonding layer 60 may include a first dielectric layer 61, in which a third bonding contact 612 and a fourth bonding contact 613 are disposed. The third bonding contact 612 (functional bonding contact) is connected to the second metal interconnect 411-1 in the first interconnect layer 41 via a third conductive channel 614 to achieve coupling with devices (e.g., memory cells) in the memory cell array 42. The fourth bonding contact 613 (dummy bonding contact) has no conductive channel connected to the second metal interconnect 411-2, and is therefore not coupled to devices in the memory cell array 42.

[0112] Figure 5 In this embodiment, the third bonding contact 612 and the third conductive channel 614 employ a dual damascene process, which involves two patterning processes (e.g., two photolithography and development processes) to increase bonding yield. Simultaneously, by achieving a proper distribution of the third bonding contact 612 and the fourth bonding contact 613 within the first bonding layer 60, the desired uniformity of metal and dielectric distribution can be achieved, avoiding inhomogeneities in device corrosion control and recess control during subsequent chemical mechanical polishing (CMP) processes.

[0113] Continue to refer to Figure 5 The semiconductor structure may also include a bonding interface 56 between the second semiconductor structure 20 and the first semiconductor structure 40.

[0114] exist Figure 5 In this embodiment, on opposite sides of the bonding interface 56, the first bonding contact 52 is coupled to the third bonding contact 612 to achieve electrical coupling between the second semiconductor structure 20 and the first semiconductor structure 40; at least some of the second bonding contacts 53 are coupled to a corresponding fourth bonding contact 613 (a dummy bonding contact), which is not part of the electrical connection across the bonding interface 56 and between the second semiconductor structure 20 and the first semiconductor structure 40. This improves bonding strength and reliability, thereby increasing product yield.

[0115] The bonded semiconductor structure may include two semiconductor structures (referred to as the first semiconductor structure and the second semiconductor structure, respectively) bonded face-to-face at the bonding interface. In some embodiments, the bonding interface may employ hybrid bonding (also referred to as "metal / dielectric hybrid bonding").

[0116] Hybrid bonding is a direct bonding technique (e.g., forming bonds between surfaces without the use of intermediate layers (e.g., solder or adhesive)) that can simultaneously achieve metal-to-metal and dielectric-to-dielectric bonding. In some embodiments, the bonding interface is the location where the first semiconductor structure and the second semiconductor structure meet and bond. In practice, the bonding interface can be a layer of a certain thickness, comprising the bottom surfaces of the first and second semiconductor structures.

[0117] Dummy bonding contacts are not part of the electrical connection between the first and second semiconductor structures. Dummy bonding contacts can be used to increase the local density of bonding contacts at the bonding interface to increase bonding yield and strength. Bonding contacts may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The remaining region of the bonding layer (including the first and second bonding layers) may be formed by dielectric layers (including the first and second dielectric layers), including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. Bonding contacts and dielectric layers in the bonding layer can be used for hybrid bonding.

[0118] In some embodiments, the first interconnect layer and the second interconnect layer include a pair of dummy interconnects that are not electrically connected to the NAND memory string and the transistor, and a pair of dummy bonding contacts can contact the pair of dummy interconnects on opposite sides of the bonding interface, respectively, without forming an electrical connection between the first semiconductor structure and the second semiconductor structure.

[0119] Figure 6 A flowchart illustrating a method for manufacturing a semiconductor structure according to an embodiment of this disclosure is shown. Figure 6 As shown, the method provided in this embodiment includes the following steps.

[0120] In S10, a first semiconductor structure is formed, the first semiconductor structure including a memory cell array and a first interconnect layer, the first interconnect layer including a first metal interconnect.

[0121] In S20, a second semiconductor structure is formed, the second semiconductor structure including a peripheral circuit and a second interconnect layer, the second interconnect layer including a second metal interconnect, the second metal interconnect being connected to a transistor in the peripheral circuit.

[0122] Wherein, the first metal interconnect and / or the second metal interconnect are covered with an anti-oxidation layer, and the anti-oxidation layer is covered with an oxide layer.

[0123] It should be noted that the first and second semiconductor structures described above can be formed independently (i.e., the execution order of S10 and S20 is not limited; they can be executed in parallel). Then, the first and second semiconductor structures are bonded together to form a bonded semiconductor structure. This allows for the selection of more advanced logic processes, enabling NAND to achieve higher I / O interface speeds and more operational functions. Once the first and second semiconductor structures are completed, they can be bonded together using billions of vertical interconnect channels (vias), merging them into one. This achieves higher storage density and reduces area. Simultaneously, by fully utilizing the independent processing advantages of the first and second semiconductor structures, parallel and modular product design and manufacturing are achieved, shortening the production cycle.

[0124] In an exemplary embodiment, forming a first semiconductor structure includes: providing a first substrate; forming the memory cell array on the first substrate; forming a first interconnect layer on the memory cell array, the first interconnect layer including the first metal interconnect; forming an anti-oxidation layer on the first metal interconnect, such that the anti-oxidation layer covers the first metal interconnect; and forming an oxide layer on the anti-oxidation layer.

[0125] In an exemplary embodiment, forming a second semiconductor structure includes: providing a second substrate; forming the peripheral circuit on the second substrate; forming a second interconnect layer on the peripheral circuit, the second interconnect layer including a second metal interconnect; forming an anti-oxidation layer on the second metal interconnect, such that the anti-oxidation layer covers the second metal interconnect; and forming an oxide layer on the anti-oxidation layer.

[0126] In this embodiment of the disclosure, an interconnect layer (including the first interconnect layer and the second interconnect layer) comprising a plurality of interconnects (including the aforementioned first metal interconnect and the second metal interconnect) is formed over a substrate (including a first substrate and a second substrate). The substrate may be a silicon substrate. In some embodiments, a memory cell array or peripheral circuitry is formed between the substrate and the interconnect layer before the interconnect layer is formed.

[0127] In some embodiments, the peripheral circuitry is a device layer comprising a plurality of transistors formed on a silicon substrate by a number of processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, CMP and any other suitable processes.

[0128] In some embodiments, the memory cell array is a device layer comprising a plurality of NAND memory strings, each NAND memory string extending vertically through a memory stack layer formed on a silicon substrate. To form the memory stack layer, a dielectric stack layer comprising alternating layers of sacrificial layers (e.g., silicon nitride) and dielectric layers (e.g., silicon oxide) can be formed on the silicon substrate using one or more thin-film deposition processes (including, but not limited to, CVD, physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof). The memory stack layer can then be formed on the silicon substrate using a gate replacement process (i.e., replacing the sacrificial layer in the dielectric stack layer with a conductor layer). In some embodiments, the fabrication process for forming the NAND memory strings includes forming a semiconductor channel extending vertically through the dielectric stack layer, and forming a composite dielectric layer (memory film) between the semiconductor channel and the dielectric stack layer, including, but not limited to, a tunneling layer, a memory layer, and a barrier layer. The semiconductor channel and the memory film can be formed using one or more thin-film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof).

[0129] An interconnect layer is formed over a memory cell array or peripheral circuitry. The interconnect layer may include interconnects, including interconnect lines and via contacts in one or more ILD layers, for electrical connection to the memory cell array or peripheral circuitry. In some embodiments, the interconnect layer includes multiple ILD layers and interconnects formed therein by multiple processes. For example, the interconnects may include conductive materials deposited by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, electrochemical deposition, or any combination thereof). The ILD layers may include dielectric materials deposited by one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof).

[0130] A second bonding layer comprising a plurality of first bonding contacts and second bonding contacts is formed above the second interconnect layer, such that some interconnects contact a corresponding one of the first bonding contacts, while some interconnects do not contact a second bonding contact. A second dielectric layer may also be formed in the second bonding layer. In some embodiments, the first bonding contacts in the second bonding layer are formed by a single patterning process.

[0131] A dielectric layer is deposited on the top surface of the second interconnect layer as a second dielectric layer using a thin-film deposition process (including but not limited to CVD, PVD, ALD, or any combination thereof). According to some embodiments, first and second bonding contacts are formed in the dielectric layer to form a second bonding layer over the second interconnect layer and peripheral circuitry. The first bonding contacts can be patterned by a single patterning process involving only one photolithography step. Excess conductors can be removed by CMP, and the top surface of the bonding layer can be planarized for bonding.

[0132] Other aspects of the semiconductor structure manufacturing method provided in this disclosure can be found in the above embodiments.

[0133] In an exemplary embodiment, forming the anti-oxidation layer on the first metal interconnect includes: depositing polysilicon on the first metal interconnect; and oxidizing the polysilicon to obtain the anti-oxidation layer.

[0134] In an exemplary embodiment, forming the anti-oxidation layer on the second metal interconnect includes: depositing polysilicon on the second metal interconnect; and oxidizing the polysilicon to obtain the anti-oxidation layer.

[0135] Figure 7 The embodiment is illustrated using a second semiconductor structure. For example... Figure 7 As shown, firstly, spaced second metal interconnects 211 are formed on the peripheral circuit 22. Then, polysilicon is deposited on the second metal interconnects 211 to form an anti-oxidation layer 212 covering the second metal interconnects 211. Next, an oxide layer 213, such as SiO2, is formed on the anti-oxidation layer 212. After forming the oxide layer 213, the anti-oxidation layer 212 includes a silicon metal bonding material layer 2121 and a silicon dioxide layer 2122. The silicon dioxide layer 2122 covers the silicon metal bonding material layer 2121.

[0136] In an exemplary embodiment, forming the anti-oxidation layer on the first metal interconnect includes: depositing a nitride or oxygen-doped silicon carbide material on the first metal interconnect to form the anti-oxidation layer.

[0137] In an exemplary embodiment, forming the anti-oxidation layer on the second metal interconnect includes: depositing a nitride or oxygen-doped silicon carbide material on the second metal interconnect to form the anti-oxidation layer.

[0138] Figure 8 The embodiment is illustrated using a second semiconductor structure. For example... Figure 8 As shown, firstly, spaced second metal interconnects 211 are formed on the peripheral circuit 22. Then, SiN / SiCO is deposited on the second metal interconnects 211 to form an anti-oxidation layer 212 (SiN / SiCO) covering the second metal interconnects 211. Subsequently, an oxide layer 213, such as SiO2, is formed on the anti-oxidation layer 212 (SiN / SiCO).

[0139] In an exemplary embodiment, forming the first interconnect layer on the memory cell array includes: generating the first metal interconnects spaced apart on the memory cell array using a multiple exposure technique.

[0140] In an exemplary embodiment, forming the second interconnect layer on the peripheral circuit includes: generating spaced second metal interconnects on the peripheral circuit using a multiple exposure technique.

[0141] The method provided in this disclosure can be applied to any scenario where an oxide layer is deposited on the surface of a metal, such as W, and is not limited to the examples described above.

[0142] The method provided in this disclosure, by depositing an anti-oxidation layer between the metal interconnect and the oxide layer, can prevent the oxidation of metals such as W in the metal interconnect, thereby improving the TDDB and Rs performance of the semiconductor structure. In the future, as the size of semiconductor structures further shrinks, the requirements for reducing the metal oxide thickness or even prohibiting oxidation will increase. Furthermore, the method provided in this disclosure is easily detectable and can be examined using TEM methods.

[0143] This disclosure provides a memory system (also referred to as a storage system), including: a memory; and a memory controller coupled to the memory and configured to control the memory. The memory includes: a first semiconductor structure comprising a memory cell array and a first interconnect layer, the first interconnect layer including a first metal interconnect; and a second semiconductor structure comprising peripheral circuitry and a second interconnect layer, the second interconnect layer including a second metal interconnect connected to a transistor within the peripheral circuitry. The first metal interconnect and / or the second metal interconnect are covered with an anti-oxidation layer, the anti-oxidation layer being covered with an oxide layer.

[0144] Figure 9 A block diagram of an exemplary system with memory is shown according to an embodiment of this disclosure. System 1000 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality device, augmented reality device, or any other suitable electronic device having memory therein.

[0145] like Figure 9 As shown, system 1000 may include a host 1008 and a storage system 1002, the storage system 1002 having one or more memories 1004 and a memory controller 1006. The host 1008 may be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor). The host 1008 may be configured to send data to or receive data from the memories 1004.

[0146] The memory 1004 can be any memory disclosed herein, such as non-volatile memory. The non-volatile memory can be NAND flash memory (e.g., three-dimensional (3D) NAND flash memory).

[0147] In some embodiments, memory controller 1006 is coupled to memory 1004 and host 1008 and is configured to control memory 1004. Memory controller 1006 can manage data stored in memory 1004 and communicate with host 1008.

[0148] In some embodiments, the memory controller 1006 is configured to send commands to the memory 1004 to cause the memory 1004 to perform corresponding operations.

[0149] In some embodiments, the memory controller 1006 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal calculators, digital cameras, mobile phones, etc.

[0150] In some embodiments, the memory controller 1006 is designed to operate in high duty cycle environments, such as solid-state drives (SSDs) or embedded multimedia cards (eMMCs), which can be used as data storage for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays. The memory controller 1006 can be configured to send commands to the memory 1004 to cause the memory 1004 to perform operations, such as read, erase, and program operations.

[0151] The memory controller 1006 can also be configured to manage various functions related to data stored or to be stored in the memory 1004, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc.

[0152] In some embodiments, the memory controller 1006 is also configured to process error correction codes (ECC) regarding data read from or written to the memory 1004. The memory controller 1006 may also perform any other suitable functions, such as formatting the memory 1004. The memory controller 1006 may communicate with external devices (e.g., the host 1008) according to a specific communication protocol. For example, the memory controller 1006 may communicate with external devices via at least one of a variety of interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Devices (IDE), Firewire, etc.

[0153] The memory controller 1006 and one or more memories 1004 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the storage system 1002 can be implemented and packaged into different types of end electronic products.

[0154] Figure 10 A block diagram of a memory system is shown as an example. Figure 10 As shown, the memory controller 1006 and a single memory 1004 can be integrated into the memory card 1102. The memory card 1102 may include a PC card (also known as a PCMCIA card, Personal Computer Memory Card International Association card), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (e.g., MMC card, RS-MMC card, MMCmicro card, etc.), an SD card (e.g., SD card, miniSD card, microSD card, SDHC card, etc.), a UFS card, etc. The memory card 1102 may also include a connector for connecting the memory card 1102 to a host computer (e.g., ...). Figure 9 The memory card connector 1104 is coupled to the host 1008.

[0155] Figure 11 An example block diagram of another storage system is shown. Figure 11 As shown, the memory controller 1006 and multiple memories 1004 can be integrated into the SSD 1106. The SSD 1106 may also include components for connecting the SSD 1106 to a host computer (e.g., ...). Figure 9 The SSD connector 1108 is coupled to the host 1008. In some embodiments, the storage capacity and / or operating speed of the SSD 1106 is greater than the storage capacity and / or operating speed of the memory card 1102.

[0156] Figure 12 A schematic circuit diagram of a memory 1300 including peripheral circuitry provided for embodiments of this disclosure. The memory 1300 may be... Figure 9 An example of memory 1004 is shown. Memory 1300 may include a memory cell array 1301 and peripheral circuitry 22 coupled to the memory cell array 1301. The memory cell array 1301 may be a NAND flash memory cell array, wherein memory cells 1306 are provided in the form of an array of memory strings 1308 of NAND flash memory, each memory string 1308 extending vertically above a substrate (not shown).

[0157] In some embodiments, the peripheral circuit 22 is configured to perform corresponding operations. It is understood that the peripheral circuit 22 may be configured to perform corresponding operations according to instructions received from the memory controller 1006.

[0158] In some embodiments, each memory string 1308 includes a plurality of memory cells 1306 that are series-coupled and vertically stacked. Each memory cell 1306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 1306. Each memory cell 1306 may be a floating-gate type memory cell that includes a floating-gate transistor, or a charge-trapping type memory cell that includes a charge-trapping transistor.

[0159] like Figure 12 As shown, each memory string 1308 may include a source select gate (SSG) 1310 at its source end and a drain select gate (DSG) 1312 at its drain end. The SSG 1310 and DSG 1312 may be configured to activate the selected memory string 1308 during read and program operations.

[0160] In some embodiments, the sources of memory strings 1308 within the same block 1304 are coupled via the same source line (SL) 1314 (e.g., a common SL). For example, all memory strings 1308 within the same block 1304 have an array common source (ACS). Figure 12 As shown, the storage string 1308 can be organized into multiple blocks 1304, each of which can have a common source line 1314 (e.g., coupled to ground). In some embodiments, each block 1304 is a basic data unit for an erase operation, that is, all storage cells 1306 on the same block 1304 are erased simultaneously.

[0161] In some embodiments, the transistor of the DSG 1312 of each memory string 1308 is coupled to a corresponding bit line (BL) 1316, and data can be read from or written to the bit line 1316 via an output bus (not shown). Each memory string 1308 can be configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having the DSG 1312) or a deselection voltage (e.g., 0V) to the corresponding DSG 1312 via one or more DSG lines 1313 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having the SSG 1310) or a deselection voltage (e.g., 0V) to the corresponding SSG 1310 via one or more SSG lines 1315.

[0162] like Figure 12 As shown, the memory cells 1306 of the memory string 1308 can be coupled via word lines (WL) 1318, which selects which row of memory cells 1306 is affected by read and program operations. Peripheral circuitry 22 can be coupled to the memory cell array 1301 via bit lines 1316, word lines 1318, source lines 1314, SSG lines 1315, and DSG lines 1313. Peripheral circuitry 22 can include any suitable analog, digital, and mixed-signal circuitry for facilitating the operation of the memory cell array 1301 by applying voltage and / or current signals to each memory cell 1306 targeted for operation via bit lines 1316, word lines 1318, source lines 1314, SSG lines 1315, and DSG lines 1313, and by sensing voltage and / or current signals from each memory cell 1306 targeted for operation. Peripheral circuitry 22 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology.

[0163] Figure 13 This is a schematic diagram of a peripheral circuit provided in an embodiment of this disclosure. (See diagram below.) Figure 13 As shown, the peripheral circuitry 22 includes one or more of the following: a page buffer / sensor amplifier 1404, a column decoder / BL driver 1406, a row decoder / WL driver 1408, a voltage generator 1410, a control logic unit 1412, a register 1414, input / output (I / O) circuitry 1416, and a data bus 1418. It should be understood that in some examples, it may also include... Figure 13 Additional peripheral circuitry not shown.

[0164] In some embodiments, the page buffer / sensor amplifier 1404 can be configured to read data from and program (write) data to the memory cell array 1301 according to control signals from the control logic unit 1412. For example, the page buffer / sensor amplifier 1404 can store a page of programming data (write data) to be programmed into the memory cell array 1301. As another example, the page buffer / sensor amplifier 1404 can also sense low-power signals from bit lines representing data bits stored in the memory cells and amplify small voltage swings to a recognizable logic level during read operations. The column decoder / BL driver 1406 can be configured to be controlled by the control logic unit 1412 and to select one or more memory strings 1308 by applying a bit line voltage generated from the voltage generator 1410.

[0165] The row decoder / WL driver 1408 can be configured to be controlled by the control logic unit 1412 and to select / deselect blocks of the memory cell array 1301 and select / deselect word lines 1418 of the blocks. The row decoder / WL driver 1408 can also be configured to drive word lines 1418 using word line voltages generated from the voltage generator 1410. In some embodiments, the row decoder / WL driver 1408 can also select / deselect and drive SSG lines 1314 and DSG lines 1313. The voltage generator 1410 can be configured to be controlled by the control logic unit 1412 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages, etc., to be supplied to the memory cell array 1301.

[0166] Control logic unit 1412 can be coupled to each part of peripheral circuitry 22 and is configured to control the operation of each part. Register 1414 can be coupled to control logic unit 1412 and may include a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Input / output circuitry 1416 can be coupled to control logic unit 1412 and acts as a control buffer to buffer inputs from the host (…). Figure 13 The input / output circuit 1416 receives control commands (not shown) and relays them to the control logic unit 1412, and buffers status information received from the control logic unit 1412 and relays it to the host. The input / output circuit 1416 can also be coupled to the column decoder / bit line driver 1406 via the data bus 1418, and acts as a data I / O interface and data buffer to buffer data and relay it to or from the memory cell array 1301.

[0167] Exemplary embodiments of this disclosure have been specifically shown and described above. It should be understood that this disclosure is not limited to the detailed structures, arrangements, or implementations described herein; rather, this disclosure is intended to cover various modifications and equivalent arrangements contained within the spirit and scope of the appended claims.

Claims

1. A semiconductor structure, characterized in that, include: A first semiconductor structure, the first semiconductor structure including a memory cell array and a first interconnect layer, the first interconnect layer including a first metal interconnect; as well as A second semiconductor structure, the second semiconductor structure including a peripheral circuit and a second interconnect layer, the second interconnect layer including a second metal interconnect, the second metal interconnect being connected to a transistor in the peripheral circuit; Wherein, the first metal interconnect and / or the second metal interconnect are covered with an anti-oxidation layer, and the anti-oxidation layer is covered with an oxide layer.

2. The semiconductor structure according to claim 1, characterized in that, A plurality of first metal interconnects are spaced apart, covered with the anti-oxidation layer, and the oxide layer is filled between adjacent first metal interconnects; The first metal interconnect is connected to the memory cells within the memory cell array.

3. The semiconductor structure according to claim 1, characterized in that, The first semiconductor structure further includes a first bonding layer, and the second semiconductor structure further includes a second bonding layer bonded to the first bonding layer; The peripheral circuitry is coupled to the memory cell array via the first bonding layer and the second bonding layer.

4. The semiconductor structure according to claim 1, characterized in that, The thickness of the anti-oxidation layer is greater than or equal to 0.5 nanometers and less than or equal to 5 nanometers.

5. The semiconductor structure according to claim 1, characterized in that, The anti-oxidation layer is insulating.

6. The semiconductor structure according to claim 5, characterized in that, The anti-oxidation layer includes a silicon metal bonding material layer and a silicon dioxide layer; The silicon dioxide layer covers the silicon metal bonding material layer.

7. The semiconductor structure according to claim 5, characterized in that, The anti-oxidation layer includes nitrides.

8. The semiconductor structure according to claim 5, characterized in that, The anti-oxidation layer comprises oxygen-doped silicon carbide material.

9. The semiconductor structure according to claim 1, characterized in that, The first metal interconnect and / or the second metal interconnect comprises tungsten.

10. The semiconductor structure according to claim 1, characterized in that, The oxide layer comprises silicon dioxide.

11. A method for manufacturing a semiconductor structure, characterized in that, include: A first semiconductor structure is formed, the first semiconductor structure including a memory cell array and a first interconnect layer, the first interconnect layer including a first metal interconnect; as well as A second semiconductor structure is formed, the second semiconductor structure including a peripheral circuit and a second interconnect layer, the second interconnect layer including a second metal interconnect, the second metal interconnect being connected to a transistor in the peripheral circuit; Wherein, the first metal interconnect and / or the second metal interconnect are covered with an anti-oxidation layer, and the anti-oxidation layer is covered with an oxide layer.

12. The method according to claim 11, characterized in that, Forming a first semiconductor structure includes: Provide a first substrate; The memory cell array is formed on the first substrate; The first interconnect layer is formed on the memory cell array, and the first interconnect layer includes the first metal interconnect; The anti-oxidation layer is formed on the first metal interconnect, so that the anti-oxidation layer covers the first metal interconnect; The oxide layer is formed on the anti-oxidation layer.

13. The method according to claim 12, characterized in that, Forming the anti-oxidation layer on the first metal interconnect includes: Polysilicon is deposited on the first metal interconnect; The anti-oxidation layer is obtained by oxidizing the polycrystalline silicon.

14. The method according to claim 12, characterized in that, Forming the anti-oxidation layer on the first metal interconnect includes: Nitride or oxygen-doped silicon carbide material is deposited on the first metal interconnect to form the anti-oxidation layer.

15. The method according to claim 12, characterized in that, The first interconnect layer is formed on the memory cell array, including: The first metal interconnects are generated on the memory cell array using a multiple exposure technique.

16. A memory system, characterized in that, include: Memory; as well as A memory controller, which is coupled to the memory and configured to control the memory; The memory includes: A first semiconductor structure, comprising a memory cell array and a first interconnect layer, wherein the first interconnect layer includes a first metal interconnect; and A second semiconductor structure, the second semiconductor structure including a peripheral circuit and a second interconnect layer, the second interconnect layer including a second metal interconnect, the second metal interconnect being connected to a transistor in the peripheral circuit; Wherein, the first metal interconnect and / or the second metal interconnect are covered with an anti-oxidation layer, and the anti-oxidation layer is covered with an oxide layer.

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