Memory device and operating method of the memory device

Abstract

A memory device includes: a bit line extending in a first horizontal direction; a vertical channel layer extending in a vertical direction on the bit line; the first dielectric layer and the second dielectric layer extend in the vertical direction, and the vertical channel layer is located between the first dielectric layer and the second dielectric layer; a pair of word lines facing each other, and the vertical channel layer, the first dielectric layer, and the second dielectric layer being located between the pair of word lines; a plate line on the vertical channel layer, the first dielectric layer and the second dielectric layer; and a capacitor structure disposed on the plate line, and at least one of the first dielectric layer and the second dielectric layer includes a ferroelectric.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0112346, filed on August 21, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Example embodiments of the present invention relate to a memory device including a ferroelectric material and a method of operating the memory device. Background Technology

[0004] As electronic products become faster and consume less power, it is beneficial to improve the programming / sensing operation and lower the operating voltage of memory devices in these products. Ferroelectric materials that can maintain spontaneous polarization even in the absence of an external electric field by arranging internal electric dipole moments are being investigated. The use of non-volatile memory utilizing ferroelectrics in electronic products may be advantageous. Summary of the Invention

[0005] The exemplary embodiments of the present invention relate to a memory device that can selectively operate as volatile or non-volatile memory and has relatively high integration and improved electrical reliability, as well as a method of operating the memory device.

[0006] The memory devices and operating methods of the present invention are not limited to the exemplary embodiments disclosed herein, and may be implemented in many other forms without departing from the spirit and scope of this disclosure.

[0007] According to some exemplary embodiments of the present invention, a memory device is provided, the memory device comprising: a bit line extending in a first horizontal direction; a vertical channel layer extending vertically on the bit line; a first dielectric layer and a second dielectric layer both extending vertically, with the vertical channel layer located between the first dielectric layer and the second dielectric layer; a pair of word lines facing each other, with the vertical channel layer, the first dielectric layer, and the second dielectric layer located between the pair of word lines; a board line located on the vertical channel layer, the first dielectric layer, and the second dielectric layer; and a capacitor structure located on the board line. At least one of the first dielectric layer and the second dielectric layer includes a ferroelectric material.

[0008] According to some exemplary embodiments of the present invention, a memory device is provided, the memory device including a lower memory structure and an upper memory structure on the lower memory structure. The lower memory structure includes: a first bit line extending in a first horizontal direction; a first vertical channel layer extending vertically on the first bit line; a first dielectric layer and a second dielectric layer both extending vertically, with the first vertical channel layer located between the first dielectric layer and the second dielectric layer; a first word line and a second word line facing each other, with the first vertical channel layer, the first dielectric layer and the second dielectric layer located between the first word line and the second word line; a first board line located on the first vertical channel layer, the first dielectric layer and the second dielectric layer; and a first capacitor structure located on the first board line. The upper memory structure includes: a second bit line extending in a first horizontal direction; a second vertical channel layer extending vertically on the second bit line; a third dielectric layer and a fourth dielectric layer both extending vertically, with the second vertical channel layer located between the third and fourth dielectric layers; a third word line and a fourth word line facing each other, with the second vertical channel layer, the third dielectric layer, and the fourth dielectric layer located between the third and fourth word lines; a second board line located on the second vertical channel layer, the third dielectric layer, and the fourth dielectric layer; and a second capacitor structure located on the second board line. At least one of the first and second dielectric layers includes a ferroelectric material, and at least one of the third and fourth dielectric layers includes a ferroelectric material.

[0009] According to some exemplary embodiments of the present invention, a memory device is provided, comprising a first memory structure and a second memory structure arranged side-by-side in a first horizontal direction. The first memory structure includes: a first bit line extending in the first horizontal direction; a first vertical channel layer extending vertically on the first bit line; a pair of first dielectric layers extending vertically, with the first vertical channel layer located between the pair of first dielectric layers; a pair of first word lines facing each other, with the first vertical channel layer and the pair of first dielectric layers located between the pair of first word lines; and a capacitor structure located on the first vertical channel layer and the pair of first dielectric layers. The second memory structure includes: a second bit line extending in the first horizontal direction; a second vertical channel layer extending vertically on the second bit line; a pair of second dielectric layers extending vertically, with the second vertical channel layer located between the pair of second dielectric layers; a pair of second word lines facing each other, with the second vertical channel layer and the pair of second dielectric layers located between the pair of second word lines; and a board line located on the second vertical channel layer and the pair of second dielectric layers. At least one of the pair of first dielectric layers and the pair of second dielectric layers includes a ferroelectric material. Attached Figure Description

[0010] These and other aspects, features, and advantages of some exemplary embodiments will become clearer from the following detailed description taken in conjunction with the accompanying drawings.

[0011] Figure 1 This is a block diagram illustrating a memory device according to some example embodiments.

[0012] Figure 2 This is a cross-sectional view of a memory device according to some example embodiments.

[0013] Figure 3 , Figure 4 , Figure 5 and Figure 6 Illustrations based on some example embodiments Figure 2 Operation of the volatile memory in the memory device shown.

[0014] Figure 7 , Figure 8 , Figure 9 and Figure 10 Show Figure 2 Operation of the non-volatile memory in the memory device shown.

[0015] Figure 11 This is a cross-sectional view showing a memory device according to some example embodiments.

[0016] Figure 12 This is a cross-sectional view showing a memory device according to some example embodiments.

[0017] Figure 13 and Figure 14 Show Figure 12 Operation of the volatile memory in the memory device shown.

[0018] Figure 15 and Figure 16 Show Figure 12 Operation of the non-volatile memory in the memory device shown.

[0019] Figure 17 and Figure 18 This is a cross-sectional view showing a memory device according to some example embodiments.

[0020] Figure 19 This is a block diagram illustrating the construction of a system including a memory device according to some example embodiments. Detailed Implementation

[0021] In the following, some exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0022] Figure 1 This is a block diagram illustrating a memory device 1000 according to some example embodiments.

[0023] Reference Figure 1According to some example embodiments, the memory device 1000 may include a memory cell array 1010, a command decoder 1020, an address buffer 1030, an address decoder 1040, a control circuit 1050, a sense amplifier (or bit line sense amplifier (BLSA)) 1060, and / or a data input / output circuit 1070.

[0024] The memory device 1000 may include a dynamic random access memory (DRAM) that uses a cell capacitor CS as a data storage cell, and a ferroelectric field-effect transistor (FeFET) that detects the cell voltage stored in the memory cell MC as data.

[0025] The memory device 1000 can input / output data DQ in response to commands CMD and addresses ADDR received from an external device (e.g., a central processing unit (CPU) or a memory controller).

[0026] The memory cell array 1010 may include a plurality of memory cells MC. The memory cell array 1010 may include a first word line WL1, a second word line WL2, a bit line BL, and a board line PL. Each of the first word line WL1, the second word line WL2, the bit line BL, and the board line PL is connected to each of the plurality of memory cells MC in the memory cell array 1010.

[0027] Each of the multiple memory cells (MCs) may include both volatile and non-volatile memory. Operations on both volatile and non-volatile memory can be performed selectively as needed.

[0028] The gate terminal (or terminal) of the volatile memory can be connected to the first word line WL1 of the memory cell array 1010. The first terminal (or terminal) of the volatile memory can be connected to the bit line BL of the memory cell array 1010. The second terminal (or terminal) of the volatile memory can be connected to the first terminal (or terminal) of the cell capacitor CS. Furthermore, the first terminal (or terminal) of the cell capacitor CS can be connected to the board line PL of the memory cell array 1010. The volatile memory can store the charge corresponding to the data in the cell capacitor CS.

[0029] The gate terminal (or terminal) of the non-volatile memory can be connected to the second word line WL2 of the memory cell array 1010. The first terminal (or terminal) of the non-volatile memory can be connected to the bit line BL of the memory cell array 1010. The second terminal (or terminal) of the non-volatile memory can be connected to the board line PL of the memory cell array 1010. The non-volatile memory can store cell voltages having amplitudes that specify or otherwise represent data in the ferroelectric layer.

[0030] The command decoder 1020 can determine the input command CMD by referring to the chip select signal / CS, row address strobe signal / RAS, column address strobe signal / CAS, and / or write enable signal / WE applied from an external device. The command decoder 1020 can generate control signals corresponding to the command CMD. The command CMD may include an activation command, a read command, a write command, and / or a precharge command.

[0031] Address buffer 1030 receives address ADDR applied from an external device. Address ADDR includes word line addresses for addressing first word lines WL1 and second word lines WL2 connected to memory cell array 1010, bit line addresses for addressing bit lines BL connected to memory cell array 1010, and board line addresses for addressing board lines PL connected to memory cell array 1010. Address buffer 1030 can transmit the word line addresses, bit line addresses, and board line addresses to address decoder 1040.

[0032] Address decoder 1040 may include a word line decoder, a bit line decoder, and a board line decoder that select the first word line WL1 and the second word line WL2, the bit line BL, and the board line PL of the memory cell MC to be accessed in response to the received address ADDR.

[0033] The word line decoder can decode the word line address to activate the first word line WL1 and / or the second word line WL2 of the memory cell MC corresponding to the word line address. The bit line decoder can decode the bit line address to provide a bit line select signal for selecting the bit line BL of the memory cell MC corresponding to the bit line address. The board line decoder can decode the board line address to provide a board line select signal for selecting the board line PL of the memory cell MC corresponding to the board line address.

[0034] The control circuit 1050 can control the sense amplifier 1060 according to the command decoder 1020. The control circuit 1050 can control the sense amplifier 1060 to sense the cell voltage of the memory cell MC. The control circuit 1050 can control the sense amplifier 1060 to perform precharge operation, charge sharing operation and / or sensing operation.

[0035] The sense amplifier (or bit line sense amplifier (BLSA)) 1060 can sense the charge stored in the memory cell MC as data. In addition, the sense amplifier 1060 can transmit the sensed data to the data input / output circuit 1070, so that the sensed data is output to the outside of the memory device 1000 through the data DQ pad.

[0036] The data input / output circuit 1070 can receive data DQ to be written into the memory cell MC from an external source (e.g., from an external source) to transfer the data DQ to the memory cell array 1010. The data input / output circuit 1070 can output bit data sensed by the sense amplifier 1060 as read data to the external source via the data DQ pad.

[0037] A memory device 1000 comprising at least one ferroelectric material in one of a pair of gate dielectric layers according to some exemplary embodiments of the present invention constitutes a hybrid memory. The hybrid memory can be selectively operated as a volatile memory or a non-volatile memory and can have relatively high integration and / or electrical reliability.

[0038] Figure 2 This is a cross-sectional view showing a memory device 10 according to some example embodiments.

[0039] Reference Figure 2 According to some example embodiments, the memory device 10 may include memory cells having a vertical channel transistor (VCT) structure.

[0040] A memory device 10 (e.g., a hybrid memory device 10) according to some exemplary embodiments of the present invention may include a substrate 101, bit lines BL, vertical channel layers CH, a first dielectric layer 110, a second dielectric layer 120, a first word line WL1, a second word line WL2, a board line PL, and a capacitor structure 140.

[0041] Substrate 101 may be a wafer comprising silicon (Si). In some example embodiments, substrate 101 may be a wafer comprising semiconductor elements (such as germanium (Ge)) or compound semiconductors (such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP)). Substrate 101 may also have a silicon-on-insulator (SOI) structure. Substrate 101 may include conductive regions, such as impurity-doped wells or impurity-doped structures.

[0042] Bit lines BL may extend on substrate 101 in a first horizontal direction (X direction). Bit lines BL may include multiple bit lines BL extending in the first horizontal direction (X direction) and spaced apart from each other in a second horizontal direction (Y direction) intersecting the first horizontal direction (X direction). Bit lines BL may include conductive lines. In some example embodiments, bit lines BL may include conductive metal nitrides (e.g., titanium nitride or tantalum nitride), or metals (e.g., tungsten (W), titanium (Ti), or tantalum (Ta)). Alternatively, bit lines BL may include metal silicides, such as titanium silicide, cobalt silicide, or nickel silicide. Alternatively, bit lines BL may include doped polycrystalline silicon.

[0043] The vertical channel layer CH can extend in the vertical direction (Z direction) on the bit line BL. Here, the vertical channel layer CH can include a single crystalline semiconductor material layer formed by a selective epitaxial growth method. In some example embodiments, the vertical channel layer CH can include a single crystalline silicon (Si). In some example embodiments, the vertical channel layer CH can include doped silicon (Si), which has a predetermined or desired conductivity type and a predetermined or desired doping concentration by controlling the dopant and / or doping concentration in the selective epitaxial growth process.

[0044] The vertical channel layer CH may include a source / drain region SD adjacent to (or near) the bit line BL at one end (or lower end) and a source / drain region SD adjacent to (or near) the board line PL at the other opposite end (or upper end). The vertical channel layer CH may refer to the channel region located between the source / drain regions SD at its opposite ends. During operation of the memory device 10, the channel region may be controlled by each of the first word line WL1 and the second word line WL2.

[0045] The first dielectric layer 110 and the second dielectric layer 120 may be disposed on the two sidewalls of the vertical channel layer CH. Each of the first dielectric layer 110 and the second dielectric layer 120 may extend in a second horizontal direction (Y direction). Furthermore, each of the first dielectric layer 110 and the second dielectric layer 120 may extend in a vertical direction (Z direction) from the lowest end of the lower source / drain region SD to the highest end of the upper source / drain region SD. The bottom surface of each of the first dielectric layer 110 and the second dielectric layer 120 may contact the top surface of the bit line BL, and the top surface of each of the first dielectric layer 110 and the second dielectric layer 120 may contact the bottom surface of the board line PL.

[0046] In a memory device 10 according to some exemplary embodiments of the present invention, at least one of the first dielectric layer 110 and the second dielectric layer 120 may include a ferroelectric material. A ferroelectric material can refer to a material having ferroelectric properties that maintain spontaneous polarization. In some exemplary embodiments, the ferroelectric material may be a single thin film structure, a stacked thin film structure, or a composite film structure having a layered structure.

[0047] For example, ferroelectric materials may include at least one of hafnium oxide, hafnium zirconium oxide, zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. Here, hafnium zirconium oxide may be a material in which hafnium oxide is doped with zirconium (Zr), or it may be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0048] Ferroelectric materials may also include doping elements found in the aforementioned materials. Doping elements may be or include at least one of the following: aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn).

[0049] In some example embodiments, the second dielectric layer 120 may include a ferroelectric material, and the first dielectric layer 110 may not include a ferroelectric material. In this case, the first dielectric layer 110 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, a high-k dielectric film having a higher dielectric constant than a silicon oxide film, or a combination thereof. Alternatively, in some example embodiments, the first dielectric layer 110 may include a ferroelectric material, and the second dielectric layer 120 may not include a ferroelectric material. In this case, the second dielectric layer 120 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, a high-k dielectric film having a higher dielectric constant than a silicon oxide film, or a combination thereof.

[0050] The first word line WL1 and the second word line WL2 may face each other, and the vertical channel layer CH, the first dielectric layer 110, and the second dielectric layer 120 are located between the first word line WL1 and the second word line WL2. In the vertical direction (Z direction), each of the first word line WL1 and the second word line WL2 may have a vertical length smaller than the vertical length of the vertical channel layer CH. The first word line WL1 and the second word line WL2 may be positioned such that the level of the uppermost surface of the vertical channel layer CH may be higher than the level of the uppermost surface of each of the first word lines WL1 and the second word line WL2, and the level of the lowermost surface of the vertical channel layer CH may be lower than the level of the lowermost surface of each of the first word lines WL1 and the second word line WL2. The first word line WL1 and the second word line WL2 may include, for example, doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or combinations thereof.

[0051] The lower insulating layer 130 may surround the first dielectric layer 110 and the second dielectric layer 120, as well as the first word line WL1 and the second word line WL2. The first word line WL1 and the second word line WL2 may be electrically isolated from other adjacent word lines by the lower insulating layer 130. The lower insulating layer 130 may include, for example, silicon oxide, silicon oxynitride, or silicon nitride.

[0052] The plate line PL can be located on the vertical channel layer CH and the first dielectric layer 110 and the second dielectric layer 120. The plate line PL can directly contact and be electrically connected to the lower electrode 141 of the capacitor structure 140. The plate line PL can directly contact and be electrically connected to the source / drain region SD above. The plate line PL can include, for example, a metal, a conductive metal nitride, a conductive metal silicide, a conductive metal oxide, or a combination thereof.

[0053] Capacitor structure 140 can be arranged on board line PL. Capacitor structure 140 can be connected to unit capacitor CS (see reference). Figure 1 The capacitor structure 140 can be electrically connected to the vertical channel layer CH. The capacitor structure 140 can be arranged in a matrix in a first horizontal direction (X direction) and a second horizontal direction (Y direction) intersecting the first horizontal direction (X direction). The capacitor structure 140 can completely overlap with the plate line PL or partially overlap with the plate line PL. In other words, the capacitor structure 140 can completely or partially contact the top surface of the plate line PL.

[0054] In some example embodiments, the capacitor structure 140 may include a lower electrode 141 and an upper electrode 145, and a capacitor dielectric layer 143 located between the lower electrode 141 and the upper electrode 145. In this configuration, the lower electrode 141 may directly contact the plate line PL. When viewed in a plan view, the lower electrode 141 may have various shapes such as circular, elliptical, rectangular, square, rhomboid, and hexagonal.

[0055] The upper insulating layer 150 may surround the board line PL and the capacitor structure 140. The capacitor structure 140 may be electrically isolated from other adjacent capacitor structures by the upper insulating layer 150. The upper insulating layer 150 may include, for example, silicon oxide, silicon oxynitride, or silicon nitride.

[0056] The memory device 10 of some exemplary embodiments of the present invention can be selectively operated as volatile memory or non-volatile memory by using or based on the difference in voltages applied to the first word line WL1 and the second word line WL2. The characteristics of the memory device 10 operating as volatile memory can be referred to as "DRAM mode", and the characteristics of the memory device 10 operating as non-volatile memory can be referred to as "FeFET mode".

[0057] The memory device 10 of some exemplary embodiments of the present invention can store data by using a capacitor structure 140 in DRAM mode, and can store data by using the polarization characteristics of either the first dielectric layer 110 or the second dielectric layer 120 in FeFET mode.

[0058] For example, the voltage applied to the first word line WL1 can be set to a range that will not cause polarization of the first dielectric layer 110, or the material constituting the first dielectric layer 110 can include an insulating material that may not have polarization characteristics. In this case, the memory device 10 can operate in DRAM mode by using the bit line BL, the vertical channel layer CH, the first dielectric layer 110, the first word line WL1, the board line PL, and the capacitor structure 140.

[0059] For example, the material constituting the second dielectric layer 120 may include a ferroelectric material with polarization characteristics, and the magnitude of the voltage applied to the second word line WL2 may be set to be within the range that causes the polarization characteristics of the second dielectric layer 120. In this case, the memory device 10 can operate in FeFET mode by using the bit line BL, the vertical channel layer CH, the second dielectric layer 120, the second word line WL2, and the board line PL.

[0060] The following describes the operating principles of the memory device 10 according to some exemplary embodiments of the present invention in each of DRAM mode and FeFET mode for programming operations (or write operations, hereinafter collectively referred to as programming operations) and sensing operations (or read operations, hereinafter referred to as sensing operations).

[0061] In some exemplary embodiments of the present invention, at least one of a pair of gate dielectric layers (e.g., a first dielectric layer and a second dielectric layer) comprising a ferroelectric material, a memory device 10 may constitute a hybrid memory, which may be selectively operated as a volatile memory (e.g., DRAM mode) or a non-volatile memory (e.g., FeFET mode), and may have relatively high integration density and electrical reliability.

[0062] Figures 3 to 6 This illustrates some example embodiments. Figure 2 A diagram illustrating the operation of the volatile memory of the memory device 10 shown.

[0063] Figures 3 to 6 The operating principles of programming and sensing operations are described when the memory device 10 according to some example embodiments of the present invention operates as a volatile memory (e.g., DRAM mode).

[0064] In order to enable the memory device 10 to operate in DRAM mode, as described above, the magnitude of the voltage applied to the first word line WL1 can be set to a range that will not cause polarization of the first dielectric layer (dashed circle), or the material constituting the first dielectric layer (dashed circle) may include an insulating material that does not have polarization characteristics.

[0065] When the memory device 10 of some exemplary embodiments of the present invention performs a programming operation in DRAM mode (see reference) Figure 3 and Figure 4 When a voltage is applied to the first word line WL1 and the bit line BL, data (e.g., "0" or "1") can be written into the cell capacitor CS.

[0066] Furthermore, when the memory device 10 of some exemplary embodiments of the present invention performs a sensing operation in DRAM mode (see...), Figure 5 and Figure 6 When the cell capacitor CS and the parasitic capacitor CBL are in operation, charge sharing is performed, and data (e.g., "0" or "1") can be read by changes in the voltage level of the bit line BL. Here, the control circuit 1050 (refer to...) Figure 1 The sense amplifier SA can be controlled to sequentially perform pre-charge operation t1, charge sharing operation t2, and sense amplification operation t3.

[0067] Figures 7 to 10 This illustrates some example embodiments. Figure 2 A diagram illustrating the operation of the non-volatile memory of the memory device 10 shown.

[0068] Figures 7 to 10 The operating principles of programming and sensing operations are described when the memory device 10 according to some example embodiments of the present invention operates as a non-volatile memory (e.g., FeFET mode).

[0069] In order to enable the memory device 10 to operate in FeFET mode, as described above, the material constituting the second dielectric layer (dashed circle) may include a ferroelectric material with polarization characteristics, and the magnitude of the voltage applied to the second word line WL2 may be set to be within the range that causes the polarization characteristics of the second dielectric layer (dashed circle).

[0070] When the memory device 10 of some exemplary embodiments of the present invention performs a programming operation in FeFET mode (see reference) Figure 7 and Figure 8 When a voltage is applied to the second word line WL2, polarization can be caused to store a cell voltage with a specified data amplitude in the second dielectric layer (dashed circle), so that data (e.g., "0" or "1") can be written.

[0071] Furthermore, when the memory device 10 of some exemplary embodiments of the present invention performs a sensing operation in FeFET mode (see reference...) Figure 9 and Figure 10When a voltage is applied to the first word line WL1 and the board line PL, data (e.g., "0" or "1") can be read by whether the parasitic capacitor CBL is charged, depending on whether the second dielectric layer (dashed circle) is polarized. Here, the control circuit 1050 (refer to...) Figure 1 The sense amplifier SA can be controlled to sequentially perform pre-charge operation t1, parasitic capacitor charging operation t2, and sense amplification operation t3.

[0072] Figure 11 This is a cross-sectional view showing a memory device 10A according to some example embodiments.

[0073] Memory device 10A can be used in some aspects with Figure 2 The memory device 10 is the same as or similar to it, and therefore can be referred to. Figure 2 It is best understood that the same markings indicate the same elements, without further detailed description.

[0074] Reference Figure 11 The memory device 10A according to some exemplary embodiments of the present invention may include a plurality of memory cells MC, each having a vertical channel transistor structure in a stacked structure.

[0075] The memory device 10A according to some exemplary embodiments of the present invention may include a lower memory structure 10L and an upper memory structure 10U on the lower memory structure 10L.

[0076] The lower memory structure 10L may include a plurality of memory cells MC arranged side by side on the substrate 101 in a first horizontal direction (X direction).

[0077] Each of the plurality of memory cells MC in the lower memory structure 10L may include a first bit line BL1 extending in a first horizontal direction (X direction), a first vertical channel layer CH1 extending in a vertical direction (Z direction) on the first bit line BL1, a first source / drain region SD1 located at the vertically opposite ends of the first vertical channel layer CH1, a first dielectric layer 110 and a second dielectric layer 120 both extending in the vertical direction (Z direction) and the first vertical channel layer CH1 located therebetween, a first word line WL1 and a second word line WL2 facing each other and the first vertical channel layer CH1 and the first dielectric layer 110 and the second dielectric layer 120 located therebetween, a first board line PL1 located on the first vertical channel layer CH1 and the first dielectric layer 110 and the second dielectric layer 120, and a first capacitor structure 140L disposed on the first board line PL1.

[0078] In some example embodiments, the interlayer insulating layer 103 may be disposed between the lower memory structure 10L and the upper memory structure 10U.

[0079] The upper memory structure 10U may include a plurality of memory cells MC arranged side by side on the interlayer insulating layer 103 in a first horizontal direction (X direction).

[0080] Each of the plurality of memory cells MC in the upper memory structure 10U may include a second bit line BL2 extending in a first horizontal direction (X direction), a second vertical channel layer CH2 extending in a vertical direction (Z direction) on the second bit line BL2, a second source / drain region SD2 located at both ends of the second vertical channel layer CH2, a third dielectric layer 113 and a fourth dielectric layer 124 both extending in the vertical direction (Z direction) and located between the second vertical channel layer CH2, a third word line WL3 and a fourth word line WL4 facing each other and located between the second vertical channel layer CH2, the third dielectric layer 113 and the fourth dielectric layer 124, a second board line PL2 located on the second vertical channel layer CH2, the third dielectric layer 113 and the fourth dielectric layer 124, and a second capacitor structure 140U disposed on the second board line PL2.

[0081] In a memory device 10A according to some exemplary embodiments of the present invention, at least one of the first dielectric layer 110 and the second dielectric layer 120 may include a ferroelectric material. Alternatively or additionally, at least one of the third dielectric layer 113 and the fourth dielectric layer 124 may include a ferroelectric material.

[0082] In some exemplary embodiments of the memory device 10A according to the present invention, the plurality of memory cells MC included in the lower memory structure 10L may be substantially the same as or similar to the plurality of memory cells MC included in the upper memory structure 10U. The operating characteristics of the plurality of memory cells MC are substantially the same as or similar to the operating characteristics of the memory device 10 described above, and for the sake of brevity, their detailed description is omitted.

[0083] Figure 12 This is a cross-sectional view showing a memory device 20 according to some example embodiments.

[0084] Memory device 20 can be in some aspects with Figure 2 The memory device 10 is the same as or similar to it, and therefore can be referred to. Figure 2 It is best understood that the same markings indicate the same elements, without further detailed description.

[0085] Reference Figure 12 The memory device 20 of some exemplary embodiments of the present invention may include memory cells having a vertical channel transistor structure.

[0086] The memory device 20 of some exemplary embodiments of the present invention may include a first memory structure 100 and a second memory structure 200, the first memory structure 100 and the second memory structure 200 being arranged side by side in a first horizontal direction (X direction), and the transmission gate TG being located between the first memory structure 100 and the second memory structure 200.

[0087] The first memory structure 100 located on one side of the substrate 101 (e.g., the left side of the figure) may include a first bit line BL1 extending in a first horizontal direction (X direction), a first vertical channel layer CH1 extending in a vertical direction (Z direction) on the first bit line BL1, a first source / drain region SD1 located at the vertically opposite ends of the first vertical channel layer CH1, a pair of first dielectric layers 110 extending in the vertical direction (Z direction) and located therebetween the first vertical channel layer CH1, a pair of first word lines WL1 facing each other and located therebetween the first vertical channel layer CH1 and the pair of first dielectric layers 110, a capacitor structure 140 located on the first vertical channel layer CH1 and the pair of first dielectric layers 110, and a first plate line PL1 located on the capacitor structure 140.

[0088] The second memory structure 200 located on the other side of the substrate 101 (e.g., the right side of the figure) may include a second bit line BL2 extending in a first horizontal direction (X direction), a second vertical channel layer CH2 extending in a vertical direction (Z direction) on the second bit line BL2, a second source / drain region SD2 located at the vertically opposite ends of the second vertical channel layer CH2, a pair of second dielectric layers 120 extending in the vertical direction (Z direction) and located therebetween the second vertical channel layer CH2, a pair of second word lines WL2 facing each other and located therebetween the second vertical channel layer CH2 and the pair of second dielectric layers 120, and a second board line PL2 located on the second vertical channel layer CH2 and the pair of second dielectric layers 120.

[0089] In some exemplary embodiments of the memory device 20 according to the present invention, at least one of a pair of first dielectric layers 110 and a pair of second dielectric layers 120 includes a ferroelectric material. In some exemplary embodiments, the first memory structure 100 may constitute a volatile memory, and the second memory structure 200 may constitute a non-volatile memory.

[0090] In some exemplary embodiments of the memory device 20 conceived according to the present invention, the first memory structure 100 or the second memory structure 200 may be selectively operated by using a transfer gate TG. Hereinafter, the characteristics of the first memory structure 100 operating as volatile memory may be referred to as "DRAM mode," and the characteristics of the second memory structure 200 operating as non-volatile memory may be referred to as "FeFET mode."

[0091] In some exemplary embodiments of the memory device 20 conceived according to the present invention, the first memory structure 100 may store data by using a capacitor structure 140, and the second memory structure 200 may store data by using the polarization characteristics of a pair of second dielectric layers 120.

[0092] In some exemplary embodiments of the memory device 20 according to the present invention, the first bit line BL1 and the second bit line BL2 may be located at the same vertical level, but may not be electrically connected to each other.

[0093] The following describes the operating principles of the memory device 20 in each of DRAM mode and FeFET mode according to some exemplary embodiments of the present invention.

[0094] In some exemplary embodiments of the present invention, at least one of a pair of first dielectric layers and a pair of second dielectric layers 120 comprising a ferroelectric material, a memory device 20 may constitute a hybrid memory, which may selectively operate as a volatile memory (e.g., DRAM mode) or a non-volatile memory (e.g., FeFET mode) and may have relatively high integration and electrical reliability.

[0095] Figure 13 and Figure 14 Show Figure 12 Operation of the volatile memory in the memory device 20 shown.

[0096] Figure 13 and Figure 14 The programming and sensing operations are illustrated when the memory device 20, according to some example embodiments of the present invention, operates as a volatile memory (e.g., DRAM mode).

[0097] When the memory device 20 of some exemplary embodiments of the present invention performs a programming operation in DRAM mode (see reference) Figure 13 When a voltage is applied to the first word line WL1 and the bit line BL, data (e.g., "0" or "1") can be written into the cell capacitor CS.

[0098] Furthermore, when the memory device 20 of some exemplary embodiments of the present invention performs a sensing operation in DRAM mode (see reference...) Figure 14 When the cell capacitor CS and the parasitic capacitor CBL are in operation, they perform charge sharing and data (e.g., "0" or "1") can be read by the change in the voltage level of the bit line BL.

[0099] Figure 15 and Figure 16 Show Figure 12 Operation of the non-volatile memory in the memory device 20 shown.

[0100] Figure 15 and Figure 16 The programming and sensing operations are illustrated when the memory device 20 according to some example embodiments of the present invention operates as a non-volatile memory (e.g., FeFET mode).

[0101] First, when the memory device 20 of some example embodiments of the present invention performs a programming operation in FeFET mode (see reference...) Figure 15 When writing data (e.g., "0" or "1"), by applying a voltage to the Writing second word line WL2, polarization can be induced in the second dielectric layer (dashed circle) to write the data.

[0102] Furthermore, when the memory device 20 of some exemplary embodiments of the present invention performs a sensing operation in FeFET mode (see reference...) Figure 16 When a voltage is applied to the Reading WL2 line, the current flowing in the board line PL can be sensed to read data (e.g., "0" or "1").

[0103] Figure 17 and Figure 18 This is a cross-sectional view showing memory devices 20A and 20B according to some example embodiments.

[0104] Memory devices 20A and 20B can be compatible with in some aspects Figure 11 The memory device 10A and Figure 12 The memory device 20 is the same as or similar to that of the memory device 20, and therefore can be referred to. Figure 11 and Figure 12 It is best understood that the same markings indicate the same elements, without further detailed description.

[0105] Reference Figure 17 The memory device 20A according to some exemplary embodiments of the present invention may include a plurality of first memory cells MC1, each having a vertical channel transistor structure in a stacked structure.

[0106] In a memory device 20A according to some exemplary embodiments of the present invention, a first memory structure 100 and a second memory structure 200 arranged side by side in a first horizontal direction (X direction) are configured as one (or a single) first memory cell MC1, and a plurality of first memory cells MC1 may be arranged in the lower part and a plurality of first memory cells MC1 may be arranged in the upper part.

[0107] Reference Figure 18 The memory device 20B according to some exemplary embodiments of the present invention may include a plurality of second memory cells MC2, each having a vertical channel transistor structure in a stacked structure.

[0108] In a memory device 20B according to some exemplary embodiments of the present invention, a first memory structure 100 and a second memory structure 200 stacked in the vertical direction (Z direction) are configured as one (or a single) second memory cell MC2, and a plurality of second memory cells MC2 may be arranged in the first horizontal direction (X direction).

[0109] In other words, in the memory device 20B of some exemplary embodiments of the present invention, a plurality of first memory structures 100 may be arranged in the upper part in the first horizontal direction (X direction), and a plurality of second memory structures 200 may be arranged in the lower part in the first horizontal direction (X direction).

[0110] Figure 19 This is a block diagram illustrating the construction of a system 1100 including a memory device according to some example embodiments.

[0111] Reference Figure 19 The system 1100 includes a controller 1110, an input / output device 1120, a memory device 1130, an interface 1140, and a bus 1150.

[0112] System 1100 may be a mobile system or a system for sending or receiving information. In some example embodiments, the mobile system may be a portable computer, a web tablet, a mobile phone, a digital music player, or a memory card.

[0113] The controller 1110 used to perform programming in the control system 1100 may include a microprocessor, digital signal processor, microcontroller, or similar device.

[0114] Input / output device 1120 can be used to input or output data to system 1100. System 1100 can be connected to external devices such as a personal computer (PC) or a network using input / output device 1120, and can exchange data with external devices. Input / output device 1120 can be, for example, a touch screen, touchpad, keyboard, or display device.

[0115] The memory device 1130 may store data for the operation of the controller 1110, or may store data processed by the controller 1110. The memory device 1130 may include any one of the memory devices 10, 10A, 20, 20A and 20B according to some exemplary embodiments of the present invention.

[0116] Interface 1140 may be or include a data transmission path between system 1100 and external devices. Controller 1110, input / output device 1120, memory device 1130 and interface 1140 may communicate with each other via bus 1150.

[0117] As described herein, any device, system, module, part, unit, controller, circuit and / or parts thereof, and / or any part thereof (including, but not limited to, command decoder 1020, address buffer 1030, address decoder 1040, control circuitry 1050, sense amplifier (or bit line sense amplifier (BLSA)) 1060, data input / output circuitry 1070, controller 1110, input / output device 1120, interface 1140, any part thereof, etc.) according to any of the example embodiments may include, may be included in, and / or may be implemented by, one or more instances of processing circuitry such as: hardware including logic circuitry; hardware / software combinations, such as a processor executing software; or combinations thereof. For example, the processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a graphics processing unit (GPU), an application processor (AP), a digital signal processor (DSP), a microcomputer, a field-programmable gate array (FPGA) and programmable logic units, a microprocessor, an application-specific integrated circuit (ASIC), a neural network processing unit (NPU), an electronic control unit (ECU), an image signal processor (ISP), etc. In some example embodiments, the processing circuitry may include a non-transitory computer-readable storage device (e.g., memory) storing a program of instructions, such as a solid-state drive (SSD), and a processor (e.g., CPU) configured to execute the program of instructions to implement functions and / or methods performed by some or all of any means, system, module, section, unit, controller, circuit, and / or portions thereof according to any of the example embodiments.

[0118] Any of the elements and / or functional blocks disclosed above may include or be implemented in processing circuitry such as: hardware including logic circuitry; hardware / software combinations, such as a processor executing software; or combinations thereof. For example, the processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc. The processing circuitry may include electrical components such as at least one of transistors, resistors, capacitors, etc. The processing circuitry may include electrical components such as logic gates including at least one of AND gates, OR gates, NAND gates, NOT gates, etc.

[0119] While several embodiments have been provided in this disclosure, it should be understood that the disclosed systems and methods may be embodied in many other specific forms without departing from the spirit or scope of this disclosure. These examples are to be considered illustrative rather than restrictive, and the invention is not limited to the details given herein. For example, various elements or components may be combined or integrated into another system, or certain features may be omitted or not implemented.

Claims

1. A memory device, comprising: Bit line, which extends in the first horizontal direction; A vertical channel layer that extends vertically along the position line; Both the first dielectric layer and the second dielectric layer extend in the vertical direction, and the vertical channel layer is located between the first dielectric layer and the second dielectric layer; A pair of word lines facing each other, with the vertical channel layer, the first dielectric layer and the second dielectric layer located between the pair of word lines; The board line is located on the vertical channel layer, the first dielectric layer, and the second dielectric layer; and A capacitor structure located on the plate line, wherein at least one of the first dielectric layer and the second dielectric layer comprises a ferroelectric material.

2. The memory device according to claim 1, wherein, The pair of letter lines includes: The first word line contacts the first dielectric layer; and The second word line contacts the second dielectric layer, and The bit line, the vertical channel layer, the first dielectric layer, the first word line, and the capacitor structure at least partially constitute a volatile memory.

3. The memory device according to claim 2, wherein, The second dielectric layer includes a ferroelectric material, and The bit lines, the vertical channel layer, the second dielectric layer, the second word line, and the board lines at least partially constitute a non-volatile memory.

4. The memory device of claim 3, further comprising a sense amplifier connected to the bit line, wherein, The volatile memory and the non-volatile memory share the sense amplifier.

5. The memory device according to claim 4, wherein, The volatile memory and the non-volatile memory are configured to operate selectively based on the difference in voltage applied to the pair of word lines.

6. The memory device according to claim 5, wherein, The volatile memory uses the capacitor structure to store data, and The non-volatile memory uses the polarization characteristics of the second dielectric layer to store data.

7. The memory device of claim 1, further comprising a first source / drain region and a second source / drain region, the first source / drain region being located at the lower end of the vertical channel layer, the second source / drain region being located at the upper end of the vertical channel layer, the lower end being opposite to the upper end in the vertical direction.

8. The memory device according to claim 7, wherein, Each of the first dielectric layer and the second dielectric layer extends in the vertical direction from the lowest end of the first source / drain region to the highest end of the second source / drain region.

9. The memory device according to claim 1, wherein, The capacitor structure includes a lower electrode, a capacitor dielectric layer, and an upper electrode, and The lower electrode contacts the plate wire.

10. The memory device according to claim 9, wherein, The top surface of each of the first dielectric layer and the second dielectric layer is coplanar with the bottom surface of the board line.

11. A memory device, comprising: The lower memory structure and the upper memory structure on the lower memory structure. The lower memory structure includes: The first line extends in the first horizontal direction; The first vertical channel layer extends vertically along the first line; Both the first dielectric layer and the second dielectric layer extend in the vertical direction, and the first vertical channel layer is located between the first dielectric layer and the second dielectric layer; The first word line and the second word line face each other, and the first vertical channel layer, the first dielectric layer and the second dielectric layer are located between the first word line and the second word line; A first board line is located on the first vertical channel layer, the first dielectric layer, and the second dielectric layer; and A first capacitor structure is located on the first plate line. The upper memory structure includes: The second line extends in the first horizontal direction; The second vertical channel layer extends in the vertical direction along the second position line; Both the third and fourth dielectric layers extend in the vertical direction, and the second vertical channel layer is located between the third and fourth dielectric layers; The third and fourth word lines face each other, and the second vertical channel layer, the third dielectric layer and the fourth dielectric layer are located between the third word line and the fourth word line; The second plate line is located on the second vertical channel layer, the third dielectric layer, and the fourth dielectric layer; and The second capacitor structure is located on the second plate line. Wherein, at least one of the first dielectric layer and the second dielectric layer includes a ferroelectric material, and At least one of the third dielectric layer and the fourth dielectric layer includes a ferroelectric material.

12. The memory device of claim 11, further comprising: The first word line contacts the first dielectric layer; as well as The second word line contacts the second dielectric layer. The first bit line, the first vertical channel layer, the first dielectric layer, the first word line, and the first capacitor structure at least partially constitute the first volatile memory. The first bit line, the first vertical channel layer, the second dielectric layer, the second word line, and the first board line at least partially constitute the first non-volatile memory.

13. The memory device of claim 12, further comprising: The third word line contacts the third dielectric layer; as well as The fourth word line contacts the fourth dielectric layer. The second bit line, the second vertical channel layer, the third dielectric layer, the third word line, and the second capacitor structure at least partially constitute the second volatile memory. The second bit line, the second vertical channel layer, the fourth dielectric layer, the fourth word line, and the second board line at least partially constitute the second non-volatile memory.

14. The memory device according to claim 13, wherein, The first volatile memory and the first non-volatile memory are configured to operate selectively based on the difference in voltage applied to the first word line and the second word line, and The second volatile memory and the second non-volatile memory are configured to operate selectively based on the difference in voltage applied to the third word line and the fourth word line.

15. The memory device according to claim 14, wherein, Each of the second dielectric layer and the fourth dielectric layer includes a ferroelectric material. The first volatile memory and the second volatile memory are configured to store data using the first capacitor structure and the second capacitor structure, and The first non-volatile memory and the second non-volatile memory are configured to store data using the polarization characteristics of the second dielectric layer and the fourth dielectric layer.

16. A memory device, comprising: A first memory structure and a second memory structure are arranged side by side in a first horizontal direction, wherein the first memory structure includes: The first line extends in the first horizontal direction; The first vertical channel layer extends vertically along the first line; A pair of first dielectric layers extending in the vertical direction, and the first vertical channel layer is located between the pair of first dielectric layers; A pair of first word lines facing each other, wherein the first vertical channel layer and the pair of first dielectric layers are located between the pair of first word lines; and A capacitor structure located on the first vertical channel layer and the pair of first dielectric layers. The second memory structure includes: The second line extends in the first horizontal direction; The second vertical channel layer extends in the vertical direction along the second position line; A pair of second dielectric layers extending in the vertical direction, and the second vertical channel layer is located between the pair of second dielectric layers; A pair of second word lines facing each other, and the second vertical channel layer and the pair of second dielectric layers are located between the pair of second word lines; and The board line is located on the second vertical channel layer and the pair of second dielectric layers, and Wherein, at least one of the pair of first dielectric layers and the pair of second dielectric layers includes a ferroelectric material.

17. The memory device according to claim 16, wherein, The first memory structure at least partially constitutes volatile memory, and The second memory structure at least partially constitutes a non-volatile memory.

18. The memory device of claim 17, further comprising a transfer gate, wherein, The volatile memory and the non-volatile memory are selectively operated using the transfer gate.

19. The memory device according to claim 18, wherein, The volatile memory is configured to store data using the capacitor structure, and The non-volatile memory is configured to store data using the polarization characteristics of the pair of second dielectric layers.

20. The memory device of claim 16, wherein, The first bit line and the second bit line are located at the same vertical level.

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