Vertical gate-all-around field effect transistor and preparation method thereof

Abstract

The invention provides a vertical gate-all-around field effect transistor and a preparation method thereof. A silicon substrate comprises a substrate and fin parts located on the substrate; the fin part openings are at least located in the fin parts of the first region and the fin parts of the second region, the second region is located on the first region, and the opening direction of the fin part openings is perpendicular to the side wall surfaces and the top surfaces of the fin parts; the bottom source drain is located in the substrate and surrounds the fin part, and the bottom source drain is exposed by the substrate; the germanium-silicon shell layer is located on the inner wall surface of the fin opening; the silicon cap layer is located on the side wall surface of the germanium-silicon shell layer, the germanium-silicon shell layer and the silicon cap layer jointly fill the fin part opening, and the silicon cap layer, the germanium-silicon shell layer and the fin part in the first region form a channel; the ring gate electrode surrounds the periphery of the side wall surface of the fin part in the first region and is separated from the silicon cap layer; and the top source drain is positioned on the top surface of the fin part, the top surface of the germanium-silicon shell layer and the top surface of the silicon cap layer. Therefore, the channel stress of the vertical gate-all-around field effect transistor is improved by forming stress in the germanium-silicon shell layer.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a vertical ring gate field-effect transistor and its fabrication method. Background Technology

[0002] Vertical gate-all-around field effect transistors (VGAAFETs) have fewer restrictions on the length of the gate electrode and the source-drain contact area compared to lateral gate-all-around field effect transistors, which is beneficial for increasing the integration density of transistors.

[0003] In traditional vertical-ring gate field-effect transistors, the source and drain stresses are difficult to effectively transfer to the channel, resulting in low channel stress in the transistor. Summary of the Invention

[0004] This invention provides a vertical ring gate field-effect transistor and its fabrication method, which can improve the channel stress of the vertical ring gate field-effect transistor.

[0005] According to a first aspect of the present invention, a vertical-ring gate field-effect transistor is provided, comprising: A silicon substrate includes a base and a fin located on the base, the fin having a first region and a second region located on the first region, the top surface of the fin forming a partial boundary of the second region; The fin opening is located at least within the fin of the first region and the fin of the second region, and the opening direction of the fin opening is perpendicular to the side wall surface and the top surface of the fin. A bottom source drain is located within the substrate and surrounding the fin, and the bottom source drain is exposed by the substrate; A germanium-silicon shell is located on the inner wall surface of the fin opening; A silicon cap layer is located on the side wall of the germanium-silicon shell layer. The germanium-silicon shell layer and the silicon cap layer together fill the fin opening. The silicon cap layer, the germanium-silicon shell layer and the fin in the first region form a channel. A ring gate electrode surrounds the periphery of the sidewall surface of the fin in the first region and is spaced from the silicon cap layer; The top source drain is located on the top surface of the fin, the top surface of the germanium-silicon shell, and the top surface of the silicon cap layer.

[0006] Optionally, the fin further includes a third region, wherein the first region is located on the third region, the fin opening is also located within the third region, and the inner wall of the fin opening is also located within the third region, and the fin opening in the second region and the fin opening in the third region are transitioned by an arc surface.

[0007] Optionally, the substrate further includes a shallow trench isolation structure located within the substrate and surrounding the bottom source drain. In a first direction, both sides of the fin have bottom source drains exposed by the fin. In a second direction, the size of the bottom source drain exposed on one side of the fin is smaller than the size of the bottom source drain exposed on the other side of the fin. The first direction is perpendicular to the second direction, and both the first direction and the second direction are perpendicular to the surface of the substrate.

[0008] Optionally, it further includes: a first isolation layer, the first isolation layer being located on the top surface of the bottom source / drain and the shallow trench isolation structure, and the annular gate electrode being located on the top surface of the first isolation layer; The second isolation layer is located between the ring gate electrode and the silicon cap layer on the top surface of the first isolation layer; The third isolation layer is located on the top surface of the second isolation layer, the upper surface of the ring gate electrode, and the top surface of the first isolation layer. The top surface of the third isolation layer is flush with the top surface of the fin.

[0009] Optionally, the ring gate electrode includes a first gate region and a second gate region, the second gate region being located on the surface of the first gate region near the silicon cap layer, and the projection of the second gate region on the substrate surface being within the projection range of the first gate region on the substrate surface.

[0010] Optionally, it may also include: an interlayer dielectric layer located on the top surface of the third isolation layer and the top surface of the top source / drain.

[0011] Optional, also includes: A top source / drain connection structure penetrates the interlayer dielectric layer and is located on the top surface of the top source / drain; A gate conductive connection structure, penetrating the third isolation layer and the interlayer dielectric layer, is located on the top surface of the first gate region; The bottom source-drain connection structure extends through the first isolation layer, the third isolation layer, and the interlayer dielectric layer, and is located on the top surface of the bottom source-drain.

[0012] According to a second aspect of the present invention, a method for fabricating a vertical-ring gate field-effect transistor (VRF) is provided for forming the above-described VRF, the method comprising: A silicon substrate is provided, the silicon substrate including a substrate and a fin located on the substrate, the fin having a first region and a second region located on the first region, the top surface of the fin forming a partial boundary of the second region; A bottom source drain exposed by the substrate is formed within the substrate surrounding the fin; After the bottom source drain is formed, fin openings are formed in the fins of the first and second regions, with the opening direction perpendicular to the sidewall and top surface of the fins; A germanium-silicon shell layer is formed on the inner wall surface of the fin opening; A silicon cap layer is formed on the sidewall of the germanium-silicon shell layer. The germanium-silicon shell layer and the silicon cap layer together fill the fin opening. The silicon cap layer, the germanium-silicon shell layer and the fin in the first region form a channel. A ring gate electrode is formed in the region spaced from the silicon cap layer on the periphery of the sidewall surface of the fin surrounding the first region; A top source / drain is formed on the top surface of the fin, the top surface of the germanium-silicon shell layer, and the top surface of the silicon cap layer.

[0013] Optionally, the fin further includes a third region, wherein the first region is located on the third region, the fin opening is also located within the third region, and the inner wall of the fin opening is also located within the third region, and the fin opening in the second region and the fin opening in the third region are transitioned by an arc surface.

[0014] Optionally, after forming the bottom source drain and before forming the fin opening, the method further includes: forming a shallow trench isolation structure surrounding the bottom source drain within the substrate, wherein the bottom source drain is exposed on both sides of the fin in a first direction, and the size of the bottom source drain exposed on one side of the fin in a second direction is smaller than the size of the bottom source drain exposed on the other side of the fin, wherein the first direction is perpendicular to the second direction, and both the first direction and the second direction are perpendicular to the surface of the substrate.

[0015] Optional, also includes: After the shallow trench isolation structure is formed and before the germanium-silicon shell is formed, a first isolation layer is formed on the top surface of the top source / drain and the top surface of the shallow trench isolation structure. During the formation of the ring gate electrode, a second isolation layer is formed between the ring gate electrode and the silicon cap layer on the surface of the first isolation layer; After the ring gate electrode is formed and before the top source drain is formed, a third isolation layer is formed on the top surface of the second isolation layer, the upper surface of the ring gate electrode, and the top surface of the first isolation layer, the top surface of the third isolation layer being flush with the top surface of the fin.

[0016] Optionally, the ring gate electrode includes a first gate region and a second gate region, the second gate region being located on the surface of the first gate region near the silicon cap layer, and the projection of the second gate region on the substrate surface being within the projection range of the first gate region on the substrate surface.

[0017] Optionally, it may also include: after forming the top source drain, depositing an interlayer dielectric layer on the top surface of the third isolation layer and on the top surface of the top source drain.

[0018] Optional, also includes: A top source / drain connection structure penetrating the interlayer dielectric layer is formed on the top surface of the top source / drain; A gate conductive connection structure penetrating the third isolation layer and the interlayer dielectric layer is formed on the top surface of the first gate region; A bottom source-drain connection structure is formed on the top surface of the bottom source-drain, penetrating the first isolation layer, the third isolation layer, and the interlayer dielectric layer.

[0019] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects: In the vertical-to-gate field-effect transistor and its fabrication method of the present invention, the channel of a conventional vertical-to-gate field-effect transistor is configured to sequentially include a silicon cap, a germanium-silicon shell, and fins from the outside in. The fins are part of the silicon substrate. In other words, the channel material is configured as silicon-germanium-silicon-silicon from the outside in. This creates stress in the germanium-silicon shell, thereby increasing the channel stress of the vertical-to-gate field-effect transistor. Furthermore, by confining the main current path within the germanium-silicon shell, the on-state current of the vertical-to-gate field-effect transistor is increased. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figures 1-23 This is a schematic cross-sectional view of each step in the fabrication method of the vertical gate ring field-effect transistor according to an embodiment of the present invention. Figure 24 This is a bar chart showing the relationship between the mass fraction of germanium in the germanium-silicon shell and the average stress of the germanium-silicon shell in an embodiment of the present invention.

[0022] Figure 25 This is a bar chart showing the relationship between the mass fraction of germanium in the germanium-silicon shell and the normalized on-state current of the vertical ring gate field-effect transistor in an embodiment of the present invention. Detailed Implementation

[0023] As described in the background section, conventional vertical-ring gate field-effect transistors have low channel stress.

[0024] In view of this, the present invention provides a vertical gate-around field-effect transistor, comprising a silicon substrate, a base, and a fin located on the base. The fin has a first region and a second region located on the first region, the top surface of the fin forming a partial boundary of the second region; a fin opening located at least within the fin in the first region and the fin in the second region, the opening direction of the fin opening being perpendicular to the sidewall and top surface of the fin; a bottom source / drain located within the base and surrounding the fin, the bottom source / drain being exposed by the base; a germanium-silicon shell located on the inner wall surface of the fin opening; a silicon cap layer located on the sidewall surface of the germanium-silicon shell, the germanium-silicon shell and the silicon cap layer together filling the fin opening, the silicon cap layer, the germanium-silicon shell layer, and the fin in the first region forming a channel; a gate-around electrode surrounding the periphery of the sidewall surface of the fin in the first region and spaced apart from the silicon cap layer; and a top source / drain located on the top surface of the fin, the top surface of the germanium-silicon shell layer, and the top surface of the silicon cap layer. This increases the channel stress of the vertical-ring gate field-effect transistor (VRF) by creating stress within the germanium-silicon shell. Furthermore, by confining the main current path within the germanium-silicon shell, the on-state current of the VRF is increased.

[0025] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0026] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0027] The technical solution of the present invention will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0028] Figures 1-23This is a schematic cross-sectional view of each step in the fabrication method of the vertical ring gate field-effect transistor according to an embodiment of the present invention.

[0029] Please refer to Figure 1 as well as Figure 2 , Figure 2 for Figure 1 A cross-sectional structural schematic diagram rotated 90 degrees shows a silicon substrate 100. The silicon substrate 100 includes a base 110 and a fin 120 located on the base 110. The fin 120 has a first region I and a second region II located on the first region I. The top surface of the fin 120 forms part of the boundary of the second region II.

[0030] In this embodiment, X represents the first direction, Y represents the second direction, and Z represents the direction perpendicular to the substrate surface.

[0031] In this embodiment, the fin 120 further includes a third region III, with the first region I located on the third region III.

[0032] Next, a bottom source drain, exposed by the substrate 110, is formed within the substrate 110 surrounding the fin 120. For an example, please refer to [link to documentation / reference] for the specific steps involved in forming the bottom source drain. Figures 3-6 .

[0033] Please refer to Figure 3 as well as Figure 4 , Figure 3 and Figure 1 The view orientation is consistent. Figure 4 and Figure 2 With the view direction consistent, a hard mask 210 is formed on the top surface of the fin 120; and a protective layer 220 is formed on the side wall surface of the fin 120. Using the hard mask 210 and the protective layer 220 as masks, the substrate 110 and part of the fin 120 are etched to form a bottom source drain trench 111.

[0034] Please refer to Figure 5 as well as Figure 6 , Figure 5 and Figure 3 The view orientation is consistent. Figure 6 and Figure 4 With the view orientation consistent, bottom source drain 112 is grown inside and outside the bottom source drain trench 111.

[0035] In this embodiment, the material of the bottom source / drain 112 is a mixture of germanium and silicon.

[0036] In this embodiment, a portion of the bottom source drain 112 is located within the substrate 110, and another portion of the bottom source drain 112 is located within the fin 120.

[0037] Remove the protective layer 220.

[0038] In this embodiment, please refer to Figure 7 as well as Figure 8 , Figure 7 and Figure 5 The view orientation is consistent. Figure 8 and Figure 6 With the views aligned, a shallow trench isolation structure 113 is formed within the substrate 110 surrounding the bottom source drain 112, such that both sides of the fin 120 have a bottom source drain 112 and the substrate 120 exposed by the fin 120 on the outer periphery of the first direction X, and the size of the bottom source drain 112 exposed by the fin 120 on one side of the fin 120 on the second direction Y is smaller than the size of the bottom source drain 112 exposed by the fin 120 on the other side. The first direction X is perpendicular to the second direction Y, and both the first direction X and the second direction Y are perpendicular to the surface of the substrate 120.

[0039] Please refer to Figure 9 as well as Figure 10 , Figure 9 and Figure 7 The view orientation is consistent. Figure 10 and Figure 8 With the views aligned, a first isolation layer 300 is formed on the top surface of the top source drain 112 and the top surface of the shallow trench isolation structure 113.

[0040] Please refer to Figure 11 , Figure 11 and Figure 9 With the same viewing direction, fin openings 121 are formed in the fins 120 of the first region I and the second region II, with the opening direction perpendicular to the side wall and top surface of the fin 120.

[0041] The fin opening 121 is also located within the third region III, and the inner wall of the fin opening 121 is also located within the third region III. The fin opening 121 in the second region II and the fin opening 121 in the third region III are connected by an arc surface.

[0042] Please refer to Figure 12 , Figure 12 and Figure 11 With the same viewing direction, a germanium-silicon shell 122 is formed on the inner wall surface of the fin opening 121.

[0043] The process for forming the germanium-silicon shell 122 is as follows: the germanium-silicon shell 122 is formed by epitaxial growth.

[0044] In this embodiment, the material of the germanium-silicon shell 122 is a mixture of germanium and silicon.

[0045] Please refer to Figure 13 , Figure 13 and Figure 12With the same viewing direction, a silicon cap layer 123 is formed on the side wall of the germanium-silicon shell layer 122. The germanium-silicon shell layer 122 and the silicon cap layer 123 together fill the fin opening 121. The silicon cap layer 123, the germanium-silicon shell layer 122 and the fin 120 in the first region I constitute a channel.

[0046] A ring gate electrode is formed in the region spaced from the silicon cap layer 123 on the periphery of the sidewall surface of the fin 120 surrounding the first region I. Furthermore, during the formation of the ring gate electrode, a second isolation layer is formed between the ring gate electrode and the silicon cap layer 123 on the surface of the first isolation layer 300. For specific steps in forming the ring gate electrode and the second isolation layer in this embodiment, please refer to [reference needed]. Figures 14-16 .

[0047] Please refer to Figure 14 , Figure 14 View direction and Figure 13 With the view orientation consistent, a second isolation material layer 410 is formed on the exposed sidewall of the silicon cap layer 123 through an oxidation process.

[0048] Please refer to Figure 15 and Figure 16 , Figure 15 and Figure 14 The view orientation is consistent. Figure 16 and Figure 10 With the view orientation consistent, a gate dielectric stack 510 is formed on a portion of the exposed surface of the first isolation layer surrounding the second isolation material layer 410, the sidewall surface of the second isolation material layer 410, the top surface of the second isolation material layer 410, and the top and sidewall surfaces of the mask layer 210.

[0049] The process for forming the gate dielectric stack 510 is as follows: hafnium dioxide and titanium nitride are deposited sequentially using atomic layer deposition.

[0050] Please refer to Figure 17 as well as Figure 18 , Figure 17 and Figure 15 The view orientation is consistent. Figure 18 and Figure 16 With the view direction consistent, remove part of the gate dielectric stack 510 located at the bottom source drain 112 and the fin 120 surrounding the second ring region II to form a ring gate electrode 500, and remove the second isolation material layer 410 surrounding the fin 120 of the second region II to form a second isolation layer 400.

[0051] In this embodiment, the ring gate electrode 500 includes a first gate region IV and a second gate region V. The second gate region V is located on the surface of the first gate region IV near the silicon cap layer 123. The projection of the second gate region V onto the surface of the substrate 110 is within the projection range of the first gate region IV onto the surface of the substrate 110.

[0052] In the second direction Y, the bottom source / drain 112 on one side of the silicon cap layer 123 is not completely covered by the ring gate electrode 500.

[0053] Next, remove the hard mask 210.

[0054] Please refer to Figure 19 , Figure 19 and Figure 17 With the same viewing direction, a third isolation layer 600 is formed on the top surface of the second isolation layer 400, the upper surface of the ring gate electrode 500, and the top surface of the first isolation layer 300. The top surface of the third isolation layer 600 is flush with the top surface of the fin 120.

[0055] Please refer to Figure 20 , Figure 20 and Figure 19 With the same viewing direction, a top source / drain 700 is formed on the top surface of the fin 120, the top surface of the germanium-silicon shell 122, and the top surface of the silicon cap layer 123.

[0056] Please refer to Figure 21 , Figure 21 and Figure 20 With the view orientation consistent, after the top source drain 112 is formed, an interlayer dielectric layer 710 is deposited on the top surface of the third isolation layer 600 and the top surface of the top source drain 112.

[0057] Please refer to Figure 22 as well as Figure 23 , Figure 22 and Figure 21 The view orientation is consistent. Figure 23 and Figure 18 With consistent view orientation, a top source / drain connection structure 810 is formed on the top surface of the top source / drain 700, penetrating the interlayer dielectric layer 710.

[0058] Please continue to refer to this. Figure 22 as well as Figure 23 A gate conductive connection structure 820 is formed on the top surface of the first gate region IV, penetrating the third isolation layer 600 and the interlayer dielectric layer 710.

[0059] Please continue to refer to this. Figure 22 as well as Figure 23 A bottom source-drain connection structure 830 is formed on the top surface of the bottom source-drain 112, penetrating the first isolation layer 300, the third isolation layer 600 and the interlayer dielectric layer 710.

[0060] By configuring the channel of a conventional vertical-ring gate field-effect transistor (VRF) as consisting of a silicon cap layer 123, a germanium-silicon shell layer 122, and a fin 120 from the outside in, where the fin 120 is part of the silicon substrate 100, that is, by configuring the trench material from the outside in as silicon-germanium-silicon-silicon, stress is generated in the germanium-silicon shell layer, thereby increasing the channel stress of the VRF. Furthermore, by confining the main current path within the germanium-silicon shell layer 122, the on-state current of the VRF is increased.

[0061] Please refer to Figure 24 A bar chart showing the relationship between the mass fraction of germanium in the germanium-silicon shell and the average stress of the germanium-silicon shell in an embodiment of the present invention, wherein... Figure 24 The x-axis represents the mass fraction of germanium in the germanium-silicon shell. Figure 24 The ordinate represents the average stress of the germanium-silicon shell.

[0062] Depend on Figure 24 It is evident that the higher the mass fraction of germanium in the germanium-silicon shell, the greater the stress in the germanium-silicon shell.

[0063] Please refer to Figure 25 A bar chart showing the relationship between the mass fraction of germanium in the germanium-silicon shell and the normalized on-state current of the vertical-ring gate field-effect transistor in this embodiment of the invention. Figure 25 The x-axis represents the mass fraction of germanium in the germanium-silicon shell. Figure 24 The ordinate represents the normalized on-state current of the vertical-ring gate field-effect transistor, and Figure 2 The filled region represents the proportion of the normalized on-state current in the germanium-silicon shell.

[0064] Depend on Figure 25 It is evident that the higher the mass fraction of germanium in the germanium-silicon shell, the larger the normalized on-state current of the vertical ring gate field-effect transistor, and the on-state current is mainly concentrated in the germanium-silicon shell.

[0065] Accordingly, embodiments of the present invention also provide a vertical ring gate field-effect transistor formed by the above method embodiments, please refer to... Figure 22 as well as Figure 23 It includes: a silicon substrate 100, a fin opening 121, a bottom source / drain 112, a germanium-silicon shell 122, a silicon cap layer 123, a ring gate electrode 500, and a top source / drain 700.

[0066] The silicon substrate 100 includes a base and a fin 120 located on the base. The fin 120 has a first region and a second region II located on the first region I. The top surface of the fin 120 forms part of the boundary of the second region II.

[0067] The fin opening 121 is located at least in the fin 120 of the first region I and the fin of the second region II, and the opening direction of the fin opening 121 is perpendicular to the side wall surface and the top surface of the fin 120.

[0068] The bottom source drain 112 is located within the base 120 and is disposed around the fin 120, and the bottom source drain 112 is exposed by the base 110.

[0069] The germanium-silicon shell 122 is located on the inner wall surface of the fin opening 121.

[0070] The silicon cap layer 123 is located on the side wall of the germanium-silicon shell layer 122. The germanium-silicon shell layer 122 and the silicon cap layer 123 together fill the fin opening 121. The silicon cap layer 123, the germanium-silicon shell layer 122 and the fin 120 in the first region I form a channel. A ring gate electrode 500 surrounds the periphery of the sidewall of the fin 120 in the first region I and is spaced apart from the silicon cap layer 123.

[0071] The top source / drain 700 is located on the top surface of the fin 120, the top surface of the germanium-silicon shell 122, and the top surface of the silicon cap layer 123.

[0072] Please continue to refer to this. Figure 22 as well as Figure 23 In this embodiment, the fin 120 further includes a third region III, the first region I is located on the third region III, the fin opening 121 is also located in the third region III, and the inner sidewall of the fin opening 121 is also located in the third region III, and the fin opening 121 of the second region II and the fin opening 121 of the third region III are transitioned by an arc surface.

[0073] Please continue to refer to this. Figure 22 as well as Figure 23 The substrate also includes a shallow trench isolation structure 113 located within the substrate 110 surrounding the bottom source drain 112. In the first direction X, the bottom source drain 112 is exposed on both sides of the fin 120. In the second direction Y, the size of the bottom source drain 112 exposed on one side of the fin 120 is smaller than the size of the bottom source drain 112 exposed on the other side of the fin 120. The first direction X is perpendicular to the second direction Y, and both the first direction X and the second direction Y are perpendicular to the surface of the substrate 110.

[0074] Please continue to refer to this. Figure 22 as well as Figure 23 The vertical ring gate field-effect transistor further includes: a first isolation layer 300, which is located on the top surface of the bottom source drain 112 and the shallow trench isolation structure 113, and a ring gate electrode 500 is located on the top surface of the first isolation layer 300.

[0075] The second isolation layer 400 is located between the ring gate electrode 500 and the silicon cap layer 123 on the top surface of the first isolation layer 300.

[0076] The third isolation layer 600 is located on the top surface of the second isolation layer 400, the upper surface of the ring gate electrode 500, and the top surface of the first isolation layer 300. The top surface of the third isolation layer 600 is flush with the top surface of the fin 120.

[0077] Please continue to refer to this. Figure 22 as well as Figure 23 The ring gate electrode 500 includes a first gate region IV and a second gate region V. The second gate region V is located on the surface of the first gate region IV near the silicon cap layer 123. The projection of the second gate region V onto the surface of the substrate 110 is within the projection range of the first gate region IV onto the surface of the substrate 110.

[0078] Please continue to refer to this. Figure 22 as well as Figure 23 The vertical ring gate field-effect transistor also includes: an interlayer dielectric layer 710, located on the top surface of the third isolation layer 600 and the top surface of the top source / drain 112.

[0079] Please continue to refer to this. Figure 22 as well as Figure 23 The vertical ring gate field-effect transistor also includes: a top source-drain connection structure 810, a gate conductive connection structure 820, and a bottom source-drain connection structure 830.

[0080] The top source / drain connection structure 810 penetrates the interlayer dielectric layer 710 and is located on the top surface of the top source / drain 700.

[0081] The gate conductive connection structure 820 penetrates the third isolation layer 600 and the interlayer dielectric layer 710 and is located on the top surface of the first gate region IV.

[0082] The bottom source-drain connection structure 830 penetrates the first isolation layer 300, the third isolation layer 600 and the interlayer dielectric layer 710 and is located on the top surface of the bottom source-drain 112.

[0083] In summary, by configuring the channel of a conventional vertical-ring gate field-effect transistor (VRF) as consisting of a silicon cap layer 123, a germanium-silicon shell layer 122, and a fin 120 from the outside in, where the fin 120 is part of the silicon substrate 100, that is, by configuring the trench material from the outside in as silicon-germanium-silicon-silicon, stress is generated in the germanium-silicon shell layer, thereby increasing the channel stress of the VRF. Furthermore, by confining the main current path within the germanium-silicon shell layer 122, the on-state current of the VRF is increased.

[0084] Since the vertical-ring gate field-effect transistor in this embodiment corresponds to the fabrication method of the vertical-ring gate field-effect transistor described above, for the explanation of each feature structure in the vertical-ring gate field-effect transistor in this embodiment, please refer to the detailed description of the corresponding part in the fabrication method of the vertical-ring gate field-effect transistor described above, and it will not be repeated here.

[0085] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A vertical-ring gate field-effect transistor, characterized in that, include: A silicon substrate includes a base and a fin located on the base, the fin having a first region and a second region located on the first region, the top surface of the fin forming a partial boundary of the second region; The fin opening is located at least within the fin of the first region and the fin of the second region, and the opening direction of the fin opening is perpendicular to the side wall surface and the top surface of the fin. A bottom source drain is located within the substrate and surrounding the fin, and the bottom source drain is exposed by the substrate; A germanium-silicon shell is located on the inner wall surface of the fin opening; A silicon cap layer is located on the side wall of the germanium-silicon shell layer. The germanium-silicon shell layer and the silicon cap layer together fill the fin opening. The silicon cap layer, the germanium-silicon shell layer and the fin in the first region form a channel. A ring gate electrode surrounds the periphery of the sidewall surface of the fin in the first region and is spaced from the silicon cap layer; The top source drain is located on the top surface of the fin, the top surface of the germanium-silicon shell, and the top surface of the silicon cap layer.

2. The vertical-ring gate field-effect transistor as described in claim 1, characterized in that, The fin further includes a third region, wherein the first region is located on the third region, the fin opening is also located within the third region, and the inner wall of the fin opening is also located within the third region, and the fin opening in the second region and the fin opening in the third region are transitioned by an arc surface.

3. The vertical-ring gate field-effect transistor as described in claim 2, characterized in that, The substrate further includes a shallow trench isolation structure located within the substrate and surrounding the bottom source drain. In a first direction, both sides of the fin have bottom source drains exposed by the fin. In a second direction, the size of the bottom source drain exposed on one side of the fin is smaller than the size of the bottom source drain exposed on the other side. The first direction is perpendicular to the second direction, and both the first direction and the second direction are perpendicular to the surface of the substrate.

4. The vertical-ring gate field-effect transistor as described in claim 3, characterized in that, Also includes: A first isolation layer is located on the top surface of the bottom source / drain and the shallow trench isolation structure, and the ring gate electrode is located on the top surface of the first isolation layer; The second isolation layer is located between the ring gate electrode and the silicon cap layer on the top surface of the first isolation layer; The third isolation layer is located on the top surface of the second isolation layer, the upper surface of the ring gate electrode, and the top surface of the first isolation layer. The top surface of the third isolation layer is flush with the top surface of the fin.

5. The vertical-ring gate field-effect transistor as described in claim 4, characterized in that, The ring gate electrode includes a first gate region and a second gate region. The second gate region is located on the surface of the first gate region near the silicon cap layer. The projection of the second gate region on the substrate surface is within the projection range of the first gate region on the substrate surface.

6. The vertical-ring gate field-effect transistor as described in claim 5, characterized in that, Also includes: An interlayer dielectric layer is located on the top surface of the third isolation layer and the top surface of the top source / drain.

7. The vertical-ring gate field-effect transistor as described in claim 6, characterized in that, Also includes: A top source / drain connection structure penetrates the interlayer dielectric layer and is located on the top surface of the top source / drain; A gate conductive connection structure, penetrating the third isolation layer and the interlayer dielectric layer, is located on the top surface of the first gate region; The bottom source-drain connection structure extends through the first isolation layer, the third isolation layer, and the interlayer dielectric layer, and is located on the top surface of the bottom source-drain.

8. A method for fabricating a vertical-ring gate field-effect transistor, characterized in that, The method includes: A silicon substrate is provided, the silicon substrate including a substrate and a fin located on the substrate, the fin having a first region and a second region located on the first region, the top surface of the fin forming a partial boundary of the second region; A bottom source drain exposed by the substrate is formed within the substrate surrounding the fin; After the bottom source drain is formed, fin openings are formed in the fins of the first and second regions, with the opening direction perpendicular to the sidewall and top surface of the fins; A germanium-silicon shell layer is formed on the inner wall surface of the fin opening; A silicon cap layer is formed on the sidewall of the germanium-silicon shell layer. The germanium-silicon shell layer and the silicon cap layer together fill the fin opening. The silicon cap layer, the germanium-silicon shell layer and the fin in the first region form a channel. A ring gate electrode is formed in the region spaced from the silicon cap layer on the periphery of the sidewall surface of the fin surrounding the first region; A top source / drain is formed on the top surface of the fin, the top surface of the germanium-silicon shell layer, and the top surface of the silicon cap layer.

9. The method for fabricating a vertical-ring gate field-effect transistor as described in claim 8, characterized in that, The fin further includes a third region, wherein the first region is located on the third region, the fin opening is also located within the third region, and the inner wall of the fin opening is also located within the third region, and the fin opening in the second region and the fin opening in the third region are transitioned by an arc surface.

10. The method for fabricating a vertical-ring gate field-effect transistor as described in claim 9, characterized in that, After forming the bottom source drain and before forming the fin opening, the method further includes: forming a shallow trench isolation structure surrounding the bottom source drain within the substrate, wherein the bottom source drain is exposed on both sides of the fin in a first direction, and the bottom source drain exposed on one side of the fin in a second direction is smaller than the bottom source drain exposed on the other side of the fin, wherein both the first direction and the second direction are perpendicular to the surface of the substrate.

11. The method for fabricating a vertical-ring gate field-effect transistor as described in claim 10, characterized in that, Also includes: After the shallow trench isolation structure is formed and before the germanium-silicon shell is formed, a first isolation layer is formed on the top surface of the top source / drain and the top surface of the shallow trench isolation structure. During the formation of the ring gate electrode, a second isolation layer is formed between the ring gate electrode and the silicon cap layer on the surface of the first isolation layer; After the ring gate electrode is formed and before the top source drain is formed, a third isolation layer is formed on the top surface of the second isolation layer, the upper surface of the ring gate electrode, and the top surface of the first isolation layer, the top surface of the third isolation layer being flush with the top surface of the fin.

12. The method for fabricating a vertical-ring gate field-effect transistor as described in claim 11, characterized in that, The ring gate electrode includes a first gate region and a second gate region. The second gate region is located on the surface of the first gate region near the silicon cap layer. The projection of the second gate region on the substrate surface is within the projection range of the first gate region on the substrate surface.

13. The method for fabricating a vertical-ring gate field-effect transistor as described in claim 12, characterized in that, Also includes: After the top source drain is formed, an interlayer dielectric layer is deposited on the top surface of the third isolation layer and the top surface of the top source drain.

14. The method for fabricating a vertical-ring gate field-effect transistor as described in claim 13, characterized in that, Also includes: A top source / drain connection structure penetrating the interlayer dielectric layer is formed on the top surface of the top source / drain; A gate conductive connection structure penetrating the third isolation layer and the interlayer dielectric layer is formed on the top surface of the first gate region; A bottom source-drain connection structure is formed on the top surface of the bottom source-drain, penetrating the first isolation layer, the third isolation layer, and the interlayer dielectric layer.

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