A vertical wire-bonding integrated computing and storage fan-out packaging structure and a preparation method thereof

Abstract

This invention relates to the field of semiconductor packaging technology, and in particular to a vertically wire-bonded in-memory computing fan-out package structure and its fabrication method. By introducing a hybrid vertical interconnect method combining vertical wire bonding and copper pillars into the fan-out package structure, this invention achieves high-density three-dimensional integration of computing chips and memory chips without using through-silicon vias (TSVs) or silicon interposers, effectively shortening the signal transmission path. This "memory below, computing above" three-dimensional stacking arrangement places the memory chip inside the package, close to the core area of ​​the redistribution layer and vertical interconnect structure. A large number of I / O signals from the memory chip can access the vertical interconnect network through a shorter path, thereby reducing interconnect parasitic parameters and improving signal integrity. Furthermore, this arrangement helps to keep the main heat sources away from the memory chip, improving the heat distribution inside the package and enhancing the reliability and process feasibility of the in-memory computing package structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and in particular to a vertical wire bonding in-memory computing fan-out package structure and its fabrication method. Background Technology

[0002] With the rapid development of applications such as artificial intelligence, high-performance computing, and big data analytics, the drawbacks of the separation of computing and storage in the traditional von Neumann architecture have become increasingly apparent. Frequent data transfer between the processor and memory generates significant latency and power consumption, creating a serious "memory wall" problem. In-memory computing technology, as a key solution to overcome this bottleneck, significantly reduces data transmission latency and improves overall system performance and energy efficiency by physically integrating computing and storage units.

[0003] In the development of in-memory computing packaging technology, fan-out packaging structures have attracted much attention due to their superior electrical performance and cost advantages. Among existing technologies, Chinese patent CN116072622A discloses a chip stacking packaging structure that utilizes a multi-layer redistribution fan-out three-dimensional structure to solve the application challenges brought by TSVs (Through-the-Video Storage). Chinese patent CN117711961A proposes a fan-out stacked chip packaging method that achieves electrical connections between multiple chips through transition pads and wire bonding.

[0004] However, existing in-memory computing packaging technologies still have many shortcomings:

[0005] First, in terms of interconnect density and bandwidth, computing units and storage units require massive, short-distance, and high-bandwidth interconnect channels. However, traditional wire bonding technology is limited by the arc structure of the bonding wire and its large footprint, making it difficult to achieve high-density vertical interconnects and unable to meet the ultra-high bandwidth requirements of in-memory computing architectures.

[0006] Secondly, in terms of integration complexity and cost control, although the existing 2.5D silicon interposer and 3D TSV technologies can provide high-density interconnects, the manufacturing process is extremely complex and costly, and they are prone to thermal stress concentration and reliability risks when stacking multiple chips.

[0007] Furthermore, in terms of system scalability and process compatibility, a single stacking method and a fixed interconnect structure are difficult to adapt to the heterogeneous integration requirements of multi-chip chips with different functions and different process nodes. In particular, when computing chips and memory chips need to be integrated at the same time, there is a lack of flexible layout and connection solutions.

[0008] Therefore, there is an urgent need for a three-dimensional integrated solution that can balance high performance, cost-effectiveness, and high reliability in order to promote the in-memory computing architecture from concept to large-scale commercial application. Summary of the Invention

[0009] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a vertically bonded in-memory computing fan-out package structure to solve the "memory wall" problem caused by the separation of computing and storage in the traditional von Neumann architecture, as well as the shortcomings of existing packaging technologies in terms of interconnect density, manufacturing cost and system scalability. At the same time, this invention will also provide a method for preparing the vertically bonded in-memory computing fan-out package structure.

[0010] To achieve the above and other related objectives, the present invention provides the following technical solutions:

[0011] A first aspect of the present invention provides a vertically wire-bonded in-memory computing fan-out package structure, comprising:

[0012] The package body has a first wiring layer and a second wiring layer arranged sequentially from top to bottom inside the package body;

[0013] Multiple copper pillars are disposed between the first and second wiring layers, the copper pillars extending along the thickness direction of the package, and are used as vertical electrical interconnects and structural supports;

[0014] The first chip is disposed below the first wiring layer, and the pads of the first chip are electrically connected to the first wiring layer by solder or bumps.

[0015] Multiple second chips are stacked below the first chip, and the second chips are fixed to each other and to each first chip by an adhesive film.

[0016] Multiple vertical wires are disposed at the pads of the second chip. The vertical wires extend along the thickness direction of the package, with one end connected to the pads of the second chip and the other end extending downward to connect to the second redistribution layer.

[0017] A molding layer I is disposed between the first and second wiring layers, wherein the molding layer I covers the first chip, the second chip, the copper pillars and the vertical conductors;

[0018] The solder balls are located at the bottom of the second wiring layer and are electrically connected to the copper pillars and vertical conductors through the second wiring layer.

[0019] A third chip is disposed above the first wiring layer, and the third chip is electrically connected to the first wiring layer.

[0020] A molding layer II is disposed above the first wiring layer, and the molding layer II covers the third chip.

[0021] Furthermore, the first and third chips are computing chips, such as CPUs, GPUs, FPGAs, ASICs, etc.; the second chip is a memory chip, such as a DRAM wafer.

[0022] This invention achieves high-density three-dimensional integration of computing and memory chips by introducing a hybrid vertical interconnect method combining vertical wire bonding and copper pillars into a fan-out package structure, without using through-silicon vias (TSVs) or silicon interposers. This effectively shortens signal transmission paths, increases interconnect bandwidth, and reduces system latency and power consumption. Simultaneously, this "memory below, computing above" three-dimensional stacking arrangement places the memory chip within the package, close to the core area of ​​the redistribution layer and vertical interconnect structure. A large number of I / O signals from the memory chip can access the vertical interconnect network through shorter paths, thereby reducing interconnect parasitic parameters and improving signal integrity. Furthermore, the computing chip is positioned above the upper redistribution structure, facilitating functional expansion and system configuration through redistribution. Additionally, this arrangement helps to keep major heat sources away from the memory chip, improving heat distribution within the package and enhancing the reliability and process feasibility of the in-memory computing package structure.

[0023] Furthermore, the molding layer I includes a first molding layer and a second molding layer. The first molding layer is close to the first redistribution layer, and the second molding layer is close to the second redistribution layer. The thickness of the first molding layer does not exceed the height of the copper pillar and the vertical conductor. The second molding layer has a lower elastic modulus than the first molding layer, so that the first molding layer is used to fix the copper pillar and the vertical conductor, and the second molding layer is used to absorb the stress difference generated by the rigid copper pillar and the flexible vertical conductor.

[0024] Furthermore, the thickness of the first molding layer accounts for 90% to 99% of the thickness of the molding layer I.

[0025] Furthermore, the first molding layer is made of a high-modulus epoxy molding material to fix the copper pillar and the vertical conductor; the second molding layer is made of a low-modulus toughened epoxy molding material to absorb the stress difference generated by the rigid copper pillar and the flexible vertical conductor.

[0026] Furthermore, the formulation of the first molding layer includes 35-45 parts by weight of epoxy resin, 10-15 parts by weight of phenolic curing agent, 35-45 parts by weight of spherical silica filler, 0.3-1.0 parts by weight of coupling agent, 0.1-0.5 parts by weight of catalyst, and 0.1-0.5 parts by weight of flow modifier.

[0027] The formulation of the second molding layer includes 40-55 parts by weight of flexible modified epoxy resin, 8-12 parts by weight of latent curing agent, 5-12 parts by weight of elastomer toughening agent, 10-20 parts by weight of fine silica, 0.3-1.0 parts by weight of coupling agent, and 0.1-0.5 parts by weight of flow modifier.

[0028] Furthermore, the first rewiring layer and / or the second rewiring layer are multi-layer rewiring structures with 3 to 6 layers.

[0029] A second aspect of the present invention provides a method for fabricating a vertically wire-bonded in-memory computing fan-out package structure, comprising the following steps:

[0030] S1. Prepare the first temporary bonding carrier, and the first chip, second chip and third chip to be mounted subsequently; the first chip and third chip are computing chips, such as CPU, GPU, FPGA, ASIC, etc.; the second chip is a memory chip, such as DRAM wafer, etc.

[0031] S2. Prepare a first redistribution layer on the surface of the first temporary bonding carrier;

[0032] S3. Make photoresist openings on the first wiring layer, and prepare copper pillars extending along the thickness direction in the openings by electroplating process.

[0033] S4. The first chip is flip-chip mounted onto the first wiring layer and soldered.

[0034] S5. Multiple second chips are stacked and mounted on the first chip in a positive mounting manner, and adjacent chips are fixed together by adhesive (DAF) film;

[0035] S6. Perform vertical wire bonding at the pads of the stacked second chip to form multiple vertical wires extending along the thickness direction.

[0036] S7. The above structure is encapsulated so that the first chip, the second chip, the copper pillar and the vertical wire are covered by the encapsulation layer I.

[0037] S8. Grind the encapsulated structure to expose the tops of the copper pillars and vertical conductors, and create a second wiring layer on the ground surface.

[0038] S9. A second temporary bonding carrier is provided on the second wiring layer, and the first temporary bonding carrier is removed.

[0039] S10. Flip the above structure so that the second temporary bonding carrier is at the bottom, mount the third chip on the first redistribution layer in a flip-chip manner, and perform bottom filling and re-encapsulation so that the third chip is covered by the encapsulation layer II.

[0040] S11. Remove the second temporary bonding carrier and prepare solder balls on the back side of the second rewiring layer to obtain a vertical wire bonding in-memory computing fan-out package structure.

[0041] Furthermore, the first temporary bonding carrier and / or the second temporary bonding carrier are selected from glass substrates, ceramics, metals, or silicon wafers.

[0042] Furthermore, the first rewiring layer and / or the second rewiring layer are multi-layer rewiring structures with 3 to 6 layers.

[0043] Furthermore, in step S2, a first redistribution layer is prepared on the first temporary bonding carrier by a coating, exposure, and development process.

[0044] Furthermore, in step S3, photoresist openings are created on the first interconnect layer by coating, exposure, and development.

[0045] Furthermore, in step S5, adjacent second chips are fixed together and between the second chip and the first chip by an adhesive (DAF) film.

[0046] Furthermore, in step S6, the diameter and height of the vertical conductor can be determined based on the overall package dimensions. The material of the vertical conductor is selected from gold, silver, copper, gold-plated copper, platinum-plated copper, etc.

[0047] Furthermore, in step S7, the molding layer I includes a first molding layer and a second molding layer formed sequentially. The thickness of the first molding layer does not exceed the height of the copper pillar and the vertical conductor. The second molding layer has an elastic modulus lower than that of the first molding layer. The first molding layer is used to fix the copper pillar and the vertical conductor, and the second molding layer is used to absorb the stress difference generated by the rigid copper pillar and the flexible vertical conductor.

[0048] Specifically, a staged molding process is used when molding the structure containing copper pillars and vertical wires. First, a first-stage molding process is performed to form a conventional molding layer, the thickness of which does not exceed the height of the copper pillars and vertical wires, to structurally fix the first chip, the second chip, the copper pillars, and the vertical wires. After the first-stage molding layer cures, a second-stage molding process is performed to form a buffer molding layer. The buffer molding layer has a lower elastic modulus than the conventional molding layer to absorb mechanical stress generated during subsequent processes and use. After curing, the two molding materials form a continuously bonded composite molding structure, which, after grinding, simultaneously exposes the copper pillars and vertical wires.

[0049] Furthermore, the first molding layer is a conventional molding layer formed by high-modulus epoxy molding material, used to fix the copper pillars and vertical conductors; the second molding layer is a buffer molding layer formed by low-modulus toughened epoxy molding material, used to absorb the stress difference generated by the rigid copper pillars and flexible vertical conductors.

[0050] Furthermore, the formulation of the first molding layer includes 35-45 parts by weight of epoxy resin, 10-15 parts by weight of phenolic curing agent, 35-45 parts by weight of spherical silica filler, 0.3-1.0 parts by weight of coupling agent, 0.1-0.5 parts by weight of catalyst, and 0.1-0.5 parts by weight of flow modifier.

[0051] The formulation of the second molding layer includes 40-55 parts by weight of flexible modified epoxy resin, 8-12 parts by weight of latent curing agent, 5-12 parts by weight of elastomer toughening agent, 10-20 parts by weight of fine silica, 0.3-1.0 parts by weight of coupling agent, and 0.1-0.5 parts by weight of flow modifier.

[0052] Furthermore, the thickness of the first molding layer accounts for 90% to 99% of the height of the copper pillar; the second molding layer completely covers all the copper pillars and vertical conductors.

[0053] Furthermore, in step S10, the number of third chips can be one or more.

[0054] As described above, the in-memory computing fan-out package structure with vertical wire bonding and its manufacturing method of the present invention have the following beneficial effects:

[0055] 1. By introducing a hybrid vertical interconnect method combining vertical wire bonding and copper pillars into the fan-out package structure, high-density three-dimensional integration of computing and memory chips is achieved without using through-silicon vias (TSVs) or silicon interposers. This effectively shortens the signal transmission path, increases interconnect bandwidth, and reduces system latency and power consumption. Compared with existing technologies, it replaces the high-cost TSV / Interposer solution, significantly reducing manufacturing costs; it achieves extremely close integration of computing and storage, fundamentally alleviating the "memory wall" problem; it improves the reliability and heat dissipation capacity of the package structure; and it enables double-sided high-density integration and system expansion.

[0056] 2. This "memory below, compute above" three-dimensional stacking arrangement places the memory chip within the core area of ​​the package, close to the redistribution layer and vertical interconnect structure. A large number of I / O signals from the memory chip can access the vertical interconnect network via shorter paths, thereby reducing interconnect parasitic parameters and improving signal integrity. Furthermore, the compute chip is positioned on top of the redistribution structure, facilitating functional expansion and system configuration through rewiring. This arrangement also helps to keep major heat sources away from the memory chip, improving heat distribution within the package and enhancing the reliability and process feasibility of the in-memory compute package.

[0057] 3. When encapsulating a structure containing copper pillars and vertical conductors, this invention employs a staged encapsulation process. First, a first-stage encapsulation is performed to form a conventional encapsulation layer, which is used to structurally fix the computing chip, memory chip, copper pillars, and vertical conductors. After the first-stage encapsulation layer has cured, a second-stage encapsulation is performed to form a buffer encapsulation layer. The buffer encapsulation layer has a lower elastic modulus than the conventional encapsulation layer, which can absorb the mechanical stress generated during subsequent processes and use. Attached Figure Description

[0058] Figure 1 This is a diagram of the first temporary bonding carrier disclosed in Embodiment 1 of the present invention.

[0059] Figure 2 This is the first rewiring layer diagram disclosed in Embodiment 1 of the present invention.

[0060] Figure 3 This is the photoresist opening diagram disclosed in Embodiment 1 of the present invention.

[0061] Figure 4 A copper pillar pattern is prepared at the photoresist opening disclosed in Embodiment 1 of the present invention.

[0062] Figure 5 This is the first chip connection diagram disclosed in Embodiment 1 of the present invention.

[0063] Figure 6 This is a diagram showing the second chip connection and vertical bonding pattern disclosed in Embodiment 1 of the present invention.

[0064] Figure 7 This is a diagram of the encapsulation layer I disclosed in Embodiment 1 of the present invention.

[0065] Figure 8 This is a diagram of the fabrication of the second rewiring layer disclosed in Embodiment 1 of the present invention.

[0066] Figure 9 This is a diagram of the second temporary bonding carrier disclosed in Embodiment 1 of the present invention.

[0067] Figure 10 This is a connection diagram of the third chip disclosed in Embodiment 1 of the present invention.

[0068] Figure 11 This is a schematic diagram of the in-memory computing fan-out package structure with vertical wire bonding disclosed in Embodiment 1 of the present invention.

[0069] Figure 12 This is a diagram of the encapsulation layer I disclosed in Embodiment 2 of the present invention.

[0070] Component designation explanation:

[0071] 1. First temporary bonding carrier; 2. First redistribution layer; 3. Photoresist; 4. Copper pillar; 5. First chip; 6. Second chip; 7. Molding layer I; 8. Second redistribution layer; 9. Second temporary bonding carrier; 10. Third chip; 11. Molding layer II; 12. Solder ball; 13. Vertical conductor. Detailed Implementation

[0072] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

[0073] Example 1

[0074] This embodiment provides a vertically wire-bonded in-memory computing fan-out package structure, such as... Figure 11 As shown, it includes:

[0075] The package body has a first wiring layer 2 and a second wiring layer 8 arranged from top to bottom inside the package body;

[0076] Multiple copper pillars 4 are disposed between the first wiring layer 2 and the second wiring layer 8. The copper pillars 4 extend along the package thickness direction and are used as vertical electrical interconnects and structural supports.

[0077] The first chip 5 is disposed below the first super-wiring layer 2, and the pads of the first chip 5 are electrically connected to the first super-wiring layer 2 through solder or bumps.

[0078] Multiple second chips 6 are stacked below the first chip 5, and the second chips 6 are fixed to each other and to the first chips 5 by adhesive film.

[0079] Multiple vertical wires 13 are disposed at the pads of the second chip 6. The vertical wires 13 extend along the package thickness direction, with one end connected to the pads of the second chip 6 and the other end extending downward to connect with the second redistribution layer 8.

[0080] A molding layer I7 is disposed between the first wiring layer 2 and the second wiring layer 8, and the molding layer I7 covers the first chip 5, the second chip 6, the copper pillar 4 and the vertical conductor 13.

[0081] Solder balls 12 are located at the bottom of the second wiring layer 8. Solder balls 12 are electrically connected to copper pillars 4 and vertical conductors 13 through the second wiring layer 8.

[0082] A third chip 10 is disposed above the first rewiring layer 2, and the third chip 10 is electrically connected to the first rewiring layer 2.

[0083] A molding layer II11 is disposed above the first redistribution layer 2, and the molding layer II11 covers the third chip 10.

[0084] Among them, the first chip 5 and the third chip 10 are computing chips, such as CPU, GPU, FPGA, ASIC, etc.; the second chip 6 is a storage chip, such as DRAM wafer, etc.

[0085] This embodiment also provides a method for fabricating the vertically wire-bonded in-memory computing fan-out package structure, including the following steps:

[0086] S1, such as Figure 1As shown, a first temporary bonding carrier 1 is prepared, which can be a glass substrate, ceramic, metal or silicon wafer; and a first chip 5, a second chip 6 and a third chip 10 to be subsequently mounted; the first chip 5 and the third chip 10 are computing chips, such as CPU, GPU, FPGA, ASIC, etc.; the second chip 6 is a memory chip, such as DRAM wafer, etc., and its thickness can be reduced by grinding according to product needs.

[0087] S2, such as Figure 2 As shown, a first redistribution layer 2 is prepared on the surface of the first temporary bonding carrier 1.

[0088] S3, such as Figure 3 As shown, photoresist 3 openings are created on the first interconnect layer 2 through coating, exposure, and development; then, copper pillars 4 extending along the thickness direction are prepared within the openings through an electroplating process, as shown. Figure 4 As shown.

[0089] S4, such as Figure 5 As shown, the first chip 5 is flip-chip mounted onto the first rewiring layer 2 and soldered together.

[0090] S5. Then, multiple second chips 6 are stacked and mounted on the first chip 5 in a positive mounting manner, and adjacent chips are fixed together by adhesive (DAF) film.

[0091] S6. Vertical wire bonding is performed at the pads of the stacked second chip 6 to form multiple vertical wires 13 extending along the thickness direction, resulting in... Figure 6 The diameter and height of the vertical lines in the structure shown can be determined based on the overall package dimensions. The materials of the vertical lines can be gold, silver, copper, gold-plated copper, platinum-plated copper, etc.

[0092] S7, such as Figure 7 As shown, the structure obtained in step S6 is encapsulated, so that the first chip 5, the second chip 6, the copper pillar 4 and the vertical wire 13 are covered by the encapsulation layer I7.

[0093] S8, such as Figure 8 As shown, the encapsulated structure is ground to expose the top of the copper pillar 4 and the vertical conductor 13, and a second wiring layer 8 is made on the ground surface.

[0094] S9, such as Figure 9 As shown, a second temporary bonding carrier 9 is provided on the second redistribution layer 8, and the first temporary bonding carrier 1 is removed.

[0095] S10. The above structure is flipped so that the second temporary bonding carrier 9 is at the bottom. The third chip 10 is flip-chip mounted on the first redistribution layer 2, and bottom filling and re-encapsulation are performed so that the third chip 10 is covered by the encapsulation layer II 11. Figure 10 As shown.

[0096] S11. Remove the second temporary bonding carrier 9 and prepare solder balls 12 on the back side of the second redistribution layer 8 to obtain the following: Figure 11 The shown is a vertically wire-bonded in-memory computing fan-out package structure.

[0097] Example 2

[0098] This embodiment provides a vertically wire-bonded in-memory computing fan-out package structure, including:

[0099] The package body has a first wiring layer and a second wiring layer arranged sequentially from top to bottom inside the package body;

[0100] Multiple copper pillars are disposed between the first and second wiring layers, the copper pillars extending along the thickness direction of the package, and are used as vertical electrical interconnects and structural supports;

[0101] The first chip is disposed below the first wiring layer, and the pads of the first chip are electrically connected to the first wiring layer by solder or bumps.

[0102] Multiple second chips are stacked below the first chip, and the second chips are fixed to each other and to each first chip by an adhesive film.

[0103] Multiple vertical wires are disposed at the pads of the second chip. The vertical wires extend along the thickness direction of the package, with one end connected to the pads of the second chip and the other end extending downward to connect to the second redistribution layer.

[0104] A molding compound layer I is disposed between the first and second rewiring layers. The molding compound layer I covers the first chip, the second chip, copper pillars, and vertical conductors. The molding compound layer I includes a first molding compound layer and a second molding compound layer. The first molding compound layer is close to the first rewiring layer, and the second molding compound layer is close to the second rewiring layer. The second molding compound layer has a lower elastic modulus than the first molding compound layer. The thickness of the first molding compound layer accounts for 90% to 99% of the thickness of the molding compound layer I.

[0105] The solder balls are located at the bottom of the second wiring layer and are electrically connected to the copper pillars and vertical conductors through the second wiring layer.

[0106] A third chip is disposed above the first wiring layer, and the third chip is electrically connected to the first wiring layer.

[0107] A molding layer II is disposed above the first wiring layer, and the molding layer II covers the third chip.

[0108] The first and third chips are computing chips, such as CPUs, GPUs, FPGAs, and ASICs; the second chip is a memory chip, such as a DRAM wafer.

[0109] This embodiment also provides a method for fabricating the vertically wire-bonded in-memory computing fan-out package structure, including the following steps:

[0110] S1. Prepare a first temporary bonding carrier, which can be a glass substrate, ceramic, metal or silicon wafer; and a first chip, a second chip and a third chip to be mounted subsequently; the first chip and the third chip are computing chips, such as CPU, GPU, FPGA, ASIC, etc.; the second chip is a memory chip, such as DRAM wafer, etc., and the thickness can be reduced by grinding according to product needs.

[0111] S2. Prepare a first redistribution layer on the surface of the first temporary bonding carrier.

[0112] S3. On the first wiring layer, a photoresist opening is made by coating, exposure and development; then, a copper pillar extending along the thickness direction is prepared in the opening by electroplating.

[0113] S4. The first chip is flip-chip mounted onto the first wiring layer and soldered.

[0114] S5. Then, multiple second chips are stacked and mounted on the first chip in a positive mounting manner, and adjacent chips are fixed together by adhesive (DAF) film.

[0115] S6. Vertical wire bonding is performed on the pads of the stacked second chip to form multiple vertical wires extending along the thickness direction. The diameter and height of the vertical wires can be determined according to the overall package size. The material of the vertical wires can be gold, silver, copper, gold-plated copper, platinum-plated copper, etc.

[0116] S7, such as Figure 12 As shown, the structure obtained in step S6 is encapsulated in stages. First, a first stage of encapsulation is performed to form a first encapsulation layer, the thickness of which accounts for 90% to 99% of the height of the copper pillars. Then, a second stage of encapsulation is performed to form a second encapsulation layer, which completely covers all the copper pillars and vertical conductors.

[0117] The formulation of the first molding layer includes 35-45 parts by weight of epoxy resin, 10-15 parts by weight of phenolic curing agent, 35-45 parts by weight of spherical silica filler, 0.3-1.0 parts by weight of coupling agent, 0.1-0.5 parts by weight of catalyst, and 0.1-0.5 parts by weight of flow modifier; the formulation of the second molding layer includes 40-55 parts by weight of flexible modified epoxy resin, 8-12 parts by weight of latent curing agent, 5-12 parts by weight of elastomer toughening agent, 10-20 parts by weight of fine silica, 0.3-1.0 parts by weight of coupling agent, and 0.1-0.5 parts by weight of flow modifier.

[0118] Because the second molding layer has a lower elastic modulus than the first molding layer, the first molding layer can be used to fix the copper pillars and vertical conductors, while the second molding layer can be used to absorb the stress difference caused by the rigid copper pillars and the flexible vertical conductors.

[0119] S8. Grind the encapsulated structure to expose the tops of the copper pillars and vertical conductors, and create a second wiring layer on the ground surface.

[0120] S9. A second temporary bonding carrier is provided on the second wiring layer, and the first temporary bonding carrier is removed.

[0121] S10. The above structure is flipped so that the second temporary bonding carrier is at the bottom. The third chip is mounted on the first redistribution layer in a flip-chip manner, and bottom filling and re-molding are performed so that the third chip is covered by the molding layer II.

[0122] S11. Remove the second temporary bonding carrier and prepare solder balls on the back side of the second rewiring layer to obtain a vertical wire bonding in-memory computing fan-out package structure.

[0123] In summary, this invention achieves high-density three-dimensional integration of computing and memory chips by introducing a hybrid vertical interconnect method combining vertical wire bonding and copper pillars into a fan-out package structure, without using through-silicon vias (TSVs) or silicon interposers, effectively shortening the signal transmission path. This "memory below, computing above" three-dimensional stacking arrangement places the memory chip inside the package, close to the core area of ​​the redistribution layer and vertical interconnect structure. A large number of I / O signals from the memory chip can access the vertical interconnect network through a shorter path, thereby reducing interconnect parasitic parameters and improving signal integrity. Furthermore, this arrangement helps to keep the main heat sources away from the memory chip, improving heat distribution within the package and enhancing the reliability and process feasibility of the in-memory computing package structure. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial applicability.

[0124] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A vertically wire-bonded in-memory computing fan-out package structure, characterized in that, include: The package body has a first wiring layer and a second wiring layer arranged sequentially from top to bottom inside the package body; Multiple copper pillars are disposed between the first and second wiring layers; The first chip is disposed below the first wiring layer, and the pads of the first chip are electrically connected to the first wiring layer. Multiple second chips are stacked below the first chip, and the second chips are fixed to each other and to each first chip by an adhesive film. Multiple vertical wires are placed at the pads of the second chip, one end of which is connected to the pads of the second chip, and the other end extends downward to connect with the second redistribution layer. A molding layer I is disposed between the first and second wiring layers, wherein the molding layer I covers the first chip, the second chip, the copper pillars and the vertical conductors; Solder balls located at the bottom of the second wiring layer; A third chip is disposed above the first wiring layer, and the third chip is electrically connected to the first wiring layer. A molding layer II is disposed above the first wiring layer, and the molding layer II covers the third chip; The first and third chips are computing chips, and the second chip is a storage chip.

2. The in-memory computing fan-out package structure with vertical wire bonding according to claim 1, characterized in that, The molding layer I includes a first molding layer and a second molding layer. The first molding layer is close to the first redistribution layer, and the second molding layer is close to the second redistribution layer. The thickness of the first molding layer does not exceed the height of the copper pillar and the vertical conductor. The second molding layer has a lower elastic modulus than the first molding layer.

3. The in-memory computing fan-out package structure with vertical wire bonding according to claim 2, characterized in that, The first encapsulation layer is made of a high-modulus epoxy encapsulation material; the second encapsulation layer is made of a low-modulus toughened epoxy encapsulation material.

4. The in-memory computing fan-out package structure with vertical wire bonding according to claim 1, characterized in that, The first rewiring layer and / or the second rewiring layer are multi-layer rewiring structures with 3 to 6 layers.

5. A method for fabricating a vertically wire-bonded in-memory computing fan-out package structure, characterized in that, Includes the following steps: S1. Prepare the first temporary bonding carrier, and the first chip, second chip and third chip to be mounted subsequently; the first chip and third chip are computing chips, and the second chip is a storage chip. S2. Prepare a first redistribution layer on the surface of the first temporary bonding carrier; S3. Make photoresist openings on the first wiring layer, and prepare copper pillars extending along the thickness direction in the openings by electroplating process. S4. The first chip is flip-chip mounted onto the first wiring layer and soldered. S5. Multiple second chips are stacked and mounted on the first chip in a positive mounting manner, and adjacent chips are fixed together by adhesive film; S6. Perform vertical wire bonding at the pads of the stacked second chip to form multiple vertical wires extending along the thickness direction. S7. The above structure is encapsulated so that the first chip, the second chip, the copper pillar and the vertical wire are covered by the encapsulation layer I. S8. Grind the encapsulated structure to expose the tops of the copper pillars and vertical conductors, and create a second wiring layer on the ground surface. S9. A second temporary bonding carrier is provided on the second wiring layer, and the first temporary bonding carrier is removed. S10. Flip the above structure so that the second temporary bonding carrier is at the bottom, mount the third chip on the first redistribution layer in a flip-chip manner, and perform bottom filling and re-encapsulation so that the third chip is covered by the encapsulation layer II. S11. Remove the second temporary bonding carrier and prepare solder balls on the back side of the second rewiring layer to obtain the vertical wire bonding storage-computing fan-out package structure.

6. The preparation method according to claim 5, characterized in that, In step S7, the molding layer I includes a first molding layer and a second molding layer formed sequentially. The thickness of the first molding layer does not exceed the height of the copper pillar and the vertical conductor. The second molding layer has an elastic modulus lower than that of the first molding layer.

7. The preparation method according to claim 6, characterized in that, The first molding layer is a conventional molding layer formed by high-modulus epoxy molding material, used to fix the copper pillars and vertical conductors; the second molding layer is a buffer molding layer formed by low-modulus toughened epoxy molding material, used to absorb the stress difference generated by the rigid copper pillars and flexible vertical conductors.

8. The preparation method according to claim 6, characterized in that, The formulation of the first molding layer includes 35-45 parts by weight of epoxy resin, 10-15 parts by weight of phenolic curing agent, 35-45 parts by weight of spherical silica filler, 0.3-1.0 parts by weight of coupling agent, 0.1-0.5 parts by weight of catalyst, and 0.1-0.5 parts by weight of flow modifier. The formulation of the second molding layer includes 40-55 parts by weight of flexible modified epoxy resin, 8-12 parts by weight of latent curing agent, 5-12 parts by weight of elastomer toughening agent, 10-20 parts by weight of fine silica, 0.3-1.0 parts by weight of coupling agent, and 0.1-0.5 parts by weight of flow modifier.

9. The preparation method according to claim 6, characterized in that, The thickness of the first molding layer accounts for 90% to 99% of the height of the copper pillar; the second molding layer completely covers all the copper pillars and vertical conductors.

10. The preparation method according to claim 5, characterized in that, In step S6, the material of the vertical conductor is selected from gold, silver, copper, gold-plated copper, or platinum-plated copper.

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