Semiconductor package structure and preparation method thereof, electronic device

Abstract

This application provides a semiconductor packaging structure and its fabrication method, as well as an electronic device. The fabrication method of the semiconductor packaging structure includes: providing a first glass temporary carrier; forming a plurality of conductive pillars on the first glass temporary carrier; placing at least one silicon bridge chip on the first glass temporary carrier, with the silicon bridge chip and the conductive pillars arranged at intervals; forming a first molding compound layer encapsulating the conductive pillars and the silicon bridge chip; forming a first redistribution layer on the side of the first molding compound layer away from the first glass temporary carrier, the first redistribution layer being electrically connected to the conductive pillars and the silicon bridge chip respectively; placing a plurality of functional chips on the side of the first redistribution layer away from the first glass temporary carrier, the functional chips being electrically connected to the first redistribution layer; and removing the first glass temporary carrier. This application suppresses overall warpage from the source by using a first glass temporary carrier with high flatness and by adopting a process sequence of first forming the molding compound interconnect core and then fabricating the redistribution layer.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, and in particular to a semiconductor packaging structure and its preparation method, and an electronic device. Background Technology

[0002] With the development of high-performance chips, chip integration is becoming increasingly higher, and the development of multi-chip heterogeneous integration has reached a bottleneck. The requirements for the mechanical strength and flatness of the substrate are becoming increasingly higher, and the performance of traditional organic substrates in terms of flatness and warpage can no longer meet the requirements. Summary of the Invention

[0003] In view of this, the purpose of this application is to propose a semiconductor packaging structure and its preparation method, as well as an electronic device, which, by using a glass temporary carrier, ensures low warpage during the manufacturing process while allowing the placement of multiple functional chips and enabling the fabrication of fine circuits.

[0004] In view of the above objectives, in a first aspect, this application provides a method for fabricating a semiconductor packaging structure, comprising: Provide the first glass temporary carrier plate; Multiple conductive pillars are formed on the first glass temporary carrier plate; At least one silicon bridge chip is disposed on a first glass temporary carrier, with the silicon bridge chip and conductive pillars arranged at intervals. Forming the first molding layer that encapsulates the conductive pillars and silicon bridge chip; A first super-wiring layer is formed on the side of the first molding layer away from the first glass temporary carrier, and the first super-wiring layer is electrically connected to the conductive pillar and the silicon bridge chip respectively. Multiple functional chips are disposed on the side of the first wiring layer away from the first glass temporary carrier, and the functional chips are electrically connected to the first wiring layer. Remove the first glass temporary carrier plate.

[0005] Optionally, a plurality of conductive pillars are formed on the first glass temporary carrier, including: A seed layer and a patterned photoresist layer are sequentially formed on a first glass temporary substrate, the photoresist layer having through holes that expose a portion of the seed layer; Conductive pillars are formed by filling the through-holes with conductive material through an electroplating process. Remove the photoresist layer.

[0006] Optionally, a first molding layer is formed to encapsulate the conductive pillars and silicon bridge chip, comprising: A molding compound is used to fill the gaps between the silicon bridge chip and multiple conductive pillars to form a first molding layer covering the conductive pillars and the silicon bridge chip; The first molding layer is ground to expose at least one end of the conductive pillar away from the first glass temporary carrier. Preferably, the thickness of the first molding layer after grinding is 30μm-150μm.

[0007] Optionally, after multiple functional chips are disposed on the side of the first wiring layer away from the first glass temporary carrier, and before the first glass temporary carrier is removed, the method further includes: An underfill layer is placed between the functional chip and the first interconnect layer; A second molding compound is formed to encapsulate multiple functional chips.

[0008] Optionally, after forming the second molding layer, the process further includes: Perform a flipping operation to connect the side surface of the second molding layer away from the silicon bridge chip to the second glass temporary carrier.

[0009] Optionally, after performing the flip operation, the following is also included: The side of the first molding layer furthest from the functional chip is ground to expose the ends of the silicon bridge chip and conductive pillars; A second wiring layer is formed on the side of the silicon bridge chip away from the functional chip. The second wiring layer is electrically connected to the conductive pillars and the silicon bridge chip, respectively. Remove the second glass temporary carrier plate.

[0010] Optionally, after forming the second routing layer, the following steps are also included: Conductive bumps are formed on the side of the second wiring layer away from the functional chip; Preferably, after removing the first temporary glass carrier plate, the method further includes: Remove the seed layer located at the end of the conductive post; The side of the first molding layer away from the functional chip is ground to expose the ends of the silicon bridge chip and the conductive pillars, and the ends of the silicon bridge chip are made flush with the ends of the conductive pillars.

[0011] Secondly, this application also provides a semiconductor packaging structure, including: At least one silicon bridge chip and a plurality of conductive pillars, wherein the silicon bridge chip and the conductive pillars are arranged at intervals; A first molding layer encapsulates the conductive pillars and the silicon bridge chip. A first wiring layer is disposed on one side of the first molding layer, and the first wiring layer is electrically connected to the conductive pillar and the silicon bridge chip respectively; Multiple functional chips are disposed on the side of the first wiring layer away from the first molding layer, and the functional chips are electrically connected to the first wiring layer; The first redistribution layer and the functional chip are located on the same side of the first molding layer.

[0012] Optionally, it also includes: The second wiring layer is disposed on the side of the silicon bridge chip away from the functional chip; Preferably, the semiconductor packaging structure further includes conductive bumps disposed on the side of the second redistribution layer away from the functional chip; Preferably, the semiconductor packaging structure further includes an underfill layer and a second molding compound layer, wherein the underfill layer is filled between the functional chip and the first redistribution layer, and the second molding compound layer encapsulates a plurality of the functional chips.

[0013] Thirdly, this application also provides an electronic device, including a semiconductor package structure obtained by the method for preparing a semiconductor package structure as described in any of the first aspects above, or a semiconductor package structure as described in any of the second aspects.

[0014] The semiconductor packaging structure provided in this application first forms a plastic interconnect core by plastic encapsulating the silicon bridge chip and conductive pillars, and then fabricates the first redistribution layer. This sequence ensures that the fine first redistribution layer is fabricated on a substrate that has been stabilized by the plastic encapsulation layer and whose stress has been released. This avoids the deformation of the redistribution layer fabricated first in the traditional process during subsequent high-stress processes such as plastic encapsulation, thereby suppressing overall warping from the source of the process. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in this application or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic flowchart of a method for fabricating a semiconductor packaging structure according to an embodiment of this application; Figure 2 This is a cross-sectional schematic diagram of a key step in the fabrication method of a semiconductor packaging structure according to an embodiment of this application; Figure 3 This is a cross-sectional schematic diagram of a semiconductor packaging structure according to an embodiment of this application; Figure 4 This is a cross-sectional schematic diagram of some steps in a method for fabricating a semiconductor packaging structure according to an embodiment of this application; Figure 5 This is a cross-sectional schematic diagram of some steps in a method for fabricating a semiconductor packaging structure according to an embodiment of this application; Figure 6 This is a cross-sectional schematic diagram of some steps in a method for fabricating a semiconductor packaging structure according to an embodiment of this application; Figure 7 This is a cross-sectional schematic diagram of some steps in a method for fabricating a semiconductor packaging structure according to an embodiment of this application; Figure 8 This is a cross-sectional schematic diagram of a semiconductor packaging structure according to another embodiment of this application.

[0017] Marker explanation: 100. Semiconductor packaging structure; 10a, First glass temporary carrier; 10b, Second glass temporary carrier; 11, Temporary bonding adhesive; 101, Seed layer; 20, Conductive pillar; 201, Photoresist layer; 202, Through-hole; 30, Silicon bridge chip; 301, Chip bonding film; 40, Functional chip; 41, First chip; 42, Second chip; 43, Third chip; 401, Underfill layer; 51, First redistribution layer; 52, Second redistribution layer; 61, First molding layer; 62, Second molding layer; 70, Conductive bump; 80, Molded interconnect core. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0019] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in the embodiments of this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0020] With the rapid development of technologies such as high-performance computing, artificial intelligence, and 5G communication, the demands for chip integration and performance are constantly increasing, making heterogeneous integration a crucial direction for advanced packaging. Under this trend, packaging structures need to accommodate more chips and achieve higher-density interconnections, placing unprecedented demands on the mechanical strength, surface flatness, and warp resistance of the packaging substrate.

[0021] Traditional organic substrates (such as FCBGA substrates) are prone to warping due to their limited material rigidity and thermal stability when supporting large-size, multi-chip structures and undergoing high-temperature processes such as die bonding and molding. This warping not only affects the precision of subsequent fine processes such as photolithography and electroplating, leading to a decrease in circuit yield, but may also cause chip connection failures, affecting the reliability of the package.

[0022] To overcome the aforementioned problems, various 2.5D packaging solutions have been proposed. One mainstream solution is to use a silicon interposer, which has a high surface flatness and can achieve vertical interconnects through through-silicon vias (TSVs). However, silicon interposers are expensive, and the manufacturing yield drops sharply as the area increases, limiting their application in large-size packages. Another solution is to use a technology that embeds silicon bridges within the molding compound, such as creating through-mold vias (TMVs) in the molding compound and embedding silicon bridges to achieve localized high-density interconnects. Although the cost is lower than that of silicon interposers, the TMV process has limitations on miniaturizing the diameter of the copper pillars, limiting further increases in interconnect density. In addition, some solutions require precise etching of grooves on the silicon interposer or silicon wafer to embed silicon bridges, a complex process that requires high processing precision.

[0023] Based on this, this application aims to provide a new packaging solution that can achieve high-density interconnection while more effectively controlling process warpage, simplifying key process steps, and having good cost-effectiveness.

[0024] like Figure 1 , Figure 2 , Figure 3 As shown, some embodiments of this application provide a method for fabricating a semiconductor package structure 100, specifically including the following steps: Step S10: Provide the first glass temporary carrier plate 10a; Step S20: Form a plurality of conductive pillars 20 on the first glass temporary carrier plate 10a; Step S30: At least one silicon bridge chip 30 is placed on the first glass temporary carrier 10a, and the silicon bridge chip 30 and a plurality of conductive pillars 20 are arranged at intervals. Step S40: Form a first molding layer 61 that encapsulates the conductive pillar 20 and the silicon bridge chip 30; Step S50: A first redistribution layer 51 is formed on the side of the first molding layer 61 away from the first glass temporary carrier 10a. The first redistribution layer 51 is electrically connected to the conductive pillar 20 and the silicon bridge chip 30 respectively. Step S60: A plurality of functional chips 40 are disposed on the side of the first wiring layer 51 away from the first glass temporary carrier 10a, and the functional chips 40 are electrically connected to the first wiring layer 51. Step S70: Remove the first glass temporary carrier plate 10a.

[0025] Specifically, the fabrication process of the semiconductor packaging structure 100 includes: preparing a glass sheet as a first temporary glass carrier 10a. The first temporary glass carrier 10a is preferably glass that has undergone chemical mechanical polishing, resulting in high flatness and smoothness. The glass material itself possesses high rigidity, a low coefficient of thermal expansion (CTE), and excellent chemical and thermal stability. Optionally, a temporary bonding adhesive 11 is coated on the surface of the first temporary glass carrier 10a for subsequent temporary bonding with the molding compound and final peeling.

[0026] On the first glass temporary carrier 10a, a seed layer 101 is formed by physical vapor deposition of a titanium / copper stack. Then, photoresist is spin-coated and patterned to form a photoresist layer 201 with through holes. Then, conductive material is filled into the through holes by copper electroplating to form multiple independent conductive pillars 20.

[0027] At least one pre-prepared silicon bridge chip 30 is attached to the first glass temporary carrier plate 10a through a chip adhesive film, and the silicon bridge chip 30 and the conductive pillar 20 are arranged at intervals on the plane.

[0028] Injection molding is performed using a molding compound, such as epoxy molding compound (EMC), which fills the spaces between multiple conductive pillars 20 and between the conductive pillars 20 and the silicon bridge chip 30, thereby forming a first molding layer 61. The first molding layer 61 encapsulates and fixes the conductive pillars 20 and the silicon bridge chip 30.

[0029] The surface of the first molding layer 61 away from the first glass temporary carrier 10a is ground to expose the top of the conductive pillar 20 and the metal bumps on the upper surface of the silicon bridge chip 30. On the flat surface formed after grinding, a first redistribution layer 51 is formed by alternately depositing a polyimide dielectric layer and a copper metal wiring pattern. The bottom metal lines of the first redistribution layer 51 are aligned and electrically connected to the top of the conductive pillar 20 and the metal bumps of the silicon bridge chip 30.

[0030] Using flip-chip bonding technology, multiple functional chips 40 are soldered to corresponding pads on the first wiring layer 51 through their own solder bumps.

[0031] In the current process of fabricating the redistribution layer (RDL) before molding and integration, the warp-sensitive fine redistribution layer is prematurely exposed to high-stress processes (such as molding and chip mounting), making it difficult to control stress accumulation. At the same time, the cost and process complexity of both the expensive silicon interposer and the silicon interposer that requires slotting as a permanent carrier limit flexibility and economy.

[0032] The semiconductor packaging structure 100 fabrication method provided in this application uses a first glass temporary carrier 10a as a carrier platform. This method includes a specific sequence of first constructing an interconnect structure and fixing it with plastic encapsulation, followed by fabricating a redistribution layer. The highly flat first glass temporary carrier 10a provides a stable initial platform for the precise forming of the interconnect structure. Furthermore, before fabricating the warp-sensitive fine wiring layer, the conductive pillars 20 and the silicon bridge chip 30 are first solidified into a single unit through plastic encapsulation, i.e., the plastic-encapsulated interconnect core 80. This ensures that the subsequent redistribution layer process is performed on a stable and flat substrate. This process sequence effectively isolates the mutual interference between the thermal / mechanical stress during the redistribution layer manufacturing process and the interconnect structure forming stress, avoiding the risk of RDL deformation caused by high-stress plastic encapsulation after fabricating the fine RDL in the traditional process. From a process flow design perspective, this helps to suppress overall warping.

[0033] Meanwhile, the fabrication method of this application avoids dependence on complex silicon etching processes and provides a potential, more simplified high-density interconnect packaging path.

[0034] Among them, the conductive post 20 mainly undertakes the vertical interconnection of power supply, grounding and some low-frequency signals, and provides the main mechanical support; while the silicon bridge chip 30 is mainly used for high-density, high-speed signal interconnection between adjacent functional chips 40, using its internal fine wiring to shorten the interconnection path and improve bandwidth.

[0035] In some embodiments, such as Figure 4 As shown, step S20, which involves forming a plurality of conductive pillars 20 on the first glass temporary carrier plate 10a, includes the following sub-steps: Step S21: A seed layer 101 and a patterned photoresist layer 201 are sequentially formed on the first glass temporary carrier 10a. The photoresist layer 201 has a through hole 202 that exposes part of the seed layer 101. Step S22: Fill the through hole 202 with conductive material through an electroplating process to form a conductive pillar 20; Step S23: Remove the photoresist layer 201.

[0036] Specifically, the process of forming conductive pillars 20 on the first glass temporary carrier plate 10a includes: forming a seed layer 101 sequentially on the surface of the first glass temporary carrier plate 10a by physical vapor deposition.

[0037] Photoresist is spin-coated onto the seed layer 101 and patterned by photolithography (exposure and development) to form a patterned photoresist layer 201. The photoresist layer 201 has multiple cylindrical through holes 202 that expose portions of the seed layer 101 below.

[0038] The structure with a patterned photoresist layer is immersed in a copper sulfate electroplating solution, and electroplating is performed using the seed layer 101 as the cathode. Copper ions are reduced and deposited in the exposed seed layer area, growing upward from the bottom of the via 202 until the via is completely filled, forming a solid electroplated copper pillar, i.e., a conductive pillar 20.

[0039] After electroplating, the patterned photoresist layer 201 is removed using organic solvents or plasma stripping processes, and the tops of each conductive pillar 20 are flush.

[0040] The conductive pillars 20 are formed through a process of seed layer deposition, photolithography patterning, and electroplating filling. This process path offers high precision and controllability, enabling precise control over the position, diameter, and shape of the conductive pillars, and achieving a high aspect ratio. The conductive pillars 20 are made of electroplated copper, and their dimensions (e.g., diameter as low as 10-20 μm) and shape consistency are superior to traditional through-hole vias (TMVs), providing a technological basis for increasing vertical interconnect density.

[0041] In some embodiments, such as Figure 5 As shown, step S30 involves placing at least one silicon bridge chip 30 on the first glass temporary carrier 10a, specifically including: attaching the silicon bridge chip 30 to the first glass temporary carrier 10a via a chip adhesive film 301.

[0042] The silicon bridge chip 30 is mounted on the first glass temporary carrier 10a via a chip adhesive film (DAF). Specifically, the chip adhesive film, pre-laminated on the back of the silicon bridge chip 30, is aligned with a predetermined position on the first glass temporary carrier 10a and picked up and placed using a high-precision pick-and-place machine. Subsequently, the chip adhesive film 301 is cured by a hot-pressing process (e.g., applying pressure at a temperature of 150-200°C), thereby fixing the silicon bridge chip 30 to the surface of the first glass temporary carrier 10a, with the silicon bridge chip 30 and the previously formed conductive pillars 20 arranged at intervals.

[0043] Compared to the complex approach of precisely etching grooves on a silicon substrate and then embedding a silicon bridge, this application simplifies the process by using surface mounting, reducing reliance on complex micro-machining of the carrier board, thereby helping to reduce manufacturing costs and improve process compatibility. Meanwhile, the chip bonding film 301 itself has a certain degree of elasticity, which can act as a stress buffer between the silicon bridge chip 30 and the first glass temporary carrier 10a.

[0044] In some embodiments, such as Figure 5As shown, step S40 forms a first molding layer 61 encapsulating the conductive pillar 20 and the silicon bridge chip 30, specifically including: A molding compound is used to fill the gaps between the silicon bridge chip 30 and the plurality of conductive pillars 20 to form a first molding layer 61 covering the conductive pillars 20 and the silicon bridge chip 30. The first molding layer 61 is ground to expose at least one end of the conductive post 20 away from the first glass temporary carrier 10a.

[0045] Specifically, the first molding compound 61 is formed by injection molding of plastic, and completely encapsulates the sidewalls of the conductive pillar 20 and the sides and back of the silicon bridge chip 30. The first molding compound 61 is then polished to expose the end of the conductive pillar 20 away from the first glass temporary carrier 10a, facilitating electrical connection with the first redistribution layer 51. The thickness of the polished first molding compound 61 can be controlled within the range of 30μm-150μm, for example, 30μm, 50μm, 100μm, 130μm, 150μm, etc. This thickness range aims to balance mechanical protection with the overall package thickness. A thickness greater than 30μm ensures that the first molding compound 61 provides reliable mechanical support and stress buffering for the silicon bridge chip 30; while controlling the upper limit within 150μm helps control the overall package thickness, meeting the requirements for thinner and lighter electronic devices.

[0046] For example, a first temporary glass substrate 10a, with the conductive pillars 20 and silicon bridge chip 30 already mounted, is placed into an injection mold. A low-stress, high-flow epoxy molding compound is selected as the material for the first encapsulation layer 61. Molten epoxy molding compound is injected into the mold cavity under high temperature and pressure, fully filling all gaps between the conductive pillars 20, around the silicon bridge chip 30, and between the conductive pillars 20 and the first temporary glass substrate 10a. Subsequently, the epoxy molding compound is thermosetting to form a dense and robust first encapsulation layer 61, thereby bonding the conductive pillars 20 and silicon bridge chip 30 into a single unit. After curing, the surface of the first encapsulation layer 61 away from the first temporary glass substrate 10a is ground to expose the internal interconnect terminals.

[0047] In this application, the structure formed by the first molding layer 61 encapsulating and fixing the conductive pillar 20 and the silicon bridge chip 30 is also referred to as the molding interconnect core 80.

[0048] The discrete conductive pillars 20 and silicon bridge chips 30 are integrated into a robust molded interconnect core 80 through a molding process, providing reliable mechanical support and protection. The surface of the formed molded interconnect core 80, after grinding, provides a unique and flat process substrate for subsequent fabrication of fine redistribution layers. Furthermore, the epoxy molding compound can absorb and homogenize some of the internal stress, contributing to improved structural reliability.

[0049] In some embodiments, such as Figure 6 As shown, after setting multiple functional chips 40 on the side of the first redistribution layer 51 away from the first glass temporary carrier 10a in step S60 and before removing the first glass temporary carrier 10a, the method for fabricating the semiconductor package structure 100 further includes the following steps: Step S601: A bottom filler layer 401 is provided between the functional chip 40 and the first redistribution layer 51; Step S602: Form a second molding layer 62 that encapsulates multiple functional chips 40.

[0050] Specifically, a dispensing device is used to drip liquid epoxy resin underfill onto the edge of the functional chip 40, using capillary action to fill the entire gap between the bottom of the functional chip 40 and the first redistribution layer 51, and then heats and cures it to form an underfill layer 401.

[0051] Then, a second injection molding process is performed using epoxy molding compound to completely encapsulate the multiple functional chips 40 and the underfill area, forming a second molding layer 62. Afterward, the upper surface of the second molding layer 62 can be ground and thinned to control the total package thickness.

[0052] The main function of the underfill layer 401 is to uniformly disperse the thermal cycling stress caused by the difference in thermal expansion coefficients between the functional chip 40 and the first redistribution layer 51, thereby improving the reliability and fatigue resistance of the flip-chip solder joints. The second molding compound layer 62 provides overall physical protection for the functional chip 40, preventing mechanical damage and environmental impact, and further enhancing the mechanical strength of the package.

[0053] In some embodiments, such as Figure 7 As shown, after the second molding layer 62 is formed in step S602, the method for fabricating the semiconductor package structure 100 further includes the following steps: Step S701: Perform a flipping operation and place the flipped structure on the second glass temporary carrier 10b, so that the surface of the second molding layer 62 away from the silicon bridge chip 30 is connected to the second glass temporary carrier 10b.

[0054] Step S702: Remove the first glass temporary carrier plate 10a.

[0055] Step S703: Remove the seed layer 101 located at the end of the conductive post 20.

[0056] Step S704: Grind the side of the first molding layer 61 away from the functional chip 40 to expose the end of the silicon bridge chip 30 and the end of the conductive post 20, and make the end of the silicon bridge chip 30 and the end of the conductive post 20 flush.

[0057] Step S705: A second wiring layer 52 is formed on the side of the silicon bridge chip 30 away from the functional chip 40. The second wiring layer 52 is electrically connected to the conductive pillar 20 and the silicon bridge chip 30 respectively.

[0058] Step S706: A conductive bump 70 is formed on the side of the second wiring layer 52 away from the functional chip 40.

[0059] Step S707: Remove the second glass temporary carrier plate 10b. Specifically, the entire structure containing the second molding layer 62 is flipped over so that one side of the second molding layer 62 faces down.

[0060] The flipped structure is fixed to the second glass temporary carrier plate 10b through the second temporary bonding layer.

[0061] At this point, the structure is supported by the second glass temporary carrier 10b. The original first glass temporary carrier 10a and temporary bonding adhesive 11 are removed, thereby exposing the original lower surface of the first molding layer 61 (i.e., the surface where the conductive pillars 20 and the bottom surface of the silicon bridge chip 30 are located).

[0062] The exposed surface of the first molding layer 61 is ground to expose the ends of the conductive pillars 20 and the silicon bridge chip 30. That is, after flipping, the lower surface (now facing upward) of the original first molding layer 61 is processed.

[0063] A second redistribution layer 52 is formed on the surface of the first molding layer 61 after grinding. The second redistribution layer 52 is electrically connected to the exposed conductive pillars 20 and the silicon bridge chip 30, respectively.

[0064] Multiple conductive bumps 70 are formed on the second redistribution layer 52.

[0065] Subsequently, the second glass temporary substrate 10b and the second temporary bonding layer are removed to obtain a semiconductor package structure with double-sided interconnects. After removing the first glass temporary substrate 10a, a seed layer 101 is attached to the end of the conductive pillar 20. The seed layer 101 is removed by wet etching or dry etching to expose the end face of the conductive pillar 20. Then, the side of the first molding layer 61 away from the functional chip 40 is polished so that the electrical connection terminal of the silicon bridge chip 30 is flush with the end of the conductive pillar 20, forming a flat surface, which facilitates the fabrication of the second redistribution layer 52.

[0066] In this application, for the sake of consistency, the side where the functional chip 40 is located is defined as the "upper side" or "top", and the side where the conductive bump 70 is located is defined as the "lower side" or "bottom". In the description of process steps, unless otherwise specified, "upper", "lower", "top", and "bottom" all refer to this definition.

[0067] The silicon bridge chip 30 is a chip with through-silicon vias (TSVs), and its upper and lower surfaces are provided with metal bumps for electrical connection with the first rewiring layer 51 and the second rewiring layer 52, as well as interconnection between functional chips. By fabricating the first rewiring layer 51 and the second rewiring layer 52 on both sides of the plastic-encapsulated interconnect core 80, the final semiconductor package structure 100 has two sets of high-density input / output systems at the top and bottom, improving I / O density and wiring design flexibility.

[0068] In some embodiments, the method for fabricating the semiconductor package structure 100 may further include integrating passive devices. For example, in step S30, passive devices such as resistors and capacitors may be mounted on specific positions on a glass temporary carrier and encapsulated together with the silicon bridge chip 30 while the silicon bridge chip 30 is being fabricated. These passive devices may also be electrically connected to the functional chip 40 through the first redistribution layer 51 to optimize system performance.

[0069] In the embodiments of this application, glass is chosen as the temporary carrier plate not only for its high flatness but also for its compatibility with subsequent processes: First, the low and adjustable coefficient of linear expansion (CTE) of glass, for example, can be adjusted to be close to that of silicon or commonly used molding compounds through material ratios, which helps reduce thermal mismatch stress between the glass and the chip or molding compound; second, its excellent chemical inertness ensures its stability in subsequent wet cleaning, electroplating, and other processes; and third, its good light transmittance facilitates optical alignment and inspection during the process. Specifically, soda-lime glass, borosilicate glass, or low-CTE glass specifically developed for advanced packaging can be used.

[0070] Some embodiments of this application also provide a semiconductor package structure 100, which can be prepared by the above-described semiconductor package structure preparation method.

[0071] like Figure 3 As shown, the semiconductor package structure 100 includes at least one silicon bridge chip 30 and a plurality of conductive pillars 20, and a first molding compound 61 encapsulating the conductive pillars 20 and the silicon bridge chip 30. The silicon bridge chip 30 and the conductive pillars 20 are spaced apart on the plane of a glass temporary carrier so that the material of the first molding compound 61 can fill the spaced spaces therein. The semiconductor package structure 100 also includes a first redistribution layer 51 and a plurality of functional chips 40. The first redistribution layer 51 is disposed on one side of the first molding compound 61 and is electrically connected to the conductive pillars 20 and the silicon bridge chip 30, respectively. The plurality of functional chips 40 are disposed on the side of the first redistribution layer 51 away from the first molding compound 61 and are electrically connected to the first redistribution layer 51.

[0072] Specifically, multiple conductive pillars 20 and at least one silicon bridge chip 30 are arranged at intervals and completely embedded in the first molding layer 61, which constitutes a support carrier for the conductive pillars 20 and the silicon bridge chip 30.

[0073] A first super-wiring layer 51 is provided on one side of the first molding layer 61. The first super-wiring layer 51 is electrically connected to the end of the conductive pillar 20 and the electrical connection structure on the silicon bridge chip 30 through its internal metal lines and contact holes.

[0074] On the side of the first wiring layer 51 away from the first molding compound layer 61, multiple functional chips 40 are flip-chip connected via solder joints. The functional chips 40 may include logic chips and memory chips. The functional chips 40 are electrically connected to the first wiring layer 51. The semiconductor package structure 100 may also include an underfill layer 401 located beneath the functional chips 40 and a second molding compound layer 62 encapsulating the functional chips 40.

[0075] The semiconductor package structure 100 provided in this application embodiment forms a plastic-encapsulated interconnect core 80 by encapsulating conductive pillars 20 and silicon bridge chips 30 with a first plastic encapsulation layer 61. Compared with traditional structures using silicon interposers or pre-fabricated RDL layers as the core carrier, the semiconductor package structure 100 of this application has better anti-warpage structural stability and better thermal expansion coefficient matching between the plastic encapsulation layer material and subsequent organic materials (such as RDL dielectric layers), which helps to reduce interlayer thermal stress. This semiconductor package structure 100 is prepared by the aforementioned first-core-then-wiring method, providing a more reliable carrier solution for high-density interconnects.

[0076] In some embodiments, the semiconductor package structure 100 further includes a second rewiring layer 52 and conductive bumps 70. The second rewiring layer 52 is disposed on the side of the silicon bridge chip 30 away from the functional chip 40, and the conductive bumps 70 are disposed on the side of the second rewiring layer 52 away from the functional chip 40.

[0077] Specifically, the conductive bumps 70 are, for example, solder balls. Multiple conductive bumps 70 are typically arranged in a grid array to form the external electrical interface of the package, which is used to finally solder the entire package structure onto the printed circuit board (PCB).

[0078] By providing a first rewiring layer 51, a second rewiring layer 52, and conductive bumps 70 on both sides of the plastic-encapsulated interconnect core 80 for external electrical connection, the plastic-encapsulated interconnect core 80 achieves high-density input / output capabilities on both sides, helping to achieve higher input / output pin density within a limited planar area. The use of conductive bumps 70 facilitates the integration of the semiconductor package structure 100 onto the system board via surface mount technology.

[0079] For example, the arrangement of multiple conductive pillars 20 is not limited to a uniform array. They can be arranged differently according to the distribution requirements of power supply, ground wire and signal line. For example, the density or diameter of conductive pillars 20 can be increased in areas where a large current supply is required.

[0080] For example, the number and location of at least one silicon bridge chip 30 can be flexibly set according to the interconnection requirements of the functional chips 40. Multiple silicon bridge chips 30 can be set up to be responsible for high-speed interconnection between different pairs of functional chips 40, realizing a modular and partitioned interconnection network.

[0081] For example, the number of layers in the first rewiring layer 51 and / or the second rewiring layer 52 can be adjusted according to the interconnect complexity and the number of I / Os, such as using a 2-layer, 4-layer or more wiring structure. Embedded passive devices, such as thin-film resistors or metal-insulator-metal capacitors fabricated using high-precision thin-film processes, can be integrated into the rewiring layer to further reduce the package area and improve electrical performance.

[0082] In addition, the conductive bump 70 is not limited to C4 solder balls, but can also be copper pillar bumps, micro bumps or combinations thereof, to accommodate different package pitches and reliability requirements.

[0083] In some embodiments, such as Figure 8 As shown, the functional chip 40 includes a first chip 41 and a second chip 42. The first chip 41 and the second chip 42 are electrically connected to the silicon bridge chip 30, and the first chip 41 and the second chip 42 are electrically connected to each other through the silicon bridge chip 30.

[0084] Different functional chips 40 can be interconnected via silicon bridges. Functional chips 40 include a first chip 41 and a second chip 42; for example, one of the first chip 41 and the second chip 42 may be a processor chip, and the other a high-bandwidth memory chip. The first chip 41 and the second chip 42 are placed spatially adjacent to each other. Both the first chip 41 and the second chip 42 have multiple input / output ports that require high-speed communication with each other. These high-speed interconnect ports are preferably connected directly to the corresponding interconnect areas on the upper surface of the lower silicon bridge chip 30 via bottom bumps, rather than via redistribution layers. High-density metal interconnects are pre-fabricated inside the silicon bridge chip 30, which can directly connect specific ports of the first chip 41 to corresponding ports of the second chip 42.

[0085] The high-speed interconnect between the first chip 41 and the second chip 42 is directly achieved through wiring within the silicon bridge chip 30. Compared to the path via the package-level redistribution layer, this method shortens the interconnect length, which helps reduce signal transmission delay and power consumption, thereby increasing the communication bandwidth between functional chips.

[0086] In other embodiments, such as Figure 3As shown, the functional chip 40 also includes a third chip 43, and the number of silicon bridge chips 30 can be configured to be two. Specifically, the first chip 41 and the second chip 42 are electrically connected via one silicon bridge chip 30, while the second chip 42 and the third chip 43 are electrically connected via another silicon bridge chip 30. This configuration allows for the construction of more complex point-to-point or mesh interconnect topologies, such as implementing a parallel high-speed data channel between a central processing unit and two adjacent high-bandwidth memory modules. Of course, depending on the system architecture requirements, the number of silicon bridge chips 30 can be further increased, for example, to three, four, or more. Each silicon bridge chip 30 can be responsible for connecting one or more specific functional chips 40, thereby modularizing and distributing the interconnect network within the package. This application does not limit the specific number of silicon bridge chips 30 and their connection relationship with the functional chips 40; those skilled in the art can flexibly configure them according to actual bandwidth, latency, and power consumption specifications.

[0087] In summary, the semiconductor packaging structure and its fabrication method provided in this application, through the synergistic design of a glass temporary carrier and a specific process sequence of first solidifying the core and then wiring, bring about multiple technical benefits: High-rigidity, low-CTE glass substrates provide a stable initial platform, while the process of first molding the interconnect core places the fabrication of the deformable RDL after a solid substrate, thus suppressing warpage from both the source and the process.

[0088] Conductive pillars with smaller diameters and higher aspect ratios (electroplated copper pillars) can be fabricated on ultra-flat glass surfaces using semiconductor photolithography and electroplating processes, breaking through the size limitations of TMV; at the same time, the stable substrate makes it possible to fabricate ultra-fine redistribution layers with smaller line widths and spacings.

[0089] Using a glass temporary carrier that is eventually removed avoids the high cost of a permanent silicon carrier; surface-mount silicon bridges replace silicon etched grooves, simplifying the process; and decoupling stress paths is also expected to improve overall process yield and reduce overall manufacturing costs.

[0090] The plastic-encapsulated interconnect core provides robust mechanical support; the double-sided redistribution layer design greatly improves I / O density and layout freedom; and the silicon bridge chip provides the shortest and most efficient high-speed interconnect path between functional chips.

[0091] Some embodiments of this application also provide an electronic device. This electronic device includes the semiconductor package structure 100 provided in any of the above embodiments.

[0092] The semiconductor packaging structure 100 of this application embodiment is applicable to a variety of high-performance electronic devices. For example, in the field of artificial intelligence (AI) computing, the semiconductor packaging structure can provide an extremely short-distance, ultra-high bandwidth interconnect between the AI ​​processor and high-bandwidth memory (HBM) through the silicon bridge chip 30, meeting its stringent requirements for computing power and data throughput. In the field of radio frequency communication, the low dielectric loss characteristics of glass make it suitable as a carrier for radio frequency front-end modules; its structure supports the integration of embedded waveguides, and the three-dimensional stacking scheme helps to integrate high-frequency chips with low-loss interconnects, providing solutions for large-scale antenna arrays to meet the challenges of data rates exceeding 100GHz in future 6G communications. In addition, the excellent insulation, thermal stability, and surface flatness of the glass substrate enable it to provide precise mechanical support and a good electrical isolation environment for microelectromechanical systems (MEMS) devices (such as miniature mass spectrometers and inertial sensors), helping to reduce parasitic effects and improve device performance.

[0093] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0094] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the inventive concept, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for fabricating a semiconductor packaging structure, characterized in that, include: Provide the first glass temporary carrier plate; Multiple conductive pillars are formed on the first glass temporary carrier plate; At least one silicon bridge chip is disposed on the first glass temporary carrier, and the silicon bridge chip is arranged at intervals with the conductive pillar; A first molding layer is formed to encapsulate the conductive pillars and the silicon bridge chip; A first redistribution layer is formed on the side of the first molding layer away from the first glass temporary carrier, and the first redistribution layer is electrically connected to the conductive pillar and the silicon bridge chip respectively. Multiple functional chips are disposed on the side of the first rewiring layer away from the first glass temporary carrier, and the functional chips are electrically connected to the first rewiring layer. Remove the first glass temporary carrier plate.

2. The method for fabricating a semiconductor packaging structure according to claim 1, characterized in that, The formation of multiple conductive pillars on the first glass temporary carrier includes: A seed layer and a patterned photoresist layer are sequentially formed on the first glass temporary carrier, wherein the photoresist layer has through holes that expose a portion of the seed layer; The conductive pillar is formed by filling the through hole with conductive material through an electroplating process; Remove the photoresist layer.

3. The method for fabricating a semiconductor packaging structure according to claim 1, characterized in that, The formation of the first molding layer encapsulating the conductive pillars and the silicon bridge chip includes: A molding compound is used to fill the gaps between the silicon bridge chip and the plurality of conductive pillars to form a first molding layer covering the conductive pillars and the silicon bridge chip; The first molding layer is ground to expose at least one end of the conductive pillar away from the first glass temporary carrier. Preferably, the thickness of the first molding layer after grinding is 30μm-150μm.

4. The method for preparing a semiconductor packaging structure according to claim 1, characterized in that, After setting multiple functional chips on the side of the first redistribution layer away from the first glass temporary carrier, and before removing the first glass temporary carrier, the method further includes: An underfill layer is provided between the functional chip and the first redistribution layer; A second molding compound is formed to encapsulate multiple of the aforementioned functional chips.

5. The method for preparing a semiconductor packaging structure according to claim 4, characterized in that, After forming the second molding layer, the process also includes: Perform a flipping operation to connect the surface of the second molding layer away from the silicon bridge chip to the second glass temporary carrier. Remove the first glass temporary carrier plate.

6. The method for fabricating a semiconductor packaging structure according to claim 5, characterized in that, After performing the flipping operation, the following is also included: The side of the first molding layer away from the functional chip is ground to expose the ends of the silicon bridge chip and the conductive pillar; A second wiring layer is formed on the side of the silicon bridge chip away from the functional chip, and the second wiring layer is electrically connected to the conductive pillar and the silicon bridge chip respectively; Conductive bumps are formed on the side of the second redistribution layer away from the functional chip; Preferably, after removing the first temporary glass carrier plate, the method further includes: Remove the seed layer located at the end of the conductive post; The side of the first molding layer away from the functional chip is ground to expose the ends of the silicon bridge chip and the conductive pillars, and the ends of the silicon bridge chip are made flush with the ends of the conductive pillars.

7. The method for fabricating a semiconductor packaging structure according to claim 6, characterized in that, After forming the second redistribution layer and the conductive bumps, the method further includes: Remove the second glass temporary carrier plate.

8. A semiconductor packaging structure, characterized in that, include: At least one silicon bridge chip and a plurality of conductive pillars, wherein the silicon bridge chip and the conductive pillars are arranged at intervals; A first molding layer encapsulates the conductive pillars and the silicon bridge chip. A first wiring layer is disposed on one side of the first molding layer, and the first wiring layer is electrically connected to the conductive pillar and the silicon bridge chip respectively; Multiple functional chips are disposed on the side of the first wiring layer away from the first molding layer, and the functional chips are electrically connected to the first wiring layer; The first redistribution layer and the functional chip are located on the same side of the first molding layer.

9. The semiconductor packaging structure according to claim 8, characterized in that, Also includes: The second wiring layer is disposed on the side of the silicon bridge chip away from the functional chip; Preferably, the semiconductor packaging structure further includes conductive bumps, which are disposed on the side of the second redistribution layer away from the functional chip; Preferably, the semiconductor packaging structure further includes an underfill layer and a second molding compound layer, wherein the underfill layer is filled between the functional chip and the first redistribution layer, and the second molding compound layer encapsulates a plurality of the functional chips.

10. An electronic device, characterized in that, The semiconductor package structure includes the semiconductor package structure prepared by any one of claims 1 to 7, or the semiconductor package structure as described in claim 8 or 9.

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