Display screen and method for improving fitting accuracy of TFT LCD (Thin Film Transistor Liquid Crystal Display) screen

Abstract

The invention discloses a display screen and method for improving the fitting accuracy of a TFT LCD (Thin Film Transistor Liquid Crystal Display) display screen, the display screen comprises an Array large board and a CF large board arranged above the Array large board, a data line metal layer of the Array large board is provided with an SD coarse alignment mark and an SD fine alignment mark, a scanning line metal layer of the Array large board is provided with a Gate coarse alignment mark and a Gate fine alignment mark, and the scanning line metal layer of the Array large board is provided with the SD coarse alignment mark and the SD fine alignment mark. A BM layer of the CF large board is provided with a CF first rough fitting label, a CF first fine fitting label, a CF second rough fitting label and a CF second fine fitting label, and the positions and the sizes of the CF first rough fitting label, the CF first fine fitting label, the CF second rough fitting label and the CF second fine fitting label correspond to the positions and the sizes of the SD rough alignment label, the SD fine alignment label, the Gate rough alignment label and the Gate fine alignment label respectively. Different coarse alignment marks and fine alignment marks can be recognized and grabbed according to different structures, so that an Array substrate and a CF substrate in a conventional structure and a Triple Gate structure can be well aligned, display abnormity caused by deviation is reduced, and the yield is increased.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically, to a display screen and method for improving the bonding accuracy of a TFT LCD display screen. Background Technology

[0002] The array substrate and the CF substrate are the core structures of a TFT LCD display. The accuracy of their bonding directly affects the display performance; significant bonding misalignment can lead to display abnormalities. Both the array substrate and the CF substrate have patterns composed of various film layers. During the manufacturing process of the array substrate, each film layer is typically aligned and assembled using the scan line metal layer 2', while the CF substrate layers are aligned and assembled using the BM layer 4'. The bonding of the array substrate and the CF substrate involves coarse and fine alignment of the patterns on the scan line metal layer 2' and the BM layer 4', followed by bonding, and the alignment accuracy is determined by reading the alignment on the scan line metal layer 2' and the BM layer 4'.

[0003] The bonding of the array substrate and the CF substrate can result in misalignment in various directions. The misalignment perpendicular to the long side of the RGB pixel ink 3' has the greatest impact on the display and is the most sensitive, most likely to cause display abnormalities. In conventional structures, the metal layer along the long side of the RGB pixel ink 3' is the data line metal layer 1', while in the Triple Gate structure it is the scan line metal layer 2', as shown in the attached diagram. Figure 1 and attached Figure 2 As shown in the figure, the three boxes represent the approximate shape of the RGB pixel ink 3'. It can be seen from the figure that the misalignment between the metal layer and the BM film layer along the long side of the RGB pixel has the greatest impact on the pixel opening; their alignment most easily affects the display of the RGB pixel.

[0004] In summary, although the Triple Gate structure uses the scan line metal layer 2' as a positioning marker to accurately reflect the bonding of pixels in the display area, the conventional structure cannot fully reflect the bonding of pixels in the display area when using the scan line metal layer 2' as a positioning marker for alignment. Summary of the Invention

[0005] The technical problem to be solved by this invention is how to achieve good alignment between the Array substrate and the CF substrate in both conventional and Triple Gate structures. This not only improves the bonding accuracy of the TFT LCD display, but also allows for clearer and more intuitive observation of the bonding status of the two substrates. This facilitates adjustments to the bonding status and the identification of defective products, thereby reducing display abnormalities caused by misalignment between the Array substrate and the CF substrate and improving the yield rate.

[0006] The technical problem to be solved by the present invention is achieved through the following technical solution: To address the aforementioned technical problems, this invention provides a display screen for improving the bonding accuracy of a TFT LCD display screen. The display screen includes an array panel and a CF panel disposed above the array panel. The data line metal layer of the array panel has an SD coarse alignment mark and an SD fine alignment mark. The scan line metal layer of the array panel has a Gate coarse alignment mark and a Gate fine alignment mark. The BM layer of the CF panel has a CF first coarse bonding mark, a CF first fine bonding mark, a CF second coarse bonding mark, and a CF second fine bonding mark. The positions and dimensions of the CF first coarse bonding mark, the CF first fine bonding mark, the CF second coarse bonding mark, and the CF second fine bonding mark correspond to the positions and dimensions of the SD coarse alignment mark, the SD fine alignment mark, the Gate coarse alignment mark, and the Gate fine alignment mark, respectively.

[0007] As a preferred embodiment of the display screen for improving the bonding accuracy of the TFT LCD display screen provided by the present invention, the SD coarse alignment mark, SD fine alignment mark, Gate coarse alignment mark and Gate fine alignment mark are combined to form a first alignment mark group, and the CF first coarse bonding mark, CF first fine bonding mark, CF second coarse bonding mark and CF second fine bonding mark are combined to form a second alignment mark group. There are multiple first alignment mark groups and they are respectively set at the top corner of the Array board. There are multiple second alignment mark groups and they are respectively set at the top corner of the CF board.

[0008] In a preferred embodiment of the display screen for improving the bonding accuracy of the TFT LCD display screen provided by the present invention, the SD coarse alignment mark, SD fine alignment mark, Gate coarse alignment mark, and Gate fine alignment mark are arranged sequentially from left to right, and the CF first coarse bonding mark, CF first fine bonding mark, CF second coarse bonding mark, and CF second fine bonding mark are arranged sequentially from left to right.

[0009] As a preferred embodiment of the display screen for improving the bonding accuracy of the TFT LCD display screen provided by the present invention, the SD coarse alignment mark, SD fine alignment mark, Gate coarse alignment mark, and Gate fine alignment mark are all frame-shaped, and the CF first coarse bonding mark, CF first fine bonding mark, CF second coarse bonding mark, and CF second fine bonding mark are all square-shaped.

[0010] In a preferred embodiment of the display screen provided by the present invention for improving the bonding accuracy of the TFT LCD display screen, the CF first coarse bonding mark, the CF first fine bonding mark, the CF second coarse bonding mark and the CF second fine bonding mark are respectively aligned with the center of the SD coarse alignment mark, the SD fine alignment mark, the Gate coarse alignment mark and the Gate fine alignment mark.

[0011] In a preferred embodiment of the display screen for improving the bonding accuracy of the TFT LCD display screen provided by the present invention, the sizes of the SD coarse alignment mark and the Gate coarse alignment mark are both larger than the sizes of the SD fine alignment mark and the Gate fine alignment mark.

[0012] As a preferred embodiment of the display screen for improving the bonding accuracy of the TFT LCD display screen provided by the present invention, the Array large board includes a plurality of TFT chips arranged in sequence, and the CF large board includes a plurality of CF chips arranged in sequence. The shape and position of each TFT chip and each CF chip are corresponding. An SD alignment ruler is provided on the data line metal layer of each TFT chip, and a Gate alignment ruler is provided on the scan line metal layer of each TFT chip. A CF first alignment ruler and a CF second alignment ruler are provided on the BM layer of each CF chip. The size and shape of the CF first alignment ruler correspond to the size and shape of the SD alignment ruler, and the size and shape of the CF second alignment ruler correspond to the size and shape of the Gate alignment ruler.

[0013] As a preferred embodiment of the display screen for improving the bonding accuracy of the TFT LCD display screen provided by the present invention, the Array board or CF board is provided with a misalignment degree alignment scale.

[0014] As a preferred embodiment of the display screen for improving the bonding accuracy of the TFT LCD display screen provided by the present invention, the misalignment degree alignment scale includes multiple misalignment degree graphics, which are arranged sequentially from left to right and each misalignment degree graphic is set with a different number below it to indicate the degree of misalignment.

[0015] A method for improving the bonding accuracy of a TFT LCD display screen, characterized in that it includes the display screen described above for improving the bonding accuracy of a TFT LCD display screen, and includes the following steps: Step 1: Confirm whether the product being manufactured is a conventional structure or a Triple Gate structure. If the product is a conventional structure, execute steps 1.1 and 2.1 in sequence. If the product is a Triple Gate structure, execute steps 1.2 and 2.2 in sequence. Step 1.1: The product has a conventional structure. The camera first captures the SD coarse alignment mark and the CF first coarse bonding mark for coarse positioning, and then captures the SD fine alignment mark and the CF first fine bonding mark for fine positioning, and then bonding the Array board and the CF board together. Step 1.2: The product is a Triple Gate structure. The camera first captures the Gate coarse alignment mark and the CF second coarse bonding mark for coarse positioning, and then captures the Gate fine alignment mark and the CF second fine bonding mark for fine positioning, and then bonding the Array board and the CF board together. Step 2.1: The product has a conventional structure. The camera captures the SD alignment scale on the TFT chip and the CF first alignment scale on the BM layer of the CF chip. The degree of misalignment of the SD alignment scale and the CF first alignment scale is used to determine the degree of offset between the TFT chip and the CF chip. Step 2.2: The product has a Triple Gate structure. The camera captures the Gate alignment scale on the TFT chip and the second CF alignment scale on the BM layer of the CF chip. The degree of misalignment between the Gate alignment scale and the second CF alignment scale is used to determine the degree of offset between the TFT chip and the CF chip.

[0016] The present invention has the following beneficial effects: Traditional solutions only create coarse and fine alignment marks on the scan line metal layer. This invention, however, not only sets coarse and fine SD alignment marks on the data line metal layer, but also coarse and fine Gate alignment marks on the scan line metal layer. During production, it is first determined whether the product being manufactured has a conventional structure or a Triple Gate structure. When the product has a conventional structure, the camera first captures the coarse SD alignment mark for coarse positioning, then captures the fine SD alignment mark for fine positioning, and then attaches the Array board and CF board. In this case, the coarse and fine Gate alignment marks on the scan line metal layer are not used. When the product has a Triple Gate structure, the camera first captures the coarse Gate alignment mark for coarse positioning, then captures the fine Gate alignment mark for fine positioning, and then attaches the Array board and CF board. In this case, the coarse and fine SD alignment marks on the data line metal layer are not used. Therefore, different coarse and fine alignment marks can be identified and captured for different structures, so that the array substrate and CF substrate can be well aligned in both conventional and Triple Gate structures. This not only improves the bonding accuracy of the TFT LCD display, but also allows for clearer and more intuitive observation of the bonding of the two substrates, so as to adjust the bonding and identify defective products. This reduces display abnormalities caused by misalignment between the array substrate and CF substrate, thereby improving the yield rate. Attached Figure Description

[0017] To more clearly illustrate the solutions in this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the stacked structure of the display screen in a conventional structure.

[0019] Figure 2 This is a schematic diagram of the stacked structure of the display screens in the Triple Gate structure.

[0020] Figure 3 This invention provides a schematic diagram of the structure of an array board for improving the bonding accuracy of a TFT LCD display.

[0021] Figure 4 for Figure 3 Enlarged view of point A in the middle.

[0022] Figure 5 This invention provides a schematic diagram of the structure of a CF board for a display screen that improves the bonding accuracy of a TFT LCD display screen.

[0023] Figure 6 for Figure 5 Enlarged view of point B in the middle.

[0024] Figure 7 This is a schematic diagram of the alignment of the array board and the CF board of a display screen, which is provided by the present invention to improve the bonding accuracy of a TFT LCD display screen.

[0025] Figure 8 for Figure 7 Enlarged view of point C in the image.

[0026] Figure 9 This is a schematic diagram of the SD alignment scale or Gate alignment scale.

[0027] Figure 10 This is a structural diagram of the first alignment scale or the second alignment scale of the CF.

[0028] Figure 11 This is a schematic diagram showing the actual shapes of two alignment scales and their overlapping structure.

[0029] Explanation of icon numbers: Data line metal layer 1'; scan line metal layer 2'; RGB pixel ink 3'; BM layer 4'; Array board 1; CF board 2; SD coarse alignment mark 11; SD fine alignment mark 12; Gate coarse alignment mark 13; Gate fine alignment mark 14; CF first coarse bonding mark 21; CF first fine bonding mark 22; CF second coarse bonding mark 23; CF second fine bonding mark 24; TFT chip 3; CF chip 4; SD alignment ruler 31; Gate alignment ruler 32; CF first alignment ruler 41; CF second alignment ruler 42. Detailed Implementation

[0030] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0031] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0032] Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0033] This invention provides a display screen for improving the bonding accuracy of a TFT LCD display screen, comprising an array panel and a CF panel disposed above the array panel. The data line metal layer of the array panel is provided with SD coarse alignment marks and SD fine alignment marks. The scan line metal layer of the array panel is provided with Gate coarse alignment marks and Gate fine alignment marks. The BM layer of the CF panel is provided with CF first coarse bonding mark, CF first fine bonding mark, CF second coarse bonding mark, and CF second fine bonding mark. The positions and dimensions of the CF first coarse bonding mark, CF first fine bonding mark, CF second coarse bonding mark, and CF second fine bonding mark correspond to the positions and dimensions of the SD coarse alignment mark, SD fine alignment mark, Gate coarse alignment mark, and Gate fine alignment mark, respectively.

[0034] Traditional solutions only create coarse and fine alignment marks on the scan line metal layer. This invention, however, not only sets coarse and fine SD alignment marks on the data line metal layer, but also coarse and fine Gate alignment marks on the scan line metal layer. During production, it is first determined whether the product being manufactured has a conventional structure or a Triple Gate structure. When the product has a conventional structure, the camera first captures the coarse SD alignment mark for coarse positioning, then captures the fine SD alignment mark for fine positioning, and then attaches the Array board and CF board. In this case, the coarse and fine Gate alignment marks on the scan line metal layer are not used. When the product has a Triple Gate structure, the camera first captures the coarse Gate alignment mark for coarse positioning, then captures the fine Gate alignment mark for fine positioning, and then attaches the Array board and CF board. In this case, the coarse and fine SD alignment marks on the data line metal layer are not used. Therefore, different coarse and fine alignment marks can be identified and captured for different structures, so that the array substrate and CF substrate can be well aligned in both conventional and Triple Gate structures. This not only improves the bonding accuracy of the TFT LCD display, but also allows for clearer and more intuitive observation of the bonding of the two substrates, so as to adjust the bonding and identify defective products. This reduces display abnormalities caused by misalignment between the array substrate and CF substrate, thereby improving the yield rate.

[0035] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. The present invention will be described in detail below with reference to the accompanying drawings and embodiments, examples of which are shown in the drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0036] Example 1, please refer to Figures 3 to 8 The present invention provides a display screen for improving the bonding accuracy of a TFT LCD display screen, comprising an array panel 1 and a CF panel 2 disposed above the array panel 1. The data line metal layer of the array panel 1 is provided with an SD coarse alignment mark 11 and an SD fine alignment mark 12. The scan line metal layer of the array panel 1 is provided with a Gate coarse alignment mark 13 and a Gate fine alignment mark 14. The BM layer of the CF panel 2 is provided with a CF first coarse bonding mark 21, a CF first fine bonding mark 22, a CF second coarse bonding mark 23, and a CF second fine bonding mark 24. The positions and dimensions of the CF first coarse bonding mark 21, the CF first fine bonding mark 22, the CF second coarse bonding mark 23, and the CF second fine bonding mark 24 correspond to the positions and dimensions of the SD coarse alignment mark 11, the SD fine alignment mark 12, the Gate coarse alignment mark 13, and the Gate fine alignment mark 14, respectively.

[0037] Traditional solutions only create coarse and fine alignment marks on the scan line metal layer. This invention, however, not only sets SD coarse alignment mark 11 and SD fine alignment mark 12 on the data line metal layer, but also sets Gate coarse alignment mark 13 and Gate fine alignment mark 14 on the scan line metal layer. During production, it is first determined whether the product being manufactured has a conventional structure or a Triple Gate structure. When the product has a conventional structure, the camera first captures the SD coarse alignment mark 11 for coarse positioning, then captures the SD fine alignment mark 12 for fine positioning, and then attaches the Array board 1 and CF board 2. In this case, the Gate coarse alignment mark 13 and Gate fine alignment mark 14 set on the scan line metal layer are not used. When the product has a Triple Gate structure, the camera first captures the Gate coarse alignment mark 13 for coarse positioning, then captures the Gate fine alignment mark 14 for fine positioning, and then attaches the Array board 1 and CF board 2. In this case, the SD coarse alignment mark 11 and SD fine alignment mark 12 set on the data line metal layer are not used. Therefore, different coarse and fine alignment marks can be identified and captured for different structures, so that the array substrate and CF substrate can be well aligned in both conventional and Triple Gate structures. This not only improves the bonding accuracy of the TFT LCD display, but also allows for clearer and more intuitive observation of the bonding of the two substrates, so as to adjust the bonding and identify defective products. This reduces display abnormalities caused by misalignment between the array substrate and CF substrate, thereby improving the yield rate.

[0038] The main reason for using coarse and fine alignment markers is that the coarse alignment marker corresponds to a lens with a relatively low magnification, which allows for rapid focusing and coarse positioning. However, this type of lens has a wide recognition range, resulting in insufficient positional information. Then, a lens with a higher magnification is used to capture the fine alignment marker for precise positioning. In other words, the approximate position of the board is first determined using the coarse alignment marker, and then the more accurate positional information is determined using the fine alignment marker.

[0039] Furthermore, the SD coarse alignment marker 11, SD fine alignment marker 12, Gate coarse alignment marker 13, and Gate fine alignment marker 14 are combined to form the first alignment marker group, and the CF first coarse bonding marker 21, CF first fine bonding marker 22, CF second coarse bonding marker 23, and CF second fine bonding marker 24 are combined to form the second alignment marker group. There are multiple first alignment marker groups, each located at the top corner of the Array board 1, and multiple second alignment marker groups, each located at the top corner of the CF board 2. The SD coarse alignment marker 11, SD fine alignment marker 12, Gate coarse alignment marker 13, and Gate fine alignment marker 14 are set sequentially from left to right, and the CF first coarse bonding marker 21, CF first fine bonding marker 22, CF second coarse bonding marker 23, and CF second fine bonding marker 24 are set sequentially from left to right. During production, the first pair of positioning labels and the second pair of positioning labels can be produced in batches at the four corners of Array board 1 and CF board 2.

[0040] Furthermore, the shapes of SD coarse alignment mark 11, SD fine alignment mark 12, Gate coarse alignment mark 13, and Gate fine alignment mark 14 are all frame-shaped, while the shapes of CF first coarse alignment mark 21, CF first fine alignment mark 22, CF second coarse alignment mark 23, and CF second fine alignment mark 24 are all square-shaped. The CF first coarse alignment mark 21, CF first fine alignment mark 22, CF second coarse alignment mark 23, and CF second fine alignment mark 24 are center-aligned with SD coarse alignment mark 11, SD fine alignment mark 12, Gate coarse alignment mark 13, and Gate fine alignment mark 14. That is, CF first coarse alignment mark 21 is center-aligned with SD coarse alignment mark 11, CF first fine alignment mark 22 is center-aligned with SD fine alignment mark 12, CF second coarse alignment mark 23 is center-aligned with Gate coarse alignment mark 13, and CF second fine alignment mark 24 is center-aligned with Gate fine alignment mark 14. Of course, other shapes can be chosen in other embodiments, which allows for quick detection of alignment misalignment between the Array substrate and the CF substrate during alignment. This avoids alignment deviations between the Gate layer and the SD layer, resulting in more accurate bonding and reducing the risk of display abnormalities caused by alignment misalignment.

[0041] Both sets of bonding labels on CF plate 2 are designed using BM film layers and are square, only differing in size. When bonding Array plate 1 and CF plate 2, it is sufficient to ensure that the center of the bonding label on the corresponding film layer on Array plate 1 is aligned with the center of the bonding label on CF plate 2.

[0042] After the camera captures the first and second alignment groups, the device moves the substrate to the position set by the device, and then attaches the Array substrate and CF substrate in a fixed position. The first and second alignment groups are generally located at the four corners of the large board.

[0043] Furthermore, the dimensions of SD coarse alignment marker 11 and Gate coarse alignment marker 13 are both larger than the dimensions of SD fine alignment marker 12 and Gate fine alignment marker 14. In this embodiment, SD coarse alignment marker 11 and Gate coarse alignment marker 13 have the same shape and size and can completely overlap; SD fine alignment marker 12 and Gate fine alignment marker 14 have the same shape and size and can completely overlap.

[0044] Example 2, please refer to Figures 3 to 11 In this embodiment, the Array board 1 includes a plurality of TFT chips 3 arranged in sequence, and the CF board 2 includes a plurality of CF chips 4 arranged in sequence. The shape and position of each TFT chip 3 and each CF chip 4 are corresponding. Each TFT chip 3 has an SD alignment ruler 31 on its data line metal layer and a Gate alignment ruler 32 on its scan line metal layer. The SD alignment ruler 31 corresponds to the data line metal corresponding to the RGB pixel ink in the long direction, and the Gate alignment ruler 32 corresponds to the scan line metal corresponding to the RGB pixel ink in the long direction. The CF chip 4 has a CF first alignment ruler 41 and a CF second alignment ruler 42 on its BM layer. The size and shape of the CF first alignment ruler 41 correspond to the size and shape of the SD alignment ruler 31, and the size and shape of the CF second alignment ruler 42 correspond to the size and shape of the Gate alignment ruler 32.

[0045] In this embodiment, each TFT chip 3 is provided with 4 SD alignment rulers 31 and 4 Gate alignment rulers 32, and the 4 SD alignment rulers 31 and 4 Gate alignment rulers 32 are distributed at the four vertices of the TFT chip 3. Each CF chip 4 is provided with 4 CF first alignment rulers 41 and 4 CF second alignment rulers 42, and the 4 CF first alignment rulers 41 and 4 CF second alignment rulers 42 are distributed at the four vertices of the TFT chip 3.

[0046] More preferably, each SD alignment ruler 31, each Gate alignment ruler 32, each CF first alignment ruler 41 and each CF second alignment ruler 42 are provided with two alignment rulers, including a horizontal alignment ruler and a vertical alignment ruler.

[0047] When the product has a conventional structure, the alignment status of each TFT LCD screen can be read by checking the alignment of the SD alignment ruler 31 and the CF first alignment ruler 41. In this case, the Gate alignment ruler 32 and the CF second alignment ruler 42 set on the scan line metal layer are not used. When the product has a Triple Gate structure, the alignment status of each TFT LCD screen can be read by checking the alignment of the Gate alignment ruler 32 and the CF second alignment ruler 42. In this case, the SD alignment ruler 31 and the CF first alignment ruler 41 set on the data line metal layer are not used. Therefore, different alignment marks can be identified and captured for different structures, so that TFT chip 3 and CF chip 4 can be well aligned in both conventional and Triple Gate structures. This eliminates the need to select and confirm the bonding status of each position on the large board later. It not only improves the bonding accuracy of the TFT LCD display, but also allows for a clearer and more intuitive observation of the bonding status of the two substrates, and facilitates the analysis of defective products. This reduces display abnormalities caused by misalignment between the Array substrate and the CF substrate, thereby improving the yield rate.

[0048] Please see Figures 9 to 11 , Figure 11 The actual shape of the SD alignment ruler 31 and the CF first alignment ruler 41 and their superimposed graphic (where the blank part is the SD alignment ruler 31 and the shaded part is the CF first alignment ruler 41) or the actual shape of the Gate alignment ruler 32 and the CF second alignment ruler 42 and their superimposed graphic (where the blank part is the Gate alignment ruler 32 and the shaded part is the CF second alignment ruler 42) are further defined as follows: the SD alignment ruler 31, the Gate alignment ruler 32, the CF first alignment ruler 41 and the CF second alignment ruler 42 each include multiple offset degree graphics, which are arranged sequentially from left to right and each offset degree graphic is set with a different number below it to indicate the degree of offset.

[0049] More preferably, the multiple misalignment degree graphics are arranged sequentially from left to right in the order of 3, 2, 1, 0, -1, -2, and -3. Of course, more or fewer misalignment degree graphics can be added or removed according to the actual situation to increase or decrease the classification of misalignment degree. In this embodiment, it can be divided into 11 misalignment conditions, namely 5, 4, 3, 2, 1, 0, -1, -2, -3, -4, and -5. By comparing the alignment of the misalignment degree graphics with the alignment of the SD alignment scale 31 and the CF first alignment scale 41 or the Gate alignment scale 32 and the CF second alignment scale 42, the bonding status on each TFT LCD screen can be read. This eliminates the need to select positions on the large board to confirm the bonding status of each position. This not only improves the bonding accuracy of the TFT LCD display, but also allows for a clearer and more intuitive observation of the bonding status of the two substrates, and facilitates the analysis of defective products. This reduces display abnormalities caused by bonding misalignment between the Array substrate and the CF substrate, thereby improving the yield rate.

[0050] This invention provides a method for improving the bonding accuracy of a TFT LCD display screen, characterized in that it includes the display screen described above for improving the bonding accuracy of a TFT LCD display screen, and comprises the following steps: Step 1: Confirm whether the product being manufactured is a conventional structure or a Triple Gate structure. If the product is a conventional structure, execute steps 1.1 and 2.1 in sequence. If the product is a Triple Gate structure, execute steps 1.2 and 2.2 in sequence. Step 1.1: The product has a conventional structure. The camera first captures the SD coarse alignment mark and the CF first coarse bonding mark for coarse positioning, and then captures the SD fine alignment mark and the CF first fine bonding mark for fine positioning, and then bonding the Array board and the CF board together. Step 1.2: The product is a Triple Gate structure. The camera first captures the Gate coarse alignment mark and the CF second coarse bonding mark for coarse positioning, and then captures the Gate fine alignment mark and the CF second fine bonding mark for fine positioning, and then bonding the Array board and the CF board together. Step 2.1: The product has a conventional structure. The camera captures the SD alignment scale on the TFT chip and the CF first alignment scale on the BM layer of the CF chip. The degree of misalignment of the SD alignment scale and the CF first alignment scale is used to determine the degree of offset between the TFT chip and the CF chip. Step 2.2: The product has a Triple Gate structure. The camera captures the Gate alignment scale on the TFT chip and the second CF alignment scale on the BM layer of the CF chip. The degree of misalignment between the Gate alignment scale and the second CF alignment scale is used to determine the degree of offset between the TFT chip and the CF chip.

[0051] Traditional solutions only create coarse and fine alignment marks on the scan line metal layer. However, step 1 of this invention not only sets SD coarse and fine alignment marks on the data line metal layer, but also sets Gate coarse and fine alignment marks on the scan line metal layer. During production, it is first determined whether the product being produced has a conventional structure or a Triple Gate structure. When the product has a conventional structure, the camera first captures the SD coarse alignment mark for coarse positioning, then captures the SD fine alignment mark for fine positioning, and then attaches the Array board and CF board. In this case, the Gate coarse and fine alignment marks set on the scan line metal layer are not used. When the product has a Triple Gate structure, the camera first captures the Gate coarse alignment mark for coarse positioning, then captures the Gate fine alignment mark for fine positioning, and then attaches the Array board and CF board. In this case, the SD coarse and fine alignment marks set on the data line metal layer are not used. Therefore, different coarse and fine alignment marks can be identified and captured for different structures, so that the array substrate and CF substrate can be well aligned in both conventional and Triple Gate structures. This not only improves the bonding accuracy of the TFT LCD display, but also allows for clearer and more intuitive observation of the bonding of the two substrates, so as to adjust the bonding and identify defective products. This reduces display abnormalities caused by misalignment between the array substrate and CF substrate, thereby improving the yield rate.

[0052] When the product has a standard structure, step 2.1 allows the alignment of each TFT LCD screen to be read using the SD alignment ruler and the first CF alignment ruler. When the product has a Triple Gate structure, step 2.2 allows the alignment of each TFT LCD screen to be read using the Gate alignment ruler and the second CF alignment ruler. This eliminates the need to select positions on the large board to confirm the bonding status of each position, which not only improves the bonding accuracy of the TFT LCD display but also allows for a clearer and more intuitive observation of the bonding status of the two substrates. It also facilitates the analysis of defective products, thereby reducing display abnormalities caused by misalignment between the Array substrate and the CF substrate and improving the yield rate.

[0053] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0054] Obviously, the embodiments described above are only some embodiments of this application, not all embodiments. The accompanying drawings show preferred embodiments of this application, but do not limit the patent scope of this application. This application can be implemented in many different forms; rather, the purpose of providing these embodiments is to provide a more thorough and comprehensive understanding of the disclosure of this application. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing specific embodiments, or make equivalent substitutions for some of the technical features. Any equivalent structures made using the content of this application's specification and drawings, directly or indirectly applied to other related technical fields, are similarly within the scope of patent protection of this application.

Claims

1. A display panel for improving the alignment accuracy of a TFT LCD display panel, characterized in that, It comprises an Array large plate and a CF large plate arranged above the Array large plate, the data line metal layer of the Array large plate is provided with SD coarse alignment marks and SD fine alignment marks, the scan line metal layer of the Array large plate is provided with Gate coarse alignment marks and Gate fine alignment marks, the BM layer of the CF large plate is provided with CF first coarse alignment marks, CF first fine alignment marks, CF second coarse alignment marks and CF second fine alignment marks, the positions and sizes of the CF first coarse alignment marks, the CF first fine alignment marks, the CF second coarse alignment marks and the CF second fine alignment marks correspond to the positions and sizes of the SD coarse alignment marks, the SD fine alignment marks, the Gate coarse alignment marks and the Gate fine alignment marks respectively.

2. The display panel of claim 1, wherein, The SD coarse alignment marks, the SD fine alignment marks, the Gate coarse alignment marks and the Gate fine alignment marks are combined into a first alignment mark group, the CF first coarse alignment marks, the CF first fine alignment marks, the CF second coarse alignment marks and the CF second fine alignment marks are combined into a second alignment mark group, the first alignment mark group has multiple groups and is arranged at the top corners of the Array large plate respectively, and the second alignment mark group has multiple groups and is arranged at the top corners of the CF large plate respectively.

3. The display panel of claim 1, wherein, The SD coarse alignment marks, the SD fine alignment marks, the Gate coarse alignment marks and the Gate fine alignment marks are sequentially arranged from left to right, and the CF first coarse alignment marks, the CF first fine alignment marks, the CF second coarse alignment marks and the CF second fine alignment marks are sequentially arranged from left to right.

4. The display panel of claim 3, wherein, The shapes of the SD coarse alignment marks, the SD fine alignment marks, the Gate coarse alignment marks and the Gate fine alignment marks are all frame-shaped, and the shapes of the CF first coarse alignment marks, the CF first fine alignment marks, the CF second coarse alignment marks and the CF second fine alignment marks are all square-shaped.

5. The display panel of claim 4, wherein, The CF first coarse alignment marks, the CF first fine alignment marks, the CF second coarse alignment marks and the CF second fine alignment marks are respectively aligned with the centers of the SD coarse alignment marks, the SD fine alignment marks, the Gate coarse alignment marks and the Gate fine alignment marks.

6. The display of claim 1, wherein, The sizes of the SD coarse alignment marks and the Gate coarse alignment marks are both greater than the sizes of the SD fine alignment marks and the Gate fine alignment marks.

7. The display of claim 1, wherein, The Array large plate comprises multiple TFT chips sequentially arranged, the CF large plate comprises multiple CF chips sequentially arranged, the shapes and positions of each TFT chip and each CF chip correspond to each other, the data line metal layer of each TFT chip is provided with an SD alignment ruler, the scan line metal layer of each TFT chip is provided with a Gate alignment ruler, the BM layer of each CF chip is provided with a CF first alignment ruler and a CF second alignment ruler, the size and shape of the CF first alignment ruler correspond to the size and shape of the SD alignment ruler, and the size and shape of the CF second alignment ruler correspond to the size and shape of the Gate alignment ruler.

8. The display of claim 7, wherein, The misalignment degree alignment ruler comprises multiple misalignment degree patterns, and different numbers are arranged below each misalignment degree pattern to represent the misalignment degree.

9. A method for improving the accuracy of TFT LCD display screen bonding, characterized in that, It includes the display screen for improving the fitting accuracy of TFT LCD display screen as claimed in claim 8, which includes the following steps: Step 1: confirming whether the product produced is a conventional structure or a Triple Gate structure, when the product is a conventional structure, sequentially executing step 1.1 and step 2.1, when the product is a Triple Gate structure, executing step 1.2 and step 2.2; Step 1.1: the product is a conventional structure, the camera first grasps the SD coarse alignment mark and the CF first coarse fitting mark for coarse positioning, then grasps the SD fine alignment mark and the CF first fine fitting mark for fine positioning and fits the Array large plate and the CF large plate; Step 1.2: the product is a Triple Gate structure, the camera first grasps the Gate coarse alignment mark and the CF second coarse fitting mark for coarse positioning, then grasps the Gate fine alignment mark and the CF second fine fitting mark for fine positioning and fits the Array large plate and the CF large plate; Step 2.1: the product is a conventional structure, the camera grasps the SD alignment mark on the TFT chip and the CF first alignment mark on the BM layer of the CF chip, and judges the offset degree of the TFT chip and the CF chip according to the offset degree of the SD alignment mark and the CF first alignment mark; Step 2.2: the product is a Triple Gate structure, the camera grasps the Gate alignment mark on the TFT chip and the CF second alignment mark on the BM layer of the CF chip, and judges the offset degree of the TFT chip and the CF chip according to the offset degree of the Gate alignment mark and the CF second alignment mark.

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