A method and system for acquiring a layout of a mask plate
By using automated screening and adding auxiliary patterns, the problem of low accuracy in optical proximity effect correction in integrated circuit manufacturing has been solved, improving pattern correction accuracy and process window, increasing manufacturing yield, and is applicable to all nodes of semiconductor manufacturing processes.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NEXCHIP SEMICON CO LTD
- Filing Date
- 2026-02-02
- Publication Date
- 2026-04-21
AI Technical Summary
In integrated circuit manufacturing, the inconsistent photolithography process windows of dense and sparse patterns lead to low accuracy of optical proximity effect correction, and the addition of auxiliary patterns manually is complex and impractical, affecting manufacturing yield.
By using filtering intervals and threshold rules, auxiliary graphics are automatically added to improve the accuracy of graphic correction. This includes filtering sparse graphics, extending the main pattern, adding auxiliary graphics, and conducting simulated lighting tests to form a third main graphic to replace the second main graphic. The addition of auxiliary graphics is optimized using computational models and empirical rules.
It improves the accuracy and efficiency of mask pattern correction, increases the process window, reduces operational difficulty, improves manufacturing yield, and is applicable to all nodes of current semiconductor manufacturing processes.
Smart Images

Figure CN121613673B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit manufacturing technology, and in particular to a method and system for obtaining the layout of a photomask. Background Technology
[0002] To ensure complete etching of the edges of the designed patterns during manufacturing, Optical Proximity Correction (OPC) is applied to the mask pattern before photolithography. This ensures that the target pattern formed on the wafer closely matches the designed layout. The photolithography process windows for densely distributed patterns differ from those for sparse patterns, resulting in a smaller common process window. Illumination conditions suitable for densely distributed patterns are not suitable for sparse patterns. Therefore, auxiliary patterns are added before OPC to help balance the exposure process windows of various main patterns.
[0003] Integrated circuit designs are complex, and it is impractical to manually add auxiliary graphics to each main graphic. Due to rule conflicts between complex graphics, auxiliary graphics for some main graphics cannot be successfully added, thus affecting the graphic correction accuracy of optical proximity effect correction. Summary of the Invention
[0004] The purpose of this invention is to provide a method and system for obtaining the layout of a photomask, so as to improve the accuracy and efficiency of the pattern correction of the photomask, thereby improving the manufacturing yield.
[0005] To solve the above-mentioned technical problems, the present invention is achieved through the following technical solution:
[0006] This invention provides a method for obtaining the layout of a photomask, comprising the following steps:
[0007] Set a filtering range to filter out sparse graphics whose key dimensions are located within the filtering range, and use them as the first main graphic, wherein the main pattern of the first main graphic is distributed in an array.
[0008] Set a filtering threshold, and filter the first main graphic whose pattern inter-interlacing distance is greater than the filtering threshold, and use it as the second main graphic, wherein the pattern inter-interlacing distance is the misalignment distance of adjacent main graphics on the extension line of auxiliary graphics;
[0009] Extend the main pattern of the second main graphic along the extension line of the auxiliary graphic until multiple main patterns are connected to obtain a third main graphic, and replace the second main graphic with the third main graphic.
[0010] According to the threshold rules of the auxiliary graphics, auxiliary graphics are added to the layout design graphics; and
[0011] Simulated lighting tests are performed on the layout design graphics and the auxiliary graphics, and the auxiliary graphics and the layout design graphics are adjusted according to the test results.
[0012] In one embodiment of the present invention, before screening the first main graphic, the layout design graphic of the mask is input, and the layout design graphic is divided into sparse graphics and dense graphics according to the distribution density of the pattern.
[0013] In one embodiment of the present invention, the step of filtering the first main graphic includes:
[0014] According to the rules for adding the auxiliary graphic, the filtering range is set, wherein the filtering range allows one auxiliary graphic to be accommodated between adjacent main patterns;
[0015] Obtain the key dimensions of the main graphic, wherein the key dimensions are the spacing between the auxiliary graphic and the main graphic in adjacent rows or columns; and
[0016] When the key dimension is within the filtering range, the main pattern is assigned to the first main graphic.
[0017] In one embodiment of the present invention, the step of filtering the second main graphic includes:
[0018] Obtain the corresponding edges of adjacent main patterns column by column or row by row, wherein the corresponding edges are perpendicular to the extension lines of the auxiliary patterns;
[0019] Based on the coordinates of the corresponding edges, the maximum distance between adjacent corresponding edges of the main patterns is obtained, which is used as the interleaving distance between the patterns; and
[0020] When the interlacing distance between the patterns is greater than the filtering threshold, the main pattern participating in the comparison is included in the second main graphic.
[0021] In one embodiment of the present invention, in the step of setting the extension line of the auxiliary graphic, the auxiliary graphic is set between the main patterns in adjacent rows or between the main patterns in adjacent columns, wherein the auxiliary graphic extends in the row direction or column direction of the main pattern.
[0022] In one embodiment of the present invention, the step of extending the main pattern of the second main graphic includes:
[0023] The side of the main pattern is divided into an inner side and an outer side, wherein the outer side is the outermost side of the second main pattern;
[0024] Set a first preset distance, and move the inner edge away from the main pattern by the first preset distance along a direction perpendicular to the extension line of the auxiliary graphic; and
[0025] Set a second preset distance, and move the outer edge away from the main pattern by the second preset distance along a direction parallel to the extension line of the auxiliary graphic.
[0026] In one embodiment of the present invention, the step of dividing the inner side and the outer side includes:
[0027] Set the detection distance;
[0028] Sequentially acquire the edges to be marked of the main pattern, and set the detection area according to the edges to be marked and the detection distance; and
[0029] If there are no pattern features in the exploration area, the edge to be marked is marked as the outer edge; if there are pattern features in the exploration area, the edge to be marked is marked as the inner edge.
[0030] In one embodiment of the present invention, the detection area is a rectangular area with the side to be marked as the length and the detection distance as the width, and the detection area coincides with the edge of the main pattern.
[0031] In one embodiment of the present invention, the step of adjusting the auxiliary graphic in the step of simulating illumination testing includes:
[0032] Simulated lighting tests are performed on the auxiliary graphic and the layout design graphic, and the lighting intensity of the auxiliary graphic is obtained as the first lighting intensity, and the lighting intensity of the layout design graphic is obtained as the second lighting intensity.
[0033] Set a light intensity threshold, wherein the light intensity threshold is related to a second light intensity; and
[0034] If the first light intensity is greater than the light intensity threshold, the auxiliary image is reacquired until the first light intensity is less than or equal to the light intensity threshold.
[0035] This invention provides a mask layout acquisition system, comprising:
[0036] The first graphic filtering module is used to set a filtering range and filter out sparse graphics whose key dimensions are located within the filtering range as the first main graphic, wherein the main pattern of the first main graphic is distributed in an array.
[0037] The second graphic filtering module is used to set a filtering threshold and filter the first main graphic whose pattern interleaving distance is greater than the filtering threshold as the second main graphic, wherein the pattern interleaving distance is the misalignment distance of adjacent main graphics on the extension line of the auxiliary graphic;
[0038] The graphic generation module is used to extend the main pattern of the second main graphic along the extension line of the auxiliary graphic until multiple main patterns are connected to obtain a third main graphic, and replace the second main graphic with the third main graphic.
[0039] An auxiliary graphic adding module is used to add auxiliary graphics to the layout design graphic according to the threshold rules of the auxiliary graphics; and
[0040] The simulation testing module is used to perform simulated lighting tests on the layout design graphics and the auxiliary graphics, and adjust the auxiliary graphics and the layout design graphics based on the test results.
[0041] As described above, this invention provides a method and system for obtaining mask layouts. Its unexpected technical effect is that, after OPC correction, the pattern formed on the mask will more closely resemble the actual design pattern. The mask correction method provided by this invention has higher convergence and a higher normalized logarithmic slope for OPC correction, resulting in a mask pattern that more closely approximates the design pattern. Therefore, it can provide a larger process window, reduce the operational difficulty of the process itself, and improve product yield. Furthermore, the method provided by this invention does not require adjustment or modification of the threshold rules for adding auxiliary patterns, thus it can be directly completed on a computer, resulting in a very high success rate for debugging. It has minimal impact on other semiconductor process flows and is applicable to all nodes of current semiconductor manufacturing processes.
[0042] Of course, any product implementing this invention does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description
[0043] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0044] Figure 1 This is a flowchart of steps S10 to S30 in one embodiment of the present invention.
[0045] Figure 2 This is a flowchart of steps S210 to S250 in one embodiment of the present invention.
[0046] Figure 3 This is a schematic diagram of a first main graphic in one embodiment of the present invention.
[0047] Figure 4 This is another schematic diagram of the first main graphic in one embodiment of the present invention.
[0048] Figure 5 This is a schematic diagram illustrating the distinction between the inner and outer sides in one embodiment of the present invention.
[0049] Figure 6 This is a schematic diagram of the main pattern extending the second main graphic in one embodiment of the present invention.
[0050] Figure 7 This is a schematic diagram of adjusting and forming a third main graphic in one embodiment of the present invention.
[0051] Figure 8 This is a schematic diagram of the structure of a third main graphic and an auxiliary graphic in one embodiment of the present invention.
[0052] Figure 9 This is a schematic diagram of another third main graphic and auxiliary graphic in one embodiment of the present invention.
[0053] Figure 10 This is a comparison chart of the convergence effect of the layout design graphics after OPC correction in one embodiment of the present invention.
[0054] Figure 11 This is a schematic diagram of the layout acquisition system in one embodiment of the present invention.
[0055] In the diagram: 10. Layout acquisition system; 11. First graphic filtering module; 12. Second graphic filtering module; 13. Graphic generation module; 14. Auxiliary graphic addition module; 15. Simulation test module. Detailed Implementation
[0056] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0057] To reduce process variations caused by different pattern densities in integrated circuit layouts, sub-resolution patterns are inserted into the surrounding areas of sparse patterns in the mask pattern as auxiliary patterns to the main pattern, thereby improving depth of focus and process window uniformity. The inserted auxiliary pattern is smaller than the imaging resolution of the lithography system. The auxiliary pattern itself may not form a lithographic pattern during exposure, but it can influence the light intensity distribution of the nearby main pattern during lithographic imaging. Similar to optical proximity correction, the insertion of sub-resolution auxiliary patterns is also divided into rule-based SRAF and model-based SRAF. This embodiment provides an auxiliary pattern based on both rule-based and model-based methods. In this embodiment, the auxiliary pattern is inserted into the sparse main pattern, and the invention does not limit the node at which the auxiliary pattern is introduced. For example, the auxiliary pattern can be introduced at the 90nm node and can be introduced simultaneously with the model-based optical proximity correction model.
[0058] Please see Figure 1 As shown, the method for obtaining the layout of the mask includes steps S10 to S30.
[0059] Step S10: Obtain the layout design of the mask.
[0060] Step S20: Add auxiliary graphics to the pattern of the mask.
[0061] Step S30: Perform optical proximity correction on the mask pattern to form the photolithographic master pattern of the mask.
[0062] Please see Figure 1 As shown, in one embodiment of the present invention, in step S10, a mask is used to block the wafer during the photolithography process. The pattern on the mask is transferred to the photomask through exposure and development. In semiconductor manufacturing, various patterns can be formed on the wafer using masks and etching. The photomask can be a photoresist. The layout design pattern of the mask is derived from the design pattern on the wafer. The present invention does not limit the layout design pattern of the mask; it directly inputs the layout design pattern. It should be noted that the layout design pattern is a regular pattern, representing the theoretical shape of the design pattern on the wafer. However, the main photolithography pattern in step S30 is the layout design pattern after optical proximity correction; the main photolithography pattern is not a regular pattern. After photolithography, the formed pattern of the main photolithography pattern on the wafer is as close as possible to the layout design pattern.
[0063] Please see Figure 1 and Figure 2As shown, in one embodiment of the present invention, in step S20, after inputting the main graphic of the layout design, auxiliary graphics are added to the mask layout according to the size and shape of the main graphic and the rules for adding auxiliary graphics. The rules for adding auxiliary graphics refer to threshold empirical rules. For example, setting a linewidth threshold for the auxiliary graphics, setting a spacing threshold between the auxiliary graphics and the main graphic, etc. Since modifications to threshold empirical rules require repeated verification through process and yield testing, and modifying a threshold empirical rule in one place may lead to errors in adding auxiliary graphics elsewhere in the entire design, the present invention does not limit the threshold empirical rules and directly uses threshold empirical rules verified through process testing. In the present invention, step S20 includes steps S210 to S250.
[0064] Step S210: Set a filtering range to filter out layout design graphics whose key dimensions are within the filtering range, and use them as the first main graphic, wherein the first main graphic includes multiple main patterns.
[0065] Step S220: Set a filtering threshold, compare the positions of the main patterns in adjacent rows or columns, obtain the interlacing distance between two adjacent first main patterns, and filter out the first main pattern whose interlacing distance exceeds the filtering threshold as the second main pattern.
[0066] Step S230: According to the rules for adding auxiliary graphics, set the extension line of the auxiliary graphics, and extend the main pattern of the second main graphic along the direction of the extension line of the auxiliary graphics until multiple main patterns are connected and form a third main graphic.
[0067] Step S240: Replace the second main graphic with the third main graphic, form auxiliary graphics according to the rules for adding auxiliary graphics, and add the auxiliary graphics to the layout design graphic.
[0068] Step S250: Design the illumination intensity of the graphic according to the layout and set the illumination intensity threshold. When the illumination intensity of the auxiliary graphic is greater than the illumination intensity threshold, repeat steps S210 to S250 until the illumination intensity of the auxiliary graphic is less than or equal to the illumination intensity threshold.
[0069] Please see Figures 1 to 4 As shown, in one embodiment of the present invention, in step S210, the filtering interval is used to measure the type of auxiliary graphics added to the mask layout. The type of auxiliary graphics includes the size and shape of the auxiliary graphics. For example... Figure 3 and Figure 4As shown, this embodiment provides a mask layout. The mask layout is a design pattern, featuring sparse and dense patterns. The auxiliary patterns of this invention are added only to the sparse patterns, thereby reducing the density difference between the sparse and dense patterns. In step S210, the key dimension of the spacing between the sparse patterns is obtained. The key dimension of the spacing refers to the minimum distance between the main patterns in adjacent rows. It should be noted that this invention does not define the mask layout pattern as an array pattern. Due to the special nature of chip products, the layout pattern on the mask naturally includes multiple rows and columns of patterns. Both sparse and dense patterns naturally include multiple rows of patterns. In this invention, in the sparse patterns, the edges of the main patterns in the same row can be aligned or misaligned. The edges of the main patterns in the same column can be aligned or staggered. Figure 3 The image shown is a sparse graphic with the edges of the main pattern aligned. Figure 4 The image shown is a sparse pattern with intersecting edges of the main pattern.
[0070] Please see Figures 1 to 3 As shown, in one embodiment of the present invention, in step S210, it is determined whether the multiple main patterns belong to the same row or column by whether their orthographic projections in the X-axis and Y-axis directions coincide. Specifically, the X-axis and Y-axis are mutually perpendicular axes, and both are located in the horizontal plane. When the orthographic projections of two main patterns in the X-axis direction coincide, the two main patterns belong to the same column. When the orthographic projections of two main patterns in the Y-axis direction coincide, the two main patterns belong to the same row. Wherein, when the coordinate sets of the orthographic projections of two main patterns intersect, the orthographic projections of the two main patterns in the corresponding direction axis coincide. The multiple main patterns of the sparse graphic are projected sequentially and compared to divide the main patterns of the sparse graphic into multiple rows and multiple columns of main patterns. In this embodiment, the multiple rows of main patterns and the multiple columns of main patterns can be numbered to distinguish each main pattern. It should be noted that the auxiliary graphics added to the main patterns of rows and columns are exactly the same. Therefore, this invention uses rows as an example to illustrate how auxiliary graphics are added between the main patterns of adjacent rows, and will not repeat how auxiliary graphics are added between the main patterns of adjacent columns.
[0071] Please see Figures 1 to 4 As shown, in one embodiment of the present invention, in step S210, the minimum spacing between two adjacent rows of main patterns is obtained as the key spacing dimension. Figure 3 As shown, the critical dimension for spacing is D1. Figure 4As shown, D4 > D3 > D1 > D2, and the key dimension of the spacing is D2. The auxiliary graphic is AF. The key dimension of the main pattern is the spacing between the auxiliary graphic and the main pattern in adjacent rows or columns. In this embodiment, the auxiliary graphic AF is placed between two adjacent rows of main patterns. The width of the auxiliary graphic AF is B1, and the spacing between the auxiliary graphic AF and the main pattern is a first distance C1 and a second distance C2. The first distance C1 and the second distance C2 can be equal or unequal. When the first distance C1 and the second distance C2 are equal, the key dimension of the main pattern is equal to the first distance C1 and the second distance C2. When the first distance C1 and the second distance C2 are unequal, the key dimension of the main pattern is equal to the larger value of the first distance C1 and the second distance C2. Therefore, when the larger value of the first distance C1 and the second distance C2 is within the filtering interval, that is, when the key dimension of the main pattern is within the filtering interval, the current sparse graphic is marked as the first main graphic. The range of the filtering interval is determined according to the rules for adding auxiliary graphics. The filtering range set in this application only allows one auxiliary graphic to be accommodated between the main patterns of adjacent rows or columns. If there is not enough space between the main patterns of adjacent rows or columns to accommodate one auxiliary graphic, the sparse graphic is not marked as the first main graphic. If there is more than one auxiliary graphic between the main patterns of adjacent rows or columns, the sparse graphic is not marked as the first main graphic.
[0072] Please see Figures 1 to 4 As shown, in one embodiment of the present invention, in step S220, a filtering threshold is set. The interleaving distance between patterns is the maximum distance between the corresponding edges of two adjacent main patterns. If the auxiliary graphic is added between main patterns in adjacent rows, the interleaving distance is the maximum distance between the corresponding edges of adjacent main patterns in adjacent rows. If the auxiliary graphic is added between main patterns in adjacent columns, the interleaving distance is the maximum distance between the corresponding edges of two main patterns in adjacent columns. It should be noted that the maximum corresponding edge distance compares the parallel edges of the two main patterns, specifically, the sides of the two main patterns in the same position, i.e., corresponding edges. For example, on the layout, the left sides of the two main patterns are corresponding edges, the right sides of the two main patterns are also corresponding edges, and so on. The side perpendicular to the extension line of the auxiliary graphic is used for comparing the maximum corresponding edge distance. In this embodiment, the filtering threshold can be a single value or a set of multiple values. Based on the number of columns and rows of the main patterns in the layout design, when comparing using the filtering threshold, a value is selected from the set as the filtering threshold. For example, for the first main graphic with a large number of rows and columns, a larger value can be selected as the filtering threshold. The filtering threshold value is a value greater than or equal to 0, thus leaving a suitable error range for the overlap distance between the two main graphics. In this embodiment, as... Figure 3As shown, by obtaining the axis of symmetry of the main pattern, if the axes of symmetry of the main patterns in the same column and adjacent rows do not coincide, then the staggered distance S of the two main patterns is greater than 0. Therefore, the two staggered patterns are included as the second main pattern. For example... Figure 3 The pattern shown is Pattern2. Similarly, for two adjacent rows of main patterns, the main patterns in each adjacent row are compared column by column. Two main patterns that meet the filtering threshold are included in the second main pattern. When the overlap S between two main patterns is 0, the two main patterns in the current column are skipped, and the comparison continues with the two main patterns in the next column, until the filtering of the first main pattern is complete.
[0073] Please see Figures 1 to 4 As shown, in one embodiment of the present invention, in step S220, and in another embodiment of the present invention, when comparing the main patterns of adjacent rows sequentially, if the interlacing distance of the main patterns in the current column is 0, and the interlacing distance of the main patterns in the preceding and following columns of the current column is greater than 0, then the main pattern of the current column can also be included in the second main pattern. In other embodiments of the present invention, an error column threshold is set. After traversing all columns of the first main pattern, patterns with a consecutive number of columns less than or equal to the error column threshold can be included in the second main pattern. For example, the error column threshold is 3. When there are 3 columns of main patterns with an interlacing distance of 0 and consecutive patterns, then these 3 columns of main patterns are also included in the second main pattern.
[0074] Please see Figures 1 to 4 As shown, in one embodiment of the present invention, in step S230, the auxiliary graphic AF is placed between the second main graphics in adjacent rows. In this embodiment, the extension line of the auxiliary graphic is consistent with the extension direction of the main pattern arrangement of the second main graphic. It should be noted that the present invention does not limit the extension line of the auxiliary graphic to one; where the spacing allows, the extension line of the auxiliary graphic includes one extension line along the X-axis direction and another extension line along the Y-axis direction. In this embodiment, and on the layout of the mask, the extension lines of the auxiliary graphic in the X-axis direction and the Y-axis direction can intersect. In this embodiment, the extension line of the auxiliary graphic is the extension direction of the auxiliary graphic, and the auxiliary graphics can be discontinuously distributed along the extension line direction.
[0075] Please see Figures 1 to 5 As shown, in one embodiment of the present invention, in step S230, during the step of extending the main pattern of the second main graphic, the inner and outer edges of the main pattern are obtained. In this embodiment, by marking and identifying the edges of the main pattern of the second main graphic, a movement operation is performed on different sides of the main pattern to form a new main pattern, and the graphic formed by the third main pattern is the third main graphic. In this embodiment, the third main graphic covers the second main graphic. In this embodiment, the sides of the main pattern are divided into outer edges and inner edges. Specifically, a detection distance is set. Figure 5As shown, a detection area is formed along the direction perpendicular to the side of the main pattern and away from the main pattern, within an area equal to the length of the side of the main pattern and the width of the detection distance. This detection area coincides with the edge of the main pattern. If a pattern feature exists within the detection area, the current side is marked as the inner side; if no pattern feature exists within the detection area, the current side is marked as the outer side. The detection distance is determined according to layout design rules; for example, the detection distance can be set to the maximum spacing between two sparse graphics defined by the layout design rules. The length of the detection area is the distance along the side of the main pattern, and the width of the detection area is the distance along the direction perpendicular to the side of the main pattern. In this application, the outermost edge of the main pattern is the outermost edge of the second main graphic.
[0076] Please see Figures 1 to 4 As shown, in one embodiment of the present invention, in step S230, the step of extending the main pattern of the second main graphic involves setting a first preset distance and a second preset distance. The inner edge of the main pattern of the second main graphic, perpendicular to the extension line of the auxiliary graphic, is obtained, and moved a first preset distance away from the main pattern along the direction perpendicular to the extension line of the auxiliary graphic. The outer edge of the main pattern of the second main graphic is obtained, and moved a second preset distance away from the main pattern along the direction perpendicular to the extension line of the auxiliary graphic. In this embodiment, the maximum spacing between adjacent main patterns along the extension line of the auxiliary graphic is S, and the first preset distance is S / 2. Extending the inner edge perpendicular to the extension line of the auxiliary graphic by the first preset distance allows the main patterns in the same row to extend and form a continuous pattern. The second preset distance can be set by the designer. In this embodiment, the second preset distance N is greater than the maximum overlap distance in the second main graphic. Figure 3 As shown, if the maximum stagger distance is S1, then N > S1.
[0077] Please see Figures 1 to 4 , Figures 6 to 8 As shown, in one embodiment of the present invention, in step S230, after extending the inner and outer edges of each main pattern, the edge closest to the auxiliary graphic among the multiple main patterns in the current row is obtained as the first reference edge, and the first reference edge is extended along the extension line of the auxiliary graphic. The edge furthest from the auxiliary graphic among the multiple main patterns in the current row is obtained as the second reference edge, and the second reference edge is extended along the extension line of the auxiliary graphic. The area formed by the intersection of the outer edge of the main pattern in the current row, the first reference edge, and the second reference edge is used as the main pattern of the third main graphic. This process is repeated row by row to process the main patterns, thereby forming the third main graphic. In this embodiment, the third main graphic can be as follows: Figure 9 The discontinuous strip pattern shown. In another embodiment of the invention, the third main pattern can be as follows: Figure 8 The continuous strip graphic shown.
[0078] Please see Figure 1 and Figure 2 , Figure 8 and Figure 9 As shown, in one embodiment of the present invention, in step S240, the third main graphic covers the second main graphic. In this embodiment, the coordinate data and graphic data of the second main graphic can be deleted from the system, retaining only the data of the first and third main graphics. It should be noted that in the present invention, the graphic inclusion relationship is as follows: the layout design graphic includes sparse graphics and dense graphics, and the sparse graphics include the first main graphic and the normal regular main graphics. According to the stagger distance of the main patterns in adjacent rows, part of the first main graphic is divided into the second main graphic. After processing the second main graphic, the original second main graphic is replaced by the third main graphic. In step S240, adding auxiliary graphics adds auxiliary graphics to the entire layout design graphic. Moreover, the present invention adds auxiliary graphics by setting threshold rules. When adding auxiliary graphics to the third main graphic, the rules used are consistent with the method of adding auxiliary graphics to the layout design graphic. Originally, rule conflicts caused by pattern design issues are avoided in the present invention by forming the third main graphic, thereby ensuring that each area can be normally added with auxiliary graphics in the step of adding auxiliary graphics with threshold rules, and the addition of auxiliary graphics is completed directly in one step.
[0079] Please see Figure 1 and Figure 2 , Figure 8 and Figure 9 As shown, it should be noted that the auxiliary graphics of this invention are added to the system's layout design graphics, rather than directly to the mask. The third main graphic is also not actually set on the mask, but is input and added to the system when adding auxiliary graphics. After completing step S250, the data of the third main graphic can be directly deleted. While retaining the data of the auxiliary graphics, the graphics participating in the OPC correction in step S30 include the layout design graphics and the auxiliary graphic AF added in step S240.
[0080] Please see Figure 1 and Figure 2 , Figure 8 and Figure 9As shown, in one embodiment of the present invention, in step S250, a simulated exposure test is performed on the layout design graphic and the added auxiliary graphic to obtain the light intensity data of the layout design graphic and the auxiliary graphic. Specifically, based on the light intensity data of the layout design graphic, a light intensity threshold can be set, for example, one-third to one-half of the light intensity of the layout design graphic. If the light intensity data of the auxiliary graphic is greater than the light intensity threshold, it is considered that the auxiliary graphic has the potential to be exposed and developed onto the mask, and the current auxiliary graphic is insufficient to meet the photolithography requirements. Therefore, in the present invention, for this situation, steps S210 to S250 are repeated, and parameter values such as the screening interval, screening threshold, first preset distance, and second preset distance are changed to regenerate the auxiliary graphic and test it until the test passes.
[0081] Please see Figure 1 As shown, in one embodiment of the present invention, in step S30, after the auxiliary pattern is added, the present invention inputs the mask layout into the optical proximity effect correction model. Specifically, in step S30, an optical model and a photoresist chemical reaction model are used to simulate the mask pattern after exposure, as well as to simulate the pattern formed on the wafer by etching. The pattern simulated on the wafer is the simulation correction pattern, while the pattern desired to be formed on the wafer according to the functional design is the target pattern. By comparing the error between the simulation correction pattern and the target pattern, the edge of the main lithography pattern is continuously adjusted, so that the error between the simulation correction pattern and the target pattern is within a preset threshold. When the error between the simulation correction pattern and the target pattern is within the preset threshold, the layout design pattern used for simulation is then the main lithography pattern, and the main lithography pattern is output. It should be noted that the main lithography pattern includes the auxiliary pattern, but in the actual lithography process, due to the low resolution of the auxiliary pattern, the auxiliary pattern is not transferred to the mask pattern. Based on steps S10 to S30, the correction and adjustment of the mask layout design pattern are completed.
[0082] It should be noted that in this embodiment, step S20 is performed before OPC correction. However, OPC correction requires multiple simulations and adjustments. Therefore, in other embodiments of the present invention, step S20 can also be inserted during the cyclic simulation of OPC, for example, between two simulations. The newly generated auxiliary graphic overwrites the original auxiliary graphic, and the original auxiliary graphic data can be deleted.
[0083] Please see Figure 1 and Figure 2 , Figure 11As shown, this invention provides a mask layout acquisition system 10. The layout acquisition system 10 includes a first graphic filtering module 11, a second graphic filtering module 12, a graphic generation module 13, an auxiliary graphic addition module 14, and a simulation testing module 15. The first graphic filtering module 11 sets a filtering interval to filter sparse graphics whose key dimensions are within the filtering interval, which are then used as first main graphics. The main patterns of the first main graphics are distributed in an array. The second graphic filtering module 12 sets a filtering threshold to filter first main graphics whose inter-pattern overlap is greater than the threshold, which are then used as second main graphics. The inter-pattern overlap is the offset distance between adjacent main patterns on the extension line of the auxiliary graphics. The graphic generation module 13 extends the main patterns of the second main graphics along the extension line of the auxiliary graphics until multiple main patterns are connected to obtain a third main graphic, which replaces the second main graphic. The auxiliary graphic addition module 14 adds auxiliary graphics to the layout design graphic according to the threshold rules of the auxiliary graphics. The simulation testing module 15 performs simulated lighting tests on the layout design graphic and the auxiliary graphics, and adjusts the auxiliary graphics and the layout design graphic based on the test results.
[0084] Please see Figure 1 and Figure 2 , Figure 10 As shown, in this invention, through the mask correction method and system of this invention, after OPC correction, the pattern formed on the mask will be closer to the actual design pattern. For example... Figure 10 As shown, the square represents the design pattern, while the circle represents the pattern formed by actual exposure. The mask correction method provided by this invention will make the circle closer to the edge of the square, resulting in higher convergence and a higher normalized logarithmic slope for OPC correction. This makes the mask pattern closer to the design pattern, thus providing a larger process window, reducing the operational difficulty of the process itself, and improving product yield. Furthermore, the method provided by this invention does not require adjustment or modification of the threshold rules for adding auxiliary patterns, so it can be completed directly on a computer with an extremely high success rate for debugging. It has minimal impact on other semiconductor process flows and is applicable to all nodes of current semiconductor manufacturing processes. Moreover, the layout acquisition method and system provided by this invention minimize manual intervention and support automatic computer operation to complete layout correction.
[0085] The embodiments of the present invention disclosed above are merely illustrative of the invention. The embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.
Claims
1. A method for obtaining the layout of a photomask, characterized in that, Includes the following steps: Input the layout design graphic of the mask, set the filtering range, and filter out sparse graphics whose key dimensions are located within the filtering range from the layout design graphic as the first main graphic, wherein the main pattern of the first main graphic is distributed in an array. Set a filtering threshold, and filter the first main graphic whose pattern inter-interlacing distance is greater than the filtering threshold, and use it as the second main graphic, wherein the pattern inter-interlacing distance is the misalignment distance of adjacent main graphics on the extension line of auxiliary graphics; Extend the main pattern of the second main graphic along the extension line of the auxiliary graphic until multiple main patterns are connected to obtain a third main graphic, and replace the second main graphic with the third main graphic. Auxiliary graphics are added to the layout design graphics according to the threshold rules of the auxiliary graphics; as well as Simulated lighting tests are performed on the layout design graphics and the auxiliary graphics, and the auxiliary graphics and the layout design graphics are adjusted according to the test results.
2. The method for obtaining the layout of a photomask according to claim 1, characterized in that, Before selecting the first main graphic, the layout design graphic is divided into sparse graphics and dense graphics according to the distribution density of patterns in the layout design graphic.
3. The method for obtaining the layout of a photomask according to claim 1, characterized in that, The steps for filtering the first main graphic include: According to the rules for adding the auxiliary graphic, the filtering range is set, wherein the filtering range allows one auxiliary graphic to be accommodated between adjacent main patterns; Obtain the key dimensions of the main pattern, wherein the key dimensions are the spacing between the auxiliary graphic and the main pattern in adjacent rows or columns; and When the key dimension is within the filtering range, the main pattern is assigned to the first main graphic.
4. The method for obtaining the layout of a photomask according to claim 1, characterized in that, The steps for filtering the second main graphic include: Obtain the corresponding edges of adjacent main patterns column by column or row by row, wherein the corresponding edges are perpendicular to the extension lines of the auxiliary patterns; Based on the coordinates of the corresponding edges, the maximum distance between adjacent corresponding edges of the main patterns is obtained, which is used as the interleaving distance between the patterns; and When the interlacing distance between the patterns is greater than the filtering threshold, the main pattern participating in the comparison is included in the second main graphic.
5. The method for obtaining the layout of a photomask according to claim 1, characterized in that, In the step of setting the extension line of the auxiliary graphic, the auxiliary graphic is set between the main patterns in adjacent rows or between the main patterns in adjacent columns, wherein the auxiliary graphic extends in the row direction or column direction of the main pattern.
6. The method for obtaining the layout of a photomask according to claim 1, characterized in that, The steps for extending the main pattern of the second main graphic include: The side of the main pattern is divided into an inner side and an outer side, wherein the outer side is the outermost side of the second main pattern; Set a first preset distance, and move the inner edge away from the main pattern by the first preset distance along a direction perpendicular to the extension line of the auxiliary graphic; and Set a second preset distance, and move the outer edge away from the main pattern by the second preset distance along a direction parallel to the extension line of the auxiliary graphic.
7. The method for obtaining the layout of a photomask according to claim 6, characterized in that, The steps of dividing the inner side and the outer side include: Set the detection distance; Sequentially acquire the edges to be marked of the main pattern, and set the detection area according to the edges to be marked and the detection distance; and If there are no pattern features in the exploration area, the edge to be marked is marked as the outer edge; if there are pattern features in the exploration area, the edge to be marked is marked as the inner edge.
8. The method for obtaining the layout of a photomask according to claim 7, characterized in that, The detection area is a rectangular area with the side to be marked as its length and the detection distance as its width, and the detection area coincides with the edge of the main pattern.
9. The method for obtaining the layout of a photomask according to claim 1, characterized in that, In the step of simulating illumination testing, the step of adjusting the auxiliary graphic includes: Simulated lighting tests are performed on the auxiliary graphic and the layout design graphic, and the lighting intensity of the auxiliary graphic is obtained as the first lighting intensity, and the lighting intensity of the layout design graphic is obtained as the second lighting intensity. Set a light intensity threshold, wherein the light intensity threshold is related to a second light intensity; and If the first light intensity is greater than the light intensity threshold, the auxiliary image is reacquired until the first light intensity is less than or equal to the light intensity threshold.
10. A mask layout acquisition system, characterized in that, include: The first graphic filtering module is used to set a filtering range and filter out sparse graphics whose key dimensions are located within the filtering range as the first main graphic, wherein the main pattern of the first main graphic is distributed in an array. The second graphic filtering module is used to set a filtering threshold and filter the first main graphic whose pattern interleaving distance is greater than the filtering threshold as the second main graphic, wherein the pattern interleaving distance is the misalignment distance of adjacent main graphics on the extension line of the auxiliary graphic; The graphic generation module is used to extend the main pattern of the second main graphic along the extension line of the auxiliary graphic until multiple main patterns are connected to obtain a third main graphic, and replace the second main graphic with the third main graphic. The auxiliary graphic adding module is used to add auxiliary graphics to the layout design graphic according to the threshold rules of the auxiliary graphics; as well as The simulation testing module is used to perform simulated lighting tests on the layout design graphics and the auxiliary graphics, and adjust the auxiliary graphics and the layout design graphics based on the test results.
Citation Information
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