Chip high-speed interconnection multichannel data synchronization method and system based on FPGA

Abstract

The invention relates to a chip high-speed interconnection multichannel data synchronization method and system based on an FPGA (Field Programmable Gate Array). The method comprises the steps that a configuration data sending end outputs multi-channel parallel benchmark test data to an FPGA, the FPGA comprises a plurality of high-speed receiving modules, a plurality of cache modules, a shift control module and a counting module, and the high-speed receiving modules receive the multi-channel parallel data and then transmit the multi-channel parallel data to the corresponding cache modules for storage; the counting module calculates the offset of the cached data of each slave channel by taking the cached data of the main channel as a reference; when the offset is larger than or equal to a first threshold value, the shift control module controls the corresponding cache module to shift in byte level, and when the offset is smaller than the first threshold value, the shift control module controls the corresponding high-speed receiving module to shift in bit level finely until the offset meets a synchronous threshold value; and switching the data sending end to output preset verification data, and when the output data of each channel cache module is consistent with the verification data, completing multi-channel synchronization. By adopting the method, accurate synchronization of multi-channel data can be realized.

Description

Technical Field

[0001] This application relates to the field of electronic engineering technology, and in particular to a method and system for high-speed chip interconnection and multi-channel data synchronization based on FPGA. Background Technology

[0002] With the rapid development of high-end computing, high-speed data acquisition, data centers, radar signal processing, and medical imaging, increasingly stringent requirements have been placed on the bandwidth and real-time performance of data processing. To meet these demands, traditional technologies typically employ multiple application-specific integrated circuits (ASICs) or processors to exchange data via high-speed serial interconnect protocols such as JESD204B / C, Aurora, and PCIe. These interconnect technologies, characterized by high transmission rates and large data capacity, have become the mainstream implementation method for multi-channel data interaction. However, in practical applications, traditional multi-channel data synchronization methods often struggle to achieve precise time alignment between different chips or multiple parallel data channels from different sources on the same chip. Differences in data transmission delays between channels can easily lead to data offset, affecting the accuracy of subsequent collaborative computation and processing. Furthermore, traditional synchronization schemes are usually designed for specific channel numbers and clock frequencies, resulting in poor adaptability and scalability. They cannot flexibly address the parameter adjustment requirements of different application scenarios, ultimately reducing the reliability and practicality of the entire data processing system. Summary of the Invention

[0003] Therefore, it is necessary to provide a method and system for high-speed interconnection and multi-channel data synchronization of FPGA-based chips to address the aforementioned technical problems.

[0004] A method for high-speed chip interconnect multi-channel data synchronization based on FPGA, the method comprising: The configuration data sending end outputs multiple parallel benchmark test data to the FPGA. The FPGA includes multiple high-speed receiving modules, multiple buffer modules, a shift control module, and a counting module. After receiving the multiple parallel data, the high-speed receiving module transmits it to the corresponding buffer module for storage. Select the master channel from the multiple parallel channels, and use the master channel data stored in the cache module as a reference to calculate the offset of each slave channel data stored in the other cache modules through the counting module. When the offset is greater than or equal to the first threshold, the shift control module controls the corresponding cache module to perform byte-level shift adjustment. When the offset is less than the first threshold, the shift control module controls the corresponding high-speed receiving module to perform bit-level fine shift adjustment until the offset meets the synchronization threshold. Switch the data sending end to output preset verification data. When the output data of the cache module corresponding to each channel is consistent with the verification data, multi-channel synchronization is completed.

[0005] A high-speed chip interconnect multi-channel data synchronization system based on FPGA, the system comprising: The data transmitter and the FPGA; the FPGA includes multiple high-speed receiving modules, multiple buffer modules, a shift control module, and a counting module; The data sending end is used to output multi-channel parallel benchmark test data, and also to switch to output preset verification data; The high-speed receiving module is connected to the data sending end and is used to receive multiple parallel data streams and transmit them to the corresponding buffer module. The cache module is used to store the received data of the corresponding channel and to perform byte-level shift adjustment in response to the control of the shift control module; The counting module is used to calculate the offset of the data stored in the cache module corresponding to each slave channel based on the data stored in the cache module corresponding to the main channel, and to feed back the offset to the shift control module. The shift control module is used to receive control data from each slave channel in real time. When the offset is greater than or equal to the first threshold, it controls the corresponding buffer module to perform byte-level shift adjustment. When the offset is less than the first threshold, it controls the corresponding high-speed receiving module to perform bit-level fine shift adjustment until the offset meets the synchronization threshold. Multi-channel synchronization is completed when the output data of the cache modules corresponding to all channels are consistent with the preset verification data.

[0006] The aforementioned FPGA-based high-speed interconnect multi-channel data synchronization method and system utilizes multiple high-speed receiving modules and buffer modules within the FPGA to receive and store multi-channel parallel benchmark test data output from the data transmitter, thus laying a stable data foundation for multi-channel synchronization. Using the master channel data as a benchmark, the offset of each slave channel data is precisely calculated by a counting module, clearly defining the target and direction of synchronization adjustments. A step-wise adjustment strategy is employed based on the offset magnitude: when the offset is large, the shift control module controls the buffer module to perform byte-level shift adjustments; when the offset is small, the high-speed receiving module performs bit-level fine shift adjustments. This effectively eliminates timing offsets of varying degrees, ensuring that the offsets meet synchronization requirements. Furthermore, by switching preset verification data to check the consistency of each channel's output, the synchronization effect can be accurately confirmed. This invention effectively solves the time misalignment problem caused by transmission delay in multi-channel parallel data, achieving precise synchronization of multi-channel data. It provides stable and aligned input data for collaborative computation in fields such as high-end computing and high-speed data acquisition, significantly improving the reliability and correctness of subsequent data processing modules. Attached Figure Description

[0007] Figure 1This is a flowchart illustrating a high-speed chip interconnect multi-channel data synchronization method based on FPGA in one embodiment. Figure 2 This is a framework diagram of an FPGA implementation method for high-speed interconnection and multi-channel data synchronization between a data transmission chip and an FPGA chip in one embodiment. Figure 3 This is a control flowchart of an FPGA implementation method for high-speed interconnection and multi-channel data synchronization between a data transmission chip and an FPGA chip, as shown in one embodiment. Detailed Implementation

[0008] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0009] In one embodiment, such as Figure 1 As shown, a method for high-speed chip interconnection and multi-channel data synchronization based on FPGA is provided, including the following steps: Step 102: Configure the data sending end to output multiple parallel benchmark test data to the FPGA. The FPGA includes multiple high-speed receiving modules, multiple buffer modules, shift control modules and counting modules. After receiving multiple parallel data, the high-speed receiving modules transmit them to the corresponding buffer modules for storage.

[0010] Benchmark test data refers to standardized data used for multi-channel synchronous benchmark comparison, which is usually a stable and repeatable sequence (such as a PRBS11 pseudo-random sequence); the high-speed receiving module is the core component in the FPGA used to receive high-speed parallel data (such as the GTY module), adapting to the high-bandwidth data transmission requirements; the buffer module is a component used to temporarily store the received data of the corresponding channel (such as a FIFO) to avoid overflow or delay during data transmission; the shift control module is the control core in the FPGA responsible for issuing shift adjustment commands and coordinating the synchronous actions of each module; the counting module is a functional module used to calculate the data offset between channels, providing data basis for shift adjustment.

[0011] It is understandable that by configuring unified benchmark test data, a consistent comparison basis is provided for subsequent offset calculations, avoiding synchronization errors caused by benchmark differences. The corresponding configuration of the high-speed receiving module and the buffer module ensures stable reception and storage of multi-channel parallel data, providing complete data support for subsequent synchronization processing. This solves the problems of easy data loss and uneven latency during multi-channel data transmission, laying the foundation for synchronization adjustment.

[0012] Step 104: Select the master channel from the multiple parallel channels, and use the master channel data stored in the cache module as a reference to calculate the offset of each slave channel data stored in the other cache modules through the counting module.

[0013] The primary channel refers to the channel selected from multiple parallel channels as the synchronization reference, and its data timing serves as the alignment standard for other channels. The secondary channel refers to the other channels besides the primary channel that need to be aligned with the primary channel's data timing. The offset refers to the time misalignment difference (CNT) between the data of each secondary channel and the data of the primary channel, which directly reflects the degree of data synchronization deviation.

[0014] Step 106: When the offset is greater than or equal to the first threshold, the corresponding cache module is controlled by the shift control module to perform byte-level shift adjustment.

[0015] The first threshold refers to the critical value that distinguishes between byte-level coarse adjustment and bit-level fine adjustment, and is used to determine the processing method of offset; byte-level shift adjustment refers to the adjustment of data storage and output timing on a byte-by-byte basis, which is achieved by controlling the read or write empty operation of the cache module and is suitable for processing large offsets.

[0016] Step 108: When the offset is less than the first threshold, the corresponding high-speed receiving module is controlled by the shift control module to perform bit-level fine shift adjustment until the offset meets the synchronization threshold.

[0017] Synchronization threshold refers to the critical value for determining whether data has reached a synchronized state. That is, the offset must be reduced to below this value to be considered as synchronized. Bit-level fine shift adjustment refers to the precise adjustment of data reception timing in units of bits, with each shift step being 1 bit, which is suitable for handling small offsets. RXSLIDE shift function is a bit-level shift function built into the high-speed receiver module, providing hardware support for fine adjustment.

[0018] It is understandable that for tiny offsets less than the first threshold, bit-level fine shift adjustment can accurately eliminate residual deviations, ensure that the timing of data in each channel is completely aligned, and solve the problem that byte-level adjustment cannot handle tiny offsets. By implementing bit-by-bit adjustment through the RXSLIDE function, synchronization accuracy is guaranteed, meeting the high-precision requirements of data synchronization in fields such as high-end computing and radar signal processing, and providing time-consistent data input for subsequent collaborative operations.

[0019] Step 110: Switch the data sending end to output preset verification data. When the output data of the corresponding cache module of each channel is consistent with the verification data, multi-channel synchronization is completed.

[0020] Preset verification data refers to standardized fixed data used to verify the synchronization results. Its uniformity ensures the accuracy of the verification. Verification data consistency means that the data output by each channel cache module is completely matched with the preset verification data, which is the core criterion for determining whether synchronization is complete.

[0021] By switching preset verification data for consistency verification, a closed-loop control of adjustment-verification is formed, avoiding the misjudgment problem caused by relying solely on offset to determine synchronization. Synchronization is only confirmed when all channel data is consistent with the verification data, ensuring the reliability of the synchronization result. This solves the problem of incomplete synchronization caused by no verification after adjustment in traditional synchronization methods, and ultimately provides stable aligned data for subsequent data processing modules, ensuring the correctness of collaborative operations.

[0022] In the aforementioned FPGA-based high-speed chip interconnect multi-channel data synchronization method, multiple high-speed receiving modules and buffer modules of the FPGA receive and store the multi-channel parallel benchmark test data output from the data transmitter, laying a stable data foundation for multi-channel synchronization. Using the master channel data as a benchmark, the offset of each slave channel data is accurately calculated by the counting module, clarifying the target and direction of synchronization adjustment. A step-wise adjustment strategy is adopted for the offset magnitude: when the offset is large, the shift control module controls the buffer module to perform byte-level shift adjustment; when the offset is small, the high-speed receiving module performs bit-level fine shift adjustment. This effectively eliminates timing offsets of varying degrees, ensuring that the offset meets synchronization requirements. Furthermore, by switching preset verification data to check the consistency of each channel output, the synchronization effect can be accurately confirmed. This embodiment of the invention effectively solves the time misalignment problem caused by transmission delay in multi-channel parallel data, achieving precise synchronization of multi-channel data. It provides stable and aligned input data for collaborative computing in fields such as high-end computing and high-speed data acquisition, significantly improving the reliability and correctness of subsequent data processing modules.

[0023] In one embodiment, the benchmark data is a pseudo-random sequence; the pseudo-random sequence includes PRBS11, which is used to provide a stable and repeatable comparison benchmark for the counting module to calculate the offset.

[0024] In one embodiment, controlling the corresponding cache module to perform byte-level shift adjustment through the shift control module includes: the shift control module outputting a read / write control signal to the corresponding cache module based on the offset value fed back by the counting module; the cache module responding to the read / write control signal, performing a read-empty or write-empty operation, and gradually reducing the offset by adjusting the timing interval between data storage and output.

[0025] In one embodiment, controlling the corresponding high-speed receiving module to perform bit-level fine shift adjustment through the shift control module until the offset meets the synchronization threshold includes: the shift control module sends a shift instruction to the high-speed receiving module according to the offset fed back by the counting module, and controls the built-in RXSLIDE shift function of the high-speed receiving module to adjust the data reception timing bit by bit, with each shift step being 1 bit, until the counting module detects that the offset has dropped to the synchronization threshold.

[0026] In one embodiment, switching the output of preset verification data at the data transmitter includes: when the counting module detects that the offset of each slave channel meets the synchronization threshold, it sends a data switching command to the data transmitter through the shift control module; the data transmitter responds to the data switching command, stops outputting benchmark test data, and switches to outputting unified preset verification data; the preset verification data is a fixed combination of values, and its lower 16 bits are 0xABCD.

[0027] In one embodiment, when the output data of the cache modules corresponding to each channel are consistent with the verification data, multi-channel synchronization is achieved by: reading the output data of each cache module channel by channel through the counting module, comparing the data of each channel with the preset verification data, and feeding back the comparison result of each channel to the shift control module in real time; when the shift control module receives that the comparison results of each channel are consistent, the shift adjustment process is terminated and multi-channel synchronization is achieved; if the comparison result of any channel is inconsistent, the shift control module controls the corresponding high-speed receiving module to re-execute bit-level fine shift adjustment until the counting module detects that the data of each channel are consistent with the verification data.

[0028] In one embodiment, the method further includes: after completing multi-channel synchronization, sending a service mode switching instruction to the data sending end through the shift control module to control the data sending end to switch back to the service data output mode; and the buffer module corresponding to each channel outputs service data according to the synchronized timing.

[0029] In one specific embodiment, such as Figure 2 The diagram illustrates a framework for a high-speed interconnection and multi-channel data synchronization FPGA implementation method between a data transmission chip and an FPGA chip. The method includes a data transmission chip, a control module, a GTY module, a FIFO module, and a counting module. The data transmission chip can output N channels of data, which are received via N GTY channels and then transmitted to the FIFO. The counting module counts the offset between the master and slave channels and feeds this count back to the control module. The control module executes a control strategy based on the CNT value. The number of channels can be modified according to specific requirements, and the test data pattern can also be configured.

[0030] like Figure 3The diagram shows a control flowchart for an FPGA implementation method of high-speed interconnection between a data transmission chip and an FPGA chip for multi-channel data synchronization. The entire synchronization process is as follows: Data is sent from the data transmission chip and transmitted to the FPGA via the high-speed port GTY. One of the N channels is selected as the master channel and used as the synchronization reference for other channels. The offset between the channel and the master channel is compared, and the offset CNT is recorded and output to the control module. First, it is determined whether CNT is less than 64. If it is greater than 64, the FIFO is controlled to perform byte-level shifting until CNT is less than 64. Then, it is determined whether CNT is equal to 0. If it is not equal to 0, the rxslide of GTY is controlled to perform bit-level shifting until CNT is 0. Then, the data transmission chip is switched to send data as PATTERN (set to 0xABCD in this case), and the read data is determined whether it is 0xABCD. If it is not 0xABCD, bit-level shifting is performed until the output is 0xABCD. At this point, the synchronization is completed.

[0031] Taking a channel number N of 16 as an example, the method of the present invention will be described. The number of channels can be backward compatible or upward expandable. The initial data sent by the data transmission chip is prbs11, and the subsequent switching test data is 0xABCD.

[0032] Step 1: Start the device and switch the data transmission chip output to prbs11. The data enters the FPGA through GTY. Step 2: Instantiate 16 FIFOs with a bit width of 64 bits to receive downlink data from GTY.

[0033] Step 3: The 16 FIFO output data enter the counting module. Based on the main channel, the offset CNT between each slave channel and the main channel is recorded, and this CNT is fed back to the control module.

[0034] Step 4: The control module determines whether the value of CNT is greater than 64. If it is greater than 64, it controls the FIFO's read / write signals to perform a read or write operation on the FIFO, achieving byte-level shifting and causing the value of CNT to decrease. If CNT is less than 64, the control module controls the GTY's rxslide port to perform bit-level shifting of the data until CNT equals 0. When CNT equals 0, the control module switches the data transmission chip's data to the test pattern and reads from the counting module whether the output data is the pattern. If it is not the pattern, it continues bit-level shifting until the output is the correct test pattern. Synchronization is now complete.

[0035] It is understood that the method of this invention aims to provide stable synchronous data for subsequent data processing and improve the reliability and correctness of the post-processing module. Its core process is as follows: First, the data transmission chip is configured to output data as PRBS11 (cycle 2047). The master channel is selected from N channels, and the offset CNT between each slave channel and the master channel is calculated. When CNT ≥ 64, byte-level shifting is performed by controlling the FIFO to write empty until CNT < 64. If CNT ≠ 0, bit-level shifting is performed using the RXSLIDE function of the xxFPGA until CNT = 0. Then, the data transmission chip outputs the lower 16 bits as a specified pattern of 0xABCD. Synchronization is successful when the lower 16 bits of the FIFO outputs from each channel are consistent. In this method, the number of channels N is configurable (default 16), the data bit width of each channel is 64 bits, and related parameters and clock frequencies can be flexibly adjusted. It supports synchronous operation of N (N>0) channels, is suitable for different clock and channel number scenarios, and has good backward compatibility and scalability.

[0036] It should be understood that, although Figure 1 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0037] In one embodiment, an FPGA-based high-speed chip interconnect multi-channel data synchronization system is provided, comprising: The data transmitter and the FPGA; the FPGA includes multiple high-speed receiving modules, multiple buffer modules, shift control modules, and counting modules; The data transmitter is used to output multi-channel parallel benchmark test data, and also to switch to output preset verification data; The high-speed receiving module is connected to the corresponding data sending end and is used to receive multiple parallel data streams and transmit them to the corresponding buffer module. The buffer module is used to store the received data of the corresponding channel and to perform byte-level shift adjustments in response to the control of the shift control module; The counting module is used to calculate the offset of the data stored in the cache module corresponding to each slave channel based on the data stored in the cache module corresponding to the main channel, and feeds back the offset to the shift control module. The shift control module is used to receive control data from each slave channel in real time. When the offset is greater than or equal to the first threshold, it controls the corresponding buffer module to perform byte-level shift adjustment. When the offset is less than the first threshold, it controls the corresponding high-speed receiving module to perform bit-level fine shift adjustment until the offset meets the synchronization threshold. Multi-channel synchronization is completed when the output data of the cache modules corresponding to all channels are consistent with the preset verification data.

[0038] Specific limitations regarding the FPGA-based high-speed interconnect multi-channel data synchronization system can be found in the limitations of the FPGA-based high-speed interconnect multi-channel data synchronization method described above, and will not be repeated here. Each module in the aforementioned FPGA-based high-speed interconnect multi-channel data synchronization system can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware or independently of the processor in a computer device, or stored in software in the memory of the computer device, so that the processor can call and execute the corresponding operations of each module.

[0039] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0040] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A method for FPGA-based chip high-speed interconnection multi-channel data synchronization, characterized in that, The method comprises: The method comprises: The method comprises: When the offset is greater than or equal to the first threshold, the corresponding cache module is controlled by the shift control module to perform byte-level shift adjustment; When the offset is less than the first threshold, the corresponding high-speed receiving module is controlled by the shift control module to perform bit-level fine shift adjustment until the offset meets the synchronization threshold; The data sending end outputs preset verification data, and when the output data of the cache modules corresponding to each channel are all consistent with the verification data, multi-channel synchronization is completed.

2. The method of claim 1, wherein, The data sending end outputs preset verification data, and when the output data of the cache modules corresponding to each channel are all consistent with the verification data, multi-channel synchronization is completed. The data sending end outputs preset verification data, and when the output data of the cache modules corresponding to each channel are all consistent with the verification data, multi-channel synchronization is completed. The method further comprises:

3. The method of claim 1, wherein, After multi-channel synchronization is completed, a service mode switching instruction is sent to the data sending end by the shift control module to control the data sending end to switch back to a service data output mode; The cache modules corresponding to each channel output service data according to the synchronized timing. The method further comprises: The shift control module outputs read-write control signals to the corresponding cache module according to the offset value fed back by the counting module; 4. The method of claim 1, wherein, The cache module responds to the read-write control signals to perform a read-empty or write-empty operation, and gradually reduces the offset by adjusting the timing interval of data storage and output. The shift control module outputs read-write control signals to the corresponding cache module according to the offset value fed back by the counting module; The cache module responds to the read-write control signals to perform a read-empty or write-empty operation, and gradually reduces the offset by adjusting the timing interval of data storage and output.

5. The method of claim 1, wherein, ​ ​ ​ 6. The method of claim 1, wherein, ​ The shift control module sends a shift instruction to the high-speed receiving module according to the offset fed back by the counting module, controls the RXSLIDE shift function built in the high-speed receiving module to adjust the data receiving timing bit by bit, and the shift step is 1 bit each time until the counting module detects that the offset decreases to a synchronization threshold.

7. The method of claim 1, wherein, The reference test data is a pseudo-random sequence; the pseudo-random sequence includes PRBS11, which is used to provide a stable and repeatable comparison reference for the counting module to calculate the offset.

8. A multi-channel data synchronization system based on FPGA chip high-speed interconnection, characterized in that, The system includes a data sending end and an FPGA; the FPGA includes a plurality of high-speed receiving modules, a plurality of cache modules, a shift control module, and a counting module. The data sending end is configured to output multiple parallel reference test data and switch to output preset verification data. The high-speed receiving module is connected with the data sending end, and is configured to receive the multiple parallel data and transmit the data to the corresponding cache module. The cache module is configured to store the received data of the corresponding channel and perform byte-level shift adjustment in response to the control of the shift control module. The counting module is configured to take the data stored in the cache module corresponding to the master channel as a reference, calculate the offset of the data stored in the cache module corresponding to each slave channel, and feed back the offset to the shift control module. The shift control module is configured to receive the control amount data of each slave channel in real time, control the corresponding cache module to perform byte-level shift adjustment when the offset is greater than or equal to a first threshold, control the corresponding high-speed receiving module to perform bit-level fine shift adjustment when the offset is less than the first threshold, and stop until the offset meets a synchronization threshold. When the data output by the cache modules corresponding to all channels are consistent with the preset verification data, the multi-channel synchronization is completed.

9. The system of claim 8, wherein, The high-speed receiving module is built-in RXSLIDE shift function, and the shift control module is signal connected with the high-speed receiving module. The shift control module sends a shift instruction to the high-speed receiving module according to the real-time offset fed back by the counting module, controls the RXSLIDE shift function to adjust the data receiving timing bit by bit, and the shift step is 1 bit each time.

10. The system of claim 8, wherein, The preset verification data is a fixed numerical combination, and the low 16-bit data is 0xABCD.

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