Embedded flash memory controller, chip system and computer readable storage medium

Abstract

The invention provides an embedded flash memory controller, a chip system and a computer readable storage medium, and belongs to the technical field of semiconductors. In the embedded flash memory controller, a cache module can continuously read and cache startup data with a fixed length in a first-in first-out cache mode under the control of a quick startup instruction, namely in a quick startup mode; and under the control of a non-quick start instruction, namely in a normal mode, reading and caching non-start data in a cache mode. Therefore, adaptive caching modes can be flexibly selected according to different scenes, the reading speed of the starting data is improved to ensure quick starting, and the reading speed of conventional non-starting data is optimized to ensure efficient operation. Therefore, the upper limit of the reading speed can be broken through, and the high-speed reading requirement of the chip is met.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to an embedded flash memory controller, chip system, and computer-readable storage medium. Background Technology

[0002] Embedded flash memory (Eflash) is a storage medium that is directly embedded inside a chip. Due to its advantages such as high integration, fast read speed, low power consumption and high security, it is widely used in various chips (such as automotive-grade chips and consumer-grade chips). Summary of the Invention

[0003] An embedded flash memory controller, chip system, and computer-readable storage medium are provided to improve the read speed of Eflash. The technical solution is as follows: On the one hand, an embedded flash memory Eflash controller is provided, wherein the Eflash controller is connected to at least two Eflashes, and the Eflash controller includes: a control module, a cache module, and a protocol conversion module; The control module is configured to: receive operation instructions, generate timing control signals according to the operation instructions, and send the timing control signals to the Eflash; The caching module is configured to: receive a fast boot command or a non-fast boot command; and in response to the fast boot command, continuously read and cache a fixed length of boot data from the Eflash using a first-in-first-out (FIFO) caching method, and send the boot data to the protocol conversion module; or in response to the non-fast boot command, read and cache non-boot data from the Eflash using a high-speed caching (Cache) method, and send the non-boot data to the protocol conversion module. The protocol conversion module is used to: receive data from the cache module and perform protocol conversion on the received data.

[0004] Optionally, the Eflash controller further includes: a configuration module; The configuration module is used to send the fast startup instruction or the non-fast startup instruction to the cache module.

[0005] Optionally, it is also used to: implement at least one of the following operations on the Eflash through register configuration: read, program, erase operation, or record the operating status of the Eflash controller.

[0006] Optionally, it is also used to: send the operation command to the control module.

[0007] Optionally, the caching module includes: a FIFO cache controller and a FIFO cache data storage; The FIFO cache controller is configured to: receive the fast boot command, and in response to the fast boot command, continuously read a fixed length of boot data from the Eflash using the FIFO caching method, and cache the boot data in the FIFO cache data storage.

[0008] Optionally, the caching module further includes: a FIFO cache monitor; The FIFO cache monitor is used to monitor the caching status executed by the FIFO cache controller.

[0009] Optionally, the caching module includes: a Cache controller and a Cache data storage; The Cache controller is configured to: receive the non-fast boot instruction, and in response to the non-fast boot instruction, read non-boot data from the Eflash using the Cache method, and cache the non-boot data in the Cache data storage.

[0010] Optionally, the caching module further includes: a cache monitor; The cache monitor is used to monitor the caching status executed by the cache controller.

[0011] Optionally, in the caching module, the FIFO cache data storage for caching the startup data and the Cache data storage for caching the non-startup data are shared.

[0012] Optionally, the caching module further includes: a selector; The selector is configured to: in response to the fast start instruction, select to read cached data via the FIFO cache controller in the cache module; and in response to the non-fast start instruction, select to read cached data via the Cache controller in the cache module.

[0013] Optionally, the control module includes: an instruction parsing unit, and at least two interface control units corresponding one-to-one with the at least two Eflashes; The instruction parsing unit is configured to: receive the operation instruction, parse the operation instruction, and send it to each of the interface control units; Each of the interface control units is configured to: generate a corresponding timing control signal based on the parsed operation instruction, and send the timing control signal to the corresponding Eflash to control the corresponding Eflash to execute the operation indicated by the operation instruction.

[0014] Optionally, the instruction parsing unit is further configured to: upon receiving multiple operation instructions, perform priority arbitration on the multiple operation instructions based on priority rules to determine the execution order of the multiple operation instructions; Each of the interface control units is configured to: control the corresponding Eflash to sequentially execute the operations indicated by each of the plurality of operation instructions according to the execution order determined by the instruction parsing unit.

[0015] Optionally, the instruction parsing unit is further configured to: perform statistical monitoring on the execution status of the operation instructions.

[0016] Optionally, the protocol conversion module is further configured to: perform error monitoring on the received data and perform protocol conversion on the data that has passed the error monitoring.

[0017] Optionally, the data received by the protocol conversion module carries an error correction code (ECC); the protocol conversion module is used to: perform ECC monitoring on the received data.

[0018] Optionally, the protocol conversion module is connected to the system bus via the Advanced Extensible Interface (AXI); The protocol conversion module is used to convert the received data to the AXI protocol.

[0019] On the other hand, a chip system is provided, the chip system comprising: at least two Eflashes, a system bus, and an Eflash controller as described in one aspect above; The Eflash controller is connected to the at least two Eflashes and the system bus respectively, and is used to realize data interaction between the at least two Eflashes and the system bus.

[0020] In another aspect, a computer-readable storage medium is provided, wherein at least one piece of program code is stored therein, the at least one piece of program code being loaded and executed by a processor to cause a computer to perform the following operation: enabling data interaction between at least two Eflashes and the system bus via an Eflash controller as described in the above aspect.

[0021] In summary, the technical solution provided in this application can bring at least the following beneficial effects: An embedded flash memory controller, a chip system, and a computer-readable storage medium are provided. In this embedded flash memory controller, the cache module can continuously read and cache a fixed length of startup data using a first-in, first-out (FIFO) cache method under the control of a fast startup instruction (i.e., when entering fast startup mode); and under the control of a non-fast startup instruction (i.e., when entering normal mode), it uses a high-speed cache method to read and cache non-startup data. Therefore, an appropriate caching method can be flexibly selected for different scenarios, improving the startup data read speed to ensure fast startup, and optimizing the read speed of regular non-startup data to ensure efficient operation. In this way, the upper limit of read speed can be broken, meeting the high-speed read requirements of the chip. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram of the structure of an embedded flash memory controller provided in an embodiment of this application; Figure 2 This is a schematic diagram of another embedded flash memory controller provided in an embodiment of this application; Figure 3 This is a schematic diagram of another embedded flash memory controller provided in the embodiments of this application; Figure 4 This is a schematic diagram of another embedded flash memory controller provided in the embodiments of this application; Figure 5 This is a schematic diagram of the structure of a chip provided in an embodiment of this application. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings. First, the key terms involved in the embodiments of this application will be briefly introduced: Eflash, as described in the background, is a non-volatile storage medium directly integrated inside a chip, featuring high integration, fast data read speed, low power consumption, and strong storage security.

[0025] Advanced eXtensible Interface (AXI): This is an interface for high-speed data transmission between modules within a chip, featuring high bandwidth, low latency, support for burst transmission, and multi-master / slave device connections.

[0026] First In First Out (FIFO) is a storage structure that follows the rule of "data is retrieved first if it is stored first". The core principle is that the order of data storage and retrieval is strictly consistent, and there is no disorder or "cutting in line" situation.

[0027] Error-Correcting Code (ECC) is an encoding technology that can automatically detect and correct errors that occur during data transmission or storage. The core of it is to calculate the check bit, or ECC, from the original data using a preset algorithm (such as Hamming code), and then add the ECC to the original data to establish a correspondence between the data and the ECC, thereby realizing error correction based on the ECC.

[0028] Advanced Peripheral Bus (APB) is a lightweight connection bus designed specifically for low-speed, low-bandwidth control peripherals within a chip, primarily used for data interaction with external devices.

[0029] Currently, both automotive-grade and consumer-grade chips typically include Eflash and an Eflash controller, which work together to read and store data. Furthermore, automotive-grade chips, directly related to driving safety, require significantly higher Eflash read speeds than consumer-grade chips. However, current Eflash read speeds have a fixed upper limit, which cannot meet the high-speed reading requirements of specialized chips like automotive-grade ones. Therefore, this application provides a high-speed Eflash controller that can work with the Eflash to maximize the read speed of different types of data, without being limited by the upper limit of the Eflash read speed.

[0030] Figure 1 This is a schematic diagram of the structure of an embedded flash memory Eflash controller provided in an embodiment of this application. Figure 1 As shown, the Eflash controller connects to at least two Eflashes, and the Eflash controller includes: a control module 01, a cache module 02, and a protocol conversion module 03.

[0031] Control module 01 is used to: receive operation instructions, generate timing control signals according to the operation instructions, and send the timing control signals to Eflash.

[0032] Optionally, the operation instructions can come from devices such as the Central Processing Unit (CPU) or the main controller. These devices can send operation instructions to the control module 01 according to the system requirements of the chip. That is, the operation instructions can come from operation requests sent by external devices. Furthermore, the operation instructions can be pre-configured or configured in real time, and can be configured in internal registers.

[0033] Optionally, the operation instructions may include: Read, Program (or Write), and Erase instructions. Read can be used to instruct the reading of data from a specified address in the Eflash; Program can be used to instruct the writing of data to the Eflash; and Erase can refer to clearing data from a specified block in the Eflash. Of course, this is for illustrative purposes only, and the operation instructions are not limited to these.

[0034] Furthermore, in this embodiment, after receiving an operation command, the control module 01 can convert the operation command into a signal that the Eflash can understand before transmitting it to the Eflash. This is called a timing control signal, which generally includes high / low levels or pulses. Of course, the operation command can also carry an identifier that indicates the identity of the Eflash, so that the control module 01 can control the operation of at least two Eflashes corresponding to the identifier. After receiving the timing control signal, the Eflash can reliably execute the operation indicated by the operation command received by the control module 01, such as reading, programming, or erasing. That is, the timing control signal sent by the control module 01 to the Eflash can control the Eflash to perform the operation indicated by the operation command.

[0035] The cache module 02 is used to: receive a fast boot command or a non-fast boot command, and in response to the fast boot command, continuously read and cache a fixed length of boot data from the Eflash using a first-in-first-out (FIFO) caching method, and send the boot data to the protocol conversion module 03; or, in response to the non-fast boot command, read and cache non-boot data from the Eflash using a high-speed cache method, and send the non-boot data to the protocol conversion module 03.

[0036] Optionally, fast startup instructions and non-fast startup instructions can also come from the CPU, main controller, or external devices, and can be pre-configured or configured in real time, and can be configured in internal registers.

[0037] Understandably, a fast start command is used to instruct the startup process to be completed in the shortest possible time, and is generally applied during the power-on startup phase. A non-fast start command, on the other hand, is generally applied during the normal operation phase after startup is complete. Therefore, a fast start command can also refer to configuring a fast start mode; a non-fast start command can also refer to configuring a normal mode. In this way, fast start mode and normal mode can be flexibly switched according to the current stage. For example, it can switch to fast start mode at the initial startup stage, and automatically exit fast start mode and enter normal mode after startup is complete.

[0038] It's also understandable that startup data refers to critical data such as programs and parameters necessary for the chip to boot reliably and normally. Non-boot data, on the other hand, refers to regular data generated after the chip starts up, such as application data.

[0039] Furthermore, in this embodiment, when the caching module 02 receives a fast startup command, i.e., when configured in fast startup mode, it can select FIFO caching mode to read and cache startup data. When the caching module 02 receives a non-fast startup command, i.e., when configured in normal mode, it can select Cache mode to read and cache startup data.

[0040] The difference between FIFO caching and Cache caching is that: In FIFO (First-In, First-Out) caching, the inherent first-in, first-out principle is utilized to quickly read and cache a fixed area and length of data in a single, continuous manner, achieving fast data access regardless of access frequency. In other words, in FIFO caching, data, regardless of priority or frequency of access, is read and cached quickly according to a strict first-in, first-out order. Thus, in fast startup mode, by using FIFO caching to quickly cache startup data, the goal of fast power-on can be achieved, prioritizing startup speed. Furthermore, FIFO caching is generally temporary; that is, cached data is cleared after being read and is not retained indefinitely.

[0041] In cache mode, data is typically cached dynamically on demand. For example, when reading data, it can first check if the data is already stored in cache module 02, also known as checking if the cache has been hit. If the data is not stored or has missed, the data is then read from the Eflash and cached. If the data is already stored or has been hit, the data can be read directly from cache module 02, saving the time spent accessing the Eflash. That is, caching can be based on a hit mechanism, where data is only read from the Eflash and cached when it is accessed and missed, which can be triggered by actual access needs. Furthermore, in cache mode, frequently accessed data is typically read and cached first, exhibiting randomness. Thus, in normal mode, by using cache mode to cache non-boot data, non-boot data can be dynamically cached on demand, reducing the frequency of accessing the Eflash, thereby improving data read speed and reducing Eflash power consumption.

[0042] In this embodiment, by flexibly selecting the appropriate caching method to read cached data in different scenarios, not only can the reading speed of startup data be effectively improved, but the reading speed of regular non-startup data can also be optimized, achieving the goal of fast startup and efficient operation. Furthermore, since the Eflash controller provided in this embodiment is connected to multiple Eflashes, data in these multiple Eflashes can be read simultaneously and in parallel, thereby further improving the data reading speed.

[0043] Protocol conversion module 03 is used to receive data from cache module 02 and perform protocol conversion on the received data.

[0044] Optionally, considering that the data protocols between different modules (e.g., the internal devices of the Eflash controller and the external devices connected to the Eflash controller) are often different, direct communication may lead to the inability to identify the data. Therefore, in this embodiment, a protocol conversion module 03 is also provided to convert the received data into a protocol and output it, which can facilitate accurate and efficient transmission of data between devices with different protocols.

[0045] It is understandable that the data received by the protocol conversion module 03 can be data retrieved from the data cached by the cache module 02, or it can be data received from an external device connected to the Eflash controller.

[0046] Based on the above description, in this embodiment, the Eflash controller can use multiple Eflash chips (or multiple Eflash granules) to read simultaneously to improve read speed, and supports both Cache and FIFO caching methods. Specifically, in fast boot mode, the Eflash controller can pre-cache a specified amount of boot data from the Eflash using FIFO caching for fast reading during power-on. Once booting is complete and the system enters normal mode, the Eflash controller can switch back to Cache mode to read other non-boot data. In other words, boot data and non-boot data can be read using different methods. This not only improves the targeted and flexible caching for different types of data but also effectively increases data read speed.

[0047] In summary, this application provides an embedded flash memory controller. In this embedded flash memory controller, the cache module can continuously read and cache a fixed length of startup data using a first-in, first-out (FIFO) cache method under the control of a fast startup instruction (i.e., when entering fast startup mode); and under the control of a non-fast startup instruction (i.e., when entering normal mode), it can read and cache non-startup data using a high-speed cache method. Therefore, an appropriate caching method can be flexibly selected for different scenarios, improving the startup data reading speed to ensure fast startup, and optimizing the reading speed of regular non-startup data to ensure efficient operation. In this way, the upper limit of read speed can be broken, meeting the high-speed read requirements of the chip.

[0048] Optionally, in some embodiments, reference is made to Figure 2 As can be seen, the Eflash controller may also include: configuration module 04.

[0049] The configuration module 04 can be used to send fast start instructions or non-fast start instructions to the cache module 02.

[0050] That is, in the embodiments of this application, the startup instructions, non-start instructions and other instructions described above can be pre-configured in the configuration module 04 inside the Eflash controller so that the cache module 02 can directly call the corresponding instructions from the configuration module 04. This reduces the control difficulty, speeds up the instruction calling speed, and thus indirectly improves the data reading speed.

[0051] Optionally, in some embodiments, the configuration module 04 can also be used to: implement at least one of the following operations on the Eflash through register configuration: read, program, erase operations, and record the running status of the Eflash controller.

[0052] That is, in this embodiment, the configuration module 04 may include a register-type storage unit. Furthermore, the read, program, and erase operations described above can be pre-integrated into the registers of the configuration module 04. Then, by configuring the register parameters, the Eflash can be controlled to perform the corresponding operations, eliminating the need for additional complex program logic and reducing control difficulty. In addition, when the Eflash controller is working, such as during read, program, and erase operations, the configuration module 04 can also synchronously record relevant information about the operating status (e.g., whether the operation was successful, whether an error occurred, and the type of error) through the registers. This facilitates subsequent status queries or troubleshooting and also prevents conflicts between subsequent operations and the currently executing operation through status feedback, thereby improving the security and reliability of Eflash operations.

[0053] Optionally, in some embodiments, the configuration module 04 can also be used to send operation instructions to the control module 01.

[0054] That is, in the embodiments of this application, the operation instructions described above can also be pre-configured by the configuration module 04 inside the Eflash controller so that when the relevant operation needs to be performed, the configuration module 04 can promptly issue the corresponding operation instructions to the control module 01, thereby instructing the control module 01 to generate an appropriate timing control signal according to the received operation instructions, so as to control the Eflash to execute the operation indicated by the operation instructions quickly and reliably.

[0055] Optionally, refer to Figure 2 It can also be seen that configuration module 04 can be connected to the APB to interact with the CPU. The APB has advantages such as low cost, low complexity, and adaptability to low-speed control, which makes it highly compatible with configuration module 04. Of course, it is not limited to this.

[0056] Optionally, in Figure 2 Based on this, further reference Figure 3 As can be seen, the control module 01 may include: an instruction parsing unit 011, and at least two interface control units 012 corresponding one-to-one with at least two Eflashes. That is, one interface control unit 012 can be set for each Eflash; different interface control units 012 can be set for different Eflashes.

[0057] The instruction parsing unit 011 can be used to receive operation instructions, parse the operation instructions, and send them to each interface control unit 012.

[0058] Each interface control unit 012 can be used to: generate a corresponding timing control signal based on the parsed operation instruction, and send the control signal to the corresponding Eflash to control the corresponding Eflash to execute the operation indicated by the operation instruction.

[0059] That is, in this embodiment, firstly, the instruction parsing unit 011 receives the various operation instructions described above and decodes and parses them to convert them into low-level control signals that the interface control unit 012 can understand. Then, each interface control unit 012 generates a timing control signal for the corresponding Eflash based on the parsed operation instructions. This timing control signal can be directly applied to the Eflash, thereby driving the Eflash to accurately and quickly execute the corresponding operation according to the parsed operation instructions.

[0060] Optionally, in some embodiments, the instruction parsing unit 011 can also be used to: when multiple operation instructions are received, perform priority arbitration on the multiple operation instructions based on priority rules to determine the execution order of the multiple operation instructions.

[0061] Accordingly, each interface control unit 012 can be used to control the corresponding Eflash to sequentially execute the operations indicated by each of the multiple operation instructions according to the execution order determined by the instruction parsing unit 011.

[0062] That is, in this embodiment of the application, when multiple operation instructions are requested simultaneously, the instruction parsing unit 011 can also sort the priorities according to the priority arbitration mechanism, so that the Eflash can execute the corresponding operations in sequence according to the priority order. In this way, orderly management of Eflash operations can be achieved, the timeliness of high-priority operations can be guaranteed, and operation conflicts can be avoided.

[0063] Generally, operations that have a higher impact on system operation have higher priority instructions, and vice versa. For example, read operation instructions have higher priority than erase operation instructions. Accordingly, each interface control unit 012 can control the corresponding Eflash to first execute the read operation indicated by the read operation instruction, and then execute the erase operation indicated by the erase operation instruction.

[0064] Optionally, the priority rules can be pre-configured in a register (e.g., a register in configuration module 04), and correspondingly, the instruction parsing unit 011 can directly call the priority rules from the register. Furthermore, this embodiment does not limit the execution order of the parsing and priority arbitration performed by the instruction parsing unit 011.

[0065] Optionally, in some embodiments, the instruction parsing unit 011 can also be used to: perform statistical monitoring on the execution of operation instructions.

[0066] For example, execution status could include the number of times various operations such as reading, programming, and erasing were performed, as well as their success or failure status. This allows for monitoring of operational behavior. The monitored data can be used by other management modules to optimize Eflash and improve its reliability.

[0067] Optionally, continue to refer to Figure 3 It can be seen that the cache module 02 may include: FIFO cache controller 021 and FIFO cache data storage 022.

[0068] The FIFO buffer controller 021 can be used to: receive a fast boot command, and in response to the fast boot command, continuously read a fixed length of boot data from the Eflash using a FIFO buffering method, and buffer the boot data into the FIFO buffer data memory 022. Correspondingly, the protocol conversion module 03 can receive boot data from the FIFO buffer data memory 022.

[0069] Optionally, continue to refer to Figure 3 As can be seen, the cache module 02 may include: a cache controller 023 and a cache data storage device 024.

[0070] The cache controller 023 can be used to: receive a non-fast boot instruction, and in response to the non-fast boot instruction, read non-boot data from the Eflash in a cache manner, and cache the non-boot data in the cache data storage 024. Correspondingly, the protocol conversion module 03 can receive non-boot data from the cache data storage 024.

[0071] That is, in this embodiment of the application, the startup data can be cached by a dedicated FIFO cache controller 021 using the FIFO caching method, and the non-startup data can be cached by a dedicated Cache controller 023 using the Cache method, so that the two caching methods are independent of each other and do not affect each other.

[0072] Optionally, continue to refer to Figure 3 As can be seen, in cache module 02, the FIFO cache data storage 022 for caching startup data and the Cache data storage 024 for caching non-startup data can be shared. That is, startup data read by FIFO cache controller 021 using FIFO caching and non-startup data read by Cache controller 023 using Cache can both be stored in the same memory. This simplifies the structure and reduces costs.

[0073] Optionally, in some embodiments, the shared memory can be partitioned to cache startup data and non-startup data separately, avoiding interference between the two.

[0074] Optionally, continue to refer to Figure 3 It can be seen that the cache module 02 may also include: FIFO cache monitor 025.

[0075] The FIFO cache monitor 025 can be used to monitor the cache status executed by the FIFO cache controller 021.

[0076] Optionally, the caching status monitored by the FIFO cache controller can refer to, for example, the FIFO cache state, including but not limited to whether data is cached using the FIFO caching method, the amount of cached data, and whether the cache is full. The information monitored by the FIFO cache monitor 025 can be accessed by management modules in devices such as the CPU to adjust the cache in a timely manner.

[0077] Optionally, continue to refer to Figure 3 It can be seen that the cache module 02 may also include: Cache monitor 026.

[0078] Cache monitor 026 can be used to monitor the caching behavior performed by Cache controller 023.

[0079] Optionally, the cache status monitored by the cache controller can refer to the cache status, including but not limited to cache hit data such as the number of hits and misses. The information monitored by the cache monitor 026 can be accessed by management modules in devices such as the CPU to optimize cache strategies in a timely manner.

[0080] Optionally, continue to refer to Figure 3 It can be seen that cache module 02 may also include: selector 027.

[0081] Selector 027 can be used to: select to read cached data via FIFO cache controller 021 in response to a fast start command, and select to read cached data via Cache controller 023 in response to a non-fast start command.

[0082] In other words, selector 027 can be set to select either the FIFO cache controller or the Cache controller to read cached data, ensuring that only one controller uses one caching method to cache data at the same time to avoid conflicts.

[0083] Optionally, continue to refer to Figure 3 As can be seen, in some embodiments, the cache module 02 may also include a cache tag.

[0084] Based on this, the Cache controller 023 can respond to non-fast boot instructions by first identifying the address of the non-boot data to be read through the Cache tag, then reading the non-boot data from the Eflash based on the address, and controlling the Cache data storage 024 to perform cache management of the non-boot data.

[0085] Optionally, in some embodiments, the protocol conversion module 03 can also be used to: perform error monitoring on the received data and perform protocol conversion on the data that has passed the error monitoring.

[0086] In other words, the protocol conversion module 03 is responsible for both converting protocols and monitoring for errors in the received data. It only outputs the data according to the converted protocol or performs protocol conversion and output when no errors are detected. This could be, for example, monitoring for bit-level errors that may occur during data transmission, i.e., the binary bits of the data. This ensures the accuracy and reliability of the data output, thereby improving the operational safety of the chip, especially suitable for automotive-grade chips.

[0087] Optionally, in some embodiments, the data received by the protocol conversion module 03 may carry an error correction code (ECC). Accordingly, the protocol conversion module 03 may be used to perform ECC monitoring on the received data.

[0088] Understandably, ECC monitoring works as follows: First, for the original data (here referring to the data received by the protocol conversion module 03), an additional set of check bits, also known as error-correcting codes (ECC), can be calculated using a specific algorithm (e.g., Hamming codes). This ECC has a strict mathematical relationship with the original data, forming complete encoded data including the original data and the check bits. Then, when the protocol conversion module 03 receives data, it can decode the original data and check bits to verify data integrity. It can also recalculate a new ECC based on the received data and compare it with the ECC of the received original data. If they match, the received data is considered error-free; if they do not match, the received data is considered error-free. Furthermore, during ECC monitoring, the protocol conversion module 03 can directly correct simple errors (e.g., single-bit errors). If it cannot correct these errors, it can report the error. Of course, its functionality is not limited to ECC monitoring.

[0089] Optionally, continue to refer to Figure 3 As can be seen, the protocol conversion module 03 can be connected to the system bus (not shown in the figure) via the advanced extensible interface AXI.

[0090] Correspondingly, the protocol conversion module 03 can be used to convert the received data to the AXI protocol.

[0091] Of course, this is not the only possibility. For example, in some embodiments, the protocol conversion module 03 can also be connected to the system bus via an interface other than AXI, such as the Advanced High-performance Bus (AHB) interface. Accordingly, the protocol conversion performed by the protocol conversion module 03 needs to be replaced with AHB protocol conversion.

[0092] Optionally, referring to the above embodiments, taking the protocol conversion module 03 connected to the system bus via AXI and the configuration module 04 connected to the APB as an example, Figure 4 A schematic diagram of the overall structure of an Eflash controller is shown. (Combined with...) Figure 4 As described above, the Eflash controller may include the following modules: (1) Eflash interface control module (Fmc_If), corresponding to the interface control unit 012 in the control module 01 described above. Accordingly, for multiple Eflashes, multiple corresponding Fmc_If modules can be set. (2) Flash operation instruction parsing module (Fmc_Misc), corresponding to the instruction parsing unit 011 in the control module 01 described above. (3) Data buffer module (Fmc_Read_Ctrl), corresponding to the buffer module 02 described above. (4) AXI protocol conversion module (AXI_Interface), corresponding to the protocol conversion module 03 described above. (5) Configuration module 04 (Fmc_Cfg). In addition, Figure 4 The identifier pfmc_top can refer to the top-level module of the Eflash controller. The following examples summarize the working principles of these modules: (1) Among the multiple Fmc_If, each Fmc_If mainly targets the corresponding Eflash in multiple Eflashes to implement the timing control of various operation instructions. That is, it generates timing control signals according to the operation instructions parsed by Fmc_Misc to control the corresponding Eflash to execute the operation indicated by the parsed operation instructions.

[0093] Optionally, Figure 4 This schematically illustrates a one-to-one correspondence between four Eflash and four Fmc_If, and Figure 4 The four Eflashes are designated Eflash#0, Eflash#1, Eflash#2, and Eflash#3; the four Fmc_Ifs are designated Fmc_If#0, Fmc_If#1, Fmc_If#2, and Fmc_If#3. And, Figure 4The total storage capacity of each Eflash shown is 2 megabytes (MB), comprising 1024 banks. Each bank includes a 128×150 storage array, i.e., 128 rows and 150 columns of storage cells. Furthermore, the data transmitted between each Eflash and its corresponding Fmc_If is 128+22 bits, where 128 refers to the effective data bit width, and 22 bits typically represent address bits or parity bits. The address bits are used to locate the storage cells within the Eflash, and the parity bits are used for data verification (such as ECC error correction). Of course, this is all illustrative. For example, in some embodiments, the storage capacity of each Eflash may be different.

[0094] (2) Fmc_Misc mainly implements instruction parsing for various operation instructions, and can also cooperate with registers to perform priority arbitration for multiple operation instructions, that is, priority sorting, and can also perform statistical monitoring of various operation instructions.

[0095] Optionally, Figure 4 The Fmc_Misc module shown includes the following sub-modules: Command configuration module Cmd_Setcfg, which configures parameters for various operation commands, such as setting execution conditions for read, write, and erase commands; Programming command module Cmd_Program, which executes programming operations and writes data to the Eflash; Power-on reset command module Cmd_Por, which performs a power-on reset operation on the Eflash; Erase command module Cmd_Erase, which performs an erase operation on the Eflash, clearing data from a specified area; Read command module Cmd_Read, which reads data from the Eflash; and Extended read command module Cmd_Eread, which supports special modes or read operations with larger data volumes. The bus arbitration module Fmc_Arb manages access permissions, preventing conflicts caused by multiple modules accessing the flash memory simultaneously. The flash monitoring module flash_Monitor monitors the operational status of the eFlash, such as storage capacity usage. However, these are not the only sub-modules included.

[0096] (3) Fmc_Read_Ctrl mainly implements data caching, and in this embodiment, Fmc_Read_Ctrl has two caching methods: Cache and FIFO. When configured in fast startup mode, FIFO caching can be used to continuously read and cache a fixed length of startup data from the Eflash. When configured in normal mode, Cache can be used to read and cache non-startup data from the Eflash. This ensures both reliable data reading and fast data reading speed.

[0097] Among them, reference Figure 4 As can be seen, Fmc_Read_Ctrl includes the following components: Cache_FIFO_MUX, corresponding to selector 027 in cache module 02 described above; FIFO_Ctrl, corresponding to FIFO cache controller 021 in cache module 02 described above; Cache_Ctrl, corresponding to cache controller 023 in cache module 02 described above; Cache_Data(share), corresponding to FIFO cache data storage 022 & Cache data storage 024 in cache module 02 described above, also known as SRAM; Cache_Tag, corresponding to cache tag in cache module 02 described above; Cache_Monitor, corresponding to cache monitor 026 in cache module 02 described above; and FIFO_Monitor, corresponding to FIFO cache monitor 025 in cache module 02 described above. Furthermore, Cache_FIFO_MUX can be responsible for data transfer to either FIFO_Ctrl or Cache_Ctrl. FIFO_Ctrl is responsible for responding to fast boot commands, continuously reading a fixed length of boot data from Eflash and caching it in Cache_Data(share). Cache_Ctrl is responsible for responding to non-fast boot commands, working with Cache_Tag to implement normal cache functionality. Cache_Monitor is responsible for real-time monitoring of cache hits. FIFO_Monitor is responsible for monitoring the FIFO status.

[0098] Optionally, Figure 4In the FIFO_Ctrl diagram shown, the (128+22bit)×4×512 indicates the data width of the FIFO. 128 bits can represent the effective data width, and 22 bits can represent parity bits (e.g., ECC) or address bits. ×4 indicates four independent FIFO channels, enabling multi-channel parallel data buffering. ×512 indicates that each channel has a storage depth of 512, meaning each channel can temporarily store 512 bytes of the aforementioned width (i.e., 128+22 bits). Figure 4 In the Cache_Ctrl diagram shown, CacheLine#0~511 and (128+22bit)×4 indicate that CacheLine#0~511 represent cache line numbers ranging from 0 to 511, meaning there are 512 cache lines in total. A cache line is the basic unit of data storage in the cache, used to temporarily store read data blocks. 128+22bit represents the data bit width of a single cache line, where 128 represents the effective data bit width and 22 bits represent parity bits (e.g., ECC) or address bits. ×4 indicates that there are 4 independent cache channels, enabling multi-channel parallel data caching. Of course, these parameters are for illustrative purposes only.

[0099] (4) AXI_Interface is mainly responsible for AXI interface protocol conversion and converting AXI interface operations into data cache module operations. It can also read data with ECC for ECC monitoring. AXI_Interface can be connected to Fmc_Read_Ctrl through the ECCCheck (i.e., ECC monitoring) part. This ECC Check can be used to implement ECC monitoring.

[0100] Optionally, Figure 4 In the `AXI_Interface` identifier (addr: 32bit, data: 128bit), `addr: 32bit` indicates that the AXI interface has a 32-bit address bus width, supporting a maximum address space of 2^32, or 4GB, used to specify the address of data in the storage system. `data: 128bit` indicates that the AXI interface has a 128-bit data bus width, processing 128 bits (16 bytes) of data per transmission. Furthermore, `AXI_128bit` on the AXI indicates that the data transmission width of the bus connected to the AXI interface is 128 bits, corresponding to `data: 128bit`. Of course, these parameters are for illustrative purposes only. Figure 4 The axi_if identifier in the middle refers to the signal set identifier of the AXI interface, which is used to connect AXI_Interface and ECC Check to realize the signal interaction between the two.

[0101] (5) Fmc_Cfg mainly implements operations such as reading / programming / erasing Eflash through register configuration, and can also record the running status of Eflash controller.

[0102] Optionally, Figure 4 The Fmc_Cfg module shown includes the following sub-modules: Fmc_Ctrl_Cfg (Flash Controller Configuration Module), which configures core operating parameters of the Eflash controller, such as bandwidth and timing; Fmc_Status (Flash Controller Status Module), which records and provides feedback on the real-time operating status of the Eflash controller, such as whether operations are complete or if errors exist; Bank_Protect (Repository Protection Module), which protects access to the Eflash repository (bank) to prevent unauthorized read / write operations and ensure data security; Apb2apb_Async (Asynchronous APB Bus Bridge Module), which connects to the APB and enables asynchronous communication between different APB buses, supporting 32-bit data transmission (i.e., APB32 as indicated in the diagram); and Reg_Read (Register Read Module), which reads the values ​​of configuration registers or status registers related to the Eflash controller. The register programming module Reg_Program can be used to write parameters to the Eflash controller's configuration registers to configure its operating mode or trigger operations. The register erasure module Reg_Erase can trigger an Eflash erasure operation by writing instructions to specific registers. The power mode module Power_Mode can be used to configure the Eflash controller's power operating mode, such as normal mode or low-power mode, to achieve power management. Of course, it is not limited to the above sub-modules.

[0103] Combination Figure 4 As described above, this application provides a high-speed data reading Eflash controller architecture. The Eflash controller can use an AXI interface, and can adopt different caching methods for different data. It can also use multiple Eflash chips to read simultaneously, resulting in a high data reading speed.

[0104] Different caching methods can be used for different types of data: for fast startup requiring rapid reading of startup data, a FIFO caching method is used for continuous reading at once; for normal mode requiring reading of non-startup data, a cache method is used for normal reading. That is, in fast startup mode, after the Eflash controller powers on, it can pre-cache a specified amount of startup data from the Eflash into the FIFO's SRAM for rapid reading during chip startup; after startup, it can enter cache mode to complete the reading of other data. This architecture offers fast reading speeds and high efficiency.

[0105] In summary, this application provides an embedded flash memory controller. In this embedded flash memory controller, the cache module can continuously read and cache a fixed length of startup data using a first-in, first-out (FIFO) cache method under the control of a fast startup instruction (i.e., when entering fast startup mode); and under the control of a non-fast startup instruction (i.e., when entering normal mode), it can read and cache non-startup data using a high-speed cache method. Therefore, an appropriate caching method can be flexibly selected for different scenarios, improving the startup data reading speed to ensure fast startup, and optimizing the reading speed of regular non-startup data to ensure efficient operation. In this way, the upper limit of read speed can be broken, meeting the high-speed read requirements of the chip.

[0106] This application also provides a chip system. For example... Figure 5 As shown, the chip system includes: at least two Eflashes, a system bus, and an Eflash controller as described above.

[0107] The Eflash controller is connected to at least two Eflashes and the system bus, and is used to realize data interaction between at least two Eflashes and the system bus.

[0108] Optionally, the chip system can be an automotive-grade chip system. That is, it can be an in-vehicle chip used in vehicles. Of course, it is not limited to this. For example, it can also be a consumer-grade chip used in products such as mobile phones and computers.

[0109] It is understandable that, since the chip system has essentially the same technical effect as the aforementioned embedded flash memory controller, for the sake of brevity, the technical effect of the chip will not be described again here.

[0110] This application also provides a computer-readable storage medium. The computer-readable storage medium stores at least one piece of program code, which is loaded and executed by a processor to cause the computer to perform the following operation: implementing data interaction between at least two Eflash flashes and the system bus via an Eflash controller as described above.

[0111] It is understood that the terminology used in the embodiments section of this application is for explaining the embodiments of this application only, and is not intended to limit this application. Unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains.

[0112] For example, the terms "first," "second," or "third," and similar words used in the patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, "an" or "a," and similar words do not indicate a quantity limitation, but rather indicate the presence of at least one. Terms such as "comprising" or "including" mean that the element or object preceding "comprising" covers the element or object listed after "comprising" or "including," and does not exclude other elements or objects. "Above," "below," "left," or "right," etc., are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly. "Connected" or "coupled" refers to an electrical connection. "And / or" indicates that three relationships can exist; for example, A and / or B can represent: A alone, A and B simultaneously, and B alone. The character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0113] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. An embedded flash (Eflash) controller, comprising: The Eflash controller is connected with at least two Eflash, and the Eflash controller comprises a control module, a cache module and a protocol conversion module; The control module is configured to receive an operation instruction and generate a timing control signal according to the operation instruction, and send the timing control signal to the Eflash; The cache module is configured to receive a fast start instruction or a non-fast start instruction, read and cache fixed-length start data from the Eflash in a first-in-first-out (FIFO) cache mode in response to the fast start instruction, and send the start data to the protocol conversion module, or read and cache non-start data from the Eflash in a cache mode in response to the non-fast start instruction, and send the non-start data to the protocol conversion module; The protocol conversion module is configured to receive data from the cache module and perform protocol conversion on the received data.

2. The Eflash controller of claim 1, wherein, The Eflash controller further comprises a configuration module; The configuration module is configured to send the fast start instruction or the non-fast start instruction to the cache module.

3. The Eflash controller of claim 2, wherein, The configuration module is further configured to achieve at least one of the following operations on the Eflash through register configuration: reading, programming, erasing operation, or recording the running state of the Eflash controller.

4. The Eflash controller of claim 2 or 3, wherein, The configuration module is further configured to send the operation instruction to the control module.

5. The Eflash controller of any of claims 1 to 3, wherein, The cache module comprises a FIFO cache controller and a FIFO cache data storage; The FIFO cache controller is configured to receive the fast start instruction and read fixed-length start data from the Eflash in the FIFO cache mode in response to the fast start instruction, and cache the start data in the FIFO cache data storage.

6. The Eflash controller of claim 5, wherein, The cache module further comprises a FIFO cache monitor; The FIFO cache monitor is configured to monitor the caching performed by the FIFO cache controller.

7. The Eflash controller of any of claims 1 to 3, wherein, The cache module comprises a cache controller and a cache data storage; The cache controller is configured to receive the non-fast start instruction and read non-start data from the Eflash in the cache mode in response to the non-fast start instruction, and cache the non-start data in the cache data storage.

8. The Eflash controller of claim 7, wherein, The cache module further comprises a cache monitor; The cache monitor is configured to monitor the caching performed by the cache controller.

9. The Eflash controller of claim 6 or 8, wherein, In the cache module, the FIFO cache data storage that caches the start data and the cache data storage that caches the non-start data are shared.

10. The Eflash controller of claim 6 or 8, wherein, The cache module further comprises a selector; The selector is configured to select the FIFO cache controller in the cache module to read cached data in response to the fast start instruction, and select the cache controller in the cache module to read cached data in response to the non-fast start instruction.

11. The Eflash controller of any of claims 1 to 3, wherein, The control module comprises an instruction analysis unit and at least two interface control units corresponding to the at least two Eflash respectively; The instruction analysis unit is configured to receive the operation instruction, analyze the operation instruction, and send the analyzed operation instruction to each interface control unit; Each interface control unit is configured to generate a corresponding timing control signal according to the analyzed operation instruction, and send the timing control signal to the corresponding Eflash to control the corresponding Eflash to perform the operation indicated by the operation instruction.

12. The Eflash controller of claim 11, wherein, The instruction analysis unit is further configured to, in the case of receiving a plurality of operation instructions, perform priority arbitration on the plurality of operation instructions based on a priority rule to determine an execution order of the plurality of operation instructions. Each interface control unit is configured to control the corresponding Eflash to sequentially perform the operation indicated by each operation instruction in the plurality of operation instructions according to the execution order determined by the instruction analysis unit.

13. The Eflash controller of claim 11, wherein, The instruction analysis unit is further configured to statistically monitor the execution of the operation instruction.

14. The Eflash controller of any of claims 1 to 3, wherein, The protocol conversion module is further configured to perform error monitoring on the received data, and perform protocol conversion on the data passing the error monitoring.

15. The Eflash controller of claim 14, wherein, The data received by the protocol conversion module carries an error correction code ECC; the protocol conversion module is configured to perform ECC monitoring on the received data.

16. The Eflash controller of any one of claims 1 to 3, wherein, The protocol conversion module is connected with a system bus through an advanced extensible interface AXI. The protocol conversion module is configured to perform AXI protocol conversion on the received data.

17. A chip system, characterized by The chip system comprises at least two Eflash, a system bus, and an Eflash controller as claimed in any one of claims 1 to 16. The Eflash controller is connected with the at least two Eflash and the system bus respectively, and is configured to realize data interaction between the at least two Eflash and the system bus.

18. A computer-readable storage medium, characterized in that, The computer readable storage medium stores at least one program code, the at least one program code is loaded and executed by the processor, so that the computer performs the following operations: realizing data interaction between at least two Eflash and a system bus through the Eflash controller as claimed in any one of claims 1 to 16.

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