A method and system for managing information of server peripheral cards

Abstract

This application provides a method and system for managing information of server peripheral cards, relating to the field of computer technology. The method includes: acquiring status information of the expansion carrier and the peripheral cards connected to it based on a microcontroller unit (MCU) in an expansion carrier within the server; transmitting the status information to a storage unit in the server's motherboard via a target bus based on the MCU; the target bus connecting the expansion carrier and the motherboard; and reading the status information from the storage unit based on the Baseboard Management Controller (BMC) in the motherboard. Therefore, status information can be obtained without I2C polling by the BMC, significantly reducing the physical resource consumption of the BMC and improving the real-time performance and efficiency of reading status information from the expansion carrier and peripheral cards.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to an information management method and system for server peripheral cards. Background Technology

[0002] In the hardware architecture of many existing general-purpose servers, the server typically consists of a central processing unit (CPU), memory, hard drives, and external expansion cards. The baseboard management controller (BMC) works in conjunction with the CPU to support the server's operation. To meet the application needs of different customers, server manufacturers typically use RISE cards and server backplanes (BPs) to accommodate various network cards, Redundant Array of Independent Disks (RAID) cards, graphics processing units (GPUs), and hard drives, among other peripheral cards.

[0003] To ensure server stability and maintainability, the BMC needs to communicate with the BP / RISER via I2C to obtain information such as the temperature, model, location, and abnormal status of peripheral cards on the BP / RISER. Typically, each BP / RISER requires a dedicated I2C channel and connector, or multiple BP / RISERs can share a single I2C channel, provided I2C address conflicts are avoided, but usually no more than two BP / RISERs are involved. However, mainstream BMCs on the market only have 12-15 I2C channels. If the server has a large number of BP / RISERs, it is difficult to meet the communication requirements. Furthermore, the BMC can only obtain information from each I2C channel sequentially, resulting in poor real-time information reading and delayed anomaly response. Summary of the Invention

[0004] This application provides a method and system for managing information of server peripheral cards, so as to at least solve the above-mentioned technical problems existing in the prior art.

[0005] According to a first aspect of this application, a method for managing information of server peripheral cards is provided, comprising: acquiring status information of the expansion carrier and peripheral cards connected to the expansion carrier based on a microcontroller unit in an expansion carrier in the server; sending the status information to a storage unit in the motherboard of the server via a target bus based on the microcontroller unit; the target bus being used to connect the expansion carrier and the motherboard; and reading the status information from the storage unit based on a baseboard management controller (BMC) in the motherboard.

[0006] In one embodiment, the server is provided with multiple expansion carriers, which are cascaded together via a target bus. One target expansion carrier is connected to the motherboard via the target bus. The step of sending the status information to the storage unit in the motherboard of the server via the target bus includes: for the microcontroller unit in the target expansion carrier, sending the status information to the storage unit via the target bus; for the microcontroller units in other expansion carriers, sending the status information to the previous expansion carrier connected to it via the target bus, until the status information is sent to the target expansion carrier, and then the target expansion carrier sends the status information to the storage unit.

[0007] In one possible implementation, the step of sending the status information to the storage unit in the motherboard of the server via the target bus includes: responding to the microcontroller detecting that a timing trigger signal issued by the complex programmable logic device (CPLD) of the motherboard satisfies a first condition, determining the bus occupancy period corresponding to the microcontroller based on the DIP switch value of the expansion carrier and the maximum number of expansion carriers in the server; during the bus occupancy period, sending the status information to the storage unit in the motherboard of the server via the target bus; wherein, the first condition is detecting the rising edge of the timing trigger signal and the timing trigger signal being at a high level; the DIP switch value represents the installation position of the expansion carrier in the server.

[0008] In one possible implementation, determining the bus occupancy period corresponding to the microcontroller based on the DIP switch value of the extended carrier and the maximum number of extended carriers in the server includes: determining the ratio of the product of the DIP switch value and the period reference value to the maximum number of extended carriers as the start time of the bus occupancy period; determining the start time corresponding to the microcontroller in the next extended carrier as the end time of the bus occupancy period; or, determining the time when the timing trigger signal does not meet the first condition as the end time of the bus occupancy period.

[0009] In one possible implementation, sending the status information to the storage unit in the motherboard of the server via the target bus includes: determining the storage space corresponding to the expansion carrier in the storage unit based on the total capacity of the storage unit, the maximum number of expansion carriers, and the DIP switch value of the expansion carriers; and writing the status information into the storage space in the storage unit via the target bus.

[0010] In one possible implementation, the starting address of the storage space is determined based on the following formula:

[0011]

[0012] The end address of the storage space is determined based on the following formula:

[0013]

[0014] in, This is the starting address of the storage space. The total capacity of the storage units. This represents the maximum number of the extended carriers. The DIP switch value of the extended carrier. This is the end address of the storage space.

[0015] In one possible implementation, the step of reading the status information from the storage unit based on the Baseboard Management Controller (BMC) in the motherboard includes: controlling the CPLD of the motherboard to pull the issued timing trigger signal to a falling edge and pull the level of the timing trigger signal low based on the BMC; and reading the status information from the storage unit based on the BMC occupying the target bus.

[0016] In one embodiment, a method for managing information of a server peripheral card further includes: in response to the microcontroller detecting an abnormality in the status information, lowering the level of an abnormality warning signal during the bus occupancy period corresponding to the microcontroller; and in response to the BMC detecting that the abnormality warning signal is low, occupying the target bus to read the status information from the storage unit.

[0017] In one embodiment, a method for managing information of a server peripheral card further includes: the BMC triggering an emergency procedure based on the status information; in response to the BMC determining that the emergency status of the extended carrier has been lifted, the warning cancellation signal is lowered to notify the extended carrier to resume normal operation.

[0018] In one embodiment, a method for managing information of a server peripheral card further includes: in response to the microcontroller detecting an abnormal status information, lowering the level of an abnormal warning signal during the bus occupancy period corresponding to the microcontroller; in response to the CPLD of the motherboard detecting that the abnormal warning signal is low and the BMC is in the startup state for a preset duration, adjusting the server fan to its maximum speed; and in response to the CPLD determining that the BMC is in normal operation or the emergency state of the expansion carrier is released, restoring the fan speed.

[0019] According to a second aspect of this application, an information management system for server peripheral cards is provided, comprising:

[0020] Motherboard, at least one expansion device;

[0021] The microcontroller unit in the expansion carrier is connected to the peripheral card via an I2C channel and is used to obtain the status information of the expansion carrier and the peripheral card connected to the expansion carrier.

[0022] The microcontroller unit is connected to the target bus via a bidirectional buffer and to the motherboard via the target bus, and is used to send the status information to the storage unit in the motherboard via the target bus;

[0023] The BMC in the motherboard is connected to the target bus based on a bidirectional buffer and is used to read the status information from the storage unit.

[0024] In one possible implementation, the at least one expansion carrier is cascaded via the target bus, and one of the target expansion carriers is connected to the motherboard via the target bus; the microcontroller unit in the target expansion carrier is further configured to: send the status information to the storage unit via the target bus; the microcontroller units in the other expansion carriers are further configured to: send the status information to the previous expansion carrier connected to them via the target bus, until the status information is sent to the target expansion carrier, and then the target expansion carrier sends the status information to the storage unit.

[0025] In one embodiment, the microcontroller unit is further configured to: receive a timing trigger signal from the CPLD of the motherboard; in response to the timing trigger signal satisfying a first condition, determine a bus occupancy period corresponding to the microcontroller unit based on the DIP switch value of the expansion carrier and the maximum number of expansion carriers in the server; during the bus occupancy period, send the status information to the storage unit in the motherboard of the server via the target bus; wherein, the first condition is detecting the rising edge of the timing trigger signal and the timing trigger signal being at a high level; the DIP switch value characterizes the installation position of the expansion carrier in the server.

[0026] In one embodiment, the microcontroller is further configured to: determine the ratio of the product of the DIP switch value and the periodic reference value to the maximum number of the extended carriers as the start time of the bus occupancy period; determine the start time corresponding to the microcontroller in the next extended carrier as the end time of the bus occupancy period; or determine the time when the timing trigger signal does not meet the first condition as the end time of the bus occupancy period.

[0027] In one embodiment, the microcontroller unit is further configured to: determine the storage space corresponding to the expansion carrier in the storage unit based on the total capacity of the storage unit, the maximum number of expansion carriers, and the DIP switch value of the expansion carriers; and write the status information to the storage space in the storage unit via a target bus.

[0028] In one possible implementation, the microcontroller determines the starting address of the storage space based on the following formula:

[0029]

[0030] The microcontroller determines the end address of the storage space based on the following formula:

[0031]

[0032] in, This is the starting address of the storage space. The total capacity of the storage units. This represents the maximum number of the extended carriers. The DIP switch value of the extended carrier. This is the end address of the storage space.

[0033] In one embodiment, the BMC is further configured to: control the CPLD of the motherboard to pull the issued timing trigger signal to the falling edge and pull the level of the timing trigger signal low; and occupy the target bus to read the status information in the storage unit.

[0034] In one embodiment, the microcontroller unit is further configured to: in response to detecting an abnormality in the status information, pull down the level of the abnormality warning signal during the bus occupancy period corresponding to the microcontroller unit; the BMC is further configured to: in response to detecting that the abnormality warning signal is low, occupy the target bus to read the status information from the storage unit.

[0035] In one possible implementation, the BMC is further configured to: trigger an emergency procedure based on the status information; and, in response to determining that the emergency status of the extended carrier has been lifted, lower the warning cancellation signal to notify the extended carrier to resume normal operation.

[0036] In one embodiment, the microcontroller unit is further configured to: in response to detecting an abnormal status information, pull down the level of the abnormal warning signal during the bus occupancy period corresponding to the microcontroller unit; the CPLD in the motherboard is further configured to: in response to detecting that the abnormal warning signal is low and the BMC is in the startup state for a preset time, adjust the server fan to the maximum speed; the CPLD in the motherboard is further configured to: in response to determining that the BMC is in normal operation or the emergency state of the expansion carrier is released, restore the fan speed.

[0037] This application discloses a method and system for managing information of server peripheral cards. The system collects its own and peripheral card status information through the microcontroller unit of the expansion carrier, actively pushes it to the motherboard storage unit via the target bus, and then the BMC reads and analyzes it. Therefore, status information can be obtained without the BMC polling via I2C, significantly reducing the physical resource consumption of the BMC and improving the real-time performance and efficiency of reading status information of the expansion carrier and peripheral cards.

[0038] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0039] The above and other objects, features, and advantages of exemplary embodiments of this application will become readily apparent upon reading the following detailed description with reference to the accompanying drawings. Several embodiments of this application are illustrated in the drawings by way of example and not limitation, in which:

[0040] In the accompanying drawings, the same or corresponding reference numerals indicate the same or corresponding parts.

[0041] Figure 1 A flowchart illustrating an information management method for a server peripheral card according to an embodiment of this application is shown.

[0042] Figure 2 This illustrates the connection method between the motherboard and the expansion carrier in the prior art;

[0043] Figure 3 A schematic diagram of the structure of the extended carrier in an embodiment of this application is shown;

[0044] Figure 4 A schematic diagram of the motherboard structure in an embodiment of this application is shown;

[0045] Figure 5 This paper illustrates a schematic diagram of the structure of an information management system for a server peripheral card according to an embodiment of this application.

[0046] Figure 6This application illustrates the installation position of the extension carrier in an embodiment of the present application. Figure 1 ;

[0047] Figure 7 This application illustrates the installation position of the extension carrier in an embodiment of the present application. Figure 2 . Detailed Implementation

[0048] To make the objectives, features, and advantages of this application more apparent and understandable, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0049] In related technologies, to ensure stable server operation and maintainability, the BMC needs to communicate with the BP / RISER via I2C to obtain information such as the temperature, model, location, and abnormal status of peripheral cards on the BP / RISER. Typically, each BP / RISER requires its own dedicated I2C channel and connector, or multiple BP / RISERs can share a single I2C channel, provided there are no I2C address conflicts. However, usually no more than two BP / RISERs are used. Due to the large number of BP / RISER cards and the limited number of I2C interfaces, I2C expansion chips are usually added to the motherboard to expand the I2C channels.

[0050] Figure 2 This illustrates the connection method between the motherboard and the expansion carrier in the prior art, such as... Figure 2 As shown, the motherboard includes components such as CPU0, CPU1, and BMC. The BMC connects to BP / RISER0~BP / RISERn via I2C or an I2C expander. J12 is the I2C communication interface between the BP / RISER board and the motherboard. Other components in BP / RISER0~BP / RISERn are similar to those in existing BP / RISER boards. Figure 2 This is not detailed in the text.

[0051] However, this existing solution has significant drawbacks: First, it consumes a large amount of physical I2C channel resources in the BMC, while mainstream BMCs on the market only have 12-15 I2C channels, which is insufficient to meet the needs of high-configuration servers; second, the BMC takes about 2 minutes to start up, and loses its I2C information reading capability during the restart process, resulting in the inability to acquire and record peripheral card temperature, asset, and abnormal information during this period; third, the internal I2C cabling of the server needs to run through the entire machine, with each board corresponding to one cabling path, resulting in complex wiring and increased risk of signal interference; fourth, the BMC is limited by the number of threads and needs to sequentially poll and read each I2C channel. The existing solutions suffer from several drawbacks. First, reading information from a fully configured hard drive can take tens of seconds to several minutes, resulting in poor real-time performance. Second, if a peripheral card experiences temperature anomalies, the BMC may delay its response and execution of emergency logic for tens of seconds. Third, some peripheral cards only publish anomaly information via I2C during specific periods or in the event of a failure. The BMC's polling mechanism can easily lead to the loss of this information, making it extremely difficult to reproduce and analyze card or disk failures. Fourth, in high-configuration servers, BP / RISER processors inevitably share the I2C channel, which can easily lead to I2C address conflicts, causing the solution to fail or the project to be delayed due to conflicts discovered during later verification. To address these shortcomings, this application proposes a method for managing information from server peripheral cards.

[0052] Figure 1 This illustration shows a flowchart of an information management method for a server peripheral card according to an embodiment of this application. Figure 1 As shown, a method for managing information of a server peripheral card includes:

[0053] Step S101: Based on the microcontroller unit in the expansion carrier in the server, obtain the status information of the expansion carrier and the peripheral cards connected to the expansion carrier.

[0054] In this embodiment, the expansion carrier is a BP / RISER, whose core function is to connect peripheral cards such as network cards, RAID cards, GPUs, and hard drives to the server, thereby enriching the server product configuration. The microcontroller unit (MCU) is an independent control module integrated on each expansion carrier. Flexible models with 32 pins or more can be selected, possessing basic functions for data acquisition, processing, and transmission. Status information is key data reflecting the operating status of the expansion carrier itself and the connected peripheral cards, specifically including but not limited to: the hardware model, serial number, and installation location identifier of the expansion carrier; the temperature data, hardware model, firmware version, operating voltage, connection status (whether it is connected normally), and abnormal alarm information (such as fault codes and fault occurrence timestamps) of the peripheral cards.

[0055] In this embodiment, the MCU can establish connections with the communication interfaces of various sensors and peripheral cards on the expansion carrier through its own I2C interface to collect the aforementioned status information in real time. For example, the MCU connects to the temperature sensor on the expansion carrier through the I2C interface to periodically collect the operating temperature of the expansion carrier; at the same time, it communicates with the hard drive connected to the expansion carrier through the I2C interface to obtain information such as the hard drive's model, current temperature, and data read / write status, thereby achieving comprehensive acquisition of the status information of the expansion carrier and peripheral cards.

[0056] Step S102: Based on the microcontroller unit, the status information is sent to the storage unit in the motherboard of the server via the target bus.

[0057] In this embodiment, after the microcontroller completes the acquisition and preliminary processing of status information, it needs to transmit the processed status information to the storage unit of the server motherboard through a preset target bus. The target bus is a communication bus specifically designed to connect the expansion carrier and the motherboard. It consists of 7 signal lines, specifically including 4 Serial Peripheral Interface (SPI) bus lines and 3 General-Purpose Input / Output (GPIO) signal lines. The SPI bus includes the Serial Clock Line (SCLK), Master Output, Slave Input (MOSI), Master Input, Slave Output (MISO), and Chip Select Line (CS). The GPIO signal lines include GPIO1, GPIO2, and GPIO3, which are used to transmit different signals.

[0058] In this embodiment, the storage unit is specifically a FLASH memory chip located on the server motherboard. It possesses non-volatile storage characteristics, enabling long-term storage of received status information. Furthermore, it supports access operations from multiple devices (MCUs and BMCs on multiple expansion carriers), providing centralized physical storage space for status information. The MCU can transmit the status information to the motherboard's memory chip via the target bus, realizing the transfer of status information from the expansion carrier to the storage unit.

[0059] Step S103: Read status information from the storage unit based on the Baseboard Management Controller (BMC) in the motherboard.

[0060] In this embodiment, the BMC is the core management module on the server motherboard, possessing functions such as device monitoring, data reading, and logic control. It connects to the target bus via a BUFFER chip, thereby gaining access to the storage unit. The BMC can initiate a read operation on the status information in the storage unit according to a preset read strategy or in response to specific trigger conditions.

[0061] In one implementation, the status information read by the BMC covers all relevant data of the expansion carriers and corresponding peripheral cards. After reading, the BMC will perform subsequent analysis and processing on this data, such as determining whether there are any anomalies or whether emergency logic needs to be triggered. In one example, the BMC can initiate a read operation at regular intervals (e.g., 30 seconds) to extract the latest status information of all RISER cards, BP cards, and their corresponding peripheral cards from the FLASH memory.

[0062] In this application, the MCU of the expansion carrier collects status information and transmits it to the FLASH memory of the motherboard via the target bus. The BMC reads the stored information from the FLASH memory, achieving efficient management of server peripheral card information. Its specific technical effects are as follows: 1. Reduced BMC physical resource consumption: Compared to the traditional solution where the BMC needs to communicate with each expansion carrier through multiple I2C channels, in this solution, the BMC only needs to interact with the storage unit via the target bus to obtain all status information, without occupying a large amount of I2C channel resources, thus solving the problem of limited BMC I2C channels in the traditional solution; 2. Continuous collection and storage of status information: The MCU of the expansion carrier works independently, unaffected by the BMC's startup status. Even if the BMC is not started (e.g., within 2 minutes after startup) or restarted, the MCU can still normally collect and transmit status information to the storage unit, ensuring continuous status information collection and storage. 1. No information loss, solving the defect in traditional solutions where the BMC cannot obtain information during startup or restart; 2. Simplified internal server wiring: The target bus uniformly connects all expansion carriers to the motherboard, eliminating the need to arrange I2C channels for each expansion carrier, greatly simplifying the internal wiring structure of the server and reducing wiring complexity and hardware design difficulty; 3. Improved real-time performance of information transmission and retrieval: The MCU actively collects and transmits information, and the storage unit centrally stores it. The BMC can directly read data from the storage unit without using a polling method to obtain information one by one, reducing the latency of information acquisition. Especially under complex configurations such as full hard drive configuration, it can still quickly obtain status information.

[0063] To facilitate understanding of this application, the following describes the expansion carrier and motherboard used in this application:

[0064] Figure 3 A schematic diagram of the structure of the extended carrier in an embodiment of this application is shown, such as... Figure 3As shown, the extended carriers (BP / RISER) in this application are all configured with two or more dedicated connectors (such as...) in their interface structure design. Figure 3 The J1 connector uses standardized pin definitions (A1~A7) to enable cascading connections between adjacent BP / RISERs, forming a chain structure. This eliminates the need for all boards to directly interface with the motherboard, greatly simplifying internal server cabling. On the other hand, the connectors reserve connection channels to the target bus, allowing BP / RISER signals to be connected to the target bus, providing a physical link for subsequent data transmission.

[0065] Each BP / RISER integrates a bidirectional BUFFER chip, which connects the MCU to the target bus. The core function of this chip is to enhance signal driving capability. When the BP / RISER interacts with adjacent boards or the motherboard, the bidirectional BUFFER chip can amplify and reshape the attenuated SPI bus signal and GPIO signal to avoid transmission errors caused by excessive cascading distance or signal interference, thus ensuring signal integrity.

[0066] Each BP / RISER is equipped with an MCU (microcontroller unit), which is connected to I2C interface, SPI interface, DIP switch, etc.

[0067] In terms of bus connection structure, both BP / RISER follow the 7-wire bus design standard. The SPI bus (SCLK, MOSI, MISO, and CS) and GPIO signal lines (GPIO1, GPIO2, and GPIO3) are integrated into the connector pins at the edge of the board via PCB routing, ensuring precise connection to the target bus. This bus structure design not only separates data transmission (implemented by the SPI bus) from control signal interaction (implemented by the GPIO signal lines), but also ensures compatibility between different BP / RISERs through fixed pin definitions, facilitating mass production and maintenance.

[0068] Figure 6 This application illustrates the installation position of the extension carrier in an embodiment of the present application. Figure 1 ; Figure 7 This application illustrates the installation position of the extension carrier in an embodiment of the present application. Figure 2 ,like Figure 6 and Figure 7 As shown, the expansion carrier installation area in the server is divided into area A, area B, area C and area D, with a total of 12 card slots.

[0069] Figure 4 A schematic diagram of the motherboard structure in an embodiment of this application is shown, as follows: Figure 4As shown, the motherboard's CPU module (including CPU0 and CPU1, etc.) is set up independently as the computing core, providing basic computing power support for subsequent data processing. At the same time, the motherboard uses the BMC (Baseboard Management Controller) as the management center, and together with the FLASH memory module, it builds a basic control and storage architecture. This centralized management module layout can more efficiently coordinate the operating status of various components on the motherboard.

[0070] In terms of signal transmission and control logic design, the motherboard incorporates a bidirectional buffer chip as a key component for signal relay and enhancement. This chip connects the BMC to modules such as FLASH and external connectors, ensuring stable signal transmission between different components and avoiding signal interference issues caused by direct connection of multiple devices. Simultaneously, the addition of a Complex Programmable Logic Device (CPLD) further refines the control division of labor. It establishes a connection with the BMC via GPIO pins, receiving control signals from the BMC and outputting commands such as start signals. It also monitors and regulates the status of hardware such as the fan module.

[0071] In terms of external expansion and interface architecture, the motherboard interfaces with external BP / RISER boards via a dedicated connector (J1), and all external interaction signals are relayed through a buffer or CPLD. The design of the motherboard-side bus is similar to that of the BP / RISER boards, and will not be described in detail here.

[0072] Each expansion carrier can establish a physical connection with the target bus through two or more connectors, thereby achieving indirect or direct connection with the motherboard. The motherboard interfaces with the target bus through a bus connector, enabling devices such as the flash memory, BMC, and CPLD on the motherboard to interact with the expansion carrier via this bus. For example, a RISE card connects to the target bus through its own connector, and then establishes a communication path with the memory chips on the motherboard through the target bus, ensuring uninterrupted transmission of status information.

[0073] Figure 5 This application illustrates a schematic diagram of the structure of an information management system for a server peripheral card according to an embodiment of the present application. Figure 5 As shown, the information management system for server peripheral cards includes a motherboard and at least one expansion carrier (BP / RISER). Multiple expansion carriers are cascaded together via a target bus. Specifically, cascading means that each expansion carrier establishes a physical connection with adjacent expansion carriers through two or more connectors, forming a chain structure. One target expansion carrier is connected to the motherboard via the target bus. The target expansion carrier is the expansion carrier directly connected to the motherboard, such as... Figure 5The middle part is BP / RISER[0]. It should be emphasized that, Figure 5 Details of other components 0 and other components 1 in BP / RISER[0] and BP / RISER[1] are as follows: Figure 3 Similar to the details of other components 2 in the motherboard, Figure 4 Similar to China, in Figure 5 It will not be displayed in detail here.

[0074] Step S102, "sending status information to the storage unit in the server's motherboard via the target bus," includes:

[0075] For the microcontroller unit in the target extended carrier, the status information is sent to the storage unit via the target bus;

[0076] For the microcontroller unit in other extended carriers, the status information is sent to the previous extended carrier connected to it via the target bus, until the status information is sent to the target extended carrier, and then the target extended carrier sends the status information to the storage unit.

[0077] In this embodiment, after the MCU in the target expansion carrier completes the collection of its own and connected peripheral card status information, it directly connects to the motherboard via the target bus and has the physical condition to directly access the motherboard's memory unit (FLASH). Therefore, it does not need to go through other expansion carriers for relay and can directly transmit the collected status information to the memory unit on the motherboard via the target bus. Figure 5 The BP / RISER[0] in the middle can directly transmit status information to the FLASH storage unit on the motherboard through the target bus.

[0078] In this embodiment, "other expansion carriers" refers to all cascaded expansion carriers other than the target expansion carrier. Since these expansion carriers are not directly connected to the motherboard, the status information they collect cannot be directly transmitted to the motherboard's storage unit. Instead, they need to be relayed through the preceding expansion carrier in the cascade link. The preceding expansion carrier refers to the adjacent expansion carrier that is closer to the target expansion carrier in the cascade link compared to the current expansion carrier. After the MCU in one of the other expansion carriers collects the status information, it sends the status information to the target bus via its own SPI interface. The status information is then transmitted via the target bus to the SPI interface of the preceding expansion carrier connected to it. The MCU of the preceding expansion carrier receives the status information and, without performing any additional processing (or only performing signal shaping, amplification, or other processing to ensure transmission quality), directly forwards the status information to its own preceding expansion carrier via the target bus. This process continues until the data is transmitted to the target expansion carrier. The target expansion carrier receives the status information from the subsequent expansion carrier and sends it to the motherboard's storage unit via the target bus.

[0079] In this application, the scalability and transmission efficiency of server peripheral card information management are further optimized through a cascaded connection design of multiple expansion carriers and a hierarchical transmission scheme for status information based on the cascaded structure. On the one hand, the cascaded connection method eliminates the need to set up a separate physical link between each expansion carrier and the motherboard. Communication between all expansion carriers and the motherboard can be achieved solely through the target bus, significantly reducing the number of internal cables in the server, simplifying the cabling structure, and reducing the complexity of hardware design and manufacturing. On the other hand, by relaying transmission through the previous expansion carrier, the status information of multiple expansion carriers can be transmitted to the target expansion carrier in an orderly manner, avoiding bus conflicts that may occur if multiple expansion carriers are directly connected to the motherboard. This also ensures the stability and reliability of status information transmission, meeting the configuration requirements of multiple expansion carriers and multiple peripheral cards in the server, and improving the applicability and scalability of the entire information management solution.

[0080] In another embodiment, step S102, "sending status information to the storage unit in the server's motherboard via the target bus," includes:

[0081] In response to the microcontroller detecting that the timing trigger signal issued by the complex programmable logic device CPLD on the motherboard meets the first condition, the bus occupancy period corresponding to the microcontroller is determined based on the DIP switch value of the expansion carrier and the maximum number of expansion carriers in the server.

[0082] During the bus occupancy period, status information is sent to the storage unit in the server's motherboard via the target bus;

[0083] The first condition is that the rising edge of the timing trigger signal is detected and the timing trigger signal is at a high level; the DIP switch value represents the installation position of the extension carrier in the server.

[0084] In this embodiment, the Complex Programmable Logic Device (CPLD) is the core logic control module integrated into the server motherboard. It is connected to the GPIO1 signal line in the target bus and is specifically responsible for continuously sending timing trigger signals, namely the BMC_BP_RISER_START_N signal. The frequency of this signal is fixed at 1Hz, which means that a complete high-low level change cycle will be generated every 1 second, providing a unified timing synchronization reference for all extended carrier MCUs.

[0085] Each MCU in the extended carrier is connected to the GPIO1 signal line of the target bus via its own GPIO interface to monitor the timing trigger signal issued by the CPLD in real time. If the rising edge of the timing trigger signal is detected and the timing trigger signal is high, the MCU is triggered to start the bus occupancy period calculation and subsequent data transmission operations, ensuring that all MCUs work together based on a unified timing reference and avoiding transmission chaos.

[0086] The DIP switches for the expansion carriers are hardware encoding modules located on each BP / RISER. Their code patterns are determined by the physical installation location during server assembly. For example, when the server can accommodate up to 16 expansion carriers, a 4-bit DIP switch is used, with different code patterns from 0000 to 1111 to uniquely distinguish the location of each expansion carrier. The DIP switch values ​​(…) The identifier is read in real time by the MCU through an internal interface and serves as the identity of the extended carrier. The maximum number of extended carriers in the server ( These are pre-set hardware configuration parameters, such as 12 or 16, which are either embedded in the MCU's program or obtained by the MCU from the motherboard during the initialization process.

[0087] Bus occupancy period refers to the time window during which a single MCU exclusively uses the target bus for data transmission. Its core purpose is to allocate non-overlapping dedicated transmission time to each MCU, avoiding conflicts caused by multiple MCUs accessing the bus simultaneously. During the bus occupancy period, the target bus is exclusively used by that MCU, and there are no access conflicts from other devices. The MCU transmits its status information to the motherboard's memory unit via the target bus. The memory unit receives the status information through the SPI interface and writes it to a preset memory address area.

[0088] If the MCU completes the transmission of all status information within the bus occupancy period, the bus can be released early. If the transmission is not completed by the end of the period, to avoid occupying the transmission time of subsequent MCUs, the transmission will be forcibly terminated. The untransmitted data will be buffered in the MCU's internal storage module, waiting for the next bus occupancy period to retry the transmission, ensuring the orderliness and integrity of data transmission. For example, if the bus occupancy period of an MCU is from 300ms to 383ms (a total of 83ms), if its status information is transmitted within 50ms, the bus will be released at 350ms; if some data is still untransmitted by the end of 83ms, the transmission will be terminated, and the remaining data will be carried over to the next round of transmission.

[0089] In this application, a unified timing trigger signal is issued by the CPLD and a first condition is set. Combined with the DIP switch values ​​of the extended carriers and the allocation of dedicated bus occupancy periods for the maximum number of devices, orderly access to the target bus by multiple extended carrier MCUs is achieved. This scheme avoids the conflict problem caused by multiple devices accessing the bus simultaneously from the aspects of timing synchronization and permission allocation. Compared with the I2C address conflict and bus contention problems that may occur in traditional schemes, it significantly improves the stability and reliability of status information transmission. At the same time, the unified timing trigger signal ensures the coordinated work of all MCUs, and the precise allocation of bus occupancy periods ensures orderly data transmission, avoids resource waste, improves the utilization rate of the target bus, and thus ensures the efficiency of status information transmission, laying the foundation for the subsequent rapid data reading by the BMC.

[0090] In one possible implementation, the bus occupancy period corresponding to the microcontroller is determined based on the DIP switch value of the expansion carrier and the maximum number of expansion carriers in the server, including:

[0091] The ratio of the product of the DIP switch value and the periodic reference value to the maximum number of extended carriers is used to determine the start time of the bus occupancy period.

[0092] The start time corresponding to the microcontroller unit in the next extended carrier is determined as the end time of the bus occupancy period, or the time when the timing trigger signal does not meet the first condition is determined as the end time of the bus occupancy period.

[0093] In this embodiment, the period reference value is a fixed time parameter set based on the frequency of the timing trigger signal. If the frequency of the timing trigger signal is 1Hz, that is, each signal period is 1000ms, then the period reference value is set to 1000ms. This value is a unified reference for the start time of the bus occupancy period for all MCUs.

[0094] In this embodiment, the logic for calculating the start time of the bus occupancy period is as follows: by using the DIP switch value ( ) and periodic benchmark value ( Multiply by , then divide by the maximum number of extended carriers ( The start time of the bus occupancy period corresponding to the MCU is obtained by calculation using the formula shown in Formula 1 below:

[0095] Formula 1

[0096] In this embodiment, the next extended carrier refers to the DIP switch value of the current extended carrier in the DIP switch value sorting. The start time of the MCU for the extended carrier corresponding to 1 plus 1 has been determined through the same calculation logic. Since the start time of all extended carriers is based on... The time interval between the start time of the next extended carrier and the start time of the current extended carrier is the dedicated bus occupancy time of the current MCU. Therefore, setting the start time of the next extended carrier to the end time of the current bus occupancy period can ensure that the bus occupancy periods of multiple MCUs are continuous and do not overlap.

[0097] In this embodiment, if the timing trigger signal no longer meets the first condition, the current MCU will forcibly release the bus to avoid the bus being occupied for a long time due to abnormality. Therefore, the time when the timing trigger signal no longer meets the first condition can also be determined as the end time of the bus occupation period.

[0098] In this application, by defining the bus occupancy period corresponding to each computing microcontroller, it is ensured that the MCUs of all expansion carriers occupy the bus sequentially according to a fixed timing sequence, completely avoiding the conflict problem caused by multiple devices accessing the bus simultaneously. Compared with the traditional solution that relies on I2C address allocation to avoid conflicts, stability and reliability are significantly improved. At the same time, the unified computing logic makes the allocation of bus occupancy periods highly scalable; when the number of expansion carriers is adjusted, only modifications are needed. The parameters can be automatically adapted to the new timing allocation without the need to redesign the control logic; the design of dual termination conditions not only ensures the continuity of bus occupation under normal circumstances, but also copes with bus release under abnormal scenarios, further improving the stability and fault tolerance of the entire information transmission process.

[0099] In another embodiment, step S102, "sending status information to the storage unit in the server's motherboard via the target bus," includes:

[0100] Based on the total capacity of the storage unit, the maximum number of expansion carriers, and the DIP switch values ​​of the expansion carriers, determine the storage space corresponding to the expansion carrier in the storage unit;

[0101] The status information is written to the storage space in the storage unit via the target bus.

[0102] In this embodiment, the total capacity of the storage unit ( The total storage capacity of the FLASH memory chips on the server motherboard is a fixed hardware parameter. For example, FLASH chips with a total capacity of 8MB, 16MB, or 32MB can be selected. This parameter is determined during the server design phase and is pre-programmed into the MCU program of each expansion carrier, or synchronized to the MCU by the BMC during the initialization process.

[0103] Storage space refers to the independent address range within a storage unit specifically allocated to a single extended carrier for storing state information. Its determination logic is as follows: first, the total capacity of the storage unit ( According to the maximum number of extended carriers ( Divide the data equally to obtain the basic storage capacity that each extended carrier can occupy; then, based on the DIP switch values ​​( Determine the specific address range corresponding to the extended carrier to ensure that the storage space of each extended carrier does not overlap and is continuously distributed.

[0104] After determining its corresponding storage space, the MCU writes the collected status information of the expansion carrier and peripheral cards to the corresponding storage space, completing the persistent storage of data. During the writing process, the MCU monitors the feedback signal of the FLASH chip in real time to confirm whether the data has been written successfully. If the writing fails (such as due to bus interference causing data transmission errors), the MCU will retry writing during the current bus occupancy period; if multiple attempts still fail, the failure information is cached in its internal storage module, and it will try again in the next bus occupancy period to ensure that the status information can be successfully written to the corresponding storage space.

[0105] In this application, dedicated storage space is allocated to each expansion carrier through the coordinated calculation of the total storage unit capacity, the maximum number of expansion carriers, and the DIP switch value, achieving ordered storage of status information. This scheme ensures that the status information of different expansion carriers is stored in partitions within the storage unit without interference, avoiding data overwriting or chaos problems that may occur when writing data from multiple devices in traditional solutions. Simultaneously, the dedicated storage space design allows the BMC to quickly locate the relevant information of the target expansion carrier when reading data, without traversing the entire storage unit, significantly improving data reading efficiency and saving time for subsequent data analysis and logical processing by the BMC. Furthermore, the storage space allocation logic is simple and has good scalability. When the total storage unit capacity or the number of expansion carriers is adjusted, only the corresponding parameters need to be modified to automatically adapt to the new storage space allocation, without redesigning the storage architecture, thus improving the flexibility and applicability of the solution.

[0106] In one possible implementation, the starting address of the storage space is determined based on the following formula 2:

[0107] Formula 2

[0108] The ending address of the storage space is determined based on the following formula 3:

[0109] Formula 3

[0110] in, This is the starting address of the storage space. The total capacity of the storage units. To expand the maximum number of carriers, To expand the DIP switch values ​​of the carrier, This is the end address of the storage space.

[0111] In another embodiment, step S103, "reading status information from the storage unit based on the Baseboard Management Controller (BMC) in the motherboard," includes:

[0112] The CPLD based on the BMC control motherboard pulls the issued timing trigger signal to the falling edge and pulls the level of the timing trigger signal low;

[0113] Status information is read from the storage unit based on the BMC occupying the target bus.

[0114] In this embodiment, when the BMC needs to read the status information from the memory cell, it will first send a control command to the CPLD. The core function of this command is to change the state of the timing trigger signal to prevent the extended carrier MCU from occupying the bus during the BMC's read operation, thus avoiding bus conflicts. After receiving the control command from the BMC, the CPLD will immediately perform a signal adjustment operation: first, it will pull the timing trigger signal, which is currently at a high level, to a falling edge (i.e., the instant it transitions from a high level to a low level), and then keep the timing trigger signal at a low level. At this time, the extended carrier MCU detects that the timing trigger signal is at a low level and will stop trying to occupy the bus, ensuring that the bus resources are completely released and providing a conflict-free bus environment for the BMC's read operation.

[0115] The BMC establishes a physical connection with the target bus through the BUFFER chip. After the CPLD completes the timing trigger signal adjustment (pulling it to the falling edge and keeping it low), the bus is in an idle state. At this time, the BMC starts the bus occupancy process and initiates a read request to the memory unit (FLASH) through the target bus.

[0116] In this application, the BMC controls the CPLD to adjust the timing trigger signal state, achieving priority access to the target bus and efficient reading of status information by the BMC. This scheme ensures that the BMC can exclusively occupy bus resources when reading data, avoiding bus contention with the extended carrier MCU and guaranteeing the stability and integrity of data reading. Simultaneously, the BMC quickly releases the bus by actively controlling the timing trigger signal, without waiting for the extended carrier MCU's bus occupancy period to end, significantly shortening the data reading waiting time and improving the real-time performance of the BMC in acquiring status information. This lays the foundation for the BMC to quickly analyze data and respond to anomalies, effectively solving the problems of high data reading latency and susceptibility to interference from other devices in traditional polling schemes.

[0117] In another embodiment, a method for managing information on a server peripheral card further includes:

[0118] In response to the microcontroller detecting an abnormal status information, the level of the abnormal warning signal is pulled low during the bus occupancy period corresponding to the microcontroller.

[0119] In response to the BMC detecting a low-level abnormal warning signal, the target bus is used to read the status information from the storage unit.

[0120] In this embodiment, the motherboard's BMC is in normal operating condition. The microcontroller unit (MCU) of the expansion carrier continuously collects status information from the expansion carrier and peripheral cards, and performs real-time anomaly detection on the collected status information. The anomaly detection is based on preset standard thresholds or normal operating ranges. For example, the normal temperature threshold for peripheral cards is set to 0℃-70℃. When the MCU collects a hard drive temperature of 85℃, it determines it as a temperature anomaly. Similarly, if the MCU does not detect a connection feedback signal from a peripheral card, it determines it as a connection anomaly. Furthermore, if a fault code (such as a hard drive bad sector fault code) is collected from a peripheral card, it determines it as a device malfunction.

[0121] The abnormal warning signal, namely BP_RISER_BMC_ALERT_N, is the signal line corresponding to GPIO2 in the target bus. The default state of this signal is high level, and a low level indicates an abnormal trigger state. Its level change is controlled by the MCU of the extended carrier, and both the BMC and CPLD monitor the level state of this signal through the target bus.

[0122] When the MCU detects an abnormal status, it does not immediately send an abnormal warning signal. Instead, it waits for its corresponding bus occupancy period to begin. During this period, the MCU uses its GPIO interface to control the abnormal warning signal, pulling it from a default high level to a low level to convey the abnormality to the BMC. The pull-down operation is only performed during the current MCU bus occupancy period, and its duration is consistent with the bus occupancy period, ensuring that the BMC can accurately capture the abnormal signal.

[0123] The BMC monitors the level of the abnormal warning signal in real time via the GPIO2 signal line of the target bus. One of its core tasks is to capture the low-level trigger event of this signal to quickly respond to possible device anomalies. When the BMC detects that the abnormal warning signal changes from high to low, it immediately initiates the emergency read process. First, the BMC sends a control command to the CPLD on the motherboard, controlling the CPLD to pull the timing trigger signal (BMC_BP_RISER_START_N) to the falling edge and keep it low, forcing all MCUs on the extended carriers to stop occupying the bus and ensuring that the target bus is in an idle state.

[0124] Subsequently, the BMC occupies the target bus and initiates a read request to the storage unit. The read range can cover the entire storage space of the storage unit, or it can prioritize reading the dedicated storage space of the extended carrier corresponding to the most recent bus occupancy period (by locating the storage address corresponding to the abnormal extended carrier through the correspondence between the time of the abnormal warning signal trigger and the bus occupancy period), quickly obtaining abnormal status information and the status information of other extended carriers, providing data support for subsequent abnormal analysis and emergency handling.

[0125] In this application, when the MCU detects an anomaly, it pulls a low warning signal during the bus occupancy period. Upon detecting the low warning signal, the BMC triggers emergency reading, enabling rapid response and precise location of server peripheral card anomalies. This solution overcomes the limitation of traditional polling schemes where the BMC needs to read information path by path to detect anomalies. By triggering the anomaly warning signal with a low level, the BMC can immediately recognize the anomaly and initiate emergency reading, significantly reducing the delay in anomaly detection and data acquisition, thus saving time for subsequent emergency handling (such as heat dissipation adjustments and fault isolation). Simultaneously, the anomaly warning signal is sent during a dedicated bus occupancy period, avoiding signal conflicts caused by multiple expansion carriers triggering anomalies simultaneously. This ensures the BMC can accurately capture anomaly information and, combined with the status data stored in the partitioned storage unit, quickly locate the abnormal expansion carrier and the specific anomaly. This effectively solves the problems of easily lost anomaly information and difficult troubleshooting in traditional solutions, improving server stability and maintainability.

[0126] In another embodiment, a method for managing information on a server peripheral card further includes:

[0127] BMC triggers emergency procedures based on status information;

[0128] In response to the BMC determining that the emergency status of the extended carrier has been lifted, the warning cancellation signal is lowered to notify the extended carrier to resume normal operation.

[0129] In this embodiment, after the BMC reads the status information in the storage unit through the target bus, it will perform a comprehensive anomaly analysis on this information. The analysis objects include the temperature, voltage, connection status, fault codes and other data of all extended carriers (BP / RISER) and corresponding peripheral cards (network card, hard disk, GPU, etc.).

[0130] The basis for anomaly analysis is the preset normal threshold range or fault judgment rules. For example, the normal threshold for peripheral card temperature is 0℃-70℃. When the temperature of a hard drive is read as 82℃, it is judged as a temperature anomaly. When the connection status of a GPU is read as "disconnected", it is judged as a connection anomaly. When a fault code fed back by a peripheral card is detected (such as hard drive bad sector fault code, network card communication fault code), it is judged as a device operation anomaly.

[0131] Emergency procedures are pre-defined processing logics within the BMC for different abnormal scenarios, with each type corresponding to a specific abnormality. When the BMC determines an abnormality, it triggers the corresponding emergency procedure based on the severity and type of the abnormality: For temperature abnormalities, emergency procedures may include increasing the fan speed in the corresponding area and reducing the operating load of related peripheral cards; for connection abnormalities, emergency procedures may include attempting to re-establish the connection, marking the abnormal device, and sending an alarm notification to the administrator; for equipment malfunction abnormalities, emergency procedures may include isolating the faulty device, activating backup devices (if available), and logging the fault.

[0132] In this embodiment, the warning cancellation signal, namely the BMC_BP_RISER_ALERT_RST_N signal, is the signal line corresponding to GPIO3 in the target bus. The default state of this signal is high level, and a low level indicates the cancellation of the notification. Its level change is controlled by the BMC, and the MCUs of all extended carriers monitor the level state of this signal through the target bus.

[0133] After triggering the emergency procedure, the BMC continuously reads the latest status information of the corresponding extended carrier from the storage unit through the target bus, monitoring in real time whether the anomaly has been alleviated or eliminated to determine whether the emergency state has been lifted. The criteria for lifting the emergency state are: the status information corresponding to the anomaly has returned to the normal threshold range, and the anomaly has not reappeared for a preset duration (e.g., 10 seconds). When the BMC determines that the emergency state has been lifted, it immediately controls the warning cancellation signal through its own GPIO interface, pulling it from the default high level to a low level. This low-level signal is transmitted to the MCUs of all extended carriers through the target bus. After each MCU detects that the warning cancellation signal is low, it knows that the emergency state has ended and will resume normal operation mode, including continuing to collect and transmit status information according to the original timing trigger signal cycle, and no longer executing temporary processing logic related to the anomaly (such as continuously sending anomaly warning signals).

[0134] This application ensures that the BMC can quickly initiate targeted emergency measures upon detecting anomalies, promptly mitigating the risks caused by the anomalies (such as equipment damage due to high temperatures or service interruptions due to connection failures). This solves the problems of traditional solutions that rely on manual intervention and have high latency in emergency response. At the same time, the early warning cancellation signal mechanism after the emergency state is lifted enables the extended carrier to promptly resume normal operation mode, avoiding resource waste or performance loss caused by the system being in an emergency state for a long time. This ensures the overall stability and efficiency of the server operation, further improves the full-process control of anomaly handling, and enhances the server's maintainability and fault tolerance.

[0135] In another embodiment, a method for managing information on a server peripheral card further includes:

[0136] In response to the microcontroller detecting an abnormal status information, the level of the abnormal warning signal is pulled low during the bus occupancy period corresponding to the microcontroller.

[0137] If the CPLD on the motherboard detects an abnormal warning signal as being at a low level and the BMC is in the startup state for a preset period of time, the server's fan will be adjusted to its maximum speed.

[0138] If the CPLD determines that the BMC is in normal operation or the emergency status of the extended carrier is lifted, the fan speed is restored.

[0139] In this embodiment, the BMC on the motherboard is in a startup or restart state. The MCU in the expansion carrier continuously collects status information of the expansion carrier and connected peripheral cards, including temperature, voltage, connection status, fault codes, etc., and compares it with preset normal thresholds or standard states in real time to determine if there is any abnormality. When the MCU detects an abnormal status, it does not immediately trigger an abnormality warning signal, but waits for its corresponding bus occupancy period to start. After entering its dedicated bus occupancy period, the MCU controls the abnormality warning signal through its GPIO interface, pulling it from a high level to a low level, and the low state continues until the end of the current bus occupancy period, ensuring that the CPLD can stably capture the abnormal signal.

[0140] The Complex Programmable Logic Device (CPLD) on the motherboard monitors the level of the anomaly warning signal (BP_RISER_BMC_ALERT_N) in real time via the GPIO2 signal line of the target bus. One of its core functions is to capture the low-level trigger event of this signal to respond to abnormal scenarios when the BMC is not operating normally. The CPLD also establishes a heartbeat signal communication link with the BMC, continuously receiving heartbeat signals from the BMC to determine its operating status. If the CPLD receives continuous heartbeat signals within a set time (e.g., 1 second), it determines that the BMC is in normal operating condition; if no heartbeat signal is received or the heartbeat signal is interrupted, it determines that the BMC is in startup state (including initial startup and restart processes). The preset duration can be 5 seconds.

[0141] When the CPLD meets two conditions simultaneously, it immediately executes fan speed adjustment: first, it detects a low-level abnormality warning signal (confirming an abnormality in the expansion carrier or peripheral card); second, the BMC remains in an active state for a preset duration after the abnormality warning signal goes low (confirming that the BMC cannot handle the abnormality immediately). The CPLD sends a control signal to the server fan's control interface to directly adjust the fan speed to 100% maximum speed, reducing the server's internal temperature as quickly as possible to prevent abnormalities (especially temperature abnormalities) from causing equipment damage or escalating the fault.

[0142] After adjusting the fan to its maximum speed, the CPLD continuously monitors two key states to determine whether to restore the fan to its default speed: First, monitoring the BMC's operating status: The CPLD continuously confirms the BMC status via a heartbeat signal. When the CPLD receives a stable BMC heartbeat signal again, and it remains uninterrupted for a preset time (e.g., 3 seconds), it determines that the BMC is in normal operating condition. At this point, the BMC can take over abnormal handling (e.g., reading status information, triggering targeted emergency procedures), and the CPLD no longer needs to maintain the fan at its maximum speed. Second, monitoring the emergency status cancellation: The CPLD continuously reads the latest status information of the corresponding expansion carrier in the storage unit via the target bus, or monitors whether the abnormal warning signal returns to a high level. When the status information shows that the abnormality has been eliminated (e.g., the temperature has returned to the normal threshold, the fault code has disappeared), and no abnormality occurs again for a preset duration (e.g., 10 seconds), it determines that the emergency status of the expansion carrier has been cancelled.

[0143] When the CPLD meets any of the above conditions, it immediately sends a recovery signal to the fan control interface to restore the fan speed from 100% maximum speed to the speed corresponding to the default heat dissipation strategy (such as the normal speed dynamically adjusted according to the overall server temperature), thus avoiding energy waste and excessive noise caused by long-term full-speed operation.

[0144] In this application, the MCU triggers an anomaly warning. If the BMC is in a startup or restart state, the CPLD independently monitors and adjusts the fan speed, resolving the issue of the BMC being unable to handle anomalies during startup / restart. This solution ensures that the CPLD can quickly respond to anomalies when the BMC cannot intervene immediately, achieving emergency cooling by maximizing the fan speed. This effectively prevents damage to server hardware from anomalies such as high temperatures, overcoming the shortcomings of traditional solutions where the BMC is unresponsive during startup. Simultaneously, the CPLD promptly restores the fan speed to its default setting after the BMC returns to normal or the emergency state is resolved, balancing emergency cooling with server energy consumption control and noise management. This ensures the stability and economy of the server throughout the entire anomaly handling process, further improving the emergency support system for server peripheral card information management.

[0145] Figure 5 This application illustrates a schematic diagram of the structure of an information management system for a server peripheral card according to an embodiment of the present application. Figure 5 As shown, an information management system for server peripheral cards includes:

[0146] Motherboard, at least one expansion carrier (BP / RISER);

[0147] The microcontroller unit in the expansion carrier is connected to the peripheral card via the I2C channel and is used to obtain the status information of the expansion carrier and the peripheral card connected to the expansion carrier;

[0148] The microcontroller unit is connected to the target bus via a bidirectional buffer and to the motherboard via the target bus. It is used to send status information to the memory unit in the motherboard via the target bus.

[0149] The BMC in the motherboard is connected to the target bus based on a bidirectional buffer and is used to read status information from the memory unit.

[0150] In one possible implementation, at least one expansion carrier is cascaded via a target bus, and one of the target expansion carriers is connected to the motherboard via the target bus;

[0151] The microcontroller unit in the target extension carrier is also used to: send status information to the storage unit via the target bus;

[0152] The microcontroller unit in other extended carriers is also used to: send status information to the previous extended carrier connected to it via the target bus, until the status information is sent to the target extended carrier, and then the target extended carrier sends the status information to the storage unit.

[0153] In one possible implementation, the microcontroller is further configured to:

[0154] Receive timing trigger signals from the CPLD on the motherboard;

[0155] In response to the timing trigger signal satisfying the first condition, the bus occupancy period corresponding to the microcontroller is determined based on the DIP switch value of the extended carrier and the maximum number of extended carriers in the server.

[0156] During the bus occupancy period, status information is sent to the storage unit in the server's motherboard via the target bus;

[0157] The first condition is that the rising edge of the timing trigger signal is detected and the timing trigger signal is at a high level; the DIP switch value represents the installation position of the extension carrier in the server.

[0158] In one possible implementation, the microcontroller is further configured to:

[0159] The ratio of the product of the DIP switch value and the periodic reference value to the maximum number of extended carriers is used to determine the start time of the bus occupancy period.

[0160] The start time corresponding to the microcontroller unit in the next extended carrier is determined as the end time of the bus occupancy period, or the time when the timing trigger signal does not meet the first condition is determined as the end time of the bus occupancy period.

[0161] In one possible implementation, the microcontroller is further configured to:

[0162] Based on the total capacity of the storage unit, the maximum number of expansion carriers, and the DIP switch values ​​of the expansion carriers, determine the storage space corresponding to the expansion carrier in the storage unit;

[0163] The status information is written to the storage space in the storage unit via the target bus.

[0164] In one implementation, the microcontroller determines the starting address of the memory space based on the following formula:

[0165]

[0166] The microcontroller determines the end address of the memory space based on the following formula:

[0167]

[0168] in, This is the starting address of the storage space. The total capacity of the storage units. To expand the maximum number of carriers, To expand the DIP switch values ​​of the carrier, This is the end address of the storage space.

[0169] In one possible implementation, the BMC is also used for:

[0170] The CPLD controlling the motherboard pulls the timing trigger signal to the falling edge and lowers the level of the timing trigger signal;

[0171] The target bus is used to read status information from the storage unit.

[0172] In one embodiment, the microcontroller is further configured to: in response to detecting an abnormal status information, pull down the level of the abnormal warning signal during the bus occupancy period corresponding to the microcontroller;

[0173] The BMC is also used to: in response to the detection of an abnormal warning signal being low, occupy the target bus to read status information from the storage unit.

[0174] In one possible implementation, the BMC is also used for:

[0175] Emergency procedures are triggered based on status information;

[0176] In response to the determination that the emergency status of the extended carrier has been lifted, the warning cancellation signal is lowered to notify the extended carrier to resume normal operation.

[0177] In one embodiment, the microcontroller is further configured to: in response to detecting an abnormal status information, pull down the level of the abnormal warning signal during the bus occupancy period corresponding to the microcontroller;

[0178] The CPLD in the motherboard is also used to: adjust the server fan to maximum speed in response to the detection of an abnormal warning signal at a low level and the BMC being in the start state for a preset time.

[0179] The CPLD in the motherboard is also used to restore the fan speed in response to determining that the BMC is in normal operation or that the emergency status of the extended carrier has been lifted.

[0180] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this application can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this application can be achieved, and this is not limited herein.

[0181] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0182] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for managing information on a server peripheral card, characterized in that, The method includes: Based on the microcontroller unit in the expansion carrier in the server, the status information of the expansion carrier and the peripheral card connected to the expansion carrier is obtained; Based on the microcontroller unit, the status information is sent to the storage unit in the motherboard of the server via a target bus; the target bus is used to connect the expansion carrier and the motherboard. The status information is read from the storage unit based on the Baseboard Management Controller (BMC) in the motherboard; The step of sending the status information to the storage unit in the motherboard of the server via the target bus includes: In response to the microcontroller detecting that the timing trigger signal issued by the complex programmable logic device CPLD on the motherboard meets the first condition, the ratio of the product of the DIP switch value and the period reference value of the expansion carrier to the maximum number of the expansion carriers is determined as the start time of the bus occupancy period corresponding to the microcontroller. The start time corresponding to the microcontroller unit in the next extended carrier is determined as the end time of the bus occupancy period, or the time when the timing trigger signal does not meet the first condition is determined as the end time of the bus occupancy period. During the bus occupancy period, the status information is sent to the storage unit in the motherboard of the server via the target bus; The first condition is that the rising edge of the timing trigger signal is detected and the timing trigger signal is at a high level; the DIP switch value represents the installation position of the expansion carrier in the server; The step of sending the status information to the storage unit in the motherboard of the server via the target bus includes: Based on the total capacity of the storage unit, the maximum number of the expansion carriers, and the DIP switch value of the expansion carriers, the storage space corresponding to the expansion carriers in the storage unit is determined; The status information is written to the storage space of the storage unit via the target bus; The starting address of the storage space is determined based on the following formula: The end address of the storage space is determined based on the following formula: in, This is the starting address of the storage space. The total capacity of the storage units. This represents the maximum number of the extended carriers. The DIP switch value of the extended carrier. This is the end address of the storage space; The method further includes: In response to the microcontroller detecting an abnormality in the status information, the level of the abnormality warning signal is lowered during the bus occupancy period corresponding to the microcontroller. If the CPLD of the motherboard detects that the abnormal warning signal is low and the BMC is in the start-up state for a preset period of time, the server fan will be adjusted to the maximum speed. In response to the CPLD determining that the BMC is in normal operation or the emergency status of the extended carrier is lifted, the fan speed is restored.

2. The method according to claim 1, characterized in that, The server is equipped with multiple expansion carriers, which are cascaded together via the target bus. One of the target expansion carriers is connected to the motherboard via the target bus. The step of sending the status information to the storage unit in the motherboard of the server via the target bus includes: For the microcontroller unit in the target extended carrier, the status information is sent to the storage unit via the target bus; For the microcontroller unit in other extended carriers, the status information is sent to the previous extended carrier connected to it via the target bus until the status information is sent to the target extended carrier, and then the target extended carrier sends the status information to the storage unit.

3. The method according to claim 1, characterized in that, The step-by-step reading of the status information from the storage unit based on the Baseboard Management Controller (BMC) in the motherboard includes: Based on the BMC, the CPLD of the motherboard will pull the timing trigger signal to the falling edge and pull the level of the timing trigger signal low; Based on the BMC occupying the target bus, the status information is read from the storage unit.

4. The method according to claim 1, characterized in that, The method further includes: In response to the microcontroller detecting an abnormality in the status information, the level of the abnormality warning signal is lowered during the bus occupancy period corresponding to the microcontroller. In response to the BMC detecting that the abnormal warning signal is low, the target bus is used to read the status information from the storage unit.

5. The method according to claim 4, characterized in that, The method further includes: The BMC triggers an emergency procedure based on the status information; In response to the BMC determining that the emergency status of the extended carrier has been lifted, the warning cancellation signal is lowered to notify the extended carrier to resume normal operation.

6. An information management system for server peripheral cards, characterized in that, The system includes: Motherboard, at least one expansion device; The microcontroller unit in the expansion carrier is connected to the peripheral card via an I2C channel and is used to obtain the status information of the expansion carrier and the peripheral card connected to the expansion carrier. The microcontroller unit is connected to the target bus via a bidirectional buffer and to the motherboard via the target bus, and is used to send the status information to the storage unit in the motherboard via the target bus; The BMC in the motherboard is connected to the target bus based on a bidirectional buffer and is used to read the status information from the storage unit. The microcontroller unit is further configured to: In response to the microcontroller detecting that the timing trigger signal issued by the complex programmable logic device CPLD on the motherboard meets the first condition, the ratio of the product of the DIP switch value and the period reference value of the expansion carrier to the maximum number of the expansion carriers is determined as the start time of the bus occupancy period corresponding to the microcontroller. The start time corresponding to the microcontroller unit in the next extended carrier is determined as the end time of the bus occupancy period, or the time when the timing trigger signal does not meet the first condition is determined as the end time of the bus occupancy period. During the bus occupancy period, the status information is sent to the storage unit in the motherboard of the server via the target bus; The first condition is that the rising edge of the timing trigger signal is detected and the timing trigger signal is at a high level; the DIP switch value represents the installation position of the expansion carrier in the server; The microcontroller unit is further configured to: Based on the total capacity of the storage unit, the maximum number of the expansion carriers, and the DIP switch value of the expansion carriers, the storage space corresponding to the expansion carriers in the storage unit is determined; The status information is written to the storage space of the storage unit via the target bus; The microcontroller determines the starting address of the storage space based on the following formula: The microcontroller determines the end address of the storage space based on the following formula: in, This is the starting address of the storage space. The total capacity of the storage units. This represents the maximum number of the extended carriers. The DIP switch value of the extended carrier. This is the end address of the storage space; The microcontroller unit is further configured to: in response to detecting an abnormality in the status information, pull down the level of the abnormality warning signal during the bus occupancy period corresponding to the microcontroller unit; The CPLD in the motherboard is also used to: in response to the detection that the abnormal warning signal is low and the BMC is in the start state for a preset period of time, adjust the server fan to the maximum speed. The CPLD in the motherboard is also used to: restore the fan speed in response to determining that the BMC is in normal operation or that the emergency status of the expansion carrier is lifted.

7. The system according to claim 6, characterized in that, The at least one expansion carrier is cascaded through the target bus, and one of the target expansion carriers is connected to the motherboard through the target bus; The microcontroller unit in the target extension carrier is further configured to: send the status information to the storage unit via the target bus; The microcontroller unit in the other extended carrier is further configured to: send the status information to the previous extended carrier connected to it via a target bus until the status information is sent to the target extended carrier, and then the target extended carrier sends the status information to the storage unit.

8. The system according to claim 6, characterized in that, The BMC is also used for: The CPLD controlling the motherboard pulls the issued timing trigger signal to the falling edge and lowers the level of the timing trigger signal; The target bus is used to read the status information from the storage unit.

9. The system according to claim 6, characterized in that, The microcontroller unit is also configured to: in response to detecting an abnormality in the status information, pull down the level of the abnormality warning signal during the bus occupancy period corresponding to the microcontroller unit; The BMC is also used to: in response to detecting that the abnormal warning signal is low, occupy the target bus to read the status information in the storage unit.

10. The system according to claim 9, characterized in that, The BMC is also used for: The emergency procedure is triggered based on the aforementioned status information; In response to determining that the emergency status of the extended carrier has been lifted, the warning cancellation signal is lowered to notify the extended carrier to resume normal operation.

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