Secondary circuit checking method and device, electronic equipment and storage medium

Abstract

The invention relates to the technical field of secondary circuit checking, and discloses a secondary circuit checking method and device, electronic equipment and a storage medium, and the method comprises the steps: collecting the operation state data of a secondary circuit of a specified transformer substation; based on a preset mapping function, mapping the running state data into a preset knowledge graph to associate corresponding target graph nodes and dynamic attribute states thereof in the preset knowledge graph so as to obtain a fusion graph; and checking the fusion atlas through a preset atlas reasoning mechanism. The method has the beneficial effects that by automatically constructing the secondary circuit knowledge graph and establishing a unified model of configuration logic and running state data, the check of the secondary circuit is not limited to field consistency check, and global modeling and automatic reasoning can be performed on a cross-device and cross-link logic dependency relationship, so that the check efficiency is improved, and the check efficiency is improved. And problems of potential implicit abnormities, breakpoints, wrong connection and the like which cannot be identified by the existing tool can be found.

Description

Technical Field

[0001] This invention relates to the field of secondary circuit verification technology, and in particular to a secondary circuit verification method, apparatus, electronic device and storage medium. Background Technology

[0002] In the secondary system of a smart substation, secondary circuit verification is a crucial step in ensuring the correct operation of protection and control devices and guaranteeing the safe and stable operation of the power grid. Secondary circuits mainly include GOOSE (General Communication Protocol) or SV (Sample Value) message exchange between IEDs (Intelligent Electronic Devices), mapping of switch contacts, remote control circuit interlocking conditions, switchboard switching logic, and consistency verification between the virtual connection logic defined in the SCD file (System Configuration Description File) and the actual wiring.

[0003] Currently, the industry commonly employs a method of manually verifying configuration files against field wiring and using script-based or simple field extraction tools to check key fields in the SCD file (such as IED name, GOOSE control block, dataset, and channel configuration). Its characteristics are: (1) Relying on engineers to compare and verify configuration fields based on experience requires checking the message interaction relationship between IEDs, whether the message subscription and publication are correct, and whether the remote signaling / pressure plate point table is accurate. Overall efficiency is low and omissions are easy to occur.

[0004] (2) Existing tools can usually only statically parse some field information in SCD files, such as IED and LN (logical nodes), GOOSE / SV control blocks and their dataset information. They lack the ability to connect this information into logical links or topologies and cannot model the dynamic dependencies between components in the loop at the system level.

[0005] (3) For phenomena such as soft pressure plate status affecting protection output linkage logic, link interruption caused by whether GOOSE message arrives, or sampling value link failure, existing methods mostly rely on manual analysis combined with test tools or waveform tools for offline analysis, and cannot perform automated analysis and diagnosis in real time during engineering debugging and operation.

[0006] Furthermore, with the expansion of substation projects, the diversification of IED equipment types, and the continuous updates of configuration versions, existing methods require engineers to re-import, compare, and modify scripts after the configuration file is updated. This cannot support incremental verification, hot-swapping, and automatic adaptation capabilities of project versions, which increases the burden on maintenance personnel and poses potential risks to system security.

[0007] Therefore, although there are existing tools for parsing SCD files and some auxiliary comparison tools, problems still exist, such as insufficient understanding of loop logic links, inability to automatically infer potential dependencies, lack of operational data fusion capabilities, and lack of automatic adaptation capabilities after version changes. These issues make it difficult to meet the high reliability, automation, and intelligent operation and maintenance requirements of smart substation secondary systems. Summary of the Invention

[0008] Based on this, it is necessary to propose a method, device, electronic equipment, and storage medium for secondary circuit verification to address the existing problem of secondary circuit verification.

[0009] A method for verifying secondary circuits, the method comprising: Collect operational status data of the secondary circuits of a designated substation; Based on a preset mapping function, the running data is mapped to a preset knowledge graph to associate the corresponding target graph node and its dynamic attribute state in the preset knowledge graph, thereby obtaining a fusion graph of the running data and the preset knowledge graph. The fused graph is verified using a preset graph reasoning mechanism.

[0010] Furthermore, before the step of mapping the runtime data to a preset knowledge graph based on a preset mapping function to associate the corresponding target graph node and its dynamic attribute state in the preset knowledge graph, thereby obtaining the fusion graph of the runtime data and the preset knowledge graph, the method further includes: Obtain the system configuration description file of the secondary circuit of the specified substation and multiple intelligent electronic devices; The system configuration description file is parsed to obtain the intelligent electronic device and its published data object of the general communication protocol message publishing end, the intelligent electronic device and its received data object of the general communication protocol message subscribing end, and the logical relationship between the general communication protocol message publishing end and the general communication protocol message subscribing end; The preset knowledge graph is constructed based on the intelligent electronic device and its published data object of the general communication protocol message publishing end, the intelligent electronic device and its received data object of the general communication protocol message subscribing end, and the logical relationship between the general communication protocol message publishing end and the general communication protocol message subscribing end.

[0011] Furthermore, after the step of constructing the preset knowledge graph based on the intelligent electronic device and its published data object at the general communication protocol message publishing end, the intelligent electronic device and its received data object at the general communication protocol message subscribing end, and the logical relationship between the general communication protocol message publishing end and the general communication protocol message subscribing end, the method further includes: Extract any set of triples from the preset knowledge graph as the target triple; Vectorize the target entities and target relations in the target triples to obtain the vector set of the target triples; The edge loss value of the vector set is calculated using a preset edge loss function; The optimized target entity and target relationship are obtained by minimizing the edge loss value through a preset optimization algorithm; The optimized target entity and target relationship are input into the preset knowledge graph to obtain the optimized preset knowledge graph.

[0012] Furthermore, after the step of constructing the preset knowledge graph based on the intelligent electronic device and its published data object at the general communication protocol message publishing end, the intelligent electronic device and its received data object at the general communication protocol message subscribing end, and the logical relationship between the general communication protocol message publishing end and the general communication protocol message subscribing end, the method further includes: Determine whether the system configuration description file has been updated; If the system configuration description file is updated, an updated knowledge graph is generated based on the updated system configuration description file; Compare the preset knowledge graph and the updated knowledge graph to obtain a set of edge differences where there are differences; Construct an incremental subgraph based on the set of edge differences; The incremental subgraph is mapped to the updated knowledge graph for verification.

[0013] Furthermore, after the step of verifying the fused graph through a preset graph inference mechanism, the method further includes: Obtain the verified abnormal edges and their probabilities; Obtain data information related to the abnormal edge; A verification report is generated based on the data and the anomaly probability.

[0014] Furthermore, after the step of generating a verification report based on the data information and the anomaly probability, the method further includes: Based on the verification report, the anomalies are processed, and the anomalies and their processing records are recorded. Send the anomaly and its processing record to the backtracking database; The preset graph reasoning mechanism is updated based on the backtracking database.

[0015] Furthermore, the preset graph reasoning mechanism can be either logic rule-based reasoning or graph embedding-based reasoning.

[0016] A secondary circuit verification device, the device comprising: The data acquisition module is used to collect operational status data of the secondary circuits of a specified substation. The mapping module is used to map the runtime data to a preset knowledge graph based on a preset mapping function, so as to associate the corresponding target graph node and its dynamic attribute state in the preset knowledge graph, thereby obtaining a fusion graph of the runtime data and the preset knowledge graph. The verification module is used to verify the fused graph through a preset graph reasoning mechanism.

[0017] An electronic device includes a memory and a processor, the memory storing a computer program that, when executed by the processor, causes the processor to perform the following steps: Collect operational status data of the secondary circuits of a designated substation; Based on a preset mapping function, the running data is mapped to a preset knowledge graph to associate the corresponding target graph node and its dynamic attribute state in the preset knowledge graph, thereby obtaining a fusion graph of the running data and the preset knowledge graph. The fused graph is verified using a preset graph reasoning mechanism.

[0018] A computer-readable storage medium storing a computer program, which, when executed by a processor, causes the processor to perform the following steps: Collect operational status data of the secondary circuits of a designated substation; Based on a preset mapping function, the running data is mapped to a preset knowledge graph to associate the corresponding target graph node and its dynamic attribute state in the preset knowledge graph, thereby obtaining a fusion graph of the running data and the preset knowledge graph. The fused graph is verified using a preset graph reasoning mechanism.

[0019] The beneficial effects of this invention are as follows: By automatically constructing a knowledge graph of secondary loops, a unified model of configuration logic and runtime data is established, so that the verification of secondary loops is not limited to field consistency checks, but can perform global modeling and automated reasoning of logical dependencies across devices and links, and discover potential hidden anomalies, breakpoints, and faulty connections that existing tools cannot identify. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] in: Figure 1 This is an application environment diagram of the secondary loop verification method in one embodiment; Figure 2 This is a flowchart of a secondary loop verification method in one embodiment; Figure 3 This is a structural block diagram of a secondary circuit verification device in one embodiment; Figure 4 This is a structural block diagram of an electronic device in one embodiment. Detailed Implementation

[0022] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0023] Figure 1 This is a diagram illustrating the application environment for secondary circuit verification in one embodiment. (Refer to...) Figure 1 This secondary loop verification method is applied to a secondary loop verification system. The secondary loop verification system includes a terminal 110 and a server 120. The terminal 110 and server 120 are connected via a network. The terminal 110 can be a desktop terminal or a mobile terminal; the mobile terminal can be at least one of a mobile phone, tablet computer, or laptop computer. The server 120 can be a standalone server or a server cluster consisting of multiple servers. The terminal 110 is used for…, and the server 120 is used for…

[0024] like Figure 2 As shown, in one embodiment, a secondary loop verification method is provided. This method can be applied to both terminals and servers; this embodiment uses a terminal application as an example. The secondary loop verification method specifically includes the following steps: S1: Collect operational status data of the secondary circuit of the specified substation; S2: Based on a preset mapping function, the running state data is mapped to a preset knowledge graph to associate the corresponding target graph node and its dynamic attribute state in the preset knowledge graph, thereby obtaining a fusion graph of the running state data and the preset knowledge graph; S3: Verify the fused graph through a preset graph reasoning mechanism.

[0025] As described in step S1 above, data is acquired from the secondary circuits of the designated substation. The secondary circuits refer to the electrical connections responsible for protection, control, alarm, monitoring, and communication. This mainly includes GOOSE / SV message exchange between IEDs (Intelligent Electronic Devices), switch contact mapping, remote control circuit interlocking conditions, switchboard switching logic, and the virtual connection logic defined in the SCD file (System Configuration Description File) and the actual wiring. Operational data acquisition can be achieved through various means, such as using monitoring equipment (e.g., data acquisition devices, intelligent electronic devices) to obtain parameters like current, voltage, frequency, temperature, and switch status in real time. Alternatively, data can be directly acquired from field devices via network protocols (e.g., MODBUS, IEC 61850). To ensure data accuracy and real-time performance, the frequency and time synchronization of data acquisition should be considered during the acquisition process to generate complete and reliable operational data. The acquired operational data set is represented as follows: in, This represents the set of all collected real-time running data items. Indicates the first The data items include, but are not limited to, remote signaling (such as circuit breaker position and disconnector status), telemetry (such as equipment status and environmental parameters), GOOSE / SV message reception status (such as frame interval and packet loss), soft switch status, and MMS link status. By collecting and analyzing this real-time data, the dynamic status of equipment and systems in the substation during operation can be effectively obtained.

[0026] As described in step S2 above, the runtime data is mapped to a preset knowledge graph based on a preset mapping function. The mapping function associates the acquired runtime data with the existing knowledge graph. A knowledge graph is a structured semantic network containing entities, their attributes, and relationships. The mapping function converts the collected dynamic data into nodes and their attributes in the knowledge graph. In practice, a reasonable mapping needs to be performed based on the characteristics of the data and the structure of the knowledge graph. For example, the current value can be mapped to a current node in the graph, and its dynamic attribute state can be updated. Specifically, through the mapping function... The real-time running data items are associated with nodes and their attributes in the graph, and the mapping is expressed as follows: in, This represents a mapping function that maps a set of real-time data items. Mapped to the set of graph nodes State attribute set . This represents the dynamic attribute state of each node in the graph under the current running state.

[0027] Through this mapping function, each node in the graph that is related to the running state data... All will be bound to a set of state values: in, Indicating the first in the atlas 1 node This represents the set of attributes of the node in its current running state, such as: "Active or Not", "Message Reception Status", "Telemetry Value", "Circuit Breaker Position", etc. By binding these status values, the statically configured graph can be combined with the dynamic status of real-time operation, providing support for subsequent intelligent reasoning and anomaly detection.

[0028] For data that exists in the configuration logic but is not detected in the runtime (e.g., a GOOSE message should be subscribed to but is not received), this invention uses a threshold function. Compare the node status in the graph with the actual received data, if the node If the expected signal or data is not received during runtime, the node and its corresponding edge will be marked as a candidate anomaly and handed over to subsequent reasoning and analysis.

[0029] Specifically, the mathematical expression for anomaly detection is: in, This represents the expected node state in the graph. The node status collected during actual operation. This is a set tolerance threshold. When the difference in node states exceeds the threshold... hour, This indicates that there is an anomaly in the node or its corresponding edge, and the process will proceed to the next step.

[0030] Through this step, the present invention integrates static configuration maps with dynamic operational data, achieving modeling of the current actual operating state of the secondary circuit. This not only ensures comprehensive monitoring of equipment status but also enables timely detection of inconsistencies between configuration logic and actual operating state, laying a solid foundation for subsequent anomaly detection and intelligent reasoning.

[0031] Furthermore, this invention incorporates real-time operational data for dynamic updates to the graph, enabling the system to adapt to changes during operation and automatically identify and adjust device states. Specifically, after operational data is accessed, the graph can adjust node states based on new operational information, ensuring the graph always maintains up-to-date state information and providing real-time and accurate data for subsequent reasoning and analysis.

[0032] Through dynamic mapping and state update mechanisms, this invention provides significant technical advantages in automated monitoring and intelligent operation and maintenance, which not only improves the detection and verification efficiency of secondary circuits, but also enhances the intelligence and adaptive capabilities of substation operation and maintenance.

[0033] As described in step S3 above, the fused graph is verified using a preset graph reasoning mechanism. The preset graph reasoning mechanism is a process of deriving new knowledge from known knowledge, and it can utilize the relationships and rules contained in the knowledge graph to verify and analyze the fused operational data.

[0034] Specifically, the preset graph reasoning mechanism can be either logic rule-based reasoning or graph embedding-based reasoning. After completing the fusion modeling of runtime data and knowledge graph, this invention automatically identifies potential abnormal connections, empty connections, logical link errors, and other problems in secondary loops through the knowledge graph reasoning mechanism, thereby achieving intelligent verification of secondary loops.

[0035] The reasoning module includes two main approaches: logic rule-based reasoning and graph embedding-based reasoning. Each approach fully utilizes the relationships between nodes and edges in the graph structure and combines them with domain knowledge to automatically identify potential anomalies in the system.

[0036] In logic-based rule-based reasoning, the relationships between nodes and edges in the graph structure are first utilized, combined with a rule base defined by domain experts. Reasoning is performed. These rules describe whether certain relationships (i.e., edges in the graph) are anomalies under specific conditions. The rule form is: in, This represents an edge in a knowledge graph. Represents tail entity The state in runtime data; if the entity If it does not exist or its state is inconsistent with the configuration logic, then If the relationship is established, it indicates a potential anomaly and a fault warning needs to be triggered. .

[0037] Specifically, the inference engine (such as Apache Jena) automatically infers from each edge in the graph based on these rules, identifying connections or links that do not conform to expectations. For example, when an IED device should receive a GOOSE message but does not, the inference mechanism will mark it as a potential anomaly and provide a basis for subsequent processing.

[0038] The goal of graph embedding-based reasoning is to map entities and relationships in a graph to a low-dimensional vector space, thereby enabling probabilistic computation of potential anomalies in edges within that space. The specific implementation includes the following steps: First, to learn graph embeddings in a low-dimensional space, a graph embedding model (such as the TransE model) is used to vectorize entities and their relationships in the knowledge graph. The embedding model measures triples using the following scoring function. Reasonableness: in, Representing the head entity respectively ,relation Tail-end entity The low-dimensional embedding vector; This represents the Euclidean norm, used to calculate the distance between vectors.

[0039] The goal of the embedding model is to minimize the scoring function, making the score of the true triples as small as possible, so that the embedding vectors of the triples accurately reflect the entity relationships in the graph. During anomaly detection, the inference engine calculates the anomaly probability of each edge based on the relative position of the entity embedding vectors. The calculation is performed using the following inference function: in, Representing an edge (corresponding triples) The probability of an anomaly; For activation functions (such as the Sigmoid function). The weight matrix is ​​a learnable matrix; This represents the embedding vector concatenation operation of the head entity, relation, and tail entity.

[0040] If the calculation yields Higher than the set threshold If an edge is detected, it is considered to have a potential anomaly, and an alarm mechanism is triggered. This process helps to discover hidden anomalies in the graph that are not directly defined, such as data loss or connection interruption in the system.

[0041] In the graph embedding-based reasoning process, the loss function This loss function is used to measure the model's performance. It optimizes the learning process by adjusting the embedding vectors to minimize the anomalous probability of normal edges and maximize the anomalous probability of potentially anomalous edges. Specifically, the loss function takes the following form: in, This represents the set of edges labeled as normal. This represents a potential anomalous edge generated through negative sampling; and Let represent the probabilities of normal edges and potentially abnormal edges, respectively. By minimizing this loss function, the model's ability to distinguish between normal and abnormal edges during actual inference can be improved, thereby effectively enhancing the accuracy of anomaly detection.

[0042] Through the above reasoning mechanism, the system can automatically verify the global logical links and status information of secondary loops and detect potential anomalies. Detected anomalies will be marked in the system and provide input for generating an anomaly report in subsequent steps. The report contains detailed information about potential anomaly edges, including the anomaly probability, the devices and logical relationships involved, and possible fault paths.

[0043] In one embodiment, before step S2, which maps the runtime data to a preset knowledge graph based on a preset mapping function to associate the corresponding target graph node and its dynamic attribute state in the preset knowledge graph, thereby obtaining a fusion graph of the runtime data and the preset knowledge graph, the method further includes: S201: Obtain the system configuration description file of the secondary circuit of the designated substation and multiple intelligent electronic devices; S202: Parse the system configuration description file to obtain the intelligent electronic device and its published data object of the general communication protocol message publishing end, the intelligent electronic device and its received data object of the general communication protocol message subscribing end, and the logical relationship between the general communication protocol message publishing end and the general communication protocol message subscribing end; S203: Construct the preset knowledge graph based on the intelligent electronic device and its published data object of the general communication protocol message publishing end, the intelligent electronic device and its received data object of the general communication protocol message subscribing end, and the logical relationship between the general communication protocol message publishing end and the general communication protocol message subscribing end.

[0044] As described in steps S201-S203 above, the construction of the preset knowledge graph is achieved. System configuration description files and information from multiple intelligent electronic devices related to the secondary circuits of a specified substation are collected. System configuration description files typically contain detailed information about the substation structure, equipment types, equipment parameters, communication protocols, and network topology. Relevant information from the general communication protocol message publishers and subscribers is extracted to identify which intelligent electronic devices are data publishers (i.e., devices responsible for sending data) and which are data subscribers (i.e., devices responsible for receiving data). Simultaneously, the data objects published or received by these devices need to be clearly defined to establish data flow relationships and real-time interaction mechanisms. The publishers of general communication protocol messages and their published data objects are considered nodes in the graph, while the subscribers of general communication protocol messages and their received data objects are considered another set of nodes. By establishing connections between these two sets of nodes, a series of edges are formed to represent their relationships, thus creating a complete knowledge graph.

[0045] In one specific embodiment, the System Configuration Description (SCD) conforming to the IEC 61850 standard is first parsed. As a standardized file for configuring the secondary system of a smart substation, the SCD file contains key configuration information such as IED (Intelligent Electronic Device) device configuration, logical nodes (LN), data objects (DO), data attributes (DA), GOOSE / SV control blocks, datasets, and message descriptions, and describes in detail the structure and communication protocols of the substation's secondary circuits.

[0046] To achieve comprehensive parsing of SCD files, this invention employs a modular tool based on an XML parser. Following the semantic rules of the IEC 61850 standard, it transforms the structured configuration information in the SCD file into a machine-readable internal data model. This model accurately reflects the structural relationships within the configuration file and provides support for subsequent knowledge graph construction and reasoning analysis.

[0047] In the specific implementation process, the IED device and its internal logical nodes are first modeled. For each IED device... It contains several logical nodes. These logical nodes constitute the internal logical system of the IED device. Based on this, the following mapping relationship is established: in, Indicates the first One IED device, Indicates the first in the device One logical node.

[0048] Next, for each GOOSE control block and its dataset description in the SCD file, extract each GOOSE control block. dataset And further identify the collection of data objects it contains. This creates a "publish-subscribe" relationship mapping. The specific form is: in, This refers to the IED device and its data objects at the GOOSE message publishing end. This represents the subscriber device for the GOOSE message and the data object it receives. The arrows indicate the logical relationship between the message publication and subscription as defined in the configuration file.

[0049] Furthermore, to accurately map and express the dependencies between components in the quadratic loop, an entity-relationship triple notation is adopted. Specifically, all logical nodes (LN), data objects (DO), data attributes (DA), and their attribute configurations are parsed to form a preliminary set of triples: in, This indicates that a certain IED device owns a certain data object. This indicates the logical dependency relationship that triggers the GOOSE message for the data object. The dot “…” indicates that the set of relationships also includes other logical relationships such as soft pressure plate mapping and control block enablement relationships.

[0050] To further enhance the model's expressive power, adjacency matrices and graph Laplacian matrices from graph theory are introduced to represent the connections and dependencies between components in a quadratic cycle. Assume the set of nodes in the graph is... The edge set is Then the adjacency matrix It can be represented as: in, For nodes and The connection relationship between them, if a connection exists. ,otherwise Based on this adjacency matrix, a graph Laplacian matrix can be further constructed. Its definition is: in, For a degree matrix, its diagonal elements Represents a node The degree of a node, i.e., the number of connections to that node. (Graph Laplacian matrix) It can effectively reflect the connectivity and dependencies in graph structures, providing an important mathematical foundation for subsequent reasoning analysis and anomaly detection.

[0051] Ultimately, the multi-level abstract model generated through this step This provides foundational data support for subsequent knowledge graph construction and reasoning analysis. The abstract model accurately reflects the logical and topological relationships of components in the substation's secondary circuits, providing a reliable data structure for intelligent verification and anomaly detection. Furthermore, leveraging the properties of the graph Laplace matrix, further graph embedding reasoning can be performed, providing strong support for the automatic detection of potential anomalies.

[0052] After completing the parsing of the configuration file and the extraction of triples, this invention further constructs a heterogeneous knowledge graph of the secondary loop to uniformly model the device entities such as IED, LN, DO, GOOSE, and soft pressure plate in the secondary system and their topological and logical relationships, thereby realizing the global visualization and reasonable structural description of the secondary loop.

[0053] The method of this invention is based on graph theory, which expresses the logical structure of a quadratic loop and the relationships between devices as a set of triples. That is, to build a knowledge graph : in, This represents the constructed knowledge graph; It is a set of entity nodes in the graph, including various components in the secondary loop such as IED, LN, DO, GOOSE, soft pressure plate, and remote signal; It is a set of directed edges in the graph, used to describe the relationships between nodes, such as connections, dependencies, triggers, and logical flows. This is a set of semantic labels for edges, used to define the semantic meaning of each edge, such as "physical connection", "GOOSE trigger", "protection linkage", etc.

[0054] In this spectrum, any triplet Represents a de novo entity End-to-end entity There is a relationship ,For example: ,express Published Message.

[0055] In one embodiment, after step S203 of constructing the preset knowledge graph based on the intelligent electronic device and its published data object at the general communication protocol message publishing end, the intelligent electronic device and its received data object at the general communication protocol message subscribing end, and the logical relationship between the general communication protocol message publishing end and the general communication protocol message subscribing end, the method further includes: S2041: Extract any set of triples from the preset knowledge graph as the target triple; S2042: Vectorize the target entities and target relations in the target triples to obtain the vector set of the target triples; S2043: Calculate the edge loss value of the vector set using a preset edge loss function; S2044: Minimize the edge loss value using a preset optimization algorithm to obtain the optimized target entity and target relationship; S2045: Input the optimized target entity and the target relationship into the preset knowledge graph to obtain the optimized preset knowledge graph.

[0056] As described in steps S2041-S2045 above, the preset knowledge graph has been optimized. To facilitate subsequent reasoning and analysis, this invention employs knowledge graph embedding technology (e.g., the TransE model) to vectorize the entities and relationships in the graph. The TransE embedding model uses the following preset edge loss function. To depict the triplet Reasonableness: in, Represents a triplet The edge loss value; Representing the head entity respectively ,relation Tail entity Low-dimensional vector embedding representation; symbol The Euclidean norm is used to measure... and The distance between them.

[0057] By minimizing this edge loss function, the embedding model embeds real-world triples into the vector space, minimizing their edge loss value and thus enhancing the ability to infer potential edges and detect anomalous connections in subsequent inferences. This embedding method can capture complex relationships and dependency structures in a low-dimensional vector space, enabling the efficient storage and analysis of logical and topological information in the graph.

[0058] Furthermore, this invention defines the following typical relationships in the graph model to accurately describe various dependencies and logical relationships in secondary loops: ① Physical connection relationship: such as direct wiring between terminals, this relationship enables data flow between devices through hardware connection; ② Logical dependencies: such as the soft pressure plate switching status affecting the triggering of GOOSE messages. This type of relationship describes the control logic and operational dependencies between devices; ③ Signal flow relationship: such as the path dependency of the sampled value message being sent from IED_A to IED_B, which represents the logical relationship of the data flow path; Other inferred relationships: such as the correlations in the secondary circuits inferred through analysis, including the collaborative relationships between devices, virtual connections, etc.

[0059] In this process, each edge of the graph has a clear semantic label, which is used to define the edge semantic label set. Each type of relation is uniquely identified to ensure the topological consistency and semantic accuracy of the graph structure. Specifically, the semantic label of an edge can be represented as a set of relations. This allows for accurate modeling of the topological structure and semantics of the entire graph.

[0060] Furthermore, to enhance the accuracy and flexibility of reasoning, this invention employs Graph Neural Network (GNN) technology to further train and optimize the embedding vectors. GNN, through iterative message passing and node update mechanisms, can effectively propagate information within the graph structure and capture complex dependencies. The state of each node is updated using information from its neighbors, thereby gradually adjusting the node's representation so that the node's embedding vector more closely matches the true logic of the graph structure.

[0061] During inference, graph neural networks can combine semantic labels of edges to dynamically adjust the information flow between nodes, enabling the effective identification of potential abnormal connections, breakpoints, and inconsistent logical relationships. For example, if a certain node... Expected to receive from node The information is received, but no relevant signal is received in the actual running state. The inference engine in the graph will mark the relationship as a potential anomaly for subsequent anomaly detection and fault diagnosis.

[0062] Through the knowledge graph constructed above, this invention achieves comprehensive modeling of secondary circuit devices, covering the relationships between devices in multiple dimensions such as physical connection, control logic, and signal transmission, providing reliable data support and decision-making basis for subsequent reasoning analysis, anomaly detection, and intelligent verification.

[0063] In one embodiment, after step S203 of constructing the preset knowledge graph based on the intelligent electronic device and its published data object at the general communication protocol message publishing end, the intelligent electronic device and its received data object at the general communication protocol message subscribing end, and the logical relationship between the general communication protocol message publishing end and the general communication protocol message subscribing end, the method further includes: S2141: Determine whether the system configuration description file has been updated; S2142: If the system configuration description file is updated, an updated knowledge graph is generated based on the updated system configuration description file; S2143: Compare the preset knowledge graph and the updated knowledge graph to obtain a set of edge differences where there are differences; S2144: Construct an incremental subgraph based on the edge difference set; S2145: Verify the mapping of the incremental subgraph to the updated knowledge graph.

[0064] As described in steps S2141-S2145 above, during the construction and operation of substation projects, the SCD configuration file and project version often need to be updated frequently, such as adding IED devices, adjusting logical nodes, and changing GOOSE channel configurations. To cope with these changes, traditional verification methods require repeated verification of the entire system, leading to low efficiency and wasted computing resources. This invention proposes a hot-swappable incremental verification mechanism that supports automatic identification of differences after project version updates, performing incremental verification only on the changed areas, avoiding overall repeated verification, and significantly improving efficiency and accuracy.

[0065] Assuming at any time The system contains knowledge graphs generated from parsing older configuration files. And the knowledge graph generated by parsing the new version's configuration file. The difference detection process involves calculating the differences between the node set and the edge set. The specific steps are as follows: Node Difference Set : Represents the set of nodes that have been newly added or whose attributes have changed. The calculation formula is: in, and These represent the node sets in the old and new versions of the graph, and the node difference set, respectively. Includes nodes that appear in the new version but did not exist in the old version.

[0066] Edge difference set : Represents the set of edges that have been added or whose attributes have changed. The calculation formula is: in, and These represent the edge sets in the old and new versions of the graph, respectively. The set difference operation... "Calculated based on node ID, attribute hash fingerprint, and edge triplet uniqueness. Edge difference set." This includes edges that appear in the new version or whose attributes have changed.

[0067] After obtaining the difference sets of nodes and edges, the system updates the graph in the new version. Constructing incremental subgraphs It contains all newly added or changed nodes and edges: in, This represents the subgraph to be incrementally verified. and These are the node difference set and the edge difference set, respectively. Let be the semantic set of the corresponding difference edges, i.e.: in, It is a semantic set containing differential edge relationships, representing the semantic labels corresponding to these edges in the new version, such as "physical connection" and "GOOSE trigger".

[0068] The optimized target entity and the target relationship (i.e., the incremental subgraph) are then used to... The data is input into the preset knowledge graph. During the state mapping process, the system associates real-time running data with nodes in the incremental subgraph to ensure that newly added or changed nodes and edges are consistent with the current running state data. Through reasoning analysis, the system identifies a set of potential abnormal edges in the discrepancies. The specific calculation formula is as follows: in, This represents the set of potential anomalous edges discovered in the difference portion. This represents the probability of an anomaly determined through a graph neural network (GNN) or logical reasoning process. This is a preset threshold for judgment. If the edge's abnormal probability... Exceeding the threshold If the edge is considered to have a potential anomaly, an alarm will be triggered and the process will proceed to the subsequent reporting stage.

[0069] Finally, based on the incremental subgraph Based on the anomaly detection results, the system generates an incremental verification report. The report only contains The corresponding inconsistencies, link paths, and inference results. Incremental verification reports can significantly reduce the size of reports and the workload of operations and maintenance personnel in reviewing them. The report content includes: ① Potential anomalies: List all detected potential anomalies, including anomaly type, anomaly probability, involved device, data object, GOOSE / SV channel, etc.

[0070] ② Link Tracing: Displays the configuration link corresponding to the anomaly item and presents the anomaly path in the form of a graph structure.

[0071] ③ Reasoning Results: Provides reasoning analysis results for each anomaly, including causal analysis and possible consequences.

[0072] Through an incremental verification mechanism, this invention not only quickly identifies potential new faults introduced by engineering changes, but also significantly improves the response speed, efficiency, and intelligence of system engineering management and secondary circuit verification. The main advantages of this mechanism include: High efficiency: Incremental verification is performed only on the changed areas, avoiding repeated checks on the entire system and significantly improving verification efficiency.

[0073] Flexibility: Supports dynamic incremental verification, adapts to rapid changes in project versions, and can cope with frequent configuration file updates.

[0074] Intelligentization: Through graph reasoning and state mapping, the system can automatically identify potential anomalies, reduce manual intervention, and improve the level of automation.

[0075] The incremental verification mechanism is applicable to large-scale substations and smart grid systems. Especially in scenarios such as engineering construction, system maintenance and version updates, it can provide engineers with real-time and accurate verification and anomaly detection results, ensuring the security and reliability of the system.

[0076] In summary, this invention automatically parses secondary circuit configuration information from the SCD configuration file, establishes a knowledge graph model based on multiple entities and relationships, and performs state mapping using operational data, achieving complete modeling and dynamic consistency detection of the secondary circuit logical links. Furthermore, through logical rule reasoning and graph neural network embedding reasoning, it can automatically identify potential anomalies, connection errors, and link breakpoints, overcoming the limitations of traditional methods in static verification and manual intervention, and improving the intelligence and accuracy of anomaly detection. Simultaneously, the incremental verification mechanism supports hot updates and rapid change detection for engineering versions, significantly avoiding the inefficiency of repeatedly verifying the entire system, greatly improving the efficiency and accuracy of verification work, especially in scenarios with frequent engineering changes, enabling efficient real-time response and accurate fault warnings. This invention's technical solution has a clear technical roadmap and implementation path, and can be widely applied to the construction, commissioning, operation, and maintenance of substations, meeting the industry's urgent needs for automation, intelligence, and traceability in secondary circuit verification, and improving system safety, reliability, and operational efficiency.

[0077] In one embodiment, after step S3 of verifying the fused graph through a preset graph inference mechanism, the method further includes: S401: Obtain the verified abnormal edges and their probabilities; S402: Obtain data information related to the abnormal edge; S403: Generate a verification report based on the data information and the anomaly probability.

[0078] As described in steps S401-S403 above, the verification report is generated. After completing the knowledge graph reasoning and potential anomaly identification, this invention, through the verification report generation module, summarizes and analyzes the reasoning results and operational mapping information to generate a structured verification report and provides an interactive confirmation interface for engineers to further verify, validate, and process. This process not only improves the traceability and verifiability of the report but also provides substation operation and maintenance personnel with efficient, intuitive, and interpretable verification analysis results.

[0079] First, based on the set of potential anomalies obtained during the reasoning process... Generate a verification report. Potential anomaly set. Includes all anomalies detected through logical reasoning and graph embedding reasoning. Verification report collection. Defined as: in, This represents a graph edge (triplet) that is marked as a potential anomaly. This represents the probability of an anomaly of the edge calculated during the reasoning process. This indicates the traceable path generated by the system, that is, the full path information from the configuration logic to the current abnormal node.

[0080] according to The report module generates the following: The report lists all potential anomalies, indicating the anomaly type, probability, involved equipment, data object, GOOSE / SV channel, soft pressure plate status, and other key information. Each anomaly item... All will include the following information: ①Exception type: Indicates whether it is a connection exception, logical error, empty connection, etc.

[0081] ②Probability of anomalies This indicates the likelihood of the anomaly and serves as an important indicator for assessing its severity.

[0082] ③Related devices: List the IED devices, logical nodes, data objects, etc. related to the anomaly.

[0083] ④ Key information: including the configuration of the GOOSE / SV channel, the switching status of the soft pressure plate, etc.

[0084] In one embodiment, after step S403 of generating a verification report based on the data information and the anomaly probability, the method further includes: S4041: Process the anomalies based on the verification report, and record the anomalies and their processing records; S4042: Send the anomaly item and its processing record to the backtracking database; S4043: Update the preset graph reasoning mechanism based on the backtracking database.

[0085] As described in steps S4041-S4043 above, the report will display the configuration links corresponding to anomalies in a graph structure. Given any two nodes in the graph... and Link tracing path Defined as starting from the link origin To the end of the link The complete path set: in, Indicates the first in the path Edges and their upstream and downstream nodes. By tracing the source path, the configuration logic that caused the anomaly and its data flow process can be intuitively displayed, helping engineers quickly locate the source of the problem.

[0086] The front-end component of the graph highlights each anomaly edge and uses color, line type, and blinking to enhance the visualization of anomaly detection. Users can click to view detailed anomaly information, including: Historical Status Change Curve: Displays the historical changes in the status of a device or connection, helping to determine when and why an anomaly occurred.

[0087] Original configuration file snippet: Displays the configuration file content related to the exception, helping engineers understand the differences between the configuration and actual operation.

[0088] The report generation process can export the verification results as structured files (such as PDF, Word, and CSV formats) or generate API data streams for subsequent system integration with other monitoring and maintenance systems. In addition, the system provides the following interactive functions: confirmation, ignore, and manual annotation: engineers can confirm anomalies based on the report content, ignore unimportant anomalies, or manually annotate the nature and cause of anomalies. The results of these operations will be stored in the backtracking database. This is to facilitate subsequent model training and anomaly detection accuracy optimization.

[0089] By tracing back to the database, the system can record feedback from engineers, accumulate data, and further improve the accuracy and intelligence of anomaly detection.

[0090] Backtracking database The system stores the processing history of all anomalies and their corresponding human feedback. Based on this feedback, the system can dynamically adjust model parameters to optimize anomaly detection and inference accuracy. The system can update the model after each anomaly handling using the following optimization formula: in, These are model parameters. It is a loss function. It's the learning rate. This represents the gradient of the loss function with respect to the model parameters. Through stepwise optimization, the model can adaptively learn based on feedback data, thereby improving the accuracy of subsequent detections. Through this process, the report not only provides a detailed analysis of anomaly identification but also offers engineers an intuitive and user-friendly interface for subsequent processing. The output and interactive confirmation of this verification report not only ensures the report's traceability and verifiability but also significantly improves the intelligence and automation level of substation operation and maintenance.

[0091] Reference Figure 3 The present invention also provides a secondary circuit verification device, the device comprising: The acquisition module 902 is used to acquire the operating status data of the secondary circuit of a specified substation; The mapping module 904 is used to map the running state data to a preset knowledge graph based on a preset mapping function, so as to associate the corresponding target graph node and its dynamic attribute state in the preset knowledge graph, thereby obtaining a fusion graph of the running state data and the preset knowledge graph. The verification module 906 is used to verify the fused graph through a preset graph reasoning mechanism.

[0092] In one embodiment, the secondary circuit verification device further includes: The system configuration description file acquisition module is used to acquire the system configuration description file of the secondary circuit of the specified substation and multiple intelligent electronic devices; The system configuration description file parsing module is used to parse the system configuration description file to obtain the intelligent electronic device and its published data object of the general communication protocol message publishing end, the intelligent electronic device and its received data object of the general communication protocol message subscribing end, and the logical relationship between the general communication protocol message publishing end and the general communication protocol message subscribing end; A preset knowledge graph construction module is used to construct the preset knowledge graph based on the intelligent electronic device and its published data object of the general communication protocol message publishing end, the intelligent electronic device and its received data object of the general communication protocol message subscribing end, and the logical relationship between the general communication protocol message publishing end and the general communication protocol message subscribing end.

[0093] In one embodiment, the secondary circuit verification device further includes: The triplet extraction module is used to extract any set of triples from the preset knowledge graph as the target triplet. The vectorization module is used to vectorize the target entities and target relations in the target triples to obtain the vector set of the target triples; The edge loss calculation module is used to calculate the edge loss value of the vector set using a preset edge loss function; The edge loss value optimization module is used to minimize the edge loss value through a preset optimization algorithm to obtain the optimized target entity and target relationship; The preset knowledge graph optimization module is used to input the optimized target entity and the target relationship into the preset knowledge graph to obtain the optimized preset knowledge graph.

[0094] In one embodiment, the secondary circuit verification device further includes: The system configuration description file determination module is used to determine whether the system configuration description file has been updated; The knowledge graph generation module is updated to generate an updated knowledge graph based on the updated system configuration description file if the system configuration description file is updated. A knowledge graph comparison module is used to compare the preset knowledge graph and the updated knowledge graph to obtain a set of edge differences where there are differences. An incremental subgraph construction module is used to construct an incremental subgraph based on the set of edge differences. The incremental subgraph verification module is used to verify the mapping of the incremental subgraph to the updated knowledge graph.

[0095] In one embodiment, the secondary circuit verification device further includes: The abnormal edge acquisition module is used to acquire the verified abnormal edges and their probabilities. The data information acquisition module is used to acquire data information related to the abnormal edge; The verification report generation module is used to generate a verification report based on the data information and the anomaly probability.

[0096] In one embodiment, the secondary circuit verification device further includes: The processing module is used to process the anomalies based on the verification report and record the anomalies and their processing records. The sending module is used to send the anomaly items and their processing records to the backtracking database; The update module is used to update the preset graph reasoning mechanism based on the backtracking database.

[0097] In one embodiment, the preset graph reasoning mechanism is either logic rule-based reasoning or graph embedding-based reasoning.

[0098] Figure 4 An internal structural diagram of an electronic device in one embodiment is shown. This electronic device can specifically be a terminal or a server, and more specifically, a computer device. Figure 4 As shown, the electronic device includes a processor, a memory, and a network interface connected via a system bus. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system and may also store a computer program. When executed by the processor, this computer program enables the processor to implement a secondary loop verification method. The internal memory may also store a computer program, which, when executed by the processor, enables the processor to implement the secondary loop verification method. Those skilled in the art will understand that… Figure 4 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the electronic device to which the present application is applied. The specific electronic device may include more or fewer components than shown in the figure, or combine certain components, or have different component arrangements.

[0099] In one embodiment, an electronic device is provided, including a memory and a processor, the memory storing a computer program that, when executed by the processor, causes the processor to perform the following steps: Collect operational status data of the secondary circuits of a designated substation; Based on a preset mapping function, the running data is mapped to a preset knowledge graph to associate the corresponding target graph node and its dynamic attribute state in the preset knowledge graph, thereby obtaining a fusion graph of the running data and the preset knowledge graph. The fused graph is verified using a preset graph reasoning mechanism.

[0100] By automatically constructing a knowledge graph of secondary loops, a unified model of configuration logic and runtime data is established, enabling the verification of secondary loops to go beyond field consistency checks. Instead, it enables global modeling and automated reasoning of logical dependencies across devices and links, uncovering potential hidden anomalies, breakpoints, and faulty connections that existing tools cannot identify.

[0101] In one embodiment, a computer-readable storage medium is provided storing a computer program that, when executed by a processor, causes the processor to perform the following steps: Collect operational status data of the secondary circuits of a designated substation; Based on a preset mapping function, the running data is mapped to a preset knowledge graph to associate the corresponding target graph node and its dynamic attribute state in the preset knowledge graph, thereby obtaining a fusion graph of the running data and the preset knowledge graph. The fused graph is verified using a preset graph reasoning mechanism.

[0102] By automatically constructing a knowledge graph of secondary loops, a unified model of configuration logic and runtime data is established, enabling the verification of secondary loops to go beyond field consistency checks. Instead, it enables global modeling and automated reasoning of logical dependencies across devices and links, uncovering potential hidden anomalies, breakpoints, and faulty connections that existing tools cannot identify.

[0103] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments described above. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and RAMbus dynamic RAM (RDRAM), etc.

[0104] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0105] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A secondary circuit verification method, characterized by, The method comprises: collecting operation state data of a specified substation secondary circuit; mapping the operation state data to a preset knowledge graph based on a preset mapping function, to associate corresponding target graph nodes and their dynamic attribute states in the preset knowledge graph, thereby obtaining a fusion graph of the operation state data and the preset knowledge graph; checking the fusion graph through a preset graph reasoning mechanism.

2. The secondary circuit verification method of claim 1, wherein, Before the step of mapping the operation state data to a preset knowledge graph based on a preset mapping function, to associate corresponding target graph nodes and their dynamic attribute states in the preset knowledge graph, thereby obtaining a fusion graph of the operation state data and the preset knowledge graph, the method further comprises: obtaining a system configuration description file and a plurality of intelligent electronic devices of the specified substation secondary circuit; parsing the system configuration description file to obtain intelligent electronic devices of a general communication protocol message publishing end and their publishing data objects, intelligent electronic devices of a general communication protocol message subscribing end and their received data objects, and a logical relationship between the general communication protocol message publishing end and the general communication protocol message subscribing end; constructing the preset knowledge graph based on the intelligent electronic devices of the general communication protocol message publishing end and their publishing data objects, the intelligent electronic devices of the general communication protocol message subscribing end and their received data objects, and the logical relationship between the general communication protocol message publishing end and the general communication protocol message subscribing end.

3. The secondary circuit verification method of claim 2, wherein, After the step of constructing the preset knowledge graph based on the intelligent electronic devices of the general communication protocol message publishing end and their publishing data objects, the intelligent electronic devices of the general communication protocol message subscribing end and their received data objects, and the logical relationship between the general communication protocol message publishing end and the general communication protocol message subscribing end, the method further comprises: extracting any group of triples in the preset knowledge graph as target triples; vectorizing target entities and target relationships in the target triples to obtain a vector set of the target triples; calculating an edge loss value of the vector set through a preset edge loss function; minimizing the edge loss value through a preset optimization algorithm to obtain optimized target entities and target relationships; inputting the optimized target entities and target relationships into the preset knowledge graph to obtain an optimized preset knowledge graph.

4. The secondary circuit verification method of claim 2, wherein, After the step of constructing the preset knowledge graph based on the intelligent electronic devices of the general communication protocol message publishing end and their publishing data objects, the intelligent electronic devices of the general communication protocol message subscribing end and their received data objects, and the logical relationship between the general communication protocol message publishing end and the general communication protocol message subscribing end, the method further comprises: determining whether the system configuration description file is updated; if the system configuration description file is updated, generating an updated knowledge graph based on the updated system configuration description file; comparing the preset knowledge graph and the updated knowledge graph to obtain a set of edge differences; constructing an incremental subgraph based on the set of edge differences; checking the incremental subgraph mapped into the updated knowledge graph.

5. The secondary circuit verification method of claim 1, wherein, The step of checking the fusion graph through the preset graph reasoning mechanism further comprises: acquiring the abnormal edge and the abnormal probability after checking; acquiring data information related to the abnormal edge; generating a checking report based on the data information and the abnormal probability.

6. The secondary circuit verification method of claim 5, wherein, The step of generating a checking report based on the data information and the abnormal probability further comprises: processing the abnormal item based on the checking report and recording the abnormal item and its processing record; sending the abnormal item and its processing record to a backtracking database; updating the preset graph reasoning mechanism based on the backtracking database.

7. The secondary circuit verification method of claim 1, wherein, The preset graph reasoning mechanism is any one of a logic rule-based reasoning and a graph embedding-based reasoning.

8. A secondary circuit verification device, characterized by The device comprises: a collection module for collecting operation state data of a secondary circuit of a specified transformer substation; a mapping module for mapping the operation state data to a preset knowledge graph based on a preset mapping function to associate corresponding target graph nodes and their dynamic attribute states in the preset knowledge graph, thereby obtaining a fusion graph of the operation state data and the preset knowledge graph; a checking module for checking the fusion graph through a preset graph reasoning mechanism.

9. A computer-readable storage medium, characterized in that, A computer program is stored, and when executed by a processor, causes the processor to perform the steps of the secondary circuit checking method according to any one of claims 1 to 7.

10. An electronic device, comprising: The device comprises a memory and a processor, and the memory stores a computer program which, when executed by the processor, causes the processor to perform the steps of the secondary circuit checking method according to any one of claims 1 to 7.

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