Memory circuit and operating method thereof

Abstract

The embodiment of the invention discloses a memory circuit and an operating method thereof. The memory circuit includes: a first memory cell configured to store a first data bit; a second memory cell configured to store a second data bit; a sense amplifier coupled to the first and second memory cells through a data bit line and a reference bit line, respectively; a first switch; and a second switch. A first switch is selectively coupled between the data bit line and a first input node of the sense amplifier, and a second switch is selectively coupled between the reference bit line and a second input node of the sense amplifier.

Description

Technical Field

[0001] Embodiments of this application relate to memory circuits and methods of operation thereof. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to the increasing integration density of various electronic components, such as transistors, diodes, resistors, and capacitors. To a large extent, this increase in integration density stems from the repeated reduction in the size of the smallest component, allowing more components to be integrated into a given area. Summary of the Invention

[0003] According to one aspect of the embodiments of this application, a memory circuit is provided, comprising: a first memory cell configured to store a first data bit; a second memory cell configured to store a second data bit; a sense amplifier coupled to the first memory cell and the second memory cell via a data bit line and a reference bit line, respectively; a first switch; and a second switch; wherein the first switch is selectively coupled between the data bit line and a first input node of the sense amplifier, and the second switch is selectively coupled between the reference bit line and a second input node of the sense amplifier.

[0004] According to another aspect of the embodiments of this application, a memory circuit is provided, comprising: a sense amplifier configured to identify data bits stored in a first memory cell by comparing a first signal present on a data bit line connecting a first memory cell to the sense amplifier and a second signal present on a reference bit line connecting a second memory cell to the sense amplifier; a first switch configured to selectively couple the data bit line to a first input node of the sense amplifier based on an enable signal; and a second switch configured to selectively couple a reference bit line to a second input node of the sense amplifier based on an enable signal.

[0005] According to another aspect of the embodiments of this application, a method for operating a memory circuit is provided, comprising: pre-charging a data bit line and a reference bit line to a first logic state, wherein the data bit line and the reference bit line are respectively coupled to a first input node and a second input node of a sense amplifier, wherein the data bit line is coupled to a data cell and the reference bit line is coupled to a reference cell; discharging the data bit line and the reference bit line, wherein the first input node and the second input node are respectively maintained coupled to the data bit line and the reference bit line, and both the first input node and the second input node are decoupled from any transistor; and latching a data bit stored in a data cell, wherein the first input node and the second input node are respectively decoupled from the data bit line and the reference bit line. Attached Figure Description

[0006] The various aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, the various parts are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various parts may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 An example block diagram of a memory circuit according to some embodiments is shown.

[0008] Figure 2 Illustrations are shown according to some embodiments Figure 1 Example circuit diagram of a memory cell in a memory circuit.

[0009] Figure 3 Illustrations are shown according to some embodiments Figure 1 Example circuit diagram of a portion of the memory circuit.

[0010] Figure 4 The operation according to some embodiments is shown. Figure 1 The waveforms of various signals during the operation of the memory circuit.

[0011] Figure 5 , Figure 6 and Figure 7 Several embodiments are shown respectively. Figure 1 Example circuit diagram of the switch for the memory circuit.

[0012] Figure 8 Illustrations are shown according to some embodiments Figure 1 Another example circuit diagram of a portion of the memory circuit.

[0013] Figure 9 Illustrations are shown according to some embodiments Figure 1 Alternative circuit diagram for the sense amplifier in the memory circuit.

[0014] Figure 10 Illustrations are shown according to some embodiments Figure 1 Another alternative circuit diagram for the sense amplifier of the memory circuit.

[0015] Figure 11 The following are illustrations of operation according to some embodiments. Figure 1 Example flowchart of a method for a memory circuit. Detailed Implementation

[0016] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific embodiments or examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0017] Furthermore, for ease of description, this document may use spacing relation terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spacing relation terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spacing relation descriptors used herein can be decoupled accordingly.

[0018] Many modern electronic devices include electronic memory devices configured to store data. Electronic memory devices are typically either volatile or non-volatile. Volatile memory devices store data when power is applied, while non-volatile memory devices retain data when power is off. Resistive random access memory (RRAM) devices are a promising candidate for next-generation non-volatile memory technology. RRAM devices have a simple structure, consume small cell area, have low switching voltage and fast switching time, and are compatible with complementary metal-oxide-semiconductor (CMOS) manufacturing processes.

[0019] RRAM devices include a variable-resistance dielectric layer disposed between conductive electrodes and are configured to operate based on a reversible switching process between resistance states. This reversible switching is achieved by selectively forming conductive filaments through the variable-resistance dielectric layer. For example, by applying a voltage across the conductive electrodes to form conductive filaments extending through the variable-resistance dielectric layer, the normally insulating variable-resistance dielectric layer can be switched on. An RRAM cell may have a first (e.g., high) resistance state corresponding to a first data state (e.g., logic "0") and a second (e.g., low) resistance state corresponding to a second data state (e.g., logic "1").

[0020] The scaling of existing RRAM circuits may be limited due to degradation in performance and reliability characteristics. For example, as the size of RRAM cells (typically formed on the back-end fabrication network) decreases relative to transistors (typically formed on the front-end fabrication network), parasitic capacitances (e.g., C) between different terminals of the transistors increase. gd The data state stored in an RRAM cell is typically determined by a sense amplifier, which consists of transistors formed on the front-end fabrication network. In existing RRAM circuits, the data lines (e.g., bit lines) of the RRAM cell are directly coupled to the input node of the sense amplifier. This direct coupling to the input node disadvantageously reduces the read window of the RRAM cell. This problem becomes increasingly critical as parasitic capacitance increases with scaling. Therefore, existing RRAM circuits are not entirely satisfactory in some respects.

[0021] This disclosure provides various embodiments of a memory circuit including a sense amplifier whose input nodes are selectively coupled to data lines of one or more corresponding memory cells. In some embodiments, the memory cells of the disclosed memory circuit may include RRAM cells. However, it should be understood that the memory cells may be any of a variety of other non-volatile memory cells, such as magnetoresistive random access memory (MRAM) cells, spintronic memory cells, one-time programmable (OTP) memory cells, etc., or may be volatile memory cells, such as static random access memory (SRAM) cells, while still within the scope of this disclosure. The sense amplifier may include a pair of cross-coupled inverters having two input nodes that are selectively coupled to a pair of access lines (e.g., a data line and a reference line), respectively. For example, during the evaluation phase, the input nodes are coupled to the access lines while being decoupled from the cross-coupled inverters; during the latching phase, the input nodes are decoupled from the access lines while being coupled to the cross-coupled inverters. By selectively coupling the input nodes to the access lines, data bits stored in the input nodes can be advantageously protected from contamination by parasitic capacitances (if any). Therefore, even if the trend of shrinking transistor size is followed, the disclosed memory circuit may not exhibit the aforementioned problems.

[0022] Figure 1 Example block diagrams of memory circuitry 100 according to various embodiments of the present disclosure are shown. As shown, memory circuitry 100 includes one or more memory arrays 110, word line (WL) drivers 120, input / output (I / O) circuitry 130, and a memory controller 140. It should be understood that, for illustrative purposes, Figure 1The block diagram has been simplified, so the memory circuit 100 may include any of a variety of other components, such as a sinker, a source line (SL) driver, a precharge circuit, etc., while still within the scope of this disclosure.

[0023] The memory array 110 includes a plurality of first storage circuits for a first memory cell 115 or a plurality of second storage circuits for a second memory cell 117, which can be configured as a two-dimensional or three-dimensional array. In some embodiments, each of the first memory cell 115 and the second memory cell 117 includes an RRAM cell. However, each of the first / second memory cells 115 / 117 may include any of a variety of other configured memory cells while still within the scope of this disclosure. For example, each of the first / second memory cells 115 / 117 may include an MRAM cell, a spintronic memory cell, an OTP memory cell, or an SRAM cell.

[0024] As will be below Figure 2 As shown, each of the first / second memory (RRAM) cells 115 / 117 can be implemented as a 1-transistor-1-resistor (1T1R) structure, such as a variable resistor connected in series with a transistor. Each of the first / second memory cells 115 / 117 in the memory array 110 can be coupled to a corresponding word line WL and a corresponding bit line BL. For example, the memory array 110 includes multiple word lines WL arranged across multiple rows, such as WL... <0> WL <1> …WL <n-1>The number "N" can be any integer. Each word line WL can extend along a first direction. The memory array 110 also includes multiple bit lines BL arranged across multiple columns, such as BL... <0> BL <1> …BL <k-1>The number "K" can be any integer. Each bit line BL can extend in a second direction perpendicular to the first direction.

[0025] In some embodiments, each of the first memory cells 115 is configured to store a data bit corresponding to a high-resistance state (high resistance) or a low-resistance state (low resistance), while each of the second memory cells 117 is configured to provide a reference resistance between the high and low resistance states. The first memory cell 115 and the second memory cell 117 are sometimes referred to as "data cell 115" and "reference cell 117," respectively. As will be discussed below, each data cell 115 is coupled to a corresponding reference cell 117 to a sense amplifier (of the I / O circuit 130), wherein the corresponding reference cell 117 is configured to provide a reference signal (e.g., voltage, current) to the sense amplifier to identify or otherwise determine the logical state of the data bit stored by the data cell 115. In some embodiments, the second memory cells 117 may be arranged along one or more columns of the K columns (sometimes referred to as "reference columns"), while the first memory cells 115 may be arranged along the remaining columns of the K columns (sometimes referred to as "data columns").

[0026] The memory controller 140 is a hardware component that can control (e.g., read) the operation of the memory array 110 via the WL controller 120 and / or I / O circuitry 130. The WL driver circuitry 120 and I / O circuitry 130 can each be implemented as one or more logic circuits, one or more analog circuits, or a combination thereof. In some embodiments, the WL driver circuitry 120 is a circuit that can provide voltage or current (e.g., a WL assertion signal with one or more pulses) via the assertion word line WL of the memory array 110, and the I / O circuitry 130 is a circuit that can provide or sense voltage or current via one or more bit lines BL of the memory array 110. As will be discussed in further detail below, the I / O circuitry 130 may include multiple sense amplifiers. Each sense amplifier can be coupled to the reference cell 117 and the data cell 115 via a pair of bit lines BL (sometimes referred to as "reference bit line RBL" and "data bit line DBL," respectively), wherein the sense amplifier has a pair of input nodes that are selectively coupled to the reference bit line RBL and the data bit line DBL via a first switch and a second switch, respectively. In some other embodiments, the memory circuit 100 may include a ratio Figure 1 The components may be more, fewer, or different. For example, the memory circuit 100 may also include a timing controller, which can provide control signals or clock signals to synchronize the operation of the WL driver circuit 120 and the I / O circuit 130.

[0027] Figure 2 An example circuit diagram of a memory cell (hereinafter referred to as "memory cell 200") of a memory array 110 according to some embodiments of the present disclosure is shown. Figure 2 In some embodiments, a memory cell 200 comprising a series-connected transistor and a variable resistor (1T1R) can represent the configuration of data cell 115 and / or reference cell 117. However, it should be understood that... Figure 2 The circuit diagrams are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0028] As shown, memory cell 200 includes a variable resistor 210 and an access transistor 220 connected in series. The variable resistor 210 can present a resistance state that can switch between a low resistance state (LRS) and a high resistance state (HRS). The resistance state indicates the data value stored in memory cell 200 (e.g., logic "1" or logic "0"). Furthermore, a first terminal of the variable resistor 210 is connected to bit line BL, a second terminal of the variable resistor 210 is connected to the first source / drain terminal of the access transistor 220, the gate terminal of the access transistor 220 is connected to word line WL, and the second source / drain terminal of the access transistor 220 is connected to the source line SL, which is normally grounded. With this configuration, for example, applying a signal with logic 1 to the gate terminal of the access transistor 220 can activate (e.g., turn on) the access transistor 220 by asserting word line WL. After activation, another signal can be applied to bit line BL to read or write to the variable resistor 210.

[0029] In some embodiments, the access transistor 220 may be formed in a front-end process network, while the variable resistor 210 may be formed in a back-end process network. In some other embodiments, both the access transistor 220 and the variable resistor 210 may be formed in a back-end process network. Generally, a front-end process network refers to a structure formed along the main surface of a semiconductor substrate, while a back-end process network refers to a structure formed in a metallization layer on the main surface of a semiconductor substrate.

[0030] The variable resistor 210 typically includes a resistive switching element / variable resistance dielectric layer sandwiched between a top electrode and a bottom electrode. In some embodiments, for example, the top electrode includes titanium (Ti) and tantalum nitride (TaN), the bottom electrode includes titanium nitride (TiN), and the variable resistance dielectric layer includes nickel oxide (NiO), titanium oxide (TiO), hafnium oxide (HfO), zirconium oxide (ZrO), zinc oxide (ZnO), tungsten oxide (WO3), aluminum oxide (Al2O3), tantalum oxide (TaO), molybdenum oxide (MoO), or copper oxide (CuO). In some embodiments, the bottom electrode may be formed in a lower layer of the metallization layer, and the top electrode may be formed in a higher layer of the metallization layer. Furthermore, a top electrode via (TEVA) may be formed above the top electrode and a bottom electrode via (BEVA) may be formed below the bottom electrode, thereby allowing the variable resistor 210 to be connected to other structures / components, such as access transistor 220, bit line BL, etc.

[0031] Figure 3 Example circuit diagrams of portions of a memory circuit 100 according to some embodiments of the present disclosure are shown. For example, Figure 3 The circuit diagram shows one of the sense amplifiers (hereinafter referred to as "Sense Amplifier 310") of the I / O circuit 130, which is coupled to one of the data cells (hereinafter referred to as "Data Cell 320") and one of the reference cells (hereinafter referred to as "Reference Cell 322") in the memory array 110.

[0032] Each of the data unit 320 and the reference unit 322 can be connected to the memory unit 200. Figure 2 Similarly, it can be constructed, for example, with a 1T1R configuration. However, similar to data unit 115, data unit 320 can be programmed using HRS (e.g., logic 0) or LRS (e.g., logic 1), while similar to reference unit 117, reference unit 322 is configured to be programmed using a constant resistance state between HRS and LRS. In other words, when programmed using HRS, data unit 320 can conduct a relatively low current, when programmed using LRS, it can conduct a relatively high current, and reference unit 322 can conduct a constant current between a relatively high current and a relatively low current.

[0033] As shown, the sensing amplifier 310 is coupled to the data unit 320 and the reference unit 322 via the data bit line DBL 330 and the reference bit line RBL 332, respectively. The sensing amplifier 310 is also coupled to the data bit line DBL 330 and the reference bit line RBL 332 via a first switch 340 and a second switch 342, respectively. Furthermore, in some embodiments, the data bit line DBL 330 is selectively coupled to a first input node "Qi" of the sensing amplifier 310 via the first switch 340, and the reference bit line RBL 332 is selectively coupled to a second input node "QBi" of the sensing amplifier 310 via the second switch 342. When the first switch 340 is activated, the input node Qi is connected to the data bit line DBL 330; when the first switch 340 is deactivated, the input node Qi is disconnected from the data bit line DBL 330. Similarly, when the second switch 342 is activated, the input node QBi is connected to the reference bit line RBL 332; when the second switch 342 is deactivated, the input node QBi is disconnected from the reference bit line RBL 332. As will be discussed below, both the first switch 340 and the second switch 342 can be activated / deactivated by a common switch enable (SWEN) signal, which transitions from a first logic state to a second logic state based on the signal (QB signal) present on the reference bit line RBL 332.

[0034] As disclosed herein, the sense amplifier 310 may include transistors M1, M2, M3, M4, M5, M6, M7, and M8. Transistors M1 through M4 may be implemented as p-type metal-oxide-semiconductor (MOS) transistors, and transistors M5 through M8 may be implemented as n-type MOS transistors. It should be understood that transistors M1 through M8 may be implemented as any of a variety of other types of transistors, while still remaining within the scope of this disclosure. In some embodiments, when transistors M3 through M6 are activated (or turned on), transistors M1, M2, M7, and M8 may "conditionally" form a pair of cross-coupled inverters. Transistors M3 through M6 may sometimes be referred to as input transistors, wherein transistors M3 and M5 form a first pair of input transistors, and transistors M4 and M6 form a second pair of input transistors.

[0035] When transistors M3 through M6 are activated, each transistor can form a conductive path between its two source / drain terminals. For example, when transistor M3 is activated, its first and second source / drain terminals forming a short circuit (or a first conductive path) are both connected to the input node Qi; when transistor M3 is deactivated, the first and second source / drain terminals are disconnected from each other, wherein the first source / drain terminal is connected to transistor M1 and the second source / drain terminal is connected to the input node Qi. When transistor M4 is activated, its first and second source / drain terminals forming a short circuit (or a second conductive path) are both connected to the input node QBi; when transistor M4 is deactivated, the first and second source / drain terminals are disconnected from each other, wherein the first source / drain terminal is connected to transistor M2 and the second source / drain terminal is connected to the input node QBi. When transistor M5 is activated, both the first and second source / drain terminals forming a short circuit (or a third conductive path) are connected to the input node Qi; when transistor M5 is deactivated, the first and second source / drain terminals are disconnected from each other, wherein the second source / drain terminal is connected to transistor M7 and the first source / drain terminal is connected to the input node Qi. When transistor M6 is activated, both the first and second source / drain terminals forming a short circuit (or a fourth conductive path) are connected to the input node QBi; when transistor M6 is deactivated, the first and second source / drain terminals are disconnected from each other, wherein the second source / drain terminal is connected to transistor M8 and the first source / drain terminal is connected to the input node QBi.

[0036] The first source / drain terminal of transistor M1 is connected to VDD, and the second source / drain terminal of transistor M1 can be connected to the input node Qi through a first conductive path formed by the activated transistor M3; the first source / drain terminal of transistor M2 is connected to VDD, and the second source / drain terminal of transistor M2 can be connected to the input node QBi through a second conductive path formed by the activated transistor M4; the first source / drain terminal of transistor M7 is connected to VSS, and the second source / drain terminal of transistor M7 can be connected to the input node Qi through a third conductive path formed by the activated transistor M5; and the first source / drain terminal of transistor M8 is connected to VSS, and the second source / drain terminal of transistor M8 can be coupled to the input node QBi through a fourth conductive path formed by the activated transistor M6. Furthermore, the gate terminals of transistors M1 and M7 are connected to each other and further coupled to the input node QBi, and the gate terminals of transistors M2 and M8 are connected to each other and further coupled to the input node Qi. Therefore, the first inverter formed by transistors M1 and M7 and the second inverter formed by transistors M2 and M8 can be cross-coupled to each other. The first inverter can have an input at input node QBi and an output at input node Qi; and the second inverter can have an input at input node Qi and an output at input node QBi.

[0037] In some embodiments, transistors M3 and M4 can be turned on / off by a first enable (ENB) signal, for example, their gate terminals are configured to receive an ENB signal; and transistors M5 and M6 can be turned on / off by a second enable (EN) signal, for example, their gate terminals are configured to receive an EN signal. The EN and ENB signals are logically opposite to each other; therefore, a pair of transistors M3 and M4 and a pair of transistors M5 and M6 can be alternately turned on. As will be discussed below, the EN / ENB signals can transition from a first logic state to a second logic state based on the signal (QB signal) present on the reference bit line RBL 332.

[0038] like Figure 3 As shown, the memory circuit 100 also includes transistors M9, M10, and M11 operably used as a precharge circuit. Transistors M9 through M11 can each be implemented as p-type MOS transistors, with their gate terminals configured to receive a precharge (PCB) signal. When activated by the PCB signal (e.g., during the precharge phase), transistor M11 can function as an equalizer, and transistors M9 and M10 can precharge the signal (Q signal) present on data bit line DBL 330 and the signal (QB signal) present on reference bit line RBL 332 to VDD (or logic 1), respectively. As will be discussed below, this precharge phase of the memory circuit 100 can occur before the evaluation phase of the memory circuit 100.

[0039] Figure 4 A memory circuit 100 for operating according to some embodiments of the present disclosure is shown. Figure 1 ) or sensing amplifier 310 ( Figure 3 Examples of time-varying waveforms of the aforementioned signals are shown. For instance, waveforms of the PCB signal, SWEN signal, Q signal, QB signal, QB_DET signal, EN signal, signal present at input node Qi (hereinafter referred to as "Qi signal"), and signal present at input node QBi (hereinafter referred to as "QBi signal") are shown. Typically, Figure 4 The waveforms shown include three different operating phases of the memory circuit 100, such as the precharge (PCH) phase, the evaluation (EVA) phase, and the latch (LAT) phase.

[0040] During the PCH phase, the PCB signal, SWEN signal, and EN signal are provided at logic 0, logic 1, and logic 0, respectively. Therefore, transistors M9 to M11 (in the pre-charge circuit) can be turned on, pre-charging (or charging) the Q and QB signals to VDD (or logic 1). In some embodiments, the QB_DET signal can remain at logic 0 as long as the QB signal drops to a certain voltage level. Furthermore, since the EN signal is logic 0 (ENB signal is logic 1), transistors M3 to M6 are all turned off; and the SWCN signal is at logic 1, activating switches 320 and 342. Therefore, without a conductive path formed between the source / drain terminals of any of transistors M3 to M6, input nodes Qi and QBi can be coupled to the data bit line DBL 330 and the reference bit line RBL 332, respectively, while being isolated.

[0041] During the EVA stage, the PCB signal, SWEN signal, and EN signal are provided at logic 1, logic 1, and logic 0, respectively. Therefore, transistors M9 to M11 (of the pre-charge circuit) can be turned off, causing data bit line DBL 330 and reference bit line RBL 332 to decouple from VDD. Since the EN signal is logic 0 (ENB signal is logic 1), transistors M3 to M6 are all turned off; and the SWEN signal is at logic 1, activating switches 320 and 342. Therefore, input nodes Qi and QBi can be coupled to data bit line DBL 330 and reference bit line RBL 332, respectively. In other words, the signals present on input node Qi and data bit line DBL 330 are identical, and the signals on input node QBi and reference bit line RBL 332 are also identical. In some embodiments, assuming no conductive path is formed between the source / drain terminals of any of transistors M3 to M6, input nodes Qi and QBi can be referred to as isolated. This can advantageously decouple parasitic coupling problems from one or more of transistors M1, M2, M7, and M8. Since both the data bit line DBL 330 and the reference bit line RBL 332 are decoupled from VDD, the Q signal (equal to the Qi signal) and the QB signal (equal to the QBi signal) can drop from VDD (or logic 1), with their respective discharge rates based on the current through the data cell 320 and the reference cell 322.

[0042] During the LAT phase, the PCB signal, SWEN signal, and EN signal are provided at logic 1, logic 0, and logic 1, respectively. Therefore, transistors M9 through M11 (of the pre-charge circuit) can be turned off, causing data bit line DBL 330 and reference bit line RBL 332 to decouple from VDD. Since the EN signal is at logic 1 (ENB signal is at logic 0), in some embodiments, transistors M3 through M6 can be turned on, causing each of transistors M3 through M6 to form a conductive path. Therefore, transistors M1, M2, M7, and M8 can operatively form a pair of cross-coupled inverters. Since the SWEN signal is at logic 0, switches 340 and 342 are deactivated, causing input nodes Qi and QBi to decouple from data bit line DBL 330 and reference bit line RBL 332, respectively. Therefore, the cross-coupled inverters can latch and amplify the difference between the Qi and QBi signals (evaluated during the EVA phase). In some embodiments, when the QB signal drops to a sufficiently low voltage level, such as VDD / 2 (as indicated by symbol arrow 401), the QB_DET signal can be switched from logic 0 to logic 1; when the QB_DET signal switches to logic 1, the SWEN signal can switch to logic 1, and the EN signal can switch to logic 1 (as indicated by symbols arrows 403 and 405, respectively).

[0043] Figure 5 , Figure 6 and Figure 7 Example circuit diagrams of a first switch 340 and a second switch 342 according to some embodiments of the present disclosure are shown respectively. It should be understood that... Figures 5-7 The circuit diagrams are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0044] exist Figure 5 In this configuration, each of the first switch 340 and the second switch 342 can be implemented as a transmission gate 510. For example, the transmission gate 510 includes a p-type transistor 520 and an n-type transistor 530, whose first source / drain terminals are connected to each other, and whose second source / drain terminals are connected to each other. The first source / drain terminals can be connected to a data bit line DBL 330 (or a reference bit line RBL 332), and the second source / drain terminals can be connected to an input node Qi (or an input node QBi). The gate terminals of the n-type transistor 530 and the p-type transistor 520 are configured to receive the SWEN signal and a logically inverted version of the SWEN signal (SWENB signal), respectively.

[0045] exist Figure 6 In this configuration, each of the first switch 340 and the second switch 342 can be implemented as a p-type transistor 610. The first source / drain terminal of transistor 610 can be connected to the data bit line DBL 330 (or the reference bit line RBL 332), and the second source / drain terminal of transistor 610 can be connected to the input node Qi (or the input node QBi). The gate terminal of transistor 610 is configured to receive a logically inverted version of the SWEN signal (SWENB signal).

[0046] exist Figure 7 In this configuration, each of the first switch 340 and the second switch 342 can be implemented as an n-type transistor 710. The first source / drain terminal of transistor 710 can be connected to data bit line DBL 330 (or reference bit line RBL 332), and the second source / drain terminal of transistor 710 can be connected to input node Qi (or input node QBi). The gate terminal of transistor 710 is configured to receive the SWEN signal.

[0047] Figure 8 Another example circuit diagram of a portion of a memory circuit 100 according to some embodiments of the present disclosure is shown. For example, Figure 8 The circuit diagram and Figure 3 The circuit diagrams are basically similar, except... Figure 8 The circuit diagram includes a first trimming circuit 810 and a second trimming circuit 820. Therefore, the following discussion will focus on the differences and will again use Figure 3 Reference figures.

[0048] As shown, trimming circuit 810 is coupled between data bit line DBL 330 and data cell 320, and trimming circuit 820 is coupled between reference bit line RBL 332 and reference cell 330. Trimming circuit 810 can adjust the level of a signal present on data bit line DBL 330 by activating one or more of its transistors, and trimming circuit 820 can adjust the level of a signal present on reference bit line RBL 332 by activating one or more transistors. For example, trimming circuit 810 may include transistor M12 and one or more transistors M13, each of which is coupled to a corresponding switch 812; and trimming circuit 820 may include transistor M14 and one or more transistors M15, each of which is coupled to a corresponding switch 822. The gate terminals of all transistors in trimming circuits 810 and 820 can be connected to a common signal. However, one or more transistors M13 can each selectively provide current flowing through data bit line DBL 330, and one or more transistors M15 can each selectively generate current flowing through reference bit line RBL 332.

[0049] Figure 9 and Figure 10 Further example circuit diagrams 910 and 1010 of the sense amplifiers (hereinafter referred to as "Sense Amplifier 910" and "Sense Amplifier 1010") of the I / O circuit 130 according to some embodiments of the present disclosure are shown respectively. Except that sense amplifier 910 has only p-type input transistors and sense amplifier 1010 has only n-type input transistors, each of sense amplifiers 910-1010 is connected to... Figure 3 The sensing amplifier 310 shown is essentially similar. Therefore, the following discussion will focus on the differences, and will again use... Figure 3 Some reference figures.

[0050] exist Figure 9 In this configuration, the sense amplifier 910 also includes transistors M1-M2 and M7-M8 operably used as a pair of cross-coupled inverters, but includes only p-type input transistors M3-M4. Therefore, while selectively coupled to the data bit line DBL 330 via switch 340, input node Qi is connected to the second source / drain terminal of transistor M3 and directly to the first source / drain terminal of transistor M7; and while selectively coupled to the reference bit line RBL 332 via switch 342, input node QBi is connected to the second source / drain terminal of transistor M4 and directly to the first source / drain terminal of transistor M8.

[0051] exist Figure 10 In this circuit, the sense amplifier 1010 also includes transistors M1-M2 and M7-M8 operably used as a pair of cross-coupled inverters, but includes only n-type input transistors M5-M6. Therefore, while maintaining selective coupling to the data bit line DBL 330 via switch 340, input node Qi is directly connected to the second source / drain terminal of transistor M1 and to the first source / drain terminal of transistor M5; input node QBi is directly connected to the second source / drain terminal of transistor M2 and to the first source / drain terminal of transistor M6.

[0052] Figure 11 A flowchart of an example method 1100 for operating a memory circuit according to some embodiments of the present disclosure is shown. For example, at least some operations (or steps) of method 1100 can be used to read data generated by the memory circuit 100 (…). Figure 1 The data bits are stored in data unit 115. The data bits can be read (or determined) by any of the disclosed sense amplifiers (e.g., sense amplifier 310). It should be noted that method 1100 is merely an example and is not intended to limit the scope of this disclosure. Therefore, it should be understood that... Figure 11 Additional operations are provided before, during, and / or after Method 1100, and this document may only briefly describe some of these other operations.

[0053] Method 1100 begins with operation 1110, pre-charging the data bit line and reference bit line to a first logic state, wherein the data bit line and reference bit line are coupled to a first input node and a second input node of a sense amplifier, respectively. In some embodiments, the data bit line is coupled to a data cell, while the reference line is coupled to a reference bit cell. Using memory circuitry 100 (and...) Figure 3 As one of the embodiments shown is a non-limiting example, before comparing the various signals (Q and QB signals) present on the data bit line DBL 330 and the reference bit line RBL 332, both the data bit line DBL 330 and the reference bit line RBL 332 are precharged to VDD (e.g., logic 1) by a precharge circuit operably formed by transistors M9 to M11. During this precharge phase, switches 340 and 342 are activated simultaneously, so that the data bit line DBL 330 and the reference bit line RBL 332 can be simultaneously coupled to the input nodes Qi and QBi of the sense amplifier 310, respectively.

[0054] Method 1100 continues to operation 1120, discharging the data line and reference line, wherein the first input node and the second input node remain coupled to the data line and reference line, respectively, and both the first input node and the second input node are decoupled from any transistor. Continuing the example above, after the data bit line DBL 330 and the reference bit line RBL 332 are precharged to VDD, transistors M9 to M11 (in the precharge circuit) are turned off, transistors M3 to M6 of the sense amplifier 310 are turned off, and switches 340-342 remain active. Therefore, the input nodes Qi and Qbi of the sense amplifier 310 are isolated from transistors M1-M2 and M7-M8, but remain coupled to the data cell 320 and the reference cell 322, respectively, through the data bit line DBL 330 and the reference bit line RBL 332. When switches 340 and 342 remain active, the Q signal is equal to the Qi signal, and the QB signal is equal to the QBi signal.

[0055] The Q signal can correspond to the logic state of a first data bit stored in data unit 320, and the QB signal can correspond to the logic state of a second data bit stored in reference unit 322. In various embodiments, the first data bit is configured to be programmed with a first logic state (e.g., HRS) or a second logic state (e.g., LRS), while the second data bit is configured to be continuously programmed with a resistance state (e.g., (HRS+LRS) / 2) between the first and second logic states. Therefore, the Q signal and the QB signal can present corresponding voltage levels that decrease from VDD by different amounts. The voltage amounts can correspond to different resistance states stored in data unit 320 and reference unit 322, respectively. For example, when the first data bit is programmed using HRS and the second data bit is set to (HRS+LRS) / 2, the Q signal can decrease from VDD at a slower discharge rate compared to the discharge rate of the QB signal. In another example, when the first data bit is programmed using LRS and the second data bit is set to (HRS+LRS) / 2, the Q signal can decrease from VDD at a faster discharge rate compared to the discharge rate of the QB signal.

[0056] Method 1100 continues to operation 1130, latching the data bits stored by the data unit, wherein the first input node and the second input node are decoupled from the data line and the reference line, respectively. Continuing the example above, after the QB signal (present on the reference bit line RBL332) drops to a sufficient voltage level (e.g., VDD / 2), transistors M3 to M6 can be turned on by the EN signal, which is further triggered by the QB_DET signal. In some embodiments, the QB_DET signal can transition from logic 0 to logic 1 when the QB signal drops to approximately VDD / 2. Simultaneously with the transition of the QB_DET signal to logic 1, switches 340 and 342 can be deactivated, for example, by the SWEN signal. As a result, the input nodes Qi and QBi of the sense amplifier 310 are decoupled from the data bit line DBL330 and the reference bit line RBL332, respectively, and transistors M1-M2 and M7-M8, operably acting as a pair of cross-coupled inverters, can latch and amplify the Q signal.

[0057] In one aspect of this disclosure, a memory circuit is disclosed. The memory circuit includes: a first memory cell configured to store a first data bit; a second memory cell configured to store a second data bit; a sense amplifier coupled to the first memory cell and the second memory cell via a data bit line and a reference bit line, respectively; a first switch; and a second switch; wherein the first switch is selectively coupled between the data bit line and a first input node of the sense amplifier, and the second switch is selectively coupled between the reference bit line and a second input node of the sense amplifier.

[0058] In some embodiments, the first data bit presents a logic high state or a logic low state, and the second data bit is associated with a constant logic state between the logic high state and the logic low state.

[0059] In some embodiments, the first switch and the second switch each include a transmission gate, a p-type transistor, or an n-type transistor.

[0060] In some embodiments, the sense amplifier further includes: a first p-type transistor; a second p-type transistor; a third p-type transistor; a fourth p-type transistor; a fifth n-type transistor; a sixth n-type transistor; a seventh n-type transistor; and an eighth n-type transistor.

[0061] In some embodiments, the first transistor, the third transistor, the fifth transistor, and the seventh transistor are connected in series between the power supply voltage and the ground voltage, and the second transistor, the fourth transistor, the sixth transistor, and the eighth transistor are connected in series between the power supply voltage and the ground voltage.

[0062] In some embodiments, the gate terminals of the first transistor and the seventh transistor are connected to the second input node, and the gate terminals of the second transistor and the eighth transistor are connected to the first input node.

[0063] In some embodiments, the gate terminals of the third transistor and the fourth transistor are configured to jointly receive the first control signal, and the gate terminals of the fifth transistor and the sixth transistor are configured to jointly receive a second control signal that is logically opposite to the first control signal.

[0064] In some embodiments, the first source / drain terminals of the third transistor and the first source / drain terminals of the fifth transistor are connected to each other at the first input node, and the first drain / source terminals of the fourth transistor and the first drain / source terminals of the sixth transistor are connected to each other at the second input node.

[0065] In some embodiments, during the evaluation phase of the sense amplifier, the third to sixth transistors are turned off, and the first, second, seventh, and eighth transistors are turned on, wherein the first and second switches are activated to couple the data bit line to the first input node and the reference bit line to the second input node.

[0066] In some embodiments, during the latching phase of the sense amplifier, the first to eighth transistors are turned on, and the first and second switches are deactivated, thereby decoupling the first input node from the data bit line and the second input node from the reference bit line.

[0067] In some embodiments, the first memory unit and the second memory unit each include a non-volatile memory unit.

[0068] In another aspect of this disclosure, a memory circuit is disclosed. The memory circuit includes: a sense amplifier configured to identify a data bit stored in the first memory cell by comparing a first signal present on a data bit line connecting a first memory cell to the sense amplifier and a second signal present on a reference bit line connecting a second memory cell to the sense amplifier; a first switch configured to selectively couple the data bit line to a first input node of the sense amplifier based on an enable signal; and a second switch configured to selectively couple the reference bit line to a second input node of the sense amplifier based on an enable signal.

[0069] In some embodiments, the first memory unit and the second memory unit each include a non-volatile memory unit.

[0070] In some embodiments, the first signal corresponds to a logic high state or a logic low state, while the second signal corresponds to a logic state between the logic high state and the logic low state.

[0071] In some embodiments, the sense amplifier further includes: a first p-type transistor; a second p-type transistor; a third p-type transistor; a fourth p-type transistor; a fifth n-type transistor; a sixth n-type transistor; a seventh n-type transistor; and an eighth n-type transistor.

[0072] In some embodiments, the first transistor, the third transistor, the fifth transistor, and the seventh transistor are connected in series between the power supply voltage and the ground voltage, and the second transistor, the fourth transistor, the sixth transistor, and the eighth transistor are connected in series between the power supply voltage and the ground voltage.

[0073] In some embodiments, during the evaluation phase of the sense amplifier, the third to sixth transistors are turned off, and the first, second, seventh, and eighth transistors are turned on, wherein the first and second switches are activated to couple the data bit line to the first input node and the reference bit line to the second input node.

[0074] In another aspect of this disclosure, a method for operating a memory circuit is disclosed. The method includes: pre-charging a data bit line and a reference bit line to a first logic state, wherein the data bit line and the reference bit line are respectively connected to a first input node and a second input node of a sense amplifier, wherein the data bit line is coupled to a data cell, and the reference bit line is coupled to a reference cell; discharging the data bit line and the reference bit line, wherein the first input node and the second input node remain coupled to the data bit line and the reference bit line, respectively, and both the first input node and the second input node are decoupled from any transistor; and latching a data bit stored in a data cell, wherein the first input node and the second input node are decoupled from the data bit line and the reference bit line, respectively.

[0075] In some embodiments, the data unit and the reference unit each include a non-volatile memory unit.

[0076] In some embodiments, the method further includes: simultaneously activating a first switch to couple a first input node to a data bit line and activating a second switch to couple a second input node to a reference bit line; or simultaneously deactivating the first switch to decouple the first input node from the data bit line and deactivating the second switch to decouple the second input node from the reference bit line.

[0077] As used herein, the terms "about" and "approximately" generally refer to the value of a given quantity that can vary depending on the specific technology node associated with the subject semiconductor device. Based on a specific technology node, the term "about" can refer to a given quantity of value, for example, varying within a range of 10-30% of the value (e.g., +10%, ±20%, or ±30% of the value).

[0078] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to them within this disclosure without departing from its spirit and scope.

Claims

1. A memory circuit, comprising: a first memory cell configured to store a first data bit; a second memory cell configured to store a second data bit; a sense amplifier coupled to the first memory cell and the second memory cell by a data bit line and a reference bit line, respectively; a first switch; and a second switch; wherein the first switch is selectively coupled between the data bit line and a first input node of the sense amplifier, and the second switch is selectively coupled between the reference bit line and a second input node of the sense amplifier. the first data bit assumes a logical high state or a logical low state, and the second data bit is associated with a constant logical state between the logical high state and the logical low state.

2. The memory circuit of claim 1, wherein, the sense amplifier further comprises:

3. The memory circuit of claim 1, wherein, a first transistor of a p-type; a second transistor of a p-type; a third transistor of a p-type; a fourth transistor of a p-type; a fifth transistor of an n-type; a sixth transistor of an n-type; a seventh transistor of an n-type; and an eighth transistor of an n-type. the first transistor, the third transistor, the fifth transistor, and the seventh transistor are connected in series between a supply voltage and a ground voltage, and the second transistor, the fourth transistor, the sixth transistor, and the eighth transistor are connected in series between the supply voltage and the ground voltage.

4. The memory circuit of claim 3, wherein, a gate terminal of the third transistor and a gate terminal of the fourth transistor are configured to collectively receive a first control signal, and a gate terminal of the fifth transistor and a gate terminal of the sixth transistor are configured to collectively receive a second control signal that is logically opposite the first control signal.

5. The memory circuit of claim 4, wherein, during an evaluation phase of the sense amplifier, the third transistor through the sixth transistor are turned off, and the first transistor, the second transistor, the seventh transistor, and the eighth transistor are turned on, wherein the first switch and the second switch are activated, thereby coupling the data bit line to the first input node and coupling the reference bit line to the second input node.

6. The memory circuit of claim 4, wherein, during a latch phase of the sense amplifier, the first transistor through the eighth transistor are turned on, and the first switch and the second switch are deactivated, thereby decoupling the first input node from the data bit line and decoupling the second input node from the reference bit line.

7. The memory circuit of claim 4, wherein, 8. A memory circuit, comprising: a sense amplifier configured to identify a data bit stored by a first memory cell based on comparing a first signal present on a data bit line connecting the first memory cell to the sense amplifier and a second signal present on a reference bit line connecting a second memory cell to the sense amplifier; a first switch configured to selectively couple the data bit line to a first input node of the sense amplifier based on an enable signal; and a second switch configured to selectively couple the reference bit line to a second input node of the sense amplifier based on the enable signal.

9. A method for operating a memory circuit, comprising: ​ ​ precharging a data bit line and a reference bit line to a first logic state, wherein the data bit line and the reference bit line are coupled to first and second input nodes of a sense amplifier, respectively, wherein the data bit line is coupled to a data cell and the reference bit line is coupled to a reference cell; discharging the data bit line and the reference bit line, wherein the first and second input nodes remain coupled to the data bit line and the reference bit line, respectively, and the first and second input nodes are both decoupled from any transistor; and latching a data bit stored by the data cell, wherein the first and second input nodes are decoupled from the data bit line and the reference bit line, respectively.

10. The method of claim 9, further comprising: simultaneously activating a first switch to couple the first input node to the data bit line and activating a second switch to couple the second input node to the reference bit line; or simultaneously deactivating the first switch to decouple the first input node from the data bit line and deactivating the second switch to decouple the second input node from the reference bit line.

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