Memory performing target refresh operation and operating method of memory

Abstract

A memory may include: a cell array including memory cells arranged in a plurality of rows and a plurality of columns; and a refresh target selection circuit configured to select a target row for a target refresh operation based on a number of activation operations for each row in the cell array and an error history for each row.

Description

Cross-references to related applications

[0001] This application claims priority to Korean Application No. 10-2024-0115357, filed on August 27, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Various embodiments of this disclosure relate to memory. Background Technology

[0003] Volatile memories such as DRAM require periodic refresh operations (i.e., normal refresh operations) to retain the data stored therein. In addition to normal refresh operations, additional refresh operations are performed on memory cells in specific rows or word lines that may lose data due to row hammering; these additional refresh operations will be referred to below as "target refresh operations." Row hammering refers to the phenomenon where a large number of activations (i.e., activation operations) in a specific row leads to the corruption of data in memory cells coupled to or adjacent to that specific row.

[0004] To prevent row hammering, the number of activation operations for each row is counted, and a target refresh operation is performed on rows that have been activated more than a predetermined number of times, as well as adjacent rows set next to those rows. Summary of the Invention

[0005] According to one embodiment of the present disclosure, a memory may include: a cell array including memory cells arranged in a plurality of rows and a plurality of columns; and a refresh target selection circuit configured to select a target row for a target refresh operation based on the number of activation operations in each row of the cell array and the error history of each row.

[0006] According to one embodiment of this disclosure, a memory may include: a normal cell region comprising normal storage cells arranged in a plurality of rows and a plurality of columns; an access counting cell region comprising access counting storage cells arranged in the same number of rows as the normal cell region and in a different number of columns than the normal cell region, and configured to store the error history of each row and the number of activation operations for each row; and a refresh target selection circuit configured to select a target row for a target refresh operation based on the error history of each row stored in the access counting cell region and the number of activation operations for each row.

[0007] According to one embodiment of this disclosure, a method for performing an error checking operation of a memory may include: activating a first row in a cell array; reading data from selected memory cells in the first row; detecting errors in the data to correct the detected errors; writing the error-corrected data to selected memory cells in the first row; writing the error detection history to predetermined memory cells in the first row; and pre-charging the first row.

[0008] According to one embodiment of the present disclosure, a method of operating a memory may include: selecting a target row for a target refresh operation based on the number of activation operations for each row in a cell array and the error history of each row; receiving a refresh management command; and refreshing the refresh target row in response to the refresh management command. Attached Figure Description

[0009] Figure 1 This is a block diagram illustrating a storage system according to one embodiment of the present disclosure.

[0010] Figure 2 This illustrates one embodiment according to the present disclosure. Figure 1 The block diagram of the memory is shown.

[0011] Figure 3 This is a view illustrating a row scoring process by refreshing the target selection circuit according to one embodiment of the present disclosure.

[0012] Figure 4 This is a flowchart illustrating an error checking operation according to one embodiment of the present disclosure. Detailed Implementation

[0013] Various embodiments of this disclosure relate to techniques for reducing errors in memory.

[0014] According to embodiments of this disclosure, errors in the memory can be reduced and the reliability of the memory can be improved.

[0015] Various embodiments based on the technical spirit of this disclosure are described below with reference to the accompanying drawings.

[0016] Figure 1 This is a block diagram illustrating a storage system 100 according to one embodiment of the present disclosure.

[0017] The storage system 100 may include a memory 120 and a memory controller 110.

[0018] The memory controller 110 can control the operation of the memory 120 according to a request from the host. The host may include a central processing unit (CPU), a graphics processing unit (GPU), and an application processor (AP). The memory controller 110 may include a host interface 111, a control block 113, a command generator 115, and a memory interface 117. The memory controller 110 may be included in the CPU, GPU, and AP. In this case, the host may represent a configuration other than the memory controller 110. For example, when the memory controller 110 is included in the CPU, the host shown in the figure may represent a component excluding the memory controller 110 from the CPU.

[0019] The host interface 111 can be an interface used for communication between the host and the memory controller 110.

[0020] Control block 113 can control the overall operation of memory controller 110 and schedule operations to be instructed on memory 120. Control block 113 can change the order in which requests are received from the host and the order in which operations to be instructed on memory 120 to improve the performance of memory 120. For example, even if the host requests a read operation from memory 120 first and a write operation later, the order can be adjusted so that the write operation is performed before the read operation.

[0021] Command generator 115 can generate commands to be applied to memory 120 according to the operation sequence determined by control block 113.

[0022] Memory interface 117 can be used as an interface between memory controller 110 and memory 120. Commands and addresses (CA) can be transferred from memory controller 110 to memory 120 through memory interface 117, and data (DATA) can be transferred / received through memory interface 117. Memory interface 117 can also be referred to as the PHY interface.

[0023] The memory 120 can perform operations instructed by the memory controller 110. See below for reference. Figure 2 Detailed description of memory 120.

[0024] Figure 2 This illustrates one embodiment according to the present disclosure. Figure 1 The block diagram of memory 120 is shown.

[0025] refer to Figure 2The memory 120 may include a command address receiving circuit 201, a data transmission / receiving circuit 203, a command decoder 210, a row control circuit 221, a column control circuit 223, an address control circuit 225, an address counter 227, a refresh target selection circuit 230, an error checking operation control circuit 241, an error recording circuit 243, a cell array 250, a row circuit 261, a normal column circuit 263, an access counting column circuit 265, an error correction circuit 271, an error correction code generation circuit 273, and an access information generation circuit 280.

[0026] The command address receiving circuit 201 can receive commands and addresses CA. According to the standard of memory 120, commands and addresses CA can be input to the same input terminal, or commands and addresses CA can be input to separate input terminals. In one embodiment, an example of inputting commands and addresses CA to the same input terminal is described. Commands and addresses CA can have multiple bits.

[0027] The data transmission / receiving circuit 203 can receive or transmit data DATA. During a write operation, the data transmission / receiving circuit 203 can receive data DATA to be written to the cell array 250, and during a read operation, it can transmit data DATA read from the cell array 250.

[0028] Command decoder 210 can decode commands and addresses CA to determine the type of operation of memory 120 as instructed by memory controller 110.

[0029] When row operations such as activation, precharge, and refresh are indicated as decoding results from command decoder 210, row control circuit 221 can control these operations. The activation signal ACT indicates an activation operation, the precharge signal PCG indicates a precharge operation, and the refresh signal REF indicates a refresh operation. Additionally, the refresh management signal RFM can indicate a refresh management operation. The refresh management operation can be used to refresh the target row selected by refresh target selection circuit 230 to prevent data loss due to row hammering attacks. This operation is also referred to as a target refresh operation or a smart refresh operation.

[0030] When column-based operations such as write and read operations are indicated by the decoding result of command decoder 210, column control circuit 223 can control these operations. The write signal WR indicates a write operation, while the read signal RD indicates a read operation.

[0031] Address control circuit 225 can classify the address received from command decoder 210 into row address R_ADD and column address C_ADD, and transmit row address R_ADD and column address C_ADD to row circuit 261 and normal column circuit 263, respectively. Address control circuit 225 can classify the received address into row address R_ADD when indicating an activation operation based on the decoding result of command decoder 210, and can classify the received address into column address C_ADD when indicating read operation and write operation based on the decoding result of command decoder 210.

[0032] Address counter 227 generates the refresh address REF_R_ADD to be used during a refresh operation. Each time the refresh signal REF is activated, address counter 227 increments the refresh address REF_R_ADD by 1. Because the refresh address REF_R_ADD changes every time the refresh signal REF is activated, all rows in the cell array 250 can be refreshed sequentially.

[0033] Cell array 250 may include storage cells arranged in multiple rows and multiple columns. Cell array 250 may include a normal cell area 251 and an access counting cell area 253. Normal cell area 251 is an area for storing write data and providing the stored data as read data. Access counting cell area 253 is an area for storing the number of activation operations for each row and the error history for each row. Normal cell area 251 and access counting cell area 253 may share rows.

[0034] Row circuit 261 can control rows in unit array 250. When the activation signal ACT is activated, row circuit 261 can activate the row in unit array 250 selected by row address R_ADD. During error checking operation, when the activation signal ACT is activated, row circuit 261 can activate the row in unit array 250 selected by error checking row address R_ADD_E. When the precharge signal PCG is activated, row circuit 261 can precharge the activated row. When the refresh signal REF is activated, row circuit 261 can refresh the row in unit array 250 selected by refresh address REF_R_ADD. Furthermore, when the refresh management signal RFM is activated, row circuit 261 can refresh the row in unit array 250 corresponding to the target row address T_R_ADD.

[0035] During a write operation, the normal column circuit 263 can write data DATA′ and error correction code ECC to the column selected by column address C_ADD in the normal cell area 251, that is, to the memory cell corresponding to the active row and the selected column. Furthermore, during a read operation, the normal column circuit 263 can read data DATA′ and error correction code ECC from the column selected by column address C_ADD in the normal cell area 251. During an error checking operation, the normal column circuit 263 can use the error checking column address C_ADD_E instead of column address C_ADD.

[0036] During the precharge operation, the access counting column circuit 265 can read access data A_DATA from the column in the access counting cell region 253 (i.e., from the column in the access counting cell region 253 coupled to the active row) and transmit the access data A_DATA to the access information generation circuit 280. Furthermore, when the access information generation circuit 280 updates the access data A_DATA, the access counting column circuit 265 again writes the updated data to the column in the access counting cell region 253, that is, writes it to the memory cell of the access counting cell region 253 coupled to the active row. Because all columns are accessed when the access counting cell region 253 is accessed, the access counting column circuit 265 does not need to use the column address C_ADD.

[0037] The access information generation circuit 280 can update the access data A_DATA transmitted from the access counting column circuit 265. Access data A_DATA includes the number of activation operations for each row and the error history for each row. For example, when access data A_DATA has 10 bits, 9 bits can be used to record the number of activation operations, and 1 bit can be used to record the error history. Whenever a precharge operation is performed, the access information generation circuit 280 can increment the number of activation operations in access data A_DATA by +1. Furthermore, when an error is found in the corresponding row during an error checking operation, the access information generation circuit 280 can record the error history information of access data A_DATA as "1". When the error history information is "0", it indicates that no error was found in the corresponding row, while when the error history information is "1", it indicates that an error was found in the corresponding row.

[0038] Error correction code generation circuit 273 can generate error correction code (ECC) using data DATA during a write operation. During a write operation, error correction code (ECC) can be generated using data DATA, but errors in the data DATA may not be corrected. Therefore, the data DATA input to error correction code generation circuit 273 can be the same as the data DATA output from error correction code generation circuit 273.

[0039] Error correction circuit 271 can use the error correction code ECC read by normal column circuit 263 during a read operation to correct errors in data DATA′ read by normal column circuit 263. Error correction can mean detecting and correcting errors in data DATA′ when they are detected. Error correction circuit 271 can also detect and correct errors in data DATA′ together with the error correction code ECC. When an error in data DATA′ is detected and corrected, the data DATA′ input to error correction circuit 271 may be different from the data DATA output from error correction circuit 271. Error signal ERR can be a signal activated when an error is detected by error correction circuit 271.

[0040] Error checking operation control circuit 241 can control the error checking operation of memory 120. When the memory controller 110 instructs the memory to set the error checking operation mode as the decoding result of command decoder 210, memory 120 can operate in the error checking operation mode and can operate under the control of error checking operation control circuit 241 in the error checking operation mode. Error checking operation (also referred to as error checking and flushing (ECS) operation) can be reading data DATA′ and error correction code ECC from normal cell area 251 of cell array 250, checking for errors in data DATA′ using error correction circuit 271, and recording the error history in error recording circuit 243. Error checking operation control circuit 241 can control the error checking operation when the error checking operation mode is set. Because row operations and column operations need to be controlled during error checking operation, error checking operation control circuit 241 can control row control circuit 221 and column control circuit 223 during error checking operation. In addition, error checking operation control circuit 241 can control error recording circuit 243 associated with error checking operation.

[0041] Error checking operation control circuit 241 can generate error checking addresses R_ADD_E and C_ADD_E for error checking operations. Error checking addresses R_ADD_E and C_ADD_E can include the error checking row address R_ADD_E and the error checking column address C_ADD_E. Each time an error checking operation is performed, error checking operation control circuit 241 can increment error checking addresses R_ADD_E and C_ADD_E by one step. When the value of the error checking row address R_ADD_E is in the range from 0 to X and the value of the error checking column address C_ADD_E is in the range from 0 to Y, error checking operation control circuit 241 can generate error checking addresses R_ADD_E and C_ADD_E as (0, 0) during the first error checking and flushing operation. During the second error checking and flushing operation, the error checking operation control circuit 241 can increment the error checking addresses R_ADD_E and C_ADD_E by 1 step, and generate the error checking addresses R_ADD_E and C_ADD_E as (0, 1). Similarly, during the third error checking and flushing operation, the error checking operation control circuit 241 can again increment the error checking addresses R_ADD_E and C_ADD_E by 1 step, and generate the error checking addresses R_ADD_E and C_ADD_E as (0, 2). The error checking addresses R_ADD_E and C_ADD_E can be increased by one step for each error checking and flushing operation, and are generated differently each time, such as (0,0) -> (0,1) -> (0,2) -> ... -> (0,Y-1) -> (0,Y) -> (1,0) -> (1,1) -> ... -> (1,Y-1) -> (1,Y) -> (2,0) -> (2,1) -> ... -> (X,Y-1) -> (X,Y). Because the error checking operation control circuit 241 changes the error checking addresses R_ADD_E and C_ADD_E each time an error checking and flushing operation is performed, error checking operations can be performed on all memory cells in the normal cell region 251 of the cell array 250 when the error checking and flushing operation is repeatedly performed.

[0042] The refresh target selection circuit 230 can select the target row for the target refresh operation using the number of activation operations for each row and the error history of each row. The target row address T_R_ADD is the address of the target row selected by the refresh target selection circuit 230. When the access information generation circuit 280 updates the access data A_DATA, the refresh target selection circuit 230 can receive the access data A_DATA and use the access data A_DATA to select the target row. The refresh target selection circuit 230 can calculate the score of each row by allocating points to rows (N-1) and (N+1) based on the number of activations in row N, by allocating weighted points to row N based on the error history of row N, and by selecting the row with the higher score as the target row. For example, the number of activations in row N can increase the score of rows (N-1) and (N+1) by 1 point each time, and the error history of row N can increase the score of row N by 300 points.

[0043] Figure 3 A refresh target selection circuit 230 according to one embodiment of this disclosure is shown assigning scores to rows 98 through 103. Reference Figure 3 The result of allocating scores to rows 98 through 103 by considering the activation count of neighboring rows and the error history of corresponding rows indicates that the highest score is assigned to row 100. In this case, the refresh target selection circuit 230 can select row 100 as the target row. The higher the activation count of neighboring rows, the higher the probability of errors occurring due to row hammering, and the existence of error history for corresponding rows indicates a high probability of errors occurring in those rows. Therefore, the target row selection operation can be performed in this way. In the example above, a weight of 300 points is described for assigning to the error history, but this is just an example, and obviously the value of the weight can be changed.

[0044] Error recording circuit 243 can record errors found during error checking operations. Upon request from memory controller 110, the error recording history collected in error recording circuit 243 can be transferred from memory 120 to memory controller 110.

[0045] In one embodiment, the error history of each row, along with the activation count of each row, is stored in the access counting unit region 253 of the cell array 250, and the refresh target selection circuit 230 uses the error history and activation count of each row stored in the access counting unit region 253. Alternatively, the error history of each row can be stored in the error recording circuit 243, and the activation count of each row can be stored in the access counting unit region 253, such that the refresh target selection circuit 230 can use the information stored in the error recording circuit 243 and the access counting unit region 253 to select the target row.

[0046] Activation operation The activation operation can be a row activation operation. During the activation operation, row circuit 261 can activate the row selected by row address R_ADD within the cell array 250. Because the normal cell area 251 and access counting cell area 253 of the cell array 250 share rows, the normal cell area 251 and access counting cell area 253 can be activated simultaneously. During the activation operation, the data in the memory cells of the selected row can be detected and amplified.

[0047] Write operation Write operations can be performed during the activation phase. For example, a write operation can be performed on row 10 when row 10 is active. During the write operation, data transmission / reception circuit 203 can receive data DATA, and error correction code generation circuit 273 can use data DATA to generate error correction code ECC. Normal column circuit 263 can write data DATA′ and error correction code ECC into the column selected by column address C_ADD in the normal cell area 251. That is, data DATA′ and error correction code ECC can be written into the storage cells of the row activated by row circuit 261 and the column selected by normal column circuit 263.

[0048] Read operation A read operation can be performed during an activation operation. For example, a read operation can be performed on the third row when it is active. During the read operation, the normal column circuit 263 can read data DATA′ and error correction code ECC from the column selected by column address C_ADD in the normal cell area 251. That is, data DATA′ and error correction code ECC can be read from the storage cells of the row activated by the row circuit 261 and the column selected by the normal column circuit 263. The data DATA′ and error correction code ECC read by the normal column circuit 263 can be transmitted to the error correction circuit 271, and the data DATA whose errors are corrected by the error correction circuit 271 can be output by the data transmission / reception circuit 203.

[0049] Pre-charge operation The precharge operation is the operation that terminates the activation operation. However, when a precharge command is applied to memory 120, an operation to count the number of activations for each row can be performed, and then an operation to precharge that row can be performed. That is, the precharge operation can be performed in the following order: (1) receiving a precharge command from memory 120, (2) reading access data A_DATA from access counting cell area 253 by access counting column circuit 265, (3) updating access data A_DATA by access information generation circuit 280, (4) writing the updated access data A_DATA to access counting cell area 253 by access counting column circuit 265, and (5) precharging or deactivating the activated row or word line by row circuit 261.

[0050] Refresh operation During a refresh operation when the refresh signal REF is activated, row circuit 261 can refresh the row in cell array 250 corresponding to the refresh address REF_R_ADD. "Refresh" can mean activating the corresponding row and then pre-charging it. During the activation operation, the data in the memory cells of the corresponding row can be detected, amplified (i.e., rewritten), and pre-charged.

[0051] During the target refresh operation when the refresh management signal RFM is activated, row circuit 261 can refresh the row in cell array 250 corresponding to the target row address T_R_ADD. Therefore, the target row selected by refresh target selection circuit 230, i.e., the row with a high probability of error occurrence, can be refreshed.

[0052] Error checking operation Error checking operations can be performed under the control of error checking operation control circuit 241. Figure 4 The error checking operation is shown below, which will be referenced. Figure 4 Describe the error checking operation.

[0053] First, an activation operation can be performed in operation 401. Row circuit 261 can activate the row in cell array 250 corresponding to the error-checking row address R_ADD_E.

[0054] Subsequently, a read operation can be performed in operation 403. The normal column circuit 263 can read data DATA′ and error correction code ECC from the column corresponding to the error-checking column address C_ADD_E in the normal cell region 251, and transmit the data DATA′ and error correction code ECC to the error correction circuit 271. That is, the data DATA′ and error correction code ECC can be read from the memory cell selected by the error-checking row address R_ADD_E and the error-checking column address C_ADD_E, and transmitted to the error correction circuit 271.

[0055] When the operation result of the error correction circuit 271 indicates that no error was found (i.e., "No" in operation 405), the row activated in operation 401 can be precharged in operation 407.

[0056] When the operation result of the error correction circuit 271 indicates that an error has been found (i.e., "yes" in operation 405), the error can be corrected by the error correction circuit 271 in operation 409, and in operation 411, the error correction code generation circuit 273 can use its error-corrected data DATA to generate a new error correction code ECC. Then, in operation 413, the error-corrected data DATA and the new error correction code ECC can be written again to the memory cell on which the read operation was performed in operation 403.

[0057] Subsequently, in operation 415, the access counting column circuit 265 can read access data A_DATA from the storage unit of the active row in the access counting unit area 253 and transmit the access data A_DATA to the access information generation circuit 280. In operation 417, the access information generation circuit 280 can update the error history of the access data A_DATA for each row to "1". Then, in operation 419, the updated access data A_DATA can be written back to the access counting unit area 253. Because the error history of each row is completely updated, the active row can be precharged in operation 407.

[0058] In error-checked operation mode, execution can be repeated while changing error-checking addresses R_ADD_E and C_ADD_E. Figure 4 The operation.

[0059] The access data A_DATA stored in the access counting cell area 253 of the cell array 250 can be periodically initialized. Once a refresh operation is performed, the number of activation operations for each row in the access data A_DATA is no longer considered. The number of activation operations for each row is used to record how many times the activation operations have been performed between refresh operation cycles. The refresh cycle for refreshing all memory cells in the memory 120 is one second or less. Therefore, the number of activation operations for each row in the access data A_DATA can be initialized within a cycle of one second or less.

[0060] The error history for each row in access data A_DATA is information collected over a very long period. For example, collecting the error history of all memory cells through error checking operations in memory 120 may take approximately 24 hours. Therefore, the error history for each row in access data A_DATA may not be initialized, or even if it is, it may be initialized over a period of 24 hours or longer.

[0061] According to the above embodiments, target refresh operations can be performed not only on rows affected by row hammering, but also on rows with their own error histories. By performing target refresh operations, it is possible to protect the memory cells affected by row hammering attacks and the data in each memory cell with an error history. Therefore, it is possible to reduce errors in the memory.

[0062] Although the technical spirit of this disclosure has been described above with reference to embodiments, this is merely for describing embodiments based on the concepts of this disclosure, and this disclosure is not limited to the embodiments described above. Various embodiments can be applied by those skilled in the art within the scope of the technical spirit of this disclosure. Furthermore, these embodiments can be combined to form additional embodiments.

Claims

1. A memory, comprising: a cell array including memory cells arranged in a plurality of rows and a plurality of columns; and a refresh target selection circuit that selects a target row for a target refresh operation based on a number of activation operations of each row in the cell array and an error history of each row.

2. The memory of claim 1, wherein, The error history of each row includes information collected during an error check operation of the memory.

3. The memory of claim 1, wherein, The cell array includes: a normal cell area that stores data; and an access count cell area that stores the number of activation operations of each row.

4. The memory of claim 3, wherein, The access count cell area also stores the error history of each row.

5. The memory of claim 4, wherein, The number of activation operations of each row stored in the access count cell area is periodically initialized, and the initialization period of the error history of each row is longer than the initialization period of the number of activation operations of each row.

6. The memory of claim 3, further comprising: an error record circuit that stores the error history of each row.

7. The memory of claim 1, wherein, The target row in the cell array is refreshed when a refresh management command is applied.

8. A memory, comprising: a normal cell area including normal memory cells arranged in a plurality of rows and a plurality of columns; an access count cell area including access count memory cells arranged in a same number of rows as the normal cell area and a different number of columns than the normal cell area, and storing a number of activation operations of each row and an error history of each row; and a refresh target selection circuit that selects a target row for a target refresh operation based on the error history of each row and the number of activation operations of each row stored in the access count cell area.

9. The memory of claim 8, further comprising: an error correction circuit that detects and corrects errors in data read from the normal cell area, wherein the error history of each row is generated based on the errors detected by the error correction circuit.

10. The memory of claim 8, wherein, The error history of each row includes information collected during an error check operation of the memory.

11. The memory of claim 8, wherein, The number of activation operations of each row stored in the access count cell area is periodically initialized, and the initialization period of the error history of each row is longer than the initialization period of the number of activation operations of each row.

12. The memory of claim 8, wherein, The target row is refreshed when a refresh management command is applied.

13. A method for performing an error check operation of a memory, the method comprising: activating a first row in a cell array; reading data of selected memory cells of the first row; detecting errors in the data to correct the detected errors; writing the error-corrected data to the selected memory cells of the first row; writing a detection history of the errors to predetermined memory cells of the first row; and pre-charging the first row.

14. The method of claim 13, further comprising: activating a second row in the cell array; reading data of the selected memory cells of the second row; checking that there is no error in the read data; and precharging the second row.

15. A method of operating a memory, the method comprising: selecting a target row for a target refresh operation based on a number of activation operations of each row in a cell array and an error history of each row; receiving a refresh management command; and refreshing the target row in response to the refresh management command. The error history of each row comprises information collected during error checking operations of the memory.

16. The operating method of claim 15, wherein, 17. The method of claim 15, further comprising: periodically initializing the number of activation operations of each row; and periodically initializing the error history of each row, wherein the initialization period of the error history of each row is longer than the initialization period of the number of activation operations of each row. ​ ​

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