Dynamic controllable frequency refreshing method and device, medium memory and storage medium

Abstract

The invention relates to the technical field of storage, in particular to a dynamic controllable frequency refreshing method and device, a medium memory and a storage medium, initial command distribution frequency is calculated by obtaining the current memory working frequency, the medium refreshing time range and the address space range, whether a command sending time point is reached or not is periodically checked according to the frequency, and the command sending time point is determined. And when arriving, judging whether the refresh command conflicts with the read-write command, and if so, dynamically adjusting the command distribution frequency. The refresh frequency can be flexibly adjusted according to the actual working condition of the memory, the problem that the read-write bandwidth is affected or the data stability is insufficient due to the fixed frequency is avoided, and the reliability and performance of the system are improved.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a dynamic controllable frequency refresh method, apparatus, medium storage device, and storage medium. Background Technology

[0002] Phase-change memory (PCM) is a memory technology that uses phase-change materials as the storage medium. Phase-change materials are materials that can transform from a crystalline state to an amorphous state at different temperatures, maintaining different resistive or reactive states. Compared to traditional hard drives, PCM technology offers advantages such as faster speeds, lower power consumption, and smaller size. However, multiple phase transitions can lead to data instability, affecting system reliability.

[0003] To address the issue of declining data retention, PCM data needs to be refreshed periodically. Existing technologies typically employ a fixed refresh rate to periodically overwrite the memory, thereby maintaining data stability. However, this method cannot be dynamically adjusted according to actual operating conditions, leading to situations where the refresh rate is too high, affecting normal read / write bandwidth, or insufficient refresh, impacting data stability. Summary of the Invention

[0004] To overcome the shortcomings of the prior art, the present invention provides a dynamic controllable frequency refresh method, device, medium storage and storage medium. By monitoring the environmental parameters of the storage in real time, the refresh frequency is intelligently adjusted, thereby significantly improving system efficiency while ensuring data stability.

[0005] A first aspect of this application provides a dynamically controllable frequency refresh method, the method comprising: Obtain the current memory operating frequency, media refresh time range, and address space range, and calculate the initial command dispatch frequency; The command distribution frequency is used to periodically check whether the command sending time point has been reached. When the command sending time is determined, it is determined whether the refresh command and read / write command conflict. The starting address is extracted from the address space to be refreshed, and the first refresh command is formed based on the starting address. After the first refresh command is successfully sent, a new address is generated according to the increment rule, and the second refresh command is formed based on the new address. This process is repeated until all refresh commands generated from the address space are successfully sent, thus completing one round of memory refresh. When it is determined that the refresh command conflicts with the read / write command, the command distribution frequency is dynamically adjusted.

[0006] In an optional implementation, dynamically adjusting the command distribution frequency when it is determined that the refresh command conflicts with the read / write command includes: Temporarily store the refresh command for the current conflict, increment the value of the remaining counter for the command by one, and clear the current cycle counter to zero; When the initial distribution frequency is reached in the next cycle, the accumulated unsent commands are sent first, followed by the refresh command for the current cycle. When it is determined that multiple consecutive cycles have conflicted, it is determined whether the command remaining counter has reached a preset threshold. When it is determined that the remaining counter for the command has reached the preset threshold, the update frequency is determined based on the current remaining total number of cycles and the remaining number of commands to be sent. The remaining counter for the command is cleared, and a periodic check is performed according to the update frequency.

[0007] In an optional implementation, the method further includes: When the current remaining total cycle and the number of remaining pending commands reach a preset ratio threshold, the enhanced mode is triggered; When it is detected that there is no conflict between the refresh command and the read / write command, the refresh command is distributed in real time, so that the refresh command is sent at full speed during the interval between the read / write commands; Once all remaining refresh commands have been successfully sent, the enhanced mode will automatically end.

[0008] In an optional implementation, the method further includes: Determine whether the current time period has reached the fixed time period; When it is determined that the current time period has reached the fixed time period, the number of commands within the fixed time period is obtained, and a new update frequency is calculated by combining the remaining total number of periods and the remaining number of commands. The new frequency is used as the current command distribution frequency, and commands are distributed according to the new update frequency until the next fixed time period arrives.

[0009] In an optional implementation, the method further includes: Once it is determined that the refresh command does not conflict with the read / write command, calculate the address of the next refresh command; The next refresh command is sent to the current memory, and the value of the command remaining counter is decremented by one.

[0010] In an optional implementation, obtaining the current memory operating frequency, media refresh time range, and address space range, and calculating the initial command dispatch frequency includes: The initial command distribution frequency is determined according to the following formula: Initial command distribution frequency = total cycle / total number of commands; Wherein, the overall cycle = operating frequency × media refresh time range, and the total number of commands = address space range = maximum address space value - minimum address space value.

[0011] A second aspect of this application provides a dynamically controllable frequency refresh device, the device comprising: The frequency calculation module is used to obtain the current memory operating frequency, media refresh time range, and address space range, and to calculate the initial command dispatch frequency; The command distribution module is used to periodically check whether the command sending time point has been reached according to the initial command distribution frequency; when it is determined that the command sending time point has been reached, it determines whether the refresh command and the read / write command conflict; wherein, the starting address is extracted from the address space to be refreshed, and the first refresh command is constructed based on the starting address; after the first refresh command is successfully sent, a new address is generated according to the increment rule, and the second refresh command is constructed based on the new address; and so on, until all refresh commands generated from the address space are successfully sent, then one round of memory refresh is completed; when it is determined that the refresh command and the read / write command conflict, the command distribution frequency is dynamically adjusted.

[0012] A third aspect of this application provides a medium memory, including a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the dynamically controllable frequency refresh method.

[0013] A fourth aspect of this application provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the above-described dynamically controllable frequency refresh method.

[0014] In summary, the dynamic controllable frequency refresh method, apparatus, medium storage device, and storage medium provided in this application have at least one of the following technical advantages: 1. Obtain the current memory's operating frequency, media refresh time range, and address space range, and calculate the initial command distribution frequency. This takes into account the actual operating conditions of the memory (operating frequency) and the characteristics of the memory itself (media refresh time range and address space range), so that the initial command distribution frequency is not fixed, but is derived based on the actual situation of the memory. 2. When a refresh command conflicts with a read / write command, the command distribution frequency is dynamically adjusted. This is the key to solving the existing technical problems in this application. By dynamically adjusting, the impact on normal read / write bandwidth caused by sending refresh commands at a fixed frequency in case of conflict (due to excessively high refresh frequency) is avoided. At the same time, since the adjustment is based on the actual situation, it also ensures that refresh is performed in a timely manner when needed, avoiding the problem of insufficient refresh affecting data stability. Therefore, this application calculates the initial command distribution frequency by obtaining relevant memory parameters, and determines whether there is a conflict with the read / write command before sending the refresh command. If there is a conflict, the command distribution frequency is dynamically adjusted. This allows for dynamic adjustment of the refresh frequency according to actual working conditions, thereby solving the problem that the fixed refresh frequency method in the prior art causes the refresh frequency to be too high in certain scenarios, affecting normal read / write bandwidth, or insufficient refresh, affecting data stability. Attached Figure Description

[0015] Figure 1 This is a timing comparison diagram of the sending of memory data refresh commands in existing technologies; Figure 2 This is a flowchart illustrating a dynamically controllable frequency refresh method according to an embodiment of this application; Figure 3 This is a flowchart illustrating an initial command distribution frequency calculation based on displacement and subtraction operations, as shown in an embodiment of this application. Figure 4 This is a schematic diagram illustrating the timing of memory refresh command transmission and conflict handling in an embodiment of this application; Figure 5 This is a schematic diagram illustrating dynamic adjustment of memory refresh frequency and timing control in an embodiment of this application; Figure 6 This is a timing diagram illustrating the transmission of memory refresh commands at an initial frequency under conflict-free conditions, as shown in an embodiment of this application. Figure 7 This is a functional block diagram of a dynamically controllable frequency refresh device shown in an embodiment of this application; Figure 8 This is a schematic diagram of the structure of a media storage device shown in an embodiment of this application. Detailed Implementation

[0016] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0017] The following will clearly and completely describe the concept, specific structure, and technical effects of the present invention in conjunction with embodiments and accompanying drawings, so as to fully understand the purpose, features, and effects of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, not all of them. Other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are all within the scope of protection of the present invention. Furthermore, all connections / linkages involved in the patent do not simply refer to direct contact between components, but rather to the ability to form a better connection structure by adding or reducing connecting accessories according to specific implementation conditions. The various technical features in this invention can be combined interactively without contradicting each other.

[0018] Most existing media refresh methods employ configured start and end addresses and a fixed frequency to perform data refresh and overwrite operations on the included addresses within a fixed time period. If the fixed frequency is reached, and the data refresh command conflicts with normal memory read / write operations, the data refresh command cannot be received at the fixed frequency. Consequently, not all addresses can be refreshed within the fixed time, leading to unstable or corrupted unrefreshed data.

[0019] For example, at a 1MHz operating frequency, a memory address space ranging from 0x0 to 0xFFFF needs to be refreshed within one minute. This requires sending 65,536 overwrite commands within 1,000,000 cycles to meet data retention requirements. A fixed frequency of approximately 16 cycles means one command is sent every 16 cycles. If a command is not prepared and successfully sent within 16 clock cycles, the interval between commands will increase until the command is successfully sent. At this point, the cycle counter `cycle_cnt` is reset and restarted. Figure 1 As shown, the command is expected to be received when cycle_cnt is 16. If the actual command is not prepared and successfully sent within the cycle, the cycle will be extended. When this periodic instability occurs frequently, it will directly lead to the inability to perform a full refresh within the specified time, resulting in data instability.

[0020] This application can be applied to all media storage devices with the same data instability problem. To facilitate understanding of the inventive concept, the following embodiments use phase-change memory as an example. The dynamically controllable frequency refresh method is described below using a dynamically controllable frequency refresh device. This dynamically controllable frequency refresh device can be a server or a service unit within a server; no specific limitation is made. The dynamically controllable frequency refresh device includes a frequency calculation module, a command distribution module, and a remaining cycle and command statistics module.

[0021] Reference Figure 2 The diagram shown is a flowchart illustrating a dynamically controllable frequency refresh method according to an embodiment of this application. The dynamically controllable frequency refresh method includes the following steps.

[0022] S21: Obtain the current memory operating frequency, media refresh time range, and address space range, and calculate the initial command dispatch frequency.

[0023] In some embodiments, after system startup, the frequency calculation module can read the current operating frequency from the clock signal source or configuration register of the memory controller, obtain the media refresh time range according to the media type, and obtain the address space range from the memory management unit or address decoder configuration register. Here, the memory operating frequency represents the number of vibrations per second, the media refresh time range (i.e., the time requirement for completing one refresh) represents the time requirement for completing one refresh, and the memory address space range represents the difference between the maximum and minimum values ​​of the address space.

[0024] Furthermore, the frequency calculation module calculates the initial command dispatch frequency using bit shifting and subtraction based on the current memory operating frequency, media refresh time range, and address space range. Specifically: Overall cycle = operating frequency × media refresh time range; Total number of commands = Address space range = Maximum address space value - Minimum address space value; Initial command distribution frequency = total cycle / total number of commands.

[0025] The initial command distribution frequency (hereinafter referred to as the initial frequency) defines the number of refresh commands to be sent in each cycle. The command distribution module uses this frequency as a benchmark to periodically check whether the command sending time has been reached. For example, if the initial frequency is 16, the module will attempt to send one refresh command every 16 cycles. (See also...) Figure 3 The total number of commands is calculated starting from the most significant bit, with the first non-zero bit shifted left to a position equal to the total number of cycles. The commands are compared; if B is greater than A, a 0 is accumulated and the bit is shifted right by one bit. If B is less than A, A is updated to A minus B, and the shift is accumulated to a power of 2. B is then shifted right, and this process is repeated. When B has shifted right to its original bit width, and A has been updated to A minus B less than B, a carry-in of 1 is used to ensure a complete disk refresh. In this embodiment, the initial frequency is 16 after the first step of calculation, and the following embodiments will all use an initial frequency of 16.

[0026] S22, periodically check whether the command sending time point has been reached according to the initial command distribution frequency.

[0027] In some embodiments, the command statistics module maintains two counters: a total cycle counter `cycle_cnt` and a command remaining counter `store_cnt`. The total cycle counter `cycle_cnt` counts according to the initial command distribution frequency. Whenever the initial frequency is reached (i.e., every `F_init` system clock cycles), the total cycle count is decremented by the number of cycles corresponding to the initial frequency, thus determining the number of cycles remaining in the remaining time. For example, if the initial total cycle count is `Cycle_total`, after one frequency cycle, the remaining total cycle count = `Cycle_total` - `F_init`. The command remaining counter `store_cnt` records the number of refresh commands that failed to be sent due to conflicts with read / write commands. Its initial value is 0. Whenever a write command (i.e., a refresh command) is successfully sent through the command distribution module, the value of the command remaining counter is decremented by one, used to maintain the number of commands remaining to be sent internally in real time. Initially, the value of the command remaining counter is the total number of commands `Cmd_total` calculated above.

[0028] The command distribution module uses the initial command distribution frequency F_init obtained by the frequency calculation module as a reference and periodically checks whether the command transmission time point has been reached. Specifically, it monitors the count of the system clock sys_clk, and considers the command transmission time point to have been reached when the count reaches a multiple of F_init.

[0029] S23, when the time point for sending the command is determined, determine whether the refresh command and the read / write command conflict.

[0030] Among them, the refresh command ensures refresh operations required by the memory medium properties (such as PCM needing to be refreshed periodically to prevent data loss). The refresh controller pre-generates the command sequence based on the medium properties (such as refresh time range) and address space range.

[0031] In some embodiments, during the power-on initialization phase, the memory first determines the address space range to be refreshed, i.e., the command sequence covers the entire address space (from the minimum address to the maximum address), and subsequent commands are sent in ascending order of address. For example, if the address space is 0x0000~0xFFFF, the initial command sequence is 0x0000, 0x0001, ..., 0xFFFF. The starting address 0x0000 is extracted from the initial command sequence, and this starting address constitutes the first refresh command. This command serves as the start signal for the refresh process, marking the formal start of the memory refresh operation. The generated first refresh command is sent to the memory control module. Upon receiving the command, the memory control module executes the corresponding refresh operation, refreshing the memory cell corresponding to address 0x0000. After completing the refresh operation, the memory control module returns an operation result signal. If this signal indicates that the first refresh command was successfully sent and executed, the next step is performed; if the sending fails, an error handling mechanism is triggered, and the first refresh command is resent until it is successfully sent. After the first refresh command is successfully sent, a new address is generated according to the address increment rule. Specifically, the current address 0x0000 is incremented by 1 to obtain a new address 0x0001, and this new address is used to construct the second refresh command. The second refresh command is sent to the memory control module, which then awaits the operation result signal. If the transmission is successful, the next new address (0x0002) is generated according to the address increment rule, and a new refresh command is constructed and sent. If the transmission fails, the current refresh command is resent until successful. This process continues, continuously generating and sending new refresh commands. As the address increments, the memory cell corresponding to each address in the address space is refreshed sequentially. When the refresh command corresponding to the last address 0xFFFF is successfully sent and executed, it indicates that all refresh commands generated from the address space have been successfully sent, thus completing one round of memory refresh.

[0032] S24, when it is determined that the refresh command conflicts with the read / write command, the command distribution frequency is dynamically adjusted.

[0033] In some embodiments, when the command sending time point is reached, the command distribution module determines whether the refresh command conflicts with the read / write command. Specifically, when a new command sending time point is reached, if the refresh command and the read / write command do not conflict, the refresh command is sent normally; if a conflict exists, based on the conflict handling mechanism, the unsent commands are accumulated in store_cnt, and compensation is sent at a later appropriate time.

[0034] In an optional implementation, dynamically adjusting the command distribution frequency when it is determined that the refresh command conflicts with the read / write command includes: Temporarily store the refresh command for the current conflict, increment the value of the remaining counter for the command by one, and clear the current cycle counter to zero; When the initial distribution frequency is reached in the next cycle, the accumulated unsent commands are sent first, followed by the refresh command for the current cycle. When it is determined that multiple consecutive cycles have conflicted, it is determined whether the command remaining counter has reached a preset threshold. When it is determined that the remaining counter for the command has reached the preset threshold, the update frequency is determined based on the current remaining total number of cycles and the remaining number of commands to be sent. The remaining counter for the command is cleared, and a periodic check is performed according to the update frequency.

[0035] In some embodiments, if a conflict exists—that is, the memory interface is performing a read / write operation and cannot process a refresh command simultaneously—the command cannot be sent successfully. The command distribution module clears `cycle_cnt` to zero and increments `store_cnt` by 1, indicating that a command that should have been sent but was not has been accumulated. In the next fixed cycle (when `cycle_cnt` counts back to its initial frequency value of 16), the command distribution module needs to send two commands: the accumulated command corresponding to `store_cnt` and the command that should have been sent in the current cycle. For example, if `store_cnt` is 1, it means there is an accumulated unsent command. When `cycle_cnt` has not counted to 16 in this cycle, if a gap without conflict with read / write commands is detected, the command distribution module will directly distribute the accumulated command. At this time, `store_cnt` is decremented by 1 and cleared to zero. The command that should have been distributed in the previous cycle is inserted into the current cycle and distributed when `cycle_cnt` counts to the fixed frequency of 16 and there is no conflict. Throughout the entire process, the initial value of the fixed frequency remains unchanged.

[0036] Reference Figure 4 As shown, `sys_clk` is the system clock, providing a timing reference for the entire system. The `Expected_cmd_rdy` signal becomes active (e.g., high level) when `cycle_cnt` reaches a fixed frequency, indicating that a refresh command is expected to be sent. The `Actual_cmd_rdy` signal reflects whether the command can actually be sent. When there is a conflict with a read / write command, `Actual_cmd_rdy` remains inactive (e.g., low level), the command cannot be sent, and `store_cnt` increments. In the next cycle, the system attempts to compensate by sending the accumulated command; if conditions permit, it sends it, and `store_cnt` decrements accordingly. The `output_cmd` signal outputs the specific refresh command when the command is successfully sent.

[0037] If the scenario of `cycle_cnt` reaching a fixed frequency and commands failing to be sent continues to occur, `store_cnt` will continuously increment. Due to frequent conflicts, the increment rate of `store_cnt` will far exceed the rate at which the reduction in transmission can be compensated within a cycle. In this embodiment, N is taken as half of the initial frequency 16, i.e., N=8. The size of the threshold has a significant impact on system performance; that is, the smaller the threshold, the easier it is for the system to trigger the frequency update condition, and the more accurate the frequency adjustment will be. However, frequent frequency calculations will increase system power consumption. During command distribution, the value of `store_cnt` continuously accumulates due to continuous command conflicts. Once `store_cnt` is greater than or equal to 8, the frequency update module will be triggered, and the fixed frequency update function will be started. When `store_cnt` accumulates to exceed the preset threshold N (e.g., N=8), the system will trigger the frequency update condition. Once the frequency update is triggered, the system will re-enter the frequency calculation process. The frequency calculation module takes the remaining total number of cycles (initial total number of cycles minus the number of cycles already consumed) and the remaining number of commands to be sent (initial total number of commands minus the number of commands already successfully sent) as input. Following the same implementation method as the initial frequency calculation described above, it re-determines the updated frequency value X by aligning the bit width and performing iterative subtraction. After calculating the updated frequency X, store_cnt is cleared to zero. The system will use the updated frequency X to replace the initial frequency for subsequent command distribution and flow control operations until store_cnt exceeds the threshold N again, triggering the next frequency calculation and update.

[0038] After obtaining the update frequency X, the system will replace the initial frequency with this update frequency for subsequent command distribution and flow control operations. The command distribution module periodically checks whether the command sending time point has been reached according to the new frequency X, and decides whether to send a refresh command based on the conflict with read and write commands, until store_cnt exceeds the threshold N again (i.e., greater than or equal to 8). At this time, the frequency will be calculated and updated again, and the above process will be repeated to dynamically adapt to the working state of the system.

[0039] Refer to together Figure 5`sys_clk` is the system clock signal, providing a timing reference for the entire system. `cycle_cnt` counts according to the initial or updated frequency. The `expected_cmd_rdy` signal becomes active when `cycle_cnt` reaches the corresponding frequency value, indicating that a refresh command is expected to be sent. The `actual_cmd_rdy` signal reflects whether a command can actually be sent. When `store_cnt` reaches the threshold N, a frequency update is triggered, the `trig_calc_freq` signal becomes active, and the system begins to recalculate the frequency. After the new updated frequency is calculated, `new_cycle_cnt` counts according to the new frequency, and the `new_expected_cmd_rdy` and `new_actual_cmd_rdy` signals also change their states accordingly based on the new frequency to achieve command distribution and flow control at the updated frequency.

[0040] It should be noted that the conditions for triggering the update frequency can be set in various ways to flexibly adapt to different work scenarios and needs, ensuring the efficiency and stability of refresh command distribution. Specifically, the conditions for triggering the update frequency can be based on the cumulative number of undistributed commands, time, or a combination of both.

[0041] 1) Triggered based on the cumulative number of undistributed commands.

[0042] When triggered based on the cumulative number of undistributed commands, the system allows configuration of a configurable cycle. Within this cycle, the number of undistributed commands determines whether to initiate a frequency update. Specifically, the system can pre-set the configurable cycle and the corresponding threshold for the number of undistributed commands based on factors such as memory characteristics and workload. For example, the configurable cycle can be set to every 100 system clock cycles, and the threshold for the number of undistributed commands can be set to 10. The remaining cycle and command statistics module continuously monitors the number of undistributed refresh commands. At the end of each configurable cycle, if the cumulative number of undistributed commands reaches or exceeds the preset threshold, the frequency update module is triggered. The frequency update module recalculates the update frequency using the same calculation method as described above, taking the remaining total number of cycles and the remaining number of commands as inputs, and determining the new frequency value through bit width alignment and iterative subtraction. After calculation, the system will replace the current frequency with the new frequency for command distribution and flow control.

[0043] 2) Time-based triggering.

[0044] In addition to triggering based on the number of undistributed commands, the system also supports triggering frequency updates using a fixed time period. The system can be configured with a fixed time period, such as 1 second or n seconds (n being a user-defined positive integer), and internally uses a timer to precisely record the time. When the timer reaches the configured fixed time period, the system automatically triggers the frequency update process. At this time, the system counts the number of cycles within that fixed time period and, combined with the remaining total number of cycles and the remaining number of commands, recalculates the update frequency. For example, if the configured fixed time is 1 second, and the system records 1000 cycles within that second, it also obtains the remaining total number of cycles and the remaining number of commands, and calculates a new frequency value using a specific algorithm. After obtaining the new frequency, the system clears the relevant counters and timers, using the new frequency as the current command distribution frequency for subsequent command distribution and flow control operations. During the operation of the new frequency, the system continues to use the time-based triggering method, reassessing whether another frequency update is needed at the end of each fixed time period.

[0045] 3) Two methods: triggering based on the cumulative number of undistributed commands and triggering based on time.

[0046] In practical applications, triggering based on the cumulative number of undistributed commands and triggering based on time can work together. For example, the system can simultaneously set a threshold based on the number of undistributed commands and a time-based period. A frequency update will be triggered when either condition is met. Specifically, the priority of the two triggering methods can be set according to actual needs. For example, if the triggering based on the number of undistributed commands is set to a higher priority, a frequency update will be triggered immediately when the number of undistributed commands reaches the threshold, without waiting for the fixed time period to end; if the threshold is not reached within the fixed time period, a frequency update will be triggered at the end of the time period. Through this collaborative approach, the system can adjust the refresh frequency in a timely manner when commands accumulate too quickly or the working time reaches a certain length, using a stable period to regulate the command distribution frequency, ensuring the timeliness and accuracy of memory data refresh, and avoiding data loss or instability caused by unreasonable frequencies.

[0047] Through the above optional implementation methods, the threshold-triggered frequency update mechanism can reasonably handle unsent commands when refresh commands and read / write commands conflict, and dynamically adjust the refresh frequency when the conflict continues, ensuring effective refresh of memory data and stable operation of the system.

[0048] In an optional implementation, the method further includes: Once it is determined that the refresh command does not conflict with the read / write command, calculate the address of the next refresh command; The next refresh command is sent to the current memory, and the value of the command remaining counter is decremented by one.

[0049] In other embodiments, when the initial frequency is reached and there is no conflict between the refresh command and the read / write command—that is, when the status signal of the memory interface determines that the memory interface is not currently performing normal read / write operations, or when normal read / write operations and refresh commands do not overlap in time—the command distribution module can successfully send the command according to the initial frequency. The address of the next refresh command is calculated according to a preset address increment rule. For example, after each successful refresh command, the address pointer is automatically incremented by 1, pointing to the address of the next memory cell to be refreshed; the refresh command with the calculated address is sent to the memory through the memory interface. Simultaneously, the value of the command remaining counter is decremented by one, indicating that a command has been successfully sent. (Refer to...) Figure 6 As shown, sys_clk is the system clock signal, which alternates between high and low levels to provide a timing reference for the entire system; cycle_cnt counts according to the initial command distribution frequency F_init, and triggers a command transmission check every F_init clock cycles; the Expected_cmd_rdy signal becomes valid (e.g., high level) when the command transmission time point is reached and there is no conflict, indicating that the refresh command is ready to be sent; the output_cmd signal outputs the specific refresh command and sends it to the memory when Expected_cmd_rdy is valid and there is no conflict.

[0050] With the above optional implementation methods, when there is no conflict between refresh command and read / write command, the system can successfully send refresh command at a calculated fixed frequency, ensuring that the memory data is refreshed in a timely manner within a specified time, thus guaranteeing the reliability of the data and the normal operation of the memory.

[0051] In an optional implementation, the method further includes: When the current remaining total cycle and the number of remaining pending commands reach a preset ratio threshold, the enhanced mode is triggered; When it is detected that there is no conflict between the refresh command and the read / write command, the refresh command is distributed in real time, so that the refresh command is sent at full speed during the interval between the read / write commands; Once all remaining refresh commands have been successfully sent, the enhanced mode will automatically end.

[0052] In some embodiments, the remaining cycle and command statistics module continuously tracks the remaining number of cycles and the remaining number of refresh commands to be sent. Simultaneously, the system allows configuration of the ratio threshold for triggering enhancement mode (i.e., enhance mode), with configurable ratios including 1:1, 1:1.25, and 1:1.5. For example, a 1:1 configuration means that enhance mode is triggered when the remaining number of commands equals the remaining number of cycles; a 1:1.25 configuration triggers it when the ratio of remaining commands to remaining cycles is 1:1.25. Furthermore, the enhance mode function itself is configurable, allowing it to be enabled or disabled at any time during system scanning to meet different work scenario requirements.

[0053] During system operation, the remaining cycle and command statistics module monitors the ratio of remaining commands to remaining cycles in real time. Once this ratio reaches a pre-configured threshold, the module triggers enhance mode. For example, assuming the configured ratio threshold is 1:1.5, when there are 10 remaining commands and 15 remaining cycles, the ratio reaches 10:15 = 1:1.5, at which point enhance mode is triggered. The trigger signal can be an internal flag; when this flag is set, it indicates that the system enters enhance mode.

[0054] Once in Enhance mode, the refresh command distribution strategy changes. In non-Enhance mode, refresh command transmission is limited by a fixed frequency, requiring periodic checks and transmissions according to a pre-calculated frequency. In Enhance mode, once refresh commands are ready, this fixed frequency no longer applies. The command distribution module monitors the memory interface status in real time. As long as it detects no conflict between refresh commands and read / write commands (i.e., the memory interface is idle or capable of handling both refresh and read / write commands simultaneously, depending on the memory's specific characteristics and interface protocol), it immediately distributes the refresh command. This means refresh commands are sent at full speed during read / write command intervals to complete the remaining command transmission task as quickly as possible. For example, if the system enters Enhance mode at a certain moment, with 5 refresh commands remaining, the command distribution module will immediately send a refresh command once it detects no read / write commands being executed on the memory interface. It will then continue monitoring the interface status and, if the conflict-free condition is met, continue sending the remaining refresh commands until all remaining commands are successfully sent. Once all remaining refresh commands have been successfully sent, Enhance mode automatically ends. At this point, the system can revert to the normal refresh command sending strategy in non-enhance mode, continuing to periodically check and send commands at a fixed frequency. Simultaneously, the relevant internal flags will be cleared to indicate that enhancement mode has been exited.

[0055] Through the above optional implementation methods, the enhancement function of the remaining cycle and command statistics module can effectively improve the sending efficiency of refresh commands under specific conditions, ensure that memory data can be refreshed in a timely and accurate manner, and guarantee the stable operation of the system.

[0056] This application enables dynamic control of command distribution during the initial fixed-frequency operation phase, effectively maintaining the stability of the initial fixed-frequency and ensuring that refresh operations are performed orderly within a predetermined frequency framework, providing a stable timing foundation for memory data refresh. When the accumulation of commands poses a risk when using the initial fixed-frequency distribution, the frequency can be adjusted in a timely manner, and the frequency adjustment parameters are configurable, allowing the system to adapt flexibly to actual conditions and control risks within a foreseeable range, ensuring the reliability and stability of refresh operations. Through the use of the enhancement function, it possesses both automatic detection capabilities and supports open configuration, maintaining the normal operation of command distribution in extreme scenarios and ensuring that data refresh tasks can still be completed under special working conditions. Through the organic combination of the above-mentioned multiple scenarios and functions, it can maximize the guarantee of comprehensive data refresh and overwrite operations on the addresses contained in the memory within a fixed time, effectively avoiding data instability problems caused by factors such as voltage drift, and significantly improving the reliability of memory data and the overall performance of the memory.

[0057] Reference Figure 7 The diagram shown is a functional block diagram of a dynamically controllable frequency refresh device according to an embodiment of this application.

[0058] In some embodiments, the dynamically controllable frequency refresh device 70 may include multiple functional modules composed of computer program segments. The computer programs for each program segment of the dynamically controllable frequency refresh device 70 may be stored in the memory of a media storage device and executed by at least one processor to perform (see details). Figure 1 (Description) The function of dynamically controllable frequency refresh. Based on its function, it can be divided into multiple functional modules. These functional modules may include: a frequency calculation module 701, a command distribution module 702, and a remaining cycle and command statistics module 703. The module referred to in this application is a series of computer program segments that can be executed by at least one processor and perform a fixed function, stored in memory. In this embodiment, the functions of each module will be detailed in subsequent embodiments.

[0059] The frequency calculation module 701 is used to obtain the current operating frequency, media refresh time range and address space range of the memory, and to calculate the initial command distribution frequency.

[0060] The command distribution module 702 is used to periodically check whether the command sending time point has been reached according to the initial command distribution frequency; when it is determined that the command sending time point has been reached, it determines whether the refresh command and the read / write command conflict; wherein the starting address is extracted from the address space to be refreshed, and the first refresh command is formed based on the starting address; after the first refresh command is successfully sent, the address is generated into a new address according to the increment rule, and the second refresh command is formed based on the new address; and so on, until all refresh commands generated from the address space are successfully sent, then one round of memory refresh is completed; when it is determined that the refresh command and the read / write command conflict, the command distribution frequency is dynamically adjusted.

[0061] The remaining cycle and command statistics module 703 is used to: trigger an enhanced mode when the current remaining total cycle and the number of remaining pending commands reach a preset ratio threshold; when it is detected that there is no conflict between the refresh command and the read / write command, distribute the refresh command in real time so that the refresh command is sent at full speed between the read / write commands; and automatically end the enhanced mode after all remaining refresh commands have been successfully sent.

[0062] It should be understood that the various variations and specific embodiments of the dynamic controllable frequency refresh method provided in the above embodiments are also applicable to the dynamic controllable frequency refresh device of this embodiment. Through the foregoing detailed description of the dynamic controllable frequency refresh method, those skilled in the art can clearly understand the implementation method of the dynamic controllable frequency refresh device in this embodiment. For the sake of brevity, it will not be described in detail here.

[0063] See Figure 8 The diagram shown is a schematic representation of the structure of a media memory according to an embodiment of this application. In a preferred embodiment of this application, the media memory 8 includes a storage medium 81, at least one processor 82, and at least one communication bus 83.

[0064] Those skilled in the art should understand that Figure 8 The structure of the media memory shown does not constitute a limitation of the embodiments of this application. It can be a bus structure or a star structure. The media memory 8 may also include more or fewer other hardware or software than shown, or different component arrangements.

[0065] In some embodiments, the media storage 8 is a device capable of automatically performing numerical calculations and / or information processing according to pre-set or stored instructions. Its hardware includes, but is not limited to, microprocessors, application-specific integrated circuits (ASICs), programmable gate arrays (FPGAs), digital processors, and embedded devices. The media storage 8 may also include user equipment, including, but not limited to, any electronic product capable of human-computer interaction with a user via a keyboard, mouse, remote control, touchpad, or voice control device, such as a personal computer, tablet computer, smartphone, or digital camera.

[0066] In the embodiments provided in this application, it should be understood that the disclosed methods, apparatus, computer-readable storage media, and media memory can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple components or modules may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection of devices, components, or modules may be electrical, mechanical, or other forms.

[0067] The components described as separate parts may or may not be physically separate. The components shown as components may or may not be physical modules; that is, they may be located in one place or distributed across multiple network modules. Some or all of the components can be selected to achieve the purpose of this embodiment according to actual needs.

[0068] Furthermore, the functional modules in the various embodiments of the present invention can be integrated into one processing module, or each component can exist physically separately, or two or more modules can be integrated into one module. The integrated modules described above can be implemented in hardware or as software functional modules.

[0069] If the integrated module is implemented as a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0070] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that the present invention is not limited to the described order of actions, because according to the present invention, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to the present invention.

[0071] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0072] The above is a detailed description of the preferred embodiments of the present invention. However, the present invention is not limited to the embodiments described. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention. All such equivalent modifications or substitutions are included within the scope defined by the claims of this application.

Claims

1. A method of dynamic controllable frequency refresh, the method comprising: The method comprises: acquiring the working frequency of a current memory, the medium refresh time range and the address space range, and calculating an initial command distribution frequency; periodically checking whether a command sending time point is reached according to the initial command distribution frequency; when it is determined that the command sending time point is reached, judging whether the refresh command and the read-write command conflict; wherein a start address is extracted from the address space to be refreshed to form a first refresh command according to the start address; after the first refresh command is successfully sent, a new address is generated according to the incremental rule to form a second refresh command according to the new address; and so on until all the refresh commands generated by the address space are successfully sent, then a round of memory refresh is completed; when it is determined that the refresh command and the read-write command conflict, dynamically adjusting the command distribution frequency.

2. The method of claim 1, wherein, The dynamic adjustment of the command distribution frequency when it is determined that the refresh command and the read-write command conflict comprises: temporarily storing the current conflicting refresh command, adding one to the value of a command remaining counter, and clearing the current cycle counter; when the next cycle reaches the initial distribution frequency, the accumulated unsent commands are preferentially sent, and then the refresh command of the current cycle is sent; when it is determined that conflicts occur in continuous multiple cycles, judging whether the command remaining counter reaches a preset threshold value; when it is determined that the command remaining counter reaches the preset threshold value, determining an updated frequency according to the current total number of remaining cycles and the number of remaining to-be-sent commands; clearing the command remaining counter, and performing periodic checking according to the updated frequency.

3. The method of claim 2, wherein, The method further comprises: when the current total number of remaining cycles and the number of remaining to-be-sent commands reach a preset proportion threshold value, triggering an enhanced mode; when it is detected that the refresh command and the read-write command do not conflict, the refresh command is distributed in real time, so that the refresh command is sent at full speed in the gap of the read-write command; when all the remaining refresh commands are successfully sent, the enhanced mode is automatically ended.

4. The method of claim 2, wherein, The method further comprises: judging whether the current time cycle reaches a fixed time cycle; when it is determined that the current time cycle reaches the fixed time cycle, acquiring the number of commands in the fixed time cycle, and combining the total number of remaining cycles and the number of remaining commands to calculate a new updated frequency; the new frequency is taken as the current command distribution frequency, and the command distribution is performed according to the new updated frequency until the next fixed time cycle arrives.

5. The method of claim 2, wherein, The method further comprises: when it is determined that the refresh command and the read-write command do not conflict, calculating the address of the next refresh command; the next refresh command is sent to the current memory, and the value of the command remaining counter is reduced by one.

6. The method of claim 1, wherein, The acquisition of the working frequency of a current memory, the medium refresh time range and the address space range, and the calculation of an initial command distribution frequency comprise: the initial command distribution frequency is determined according to the following formula: initial command distribution frequency = total cycle / total command number; wherein, total cycle = working frequency × medium refresh time range, and total command number = address space range = address space maximum - address space minimum.

7. A dynamically controllable frequency refresh device, characterized by The device comprises: A frequency calculation module is configured to acquire a working frequency of a current memory, a medium refresh time range and an address space range, and calculate an initial command distribution frequency; A command distribution module is configured to periodically check whether a command sending time point is reached according to the initial command distribution frequency, determine whether a refresh command and a read-write command conflict when it is determined that the command sending time point is reached, extract a start address from an address space to be refreshed to form a first refresh command according to the start address, generate a new address according to an incremental rule after the first refresh command is successfully sent to form a second refresh command according to the new address, and so on until all refresh commands generated from the address space are successfully sent, so that a round of memory refresh is completed, and dynamically adjust the command distribution frequency when it is determined that the refresh command and the read-write command conflict.

8. A media storage, characterized by A computer program is stored in a memory and executable on a processor, and the processor implements steps of the dynamic controllable frequency refresh method according to any one of claims 1 to 6 when the computer program is executed.

9. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program is executable on the processor to implement steps of the dynamic controllable frequency refresh method according to any one of claims 1 to 6.

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