Method and system for balancing gate charges of MOS (Metal Oxide Semiconductor) transistor of parasitic capacitance charge counteracting logic

Abstract

The invention discloses an MOS (Metal Oxide Semiconductor) transistor grid charge balancing method and system for parasitic capacitance charge counteracting logic, and relates to the field of power electronic device driving. According to the method, a gate voltage second derivative characteristic signal is extracted through a cascade analog differentiating circuit to identify parasitic capacitance transient disturbance, and asynchronous quantization is triggered to generate a digital quantized value when an amplitude exceeds a threshold value; a clockless asynchronous combinatorial logic retrieval circuit retrieves a charge compensation control index from a charge compensation lookup table; after the programmable current mirror array is decoded, the current mirror branch is selectively conducted, and quantitative compensation charges are applied to a grid node; the waveform deviation integral circuit obtains compensated waveforms, detects characteristic moments to achieve time domain synchronization, calculates a waveform deviation integral value and dynamically modifies a lookup table mapping relation to form closed-loop feedback. According to the scheme, transient disturbance and normal switching are distinguished through second derivative characteristics, synchronous sampling delay is eliminated through a clock-free architecture, and online self-adaptive optimization of compensation parameters is achieved through closed-loop negative feedback.

Description

Technical Field

[0001] This invention relates to the field of power electronic device driving technology, specifically to a method and system for gate charge balancing of MOS transistors based on parasitic capacitance transient disturbance detection and closed-loop compensation. Background Technology

[0002] With the development of power electronics technology, power semiconductor devices such as MOS transistors and IGBTs have been widely used in motor drives, switching power supplies, inverters, and electric vehicles. The gate drive circuit, as a key interface between the power device and the control circuit, directly affects the switching characteristics, efficiency, and reliability of the entire system. During the switching process of power devices, parasitic capacitances between the gate and drain (Miller capacitance) and between the gate and source can cause transient disturbances to the gate voltage. These disturbances may lead to mis-turn-on or mis-turn-off of the device, resulting in serious consequences such as bridge arm shoot-through.

[0003] Currently, the industry has developed various technologies to address the gate voltage disturbance problem caused by parasitic capacitance. Active Miller clamping technology activates a clamping circuit when the gate voltage exceeds a set threshold, limiting the gate voltage to a safe range. Load-adaptive drive technology adjusts the drive strength based on changes in load current. Additionally, there is drive rate control technology based on dV / dt detection, which adjusts the gate drive capability by monitoring the drain voltage change rate. These technologies have improved the switching characteristics of power devices to some extent.

[0004] However, existing technologies still have the following shortcomings in dealing with parasitic capacitance transient disturbances: First, existing voltage threshold detection or first derivative detection methods are difficult to effectively distinguish between gate voltage changes caused by parasitic capacitance transient disturbances and voltage changes during normal switching processes, which may lead to false detections; Second, the detection and processing circuits using synchronous sampling architecture have inherent delays introduced by the clock cycle, resulting in excessively long response times between the occurrence of disturbances and the execution of compensation, which is difficult to meet the needs of high-speed switching applications; Third, fixed compensation amounts or simple graded compensation methods cannot accurately match disturbances of different amplitudes and directions; Fourth, existing solutions generally use open-loop control or simple single-point feedback, lacking an effective closed-loop feedback adjustment mechanism. After the compensation parameters are set, they cannot be adaptively optimized online according to the actual compensation effect, resulting in the compensation effect being greatly affected by changes in operating conditions and the system lacking overall synergistic effect.

[0005] Therefore, there is a need for a MOS transistor gate charge balancing technology that can accurately identify parasitic capacitance transient disturbances, respond quickly, finely match compensation requirements, and has closed-loop adaptive optimization capabilities. Summary of the Invention

[0006] The purpose of this invention is to provide a method and system for balancing the gate charge of a MOS transistor with parasitic capacitance charge cancellation logic, in order to solve the following technical problems existing in the prior art: existing voltage threshold detection or first derivative detection methods are difficult to effectively distinguish between parasitic capacitance transient disturbances and normal switching processes; synchronous sampling architecture has response delays that cause compensation timing to lag; fixed compensation amounts cannot adapt to disturbances of different amplitudes and directions; and the lack of an effective closed-loop feedback adjustment mechanism makes it impossible for compensation parameters to be adaptively optimized according to actual effects, resulting in a lack of overall synergistic effect in the system.

[0007] To achieve the above objectives, this invention provides a method for gate charge balancing of a MOS transistor using parasitic capacitance charge cancellation logic, comprising the following steps: continuously capturing the second derivative characteristic signal of the gate voltage attributable to transient disturbances of parasitic capacitance using a cascaded analog differentiating circuit, and generating a trigger pulse signal when the amplitude of the second derivative characteristic signal exceeds a preset trigger threshold; asynchronously quantizing the second derivative characteristic signal of the gate voltage in response to the trigger pulse signal to generate a digital quantized value; and using a clockless asynchronous combinational logic lookup circuit based on the mapping relationship currently stored in the charge compensation lookup table. The system retrieves the charge compensation control index corresponding to the digital quantization value; decodes the charge compensation control index using a programmable current mirror array, and selectively turns on the internal current mirror branch according to the decoding result to apply quantization compensation charge to the gate node to offset the transient disturbance of the parasitic capacitance; obtains the gate voltage waveform after applying the quantization compensation charge using a waveform deviation integration circuit, detects the characteristic moment of the gate voltage waveform to achieve time-domain synchronization with the preset reference voltage waveform, calculates the time-domain waveform deviation integral value after synchronization, and dynamically modifies the mapping relationship in the charge compensation lookup table based on the time-domain waveform deviation integral value.

[0008] Furthermore, the step of continuously capturing the gate voltage second derivative characteristic signal of the MOS transistor gate voltage using a cascaded analog differentiating circuit includes: obtaining the second derivative of the gate voltage with respect to time as the gate voltage second derivative characteristic signal through a multi-stage series high-pass differentiating network in the cascaded analog differentiating circuit; comparing the absolute value of the second derivative with the preset trigger threshold; and outputting the trigger pulse signal when the absolute value is greater than the preset trigger threshold.

[0009] Furthermore, the step of using a clockless asynchronous combinational logic retrieval circuit to retrieve the charge compensation control index corresponding to the digital quantization value includes: using an asynchronous parallel comparator array as a quantization front end; directly converting the second derivative characteristic signal of the gate voltage into the digital quantization value when the trigger pulse signal is received; triggering an internal latch to latch the digital quantization value and initiating an asynchronous lookup operation on the internal charge compensation lookup table; and outputting the charge compensation control index corresponding to the digital quantization value independently of the system clock signal through the asynchronous lookup operation.

[0010] Furthermore, the decoding of the charge compensation control index using a programmable current mirror array includes: utilizing at least two preset weighted current mirror branches in the programmable current mirror array, wherein the current mirror branches are configured to perform current injection or current extraction operations according to a control signal; selectively conducting the source current branch for current injection or the leakage current branch for current extraction according to the polarity control bit and amplitude control bit in the charge compensation control index, thereby synthesizing the quantized compensation charge corresponding to the charge compensation control index.

[0011] Further, the step of calculating the integral value of the time-domain waveform deviation of the gate voltage waveform relative to the preset reference voltage waveform includes: after the switching action of the MOS transistor is completed, detecting a specific characteristic moment of the actual gate voltage waveform as a synchronization reference point; determining a time window for integration calculation based on the synchronization reference point; acquiring reference data of the preset reference voltage waveform within the time window; calculating the difference between the actual gate voltage data and the reference data within the time window, and integrating the difference to obtain the integral value of the time-domain waveform deviation.

[0012] Further, the step of dynamically modifying the mapping relationship in the charge compensation lookup table based on the integral value of the time-domain waveform deviation includes: determining the polarity of the integral value of the time-domain waveform deviation; if the polarity indicates an overcompensated state, then retrieving the current charge compensation control index corresponding to the digital quantization value in the charge compensation lookup table, reducing the value of the current charge compensation control index by a preset fine-tuning step, and updating and storing the reduced charge compensation control index in the charge compensation lookup table; if the polarity indicates an undercompensated state, then retrieving the current charge compensation control index corresponding to the digital quantization value in the charge compensation lookup table, increasing the value of the current charge compensation control index by a preset fine-tuning step, and updating and storing the increased charge compensation control index in the charge compensation lookup table.

[0013] Furthermore, the method also includes: continuously monitoring the conduction duration of the programmable current mirror array; if the conduction duration exceeds a preset fuse threshold, forcibly turning off the programmable current mirror array and resetting the state of the clockless asynchronous combinational logic retrieval circuit.

[0014] To achieve the above objectives, the present invention also provides a MOS transistor gate charge balancing system with parasitic capacitance charge cancellation logic, comprising: A cascaded analog differentiating circuit is configured to continuously capture the second derivative characteristic signal of the gate voltage of a MOS transistor, which is attributed to the transient disturbance of parasitic capacitance, and generate a trigger pulse signal when the amplitude of the second derivative characteristic signal of the gate voltage exceeds a preset trigger threshold. An asynchronous quantization interface circuit is configured to convert the second derivative characteristic signal of the gate voltage into a digital quantized value in response to the trigger pulse signal; A clockless asynchronous combinational logic retrieval circuit is configured to retrieve the charge compensation control index corresponding to the digital quantization value based on the mapping relationship currently stored in the charge compensation lookup table; A programmable current mirror array is configured to decode the charge compensation control index and selectively turn on the internal current mirror branches according to the decoding result to apply quantized compensation charge to the gate node to counteract the parasitic capacitance transient disturbance. The waveform deviation integration circuit is configured to acquire the gate voltage waveform after the quantization compensation charge is applied, calculate the time-domain waveform deviation integral value of the gate voltage waveform relative to the preset reference voltage waveform after waveform alignment, and dynamically modify the mapping relationship in the charge compensation lookup table based on the time-domain waveform deviation integral value.

[0015] Furthermore, the system is also configured to perform the method as described in any of the further features of the method described above.

[0016] Compared with the prior art, the beneficial effects of the present invention are as follows: By employing a cascaded analog differentiating circuit to extract the second derivative characteristic signal of the gate voltage as a basis for disturbance detection, since the second derivative reflects the rate of change of voltage change, it has a high response amplitude for parasitic capacitance transient disturbances with steep rising or falling edges, but a small response for normal switching processes with relatively gentle changes. Therefore, it can effectively distinguish between parasitic capacitance transient disturbances and normal switching behavior, thus improving the accuracy and selectivity of disturbance detection.

[0017] By employing a clockless asynchronous combinational logic retrieval circuit for trigger quantization and table lookup operations, the entire processing link is independent of the system clock signal. Its delay depends only on the gate-level propagation delay of the combinational logic, eliminating the latency of waiting for the clock edge in the synchronous sampling architecture. Therefore, it can achieve a fast response from disturbance detection to compensation execution, reducing response latency.

[0018] By employing a programmable current mirror array and using the polarity control bit and amplitude control bit in the charge compensation control index for decoding control, it is possible to selectively conduct the source current branch used for current injection or the leakage current branch used for current extraction, and synthesize compensation charges of different magnitudes through weighted current mirror branches. Therefore, it is possible to accurately match parasitic capacitance disturbances of different directions and amplitudes, thereby improving the matching accuracy between compensation charges and disturbance characteristics.

[0019] By employing a waveform deviation integral circuit to obtain the compensated waveform and calculating the integral value of the time-domain waveform deviation from the reference waveform, the over-compensation or under-compensation state is determined based on the polarity of the deviation integral value, and the mapping relationship in the charge compensation lookup table is adjusted accordingly, forming a complete closed-loop feedback mechanism of "detection-quantification-compensation-evaluation-correction". This closed-loop mechanism adopts a cross-cycle adaptive adjustment strategy, performing compensation in the current cycle and evaluating the effect after the cycle ends. The evaluation result is used to correct the compensation parameters for the next cycle, utilizing the repeatability of power switch actions to achieve iterative optimization of the compensation parameters. Since the inherent characteristic of closed-loop negative feedback control is to minimize the system error, the compensation parameters can automatically converge to the optimal value of the current operating condition, realizing online adaptive optimization of the compensation parameters. This makes the detection, quantization, compensation, and correction links form an organic whole, producing an overall synergistic effect and overcoming the limitations of open-loop designs in existing technologies that cannot adapt to changes in operating conditions.

[0020] Furthermore, by using characteristic moment detection to achieve waveform alignment before deviation calculation, time offset errors caused by switching moment jitter are avoided; by using an integral method to accumulate the deviation rather than relying on single-point measurement, it has an average filtering effect on random noise, thus enhancing the robustness of feedback control. Attached Figure Description

[0021] Figure 1 A schematic flowchart illustrating a method for balancing the gate charge of a MOS transistor with parasitic capacitance charge cancellation logic, provided in an embodiment of the present invention. Figure 2 A structural block diagram of a MOS transistor gate charge balancing system with parasitic capacitance charge cancellation logic provided in an embodiment of the present invention; Figure 3 A schematic diagram of the circuit principle of the cascaded analog differentiating circuit provided in an embodiment of the present invention; Figure 4This is a schematic diagram of the structure of a programmable current mirror array provided in an embodiment of the present invention; Figure 5 A schematic diagram of the waveform deviation integration and lookup table correction process provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of the circuit principle of the feature time detector provided in an embodiment of the present invention.

[0022] Explanation of reference numerals in the attached figures: S1 is the step of continuously capturing the second derivative characteristic signal of the gate voltage using a cascaded analog differentiator circuit and generating a trigger pulse signal. S2 is the step of asynchronous quantization processing of the second derivative signal; S3 The steps for retrieving the charge compensation control index using a clockless asynchronous combinational logic retrieval circuit; S4 is the step of applying quantized compensation charge to the gate node using a programmable current mirror array; S5 The steps of calculating the time-domain waveform deviation integral value using a waveform deviation integrator circuit and dynamically modifying the charge compensation lookup table; S6 monitors the conduction duration and performs fuse protection procedures; 10 Cascaded analog differentiating circuit; 11 First-stage high-pass differentiating network; 12 Second-stage high-pass differentiating network; 13 Threshold comparator; 14 Full-wave rectifier circuit; 20 Asynchronous quantization interface circuit; 21 Asynchronous parallel comparator array; 22 Priority encoder; 23 Latch; 30 Clockless asynchronous combinational logic lookup circuit; 31 Combinational logic lookup table; 32 Charge-compensated lookup table memory; 40 Programmable current mirror array; 41 Polarity decoding circuit; 42 Amplitude decoding circuit; 43 Source current branch group; 44 Leakage current branch group; 45 First weighted current mirror branch; 46 Second weighted current mirror branch; 50 Waveform deviation integration circuit; 51 Sample and hold circuit; 52 Feature moment detector; 52a Feature moment detector using threshold voltage detection; 52b Feature moment detector using zero-crossing rate of change detection; 52c Feature moment detector using percentage threshold detection; 53 Difference calculation circuit; 54 Integrator; 55 Polarity determination circuit; 56 Step size adjustment circuit; 60 Fuse protection circuit; 61 On-time duration counter; 62 Fuse detection circuit; 63 Forced shutdown circuit; 64 Status reset circuit.

[0023] Among them, markings 21-23, 31-32, and 61-64 represent the functional sub-modules within each main module. Their structure and functions are described in detail in the main text of the manual and are not shown separately in the accompanying drawings. Detailed Implementation

[0024] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The following embodiments are used to illustrate the present invention, but are not intended to limit the scope of the present invention.

[0025] Example 1: See Figure 1 This embodiment provides a method for gate charge balancing of MOS transistors using parasitic capacitance charge cancellation logic. This embodiment focuses on describing the underlying processing logic of the technical solution and does not limit specific business application scenarios. The technical solution of this embodiment can be executed by an analog mixed-signal circuit including a cascaded analog differentiating circuit, an asynchronous quantization interface circuit, a clockless asynchronous combinational logic retrieval circuit, a programmable current mirror array, and a waveform deviation integration circuit.

[0026] In step S1, a cascaded analog differentiating circuit continuously captures the second derivative characteristic signal of the gate voltage attributable to the transient disturbance of parasitic capacitance in the MOS transistor gate voltage, and generates a trigger pulse signal when the amplitude of the second derivative characteristic signal exceeds a preset trigger threshold. Specifically, the input terminal of the cascaded analog differentiating circuit is connected to the gate node of the MOS transistor to sample the gate voltage signal in real time. The cascaded analog differentiating circuit contains multiple stages of series-connected high-pass differentiating networks. Each stage of the high-pass differentiating network is implemented by an RC network composed of resistors and capacitors, and its transfer function is approximately a first-order differential characteristic. The first-stage high-pass differentiating network receives the gate voltage signal, performs first-order differentiation on it, and outputs the first-order derivative signal of the gate voltage, which reflects the rate of change of the gate voltage. The second-stage high-pass differentiating network further differentiates the first-order derivative signal and outputs the second-order derivative signal of the gate voltage. Through the cascaded processing of the two stages of series-connected differentiating networks, the second derivative of the gate voltage with respect to time is obtained as the second derivative characteristic signal of the gate voltage. The technical principle behind using the second derivative for detection lies in the fact that the second derivative reflects the rate of change of voltage, essentially characterizing the acceleration characteristics of the signal. For parasitic capacitance transient disturbances, the mechanism involves a rapid jump in the switching node voltage coupled to the gate node via Miller capacitance. This coupling process is completed in an extremely short time, constituting a sudden, step-type disturbance. Its voltage change rate rises sharply from zero to a peak value within nanoseconds and then falls back down, resulting in a sharp, large-amplitude pulse response in the second derivative. In contrast, during normal switching, the output stage of the drive circuit charges or discharges the gate capacitor through a push-pull structure. This process is controlled by the time constant formed by the internal resistance of the drive circuit and the gate capacitor, resulting in a relatively smooth exponential rise or fall waveform. Its voltage change rate changes slowly over time, and the amplitude of the second derivative is smaller. From a signal morphology perspective, the rise time of parasitic capacitance disturbances is typically in the single-digit nanosecond range, while the rise time of normal switching processes is in the tens to hundreds of nanoseconds range, a difference of more than an order of magnitude, leading to a significant difference in the peak value of the second derivative. In an alternative embodiment, the cascaded analog differentiator circuit can also receive a drive command signal from the drive control logic. When the drive command signal indicates that the current period is within a normal switching window, the preset trigger threshold of the threshold comparator is dynamically increased or the detection function is temporarily disabled, thereby further enhancing the ability to distinguish between parasitic capacitance disturbances and normal switching behavior. Therefore, by detecting the amplitude of the second derivative signal, parasitic capacitance transient disturbances and normal switching behavior can be effectively distinguished. Subsequently, the threshold comparator compares the absolute value of the second derivative characteristic signal of the gate voltage with the preset trigger threshold. When the absolute value is greater than the preset trigger threshold, it is determined that a parasitic capacitance transient disturbance event has been detected, and the threshold comparator outputs a trigger pulse signal. The selection of the preset trigger threshold needs to comprehensively consider the balance between noise margin and detection sensitivity, and is usually set to 2 to 5 times the noise amplitude.To obtain the absolute value of the second derivative, a full-wave rectifier circuit can be used to rectify the second derivative signal, or an analog multiplier can be used to calculate the square of the second derivative signal and then perform a square root operation. Through these methods, accurate identification of parasitic capacitance transient disturbances is achieved, providing a reliable trigger signal for subsequent compensation processing.

[0027] In step S2, in response to the trigger pulse signal, the second derivative characteristic signal of the gate voltage is asynchronously quantized to generate a digital quantized value. Specifically, the asynchronous quantization interface circuit uses an asynchronous parallel comparator array as the quantization front end. When the trigger pulse signal is received, the asynchronous parallel comparator array is activated, simultaneously comparing the current second derivative characteristic signal of the gate voltage with multiple preset reference voltage thresholds. The asynchronous parallel comparator array contains multiple voltage comparators operating in parallel, each comparator corresponding to a reference voltage threshold. All comparators output the comparison results simultaneously, forming an initial quantization result in the form of a thermometer code. The thermometer code is then converted into binary code by a priority encoder as the digital quantized value. In one specific implementation, if a 4-bit quantization precision is used, the asynchronous parallel comparator array contains 15 comparators, corresponding to 16 quantization levels; if a 6-bit quantization precision is used, the asynchronous parallel comparator array contains 63 comparators, corresponding to 64 quantization levels. The choice of the number of quantization bits needs to comprehensively consider the compensation accuracy requirements and circuit complexity. A higher number of quantization bits means finer compensation control, but it also increases circuit area and power consumption. The key feature of asynchronous quantization is that it operates independently of the system clock signal. The quantization operation starts and completes immediately after the trigger pulse signal arrives, and its delay depends only on the gate-level propagation delay of the comparator and encoder, eliminating the latency of waiting for the clock edge in synchronous sampling architectures. The latch latches the digital quantized value under the control of the trigger pulse signal and initiates an asynchronous lookup operation on the subsequent charge compensation lookup table.

[0028] In step S3, a clockless asynchronous combinational logic lookup circuit retrieves the charge compensation control index corresponding to the digital quantization value based on the mapping relationship currently stored in the charge compensation lookup table. Specifically, the clockless asynchronous combinational logic lookup circuit internally includes a combinational logic lookup table and a charge compensation lookup table memory. The charge compensation lookup table memory pre-stores the mapping relationship from the digital quantization value to the charge compensation control index, which characterizes the amount of compensation charge required for gate voltage second derivative characteristic signals of different amplitudes. When the digital quantization value is output from the latch, the combinational logic lookup table uses the digital quantization value as the address input and directly reads the corresponding charge compensation control index from the charge compensation lookup table memory. Since the combinational logic lookup table is implemented using pure combinational logic and does not contain sequential logic elements, the delay from the input address to the output data depends only on the gate-level propagation delay of the combinational logic, which is typically on the order of nanoseconds. The charge compensation control index consists of two parts: a polarity control bit and an amplitude control bit. The polarity control bit is used to indicate the compensation direction, and the amplitude control bit is used to indicate the compensation magnitude. The core advantage of clockless asynchronous combinational logic lookup circuits lies in their zero clock cycle delay characteristic. The entire lookup table retrieval operation is completed independently of the system clock signal, shortening the response time from disturbance detection to compensation execution. In one specific implementation, the charge compensation lookup table memory is implemented using SRAM or a register array, supporting read and write update operations to dynamically modify the mapping relationship during subsequent closed-loop feedback. The initial mapping relationship in the charge compensation lookup table memory can be determined in the following ways: First, based on the nominal gate-drain capacitance, gate-source capacitance, and switching characteristic parameters in the power device datasheet, the estimated compensation charge corresponding to different disturbance amplitudes is theoretically calculated, and the calculation results are converted into charge compensation control indexes and written into the lookup table as initial values. Second, during the system power-on initialization phase or in a specific calibration mode, a test disturbance of known amplitude is applied, and the compensation effect is observed. The charge compensation control indexes corresponding to each address are iteratively adjusted until the target compensation accuracy is achieved, and the calibrated mapping relationship is then stored. Third, a default linear mapping relationship is used as the initial value, relying on the subsequent closed-loop feedback mechanism to gradually converge to the optimal configuration during actual operation.

[0029] In step S4, the charge compensation control index is decoded using a programmable current mirror array, and the internal current mirror branches are selectively turned on according to the decoding result to apply quantized compensation charge to the gate node to counteract parasitic capacitance transient disturbances. Specifically, the programmable current mirror array includes a polarity decoding circuit, an amplitude decoding circuit, a source current branch group, and a drain current branch group. The polarity decoding circuit decodes the polarity control bit in the charge compensation control index and selects to turn on the source current branch group or the drain current branch group according to the state of the polarity control bit. When the polarity control bit indicates that positive charge needs to be injected into the gate node, the polarity decoding circuit enables the source current branch group, which provides source current to the gate node to achieve positive charge injection; when the polarity control bit indicates that charge needs to be extracted from the gate node, the polarity decoding circuit enables the drain current branch group, which extracts current from the gate node to achieve charge extraction. The amplitude decoding circuit decodes the amplitude control bit in the charge compensation control index to control the selective turning on of the weighted current mirror branches. The programmable current mirror array has multiple pre-set weighted current mirror branches. The current capability of each current mirror branch is designed according to a binary weighting method, with the current capability ratio of the first weighted current mirror branch to the second weighted current mirror branch being 1:2:4:8. The amplitude decoding circuit controls the conduction or cutoff of the corresponding weighted current mirror branch according to each bit of the amplitude control bit. By combining different weighted current mirror branches, a compensation current covering a wide range can be synthesized. After the current mirror branch is turned on, a compensation current is applied to the gate node for a certain period of time. The compensation current charges or discharges the gate capacitor, thereby achieving charge compensation. The amount of compensation charge is determined by the product of the compensation current and the duration. Through the combination of polarity control and amplitude control, the programmable current mirror array can accurately match parasitic capacitance transient disturbances of different directions and amplitudes, improving the matching accuracy between compensation charge and disturbance characteristics.

[0030] In step S5, the gate voltage waveform after applying quantized compensation charge is obtained using a waveform deviation integration circuit. The characteristic moments of the gate voltage waveform are detected to achieve time-domain synchronization with a preset reference voltage waveform. The synchronized time-domain waveform deviation integral value is calculated, and the mapping relationship in the charge compensation lookup table is dynamically modified based on the time-domain waveform deviation integral value. See also... Figure 5Specifically, the waveform deviation integration circuit is functionally divided into four stages: triggering, acquisition, analysis, and adjustment, forming a complete closed-loop feedback mechanism. In the triggering stage, after the switching action of the MOS transistor is completed, the waveform deviation integration circuit receives the switching completion signal as the start trigger for deviation evaluation. The triggering timing is selected after the compensation charge is applied to ensure that the acquired waveform is the complete compensated waveform. In the acquisition stage, the sample-and-hold circuit samples the gate voltage waveform after the quantization compensation charge is applied. The sample-and-hold circuit continuously acquires gate voltage data points at fixed sampling intervals within a preset sampling time window. The start and end times of the sampling window are determined by a characteristic time detector. The characteristic time detector detects specific characteristic moments of the actual gate voltage waveform as synchronization reference points. These specific characteristic moments can be selected as the moment when the gate voltage reaches a preset threshold voltage, the moment when the gate voltage rate of change crosses zero, or the moment when the gate voltage reaches a steady-state value. Based on the synchronization reference point, a time window for integration calculation is determined, covering the main range affected by parasitic capacitance transient disturbances. In the analysis stage, the difference calculation circuit obtains reference data of the preset reference voltage waveform at the corresponding moment within the time window. The preset reference voltage waveform is stored in internal memory or generated in real time through theoretical calculation. The specific methods for generating the preset reference voltage waveform include: First, circuit simulation based on the ideal switching model of the power device to obtain the ideal waveform trajectory of the gate voltage under the influence of no parasitic capacitance disturbance, and storing the discretized simulation waveform data in the internal ROM; Second, during the system debugging or calibration phase, the power device is operated under low dV / dt conditions to make the Miller coupling effect negligible, and the gate voltage waveform at this time is collected as a reference and stored in the internal non-volatile memory; Third, for application scenarios where the gate voltage should be restored to the static drive level after compensation, the reference waveform can be simplified to a constant value, that is, the reference value is 0V or negative bias voltage when the low side is turned off, and the reference value is the drive voltage value when the high side is turned on. The difference calculation circuit subtracts the actual gate voltage data and the reference data point by point within the time window to obtain the waveform deviation value of each sampling point. The integrator performs integration calculation on the waveform deviation value of all sampling points within the time window to obtain the time domain waveform deviation integral value. The integration calculation can be implemented using an analog integrator or a digital accumulator. The integral value of the time-domain waveform deviation reflects the overall degree of deviation between the compensated actual waveform and the ideal reference waveform. During the adjustment phase, the polarity determination circuit determines the polarity of the integral value. If the integral value is negative, it indicates that the compensated actual waveform is generally lower than the reference waveform, indicating overcompensation and a large compensation charge. If the integral value is positive, it indicates that the compensated actual waveform is generally higher than the reference waveform, indicating undercompensation and a small compensation charge. The step size adjustment circuit adjusts the mapping relationship in the charge compensation lookup table based on the polarity determination result.If an overcompensated state exists, the step size adjustment circuit retrieves the charge compensation control index corresponding to the current digital quantization value from the charge compensation lookup table, reduces the value of the charge compensation control index by a preset fine-tuning step, and updates and stores the reduced charge compensation control index in the charge compensation lookup table. If an undercompensated state exists, the step size adjustment circuit increases the value of the charge compensation control index by a preset fine-tuning step, and updates and stores the increased charge compensation control index in the charge compensation lookup table. The preset fine-tuning step is usually set to one least significant bit to ensure the smoothness and convergence of the adjustment process and avoid oscillations caused by excessively large step sizes. In another implementation, the fine-tuning step size can be adaptively adjusted based on the absolute value of the integral value of the time-domain waveform deviation. When the deviation is large, a larger step size is used to accelerate convergence; when the deviation is small, a smaller step size is used for fine adjustment. Through the above iterative process of acquisition, analysis, and adjustment, the mapping relationship in the charge compensation lookup table gradually approaches the optimal configuration under the current operating condition, and the compensation parameters achieve online adaptive optimization. Because the inherent characteristic of closed-loop negative feedback control is to minimize system error, even if the initial mapping relationship deviates from the optimal value, after several switching cycles of iterative correction, the mapping relationship will automatically converge to the optimal value under the current operating condition. This closed-loop feedback mechanism adopts a cross-cycle adaptive adjustment strategy, that is, compensation operation is performed in the current switching cycle, the compensation effect is evaluated after the current cycle ends, and the evaluation result is used to correct the compensation parameters for the next cycle. Unlike traditional real-time closed-loop control within a cycle, the closed-loop characteristics of this scheme are reflected in the iterative optimization process of multiple switching cycles. Utilizing the repetitive nature of the switching actions of the power electronic system, the compensation parameters are gradually brought closer to the optimal value through a continuous "execution-evaluation-correction" iterative cycle. This cross-cycle closed-loop mechanism makes the detection, quantization, compensation, and correction links form an organic whole, generating an overall synergistic effect and overcoming the limitations of existing open-loop designs that cannot adapt to changes in operating conditions. Furthermore, by using characteristic moment detection to achieve waveform alignment before deviation calculation, time offset errors caused by switching moment jitter are avoided; by using an integral method to accumulate the deviation rather than relying on single-point measurement, it has an average filtering effect on random noise, thus enhancing the robustness of feedback control.

[0031] In step S6, the conduction duration of the programmable current mirror array is continuously monitored. If the conduction duration exceeds a preset fusing threshold, the programmable current mirror array is forcibly turned off, and the state of the clockless asynchronous combinational logic retrieval circuit is reset. See also Figure 2The fuse protection circuit 60 includes an on-duration counter 61, a fuse judgment circuit 62, a forced shutdown circuit 63, and a state reset circuit 64. Specifically, the on-duration counter 61 starts counting when any current mirror branch of the programmable current mirror array 40 is turned on. The counter uses the system clock or a dedicated high-frequency clock as the counting time base, and the count value increments by one every clock cycle. When all current mirror branches are turned off, the on-duration counter 61 is reset to zero. The preset fuse threshold is determined based on the thermal capacity of the power MOSFET, the safe operating area (SOA) limit, and circuit reliability requirements. The fuse threshold is converted into a counting threshold value. When the count value of the on-duration counter 61 reaches or exceeds the counting threshold value, the fuse judgment circuit 62 outputs a fuse trigger signal. The fuse trigger signal drives the forced shutdown circuit 63, which pulls down the gate control voltage of all current mirror branches of the programmable current mirror array 40 to the shutdown level, cutting off all compensation current. Simultaneously, the fuse trigger signal drives the state reset circuit 64 to send a reset signal to the clockless asynchronous combinational logic retrieval circuit 30, resetting sequential logic elements such as latches and counters to their initial states. After the fuse protection is triggered, the circuit enters a protection lockout state, and can only resume normal operation after receiving an external unlock signal or the system is powered on again. In another embodiment, the fuse protection can also be configured as a soft reset mode, automatically unlocking and resuming normal operation after a preset cooling delay following fuse triggering. Through the fuse protection mechanism, damage to power devices and drive circuits caused by prolonged conduction of the current mirror branch due to faults is effectively prevented, improving the safety and reliability of the system.

[0032] Combining steps S1 to S6 above, the MOS transistor gate charge balancing method with parasitic capacitance charge cancellation logic in this embodiment forms a complete signal processing closed loop encompassing detection, quantization, compensation, evaluation, correction, and protection. The second-order derivative characteristic signal extracted by the cascaded analog differentiating circuit accurately identifies transient disturbances in parasitic capacitance; the asynchronous quantization interface circuit quickly converts the analog signal into a digital quantized value; the clockless asynchronous combinational logic retrieval circuit retrieves compensation parameters with zero clock cycle delay; the programmable current mirror array precisely applies compensation charge; and the waveform deviation integration circuit evaluates the compensation effect and dynamically optimizes the lookup table parameters. The coordinated operation of these components achieves active balancing control of the MOS transistor gate charge.

[0033] Example 2: Based on the general method provided in Embodiment 1 above, this embodiment provides a specific application scenario: a power MOSFET half-bridge drive application. See also... Figure 1 and Figure 5In this scenario, the above method is applied to the gate drive circuit of a half-bridge power stage composed of a high-side MOSFET and a low-side MOSFET to solve the problem of false turn-on of the low-side MOSFET caused by Miller capacitance coupling when the high-side MOSFET is turned off in the half-bridge topology. In the half-bridge topology, the drains or sources of the high-side MOSFET and the low-side MOSFET are connected to the switching node. When the high-side MOSFET is turned off rapidly, the switching node voltage rises rapidly. This voltage change is coupled to the gate of the low-side MOSFET through the gate-drain parasitic capacitance, i.e., the Miller capacitance, causing a positive transient disturbance in the gate voltage of the low-side MOSFET. If the amplitude of this disturbance exceeds the threshold voltage of the low-side MOSFET, it will cause the low-side MOSFET to falsely turn on, thereby causing a shoot-through short circuit in the bridge arm, and in severe cases, damaging the power device.

[0034] This embodiment uses the low-side MOSFET as the protected object for detailed description. It is assumed that the half-bridge drive circuit uses a power MOSFET with a withstand voltage of 100V, the low-side MOSFET has a gate-drain capacitance of 100pF, a gate-source capacitance of 1000pF, a threshold voltage of 3V, and a drive voltage of 12V. The input of the cascaded analog differentiating circuit is connected to the gate node of the low-side MOSFET to monitor the gate voltage signal in real time.

[0035] In step S1, when the high-side MOSFET is rapidly turned off within 15 ns, the switching node voltage jumps from near ground potential to the bus voltage in a very short time. Assuming the bus voltage is 48V, the voltage change rate dV / dt is approximately 3.2V / ns. This voltage change is coupled to the gate of the low-side MOSFET through Miller capacitance, causing a transient disturbance in the gate voltage. In the cascaded analog differentiating circuit, the first-stage high-pass differentiating network uses an RC network with a resistance of 1kΩ and a capacitance of 10pF, with a time constant of 10ns; the second-stage high-pass differentiating network uses the same RC parameter configuration. When the gate voltage disturbance caused by Miller coupling arrives, the second derivative signal exhibits a pulse waveform with a large amplitude due to the steep rise of the disturbance. The preset trigger threshold of the threshold comparator is set to 0.2V, which is selected by comprehensively considering the inherent noise level of the circuit and the detection sensitivity. When the absolute value of the second derivative signal exceeds 0.2V, the threshold comparator outputs a trigger pulse signal, indicating that a Miller coupling disturbance event has been detected. In this application scenario, the falling edge of the drive signal during the normal turn-off process is on the order of 100ns, and its second derivative amplitude is much smaller than that of the second derivative amplitude of the Miller coupling disturbance, thus effectively distinguishing the two.

[0036] In step S2, the asynchronous quantization interface circuit quantizes the second derivative signal at the current moment. This embodiment uses 6-bit quantization precision. The asynchronous parallel comparator array contains 63 comparators, with a reference voltage covering a range from 0V to 0.63V. Each comparator corresponds to a quantization step size of 10mV. Assuming the current second derivative signal amplitude is 0.35V, 35 comparators in the thermometer code output will be high-level. The priority encoder converts the thermometer code into a 6-bit binary quantized value of 100011, corresponding to the decimal value 35. The entire asynchronous quantization process is completed within approximately 8ns after the trigger pulse signal arrives. This delay includes only the comparator propagation delay of approximately 5ns and the priority encoder propagation delay of approximately 3ns. Regarding the relationship between the detection link delay and the effectiveness of compensation, the following technical principle needs to be explained: The total link delay from the second derivative detection to the application of the compensation current is approximately 40ns to 60ns. This delay seems to be greater than the duration of the Miller coupling disturbance, but the compensation is still effective because of the capacitive energy storage characteristics of the gate node. Specifically, when the Miller capacitance couples charge into the gate node, this charge is stored in the gate-source capacitance, causing a shift in the gate voltage. This shift does not dissipate on its own but persists until it is absorbed or compensated by external circuitry. The goal of compensation is not to cancel out the disturbance at the instant it occurs, but to achieve charge balance before the gate voltage shift causes device malfunction. The criterion for device malfunction is that the gate voltage exceeds a threshold voltage for a duration sufficient to allow the conductive channel to fully form. For a typical power MOSFET, this response hysteresis time is on the order of 50ns to 100ns. Therefore, as long as the total delay of the detection link is less than this response hysteresis time, the compensation charge can pull the gate voltage back to a safe range before the device malfunctions, achieving effective protection.

[0037] In step S3, the clockless asynchronous combinational logic lookup circuit uses the digital quantized value 100011 as the address input to read the corresponding charge compensation control index from the charge compensation lookup table memory. The charge compensation lookup table memory is implemented using a 64×7-bit SRAM array, storing the charge compensation control indices corresponding to 64 addresses. Assuming that in the initial state, the charge compensation control index corresponding to address 35 is 1101010, where the highest bit 1 is the polarity control bit indicating the current extraction direction, and the lower 6 bits 101010 are the amplitude control bits corresponding to the decimal value 42. The lookup delay of the combinational logic lookup table is approximately 3ns, completed independently of the system clock.

[0038] In step S4, the programmable current mirror array performs decoding and compensation according to the charge compensation control index 1101010. The polarity decoding circuit resolves polarity control bit 1, enabling the leakage current branch group, preparing to extract charge from the gate node to offset the positive charge injected by Miller coupling. The amplitude decoding circuit resolves amplitude control bit 101010, controlling the selective conduction of the weighted current mirror branches. The programmable current mirror array in this embodiment includes 6 weighted current mirror branches with current capabilities of 1mA, 2mA, 4mA, 8mA, 16mA, and 32mA, arranged in binary weighted order. The amplitude control bit 101010 corresponds to bits 1, 3, and 5 being high in its binary representation, thus enabling the conduction of three current mirror branches with current capabilities of 2mA, 8mA, and 32mA, resulting in a total compensation current of 42mA. The duration of the compensation current is determined by the trigger pulse width. Assuming a duration of 20 ns, the programmable current mirror array multiplies the compensation current value by the duration to obtain an applied compensation charge of approximately 840 fC. Regarding the relationship between this compensation charge and the total Miller coupling charge: a 48V change in the switching node voltage coupled through a 100pF Miller capacitor generates a total coupling charge of approximately 4800 fC, but not all of this total charge remains at the gate node. During the low-side MOSFET turn-off period, the pull-down output stage of the drive circuit remains on, and its equivalent output impedance is typically in the single-digit ohm range. Most of the transient current generated by Miller capacitor coupling is absorbed by the low-impedance output stage of the drive circuit and discharged to ground. Only a small portion of the charge remains on the gate-source capacitance before the drive circuit responds, forming a net disturbance offset in the gate voltage. The proportion of this residual charge depends on the voltage division relationship between the drive circuit output impedance and the gate equivalent impedance, as well as the ratio of the disturbance rise time to the drive circuit response time. Under the parameter configuration of this embodiment, the net disturbance charge remaining on the gate is approximately one-fifth to one-sixth of the total coupled charge, i.e., on the order of 800fC to 1000fC. Therefore, the initial compensation charge setting of 840fC is reasonable. This compensation charge is drawn from the low-side MOSFET gate to offset the net disturbance charge remaining after Miller coupling injection, restoring the gate voltage to a safe level.

[0039] In step S5, the waveform deviation integration circuit initiates the compensation effect evaluation process after the switching action is completed. During the triggering phase, after the high-side MOSFET turn-off process ends and the switching node voltage stabilizes, the waveform deviation integration circuit receives the evaluation start signal. During the acquisition phase, the sample-and-hold circuit continuously acquires 100 gate voltage data points within a 200ns time window with a 2ns sampling interval. A feature moment detector detects the moment when the gate voltage signal drops from the disturbance peak to 50% of the steady-state value as the synchronization reference point. During the analysis phase, the difference calculation circuit reads the preset reference voltage waveform data from the internal memory. This reference waveform is a constant value where the gate voltage remains near 0V under ideal conditions. Assuming that the average value of the acquired actual gate voltage waveform within the time window is 0.15V, which is higher than the reference value of 0V, the difference calculation circuit calculates the deviation value of each sampling point and sends it to the integrator. The integrator accumulates the deviation values ​​of the 100 sampling points to obtain a positive time-domain waveform deviation integral value of 15V·ns. During the adjustment phase, the polarity determination circuit determines that the integral value of the time-domain waveform deviation is positive, indicating that there is currently an undercompensation state. That is, the compensation charge of 840fC is insufficient to offset the charge injected by Miller coupling, and the gate voltage still has a residual rise. The step size adjustment circuit increases the value of the charge compensation control index 1101010 corresponding to address 35 by a preset fine-tuning step size of 1 least significant bit, updating it to the decimal value 43 corresponding to 1101011, and writes the updated charge compensation control index back to address 35 of the charge compensation lookup table memory.

[0040] In the next switching cycle, when a Miller coupling disturbance of the same amplitude occurs again, step S1 detects the second derivative signal, step S2 quantizes it to obtain the same digital quantization value 100011, step S3 looks up the updated charge compensation control index 1101011, and step S4 decodes it to obtain four current mirror branches with conduction current capabilities of 1mA, 2mA, 8mA, and 32mA, synthesizing a total compensation current of 43mA and applying a compensation charge of 860fC. Step S5 re-evaluates the compensation effect. If the integral value of the time-domain waveform deviation is still positive but the absolute value decreases, it indicates that the compensation amount is closer to the optimal value, and fine-tuning continues. After several switching cycles of iterative correction, the charge compensation control index gradually approaches the optimal value that makes the integral value of the time-domain waveform deviation approach zero.

[0041] Assuming that after 50 switching cycles of closed-loop iteration, the charge compensation control index corresponding to address 35 stabilizes at 1110010, corresponding to a combined compensation current of 50mA and a compensation charge of 1000fC. At this point, the integral value of the time-domain waveform deviation fluctuates slightly around zero, indicating that the compensation parameters have converged to the optimal configuration for the current operating condition. If the system operating condition changes, for example, an increase in load current leading to an increase in the rate of change of switching node voltage dV / dt, and an enhanced Miller coupling effect, the integral value of the time-domain waveform deviation will deviate from zero again. The closed-loop feedback mechanism will automatically initiate a new round of parameter adjustment, enabling the compensation amount to track changes in operating condition and achieve adaptive optimization.

[0042] The synergistic effect of this closed-loop feedback mechanism is reflected in the following aspects: In an open-loop compensation system lacking closed-loop feedback, the compensation parameters are fixed during the design phase and cannot adapt to changes in operating conditions caused by factors such as device aging, temperature drift, and load changes, leading to the accumulation and deterioration of overcompensation or undercompensation problems over time; while the closed-loop feedback mechanism in this embodiment forms an organic whole between the detection link, the compensation link, and the evaluation link. The disturbance amplitude information provided by the detection link drives the execution of the compensation link, and the deviation information provided by the evaluation link provides feedback to correct the compensation parameters. The three work together to form a dynamic balance, and the system always maintains the optimal compensation effect under changing operating conditions, producing an overall synergistic gain effect far exceeding the simple superposition of each link.

[0043] In step S6, the conduction duration of the programmable current mirror array is continuously monitored. If the conduction duration exceeds a preset fuse threshold, the programmable current mirror array is forcibly turned off, and the state of the clockless asynchronous combinational logic retrieval circuit is reset. Specifically, the conduction duration counter starts counting when the current mirror branch is on, increments by one every clock cycle, and is reset to zero when the current mirror branch is off. The preset fuse threshold is set to 200ns, which is determined based on the thermal capacity and safe operating area limitations of the power MOSFET. If the count value of the conduction duration counter exceeds the count threshold corresponding to the fuse threshold, an abnormal state is determined, possibly due to a circuit fault preventing the current mirror branch from turning off normally. At this time, the fuse protection circuit forcibly turns off all current mirror branches of the programmable current mirror array and sends a reset signal to the clockless asynchronous combinational logic retrieval circuit, resetting the circuit state to the initial safe state. Through the fuse protection mechanism, potential damage to the power MOSFET gate caused by prolonged conduction of the current mirror branch is avoided, improving the reliability of the system.

[0044] In other implementations, the aforementioned power MOSFET half-bridge drive scenario can also be extended to a full-bridge drive topology. In a full-bridge drive topology, the four power MOSFETs are divided into two groups of half-bridges, and each group of half-bridges can be protected using the gate charge balancing method described in this embodiment. Furthermore, the method of this embodiment is also applicable to IGBT drive scenarios and drive scenarios for wide-bandgap semiconductor devices such as GaN HEMTs and SiC MOSFETs. These devices also suffer from gate voltage disturbances caused by Miller capacitance coupling. By adjusting the RC time constant and preset trigger threshold of the cascaded analog differentiating circuit to match the switching characteristics of different devices, effective protection can be achieved.

[0045] Based on the above embodiments, the specific implementation method of continuously capturing the second derivative characteristic signal of the gate voltage using a cascaded analog differentiating circuit is as follows. See Figure 3 In cascaded analog differentiating circuits, multi-stage series high-pass differentiating networks are implemented using two- or three-stage cascaded RC high-pass networks. Each stage of the RC high-pass network consists of a resistor and a capacitor connected in series. One end of the capacitor serves as the input, receiving the signal from the previous stage, while the other end of the resistor serves as the output, outputting the differentiated signal. For a two-stage series configuration, the first-stage RC high-pass network performs a first-order differentiation on the gate voltage signal, outputting the voltage change rate signal; the second-stage RC high-pass network performs a second-order differentiation on the first-order differentiated signal, outputting the voltage change rate signal, i.e., the second derivative signal. The time constant τ=RC of each stage of the RC high-pass network needs to be matched with the frequency characteristics of the disturbance being detected. For power device applications with switching periods on the order of 100ns, the time constant is typically set in the range of 10ns to 100ns. A smaller time constant can detect higher-frequency disturbances but will amplify high-frequency noise; a larger time constant has a better suppression effect on high-frequency noise but reduces the sensitivity to disturbances. In a preferred embodiment, the time constant of the first-stage RC high-pass network is set to 20 ns, and the time constant of the second-stage RC high-pass network is set to 15 ns. The absolute value of the second derivative is obtained through a full-wave rectifier circuit 14, which flips the negative half-cycle of the second derivative signal to the positive half-cycle and outputs the absolute value of the second derivative signal for subsequent threshold comparator 13 to make threshold judgment.

[0046] Furthermore, the specific implementation of retrieving the charge compensation control index using a clockless asynchronous combinational logic retrieval circuit is as follows. The asynchronous parallel comparator array adopts a parallel comparison architecture of Flash ADC, containing 2 n-1 voltage comparators, where n is the number of quantization bits. Taking 6-bit quantization precision as an example, the asynchronous parallel comparator array contains 63 comparators. The positive input of each comparator is connected to the second derivative characteristic signal of the gate voltage, and the negative input is connected to different taps of the reference voltage divider network. The reference voltage divider network consists of 64 equivalent resistors connected in series. The two ends of the series resistor chain are connected to the upper and lower limits of the reference voltage, respectively, and the taps of each resistor node provide a uniformly distributed reference voltage. When the trigger pulse signal arrives, the latch synchronously latches the output states of the 63 comparators to form a thermometer code. The thermometer code encoder converts the thermometer code into a 6-bit binary code, which is the digital quantization value. The triggering of the latch is controlled by the trigger pulse signal to ensure precise synchronization between the quantization time and the disturbance detection time. The asynchronous polling operation is implemented through pure combinational logic. The digital quantization value is directly used as the address input of the charge compensation lookup table memory, and the memory outputs the charge compensation control index stored at the corresponding address. The entire process does not depend on the system clock signal.

[0047] Furthermore, the specific implementation method of decoding the charge compensation control index using a programmable current mirror array is as follows. See [link to documentation]. Figure 4 The programmable current mirror array has at least two pre-set weighted current mirror branches, each configured to perform current injection or current extraction operations based on control signals. The charge compensation control index consists of two parts: a polarity control bit and an amplitude control bit. The polarity control bit is a 1-bit binary number. When the polarity control bit is logic 0, the polarity decoding circuit enables the power current branch group to selectively conduct the current mirror branch used for current injection; when the polarity control bit is logic 1, the polarity decoding circuit enables the leakage current branch group to selectively conduct the current mirror branch used for current extraction. The amplitude control bit is a multi-bit binary number, with each bit controlling the conduction state of one weighted current mirror branch. The current capability of the weighted current mirror branches is designed according to a binary weighting ratio of 1:2:4:8, implemented through the MOSFET channel width-to-length ratio (W / L). The channel width-to-length ratio of the first weighted current mirror branch is designed as a reference value, the channel width-to-length ratio of the second weighted current mirror branch is twice the reference value, and so on. The amplitude decoding circuit controls the gate control voltage of the corresponding weighted current mirror branch according to the high and low level states of each bit of the amplitude control, enabling or disabling the branch. The output currents of each weighted current mirror branch are superimposed at a common output node to synthesize a quantized compensation current corresponding to the charge compensation control index. The compensation current is applied to the gate of the MOS transistor through the output terminal connected to the gate node, charging or discharging the gate capacitor to achieve charge compensation.

[0048] Further, the specific implementation of calculating the integral value of the time-domain waveform deviation of the gate voltage waveform relative to the preset reference voltage waveform is as follows. After the switching action of the MOS transistor is completed, a characteristic moment detector detects a specific characteristic moment of the actual gate voltage waveform as a synchronization reference point. The selection of the specific characteristic moment includes the moment when the gate voltage reaches a preset threshold voltage, the moment when the gate voltage rate of change crosses zero, or the moment when the gate voltage reaches a percentage threshold of the steady-state value. In one embodiment, the characteristic moment detector includes a voltage comparator and an edge detection circuit. The voltage comparator compares the actual gate voltage with the preset threshold voltage, and the edge detection circuit captures the rising or falling edge of the comparator output as the synchronization reference point. A time window for integration calculation is determined based on the synchronization reference point. The start time of the time window is a preset offset before the synchronization reference point, and the end time of the time window is a preset offset after the synchronization reference point. The preset reference voltage waveform is stored in an internal ROM or RAM, representing the time-domain characteristics of the gate voltage under ideal compensation conditions. At each sampling moment within the time window, the difference calculation circuit obtains corresponding data from the actual waveform sample value and the stored reference waveform value, respectively, and calculates the difference between the two. The integrator accumulates all differences within the time window. In the analog implementation, an operational amplifier integrator circuit is used; in the digital implementation, a digital accumulator is used. The final output is the integral value of the time-domain waveform deviation. See also... Figure 6 The specific circuit implementation of the characteristic moment detector is as follows: For the detection method where the gate voltage reaches a preset threshold voltage, the characteristic moment detector 52a includes a voltage comparator. Its non-inverting input is connected to the output of the sample-and-hold circuit, and its inverting input is connected to the preset threshold voltage source. When the sampled voltage rises or falls across the threshold voltage, the comparator output jumps. This jump edge is captured by the edge detection circuit and generates a synchronization flag pulse. For the detection method where the gate voltage change rate crosses zero, the characteristic moment detector 52b includes a differentiating circuit and a zero-crossing comparator. The differentiating circuit performs a first-order derivative on the sampled voltage to obtain the change rate signal. The zero-crossing comparator detects the moment when the change rate signal crosses zero level as a synchronization reference. For the detection method where the gate voltage reaches a steady-state percentage threshold, the characteristic moment detector 52c includes a peak detection circuit, a voltage divider network, and a voltage comparator. The peak detection circuit captures the peak value of the sampled voltage, the voltage divider network generates a preset percentage of the peak value as a dynamic threshold, and the voltage comparator detects the moment when the sampled voltage reaches this dynamic threshold.

[0049] Further, the specific implementation of dynamically modifying the mapping relationship in the charge compensation lookup table based on the integral value of the time-domain waveform deviation is as follows: The polarity determination circuit determines the polarity of the integral value of the time-domain waveform deviation. In the analog implementation, a sign comparator determines the sign of the integral value relative to the zero reference; in the digital implementation, the polarity is determined by detecting the sign bit of the integral value. If the polarity indicates an overcompensated state (i.e., a negative integral value of the time-domain waveform deviation indicates that the actual waveform is lower than the reference waveform), the step size adjustment circuit retrieves the current charge compensation control index corresponding to the current digital quantization value in the charge compensation lookup table and reduces the value of the current charge compensation control index by a preset fine-tuning step size. A typical value for the preset fine-tuning step size is one least significant bit (LSB) to ensure the stability of the adjustment process. The reduced charge compensation control index is updated and stored at the corresponding address in the charge compensation lookup table memory via a write interface. If the polarity indicates an undercompensated state (i.e., a positive integral value of the time-domain waveform deviation indicates that the actual waveform is higher than the reference waveform), the step size adjustment circuit increases the value of the current charge compensation control index by the preset fine-tuning step size and updates and stores the increased charge compensation control index in the charge compensation lookup table. In another implementation, the fine-tuning step size can be adaptively adjusted based on the absolute value of the integral of the time-domain waveform deviation. Multiple step size levels are set: a large step size is used to accelerate convergence when the absolute value is greater than a first threshold; a medium step size is used when the absolute value is between the first and second thresholds; and a small step size is used for fine adjustment when the absolute value is less than the second threshold. The lookup table update operation is performed after the current switching cycle ends, and the updated charge compensation control index takes effect in the next switching cycle. Through continuous closed-loop iterative correction, the charge compensation parameters gradually converge to the optimal value that makes the integral of the time-domain waveform deviation approach zero.

[0050] Furthermore, the method also includes the following implementation of the fuse protection mechanism: A conduction duration counter starts counting when any current mirror branch of the programmable current mirror array is turned on. The counter uses the system clock or a dedicated high-frequency clock as its counting time base, and the count value increments by one each clock cycle. When all current mirror branches are turned off, the conduction duration counter is reset to zero. A preset fuse threshold is determined based on the thermal capacity of the power MOSFET, the safe operating area (SOA) limit, and circuit reliability requirements. The fuse threshold is converted into a counting threshold value. When the count value of the conduction duration counter reaches or exceeds the counting threshold value, the fuse judgment circuit outputs a fuse trigger signal. The fuse trigger signal drives a forced shutdown circuit, which pulls down the gate control voltage of all current mirror branches of the programmable current mirror array to the shutdown level, cutting off all compensation currents. Simultaneously, the fuse trigger signal drives a state reset circuit, sending a reset signal to the clockless asynchronous combinational logic retrieval circuit to reset the latches, counters, and other sequential logic elements to their initial states. After the fuse protection is triggered, the circuit enters a protection lockout state and will not resume normal operation until an external unlocking signal is received or the system is powered on again. In another implementation, the fuse protection can also be configured as a soft reset mode, automatically unlocking and resuming normal operation after a preset cooling delay following fuse triggering. This fuse protection mechanism effectively prevents damage to power devices and drive circuits caused by prolonged conduction of the current mirror branch due to a fault, improving the safety and reliability of the system.

[0051] Example 3: See Figure 2 This embodiment also provides a MOS transistor gate charge balancing system with parasitic capacitance charge cancellation logic, used to execute the above-mentioned MOS transistor gate charge balancing method with parasitic capacitance charge cancellation logic. The system includes a cascaded analog differentiating circuit 10, an asynchronous quantization interface circuit 20, a clockless asynchronous combinational logic retrieval circuit 30, a programmable current mirror array 40, and a waveform deviation integration circuit 50. The modules interact with each other through preset signal channels.

[0052] The cascaded analog differentiating circuit 10 is used to perform the function corresponding to step S1 in the above method. Specifically, the cascaded analog differentiating circuit 10 is configured to continuously capture the second derivative characteristic signal of the gate voltage attributable to the transient disturbance of parasitic capacitance in the gate voltage of the MOS transistor, and generate a trigger pulse signal when the amplitude of the second derivative characteristic signal of the gate voltage exceeds a preset trigger threshold. The input terminal of the cascaded analog differentiating circuit 10 is connected to the gate node of the MOS transistor, and the output terminal is connected to the input terminal of the asynchronous quantization interface circuit 20. In one implementation, the cascaded analog differentiating circuit 10 includes a first-stage high-pass differentiating network 11, a second-stage high-pass differentiating network 12, a full-wave rectifier circuit 14, and a threshold comparator 13. The first-stage high-pass differentiating network 11 receives the gate voltage signal and outputs a first-order differential signal, and the second-stage high-pass differentiating network 12 receives the first-order differential signal and outputs a second-order differential signal, i.e., the second derivative characteristic signal of the gate voltage. The full-wave rectifier circuit 14 performs full-wave rectification on the second-derivative signal and outputs the absolute value of the second-derivative signal. The threshold comparator 13 compares the absolute value signal output by the full-wave rectifier circuit 14 with a preset trigger threshold. When the absolute value exceeds the threshold, it outputs a trigger pulse signal.

[0053] The asynchronous quantization interface circuit 20 performs the function corresponding to step S2 in the above method. Specifically, the asynchronous quantization interface circuit 20 is configured to convert the second derivative characteristic signal of the gate voltage into a digital quantized value in response to a trigger pulse signal. The signal input terminal of the asynchronous quantization interface circuit 20 is connected to the second derivative signal output terminal of the cascaded analog differentiator circuit 10, the trigger input terminal is connected to the trigger pulse output terminal of the threshold comparator 13, and the digital output terminal is connected to the address input terminal of the clockless asynchronous combinational logic retrieval circuit 30. In one implementation, the asynchronous quantization interface circuit 20 includes an asynchronous parallel comparator array 21, a priority encoder 22, and a latch 23. The asynchronous parallel comparator array 21 compares the second derivative characteristic signal of the gate voltage with multiple reference voltage thresholds in parallel and outputs the comparison result in the form of thermometer code. The priority encoder 22 converts the thermometer code into a binary encoded digital quantized value. The latch 23 latches the digital quantized value under the control of the trigger pulse signal and outputs the latched digital quantized value to the clockless asynchronous combinational logic retrieval circuit 30.

[0054] The clockless asynchronous combinational logic retrieval circuit 30 is used to perform the function corresponding to step S3 in the above method. Specifically, the clockless asynchronous combinational logic retrieval circuit 30 is configured to retrieve the charge compensation control index corresponding to the digital quantization value based on the mapping relationship currently stored in the charge compensation lookup table. The address input terminal of the clockless asynchronous combinational logic retrieval circuit 30 is connected to the digital output terminal of the asynchronous quantization interface circuit 20, the control index output terminal is connected to the control input terminal of the programmable current mirror array 40, and the lookup table update input terminal is connected to the feedback output terminal of the waveform deviation integration circuit 50. In one implementation, the clockless asynchronous combinational logic retrieval circuit 30 includes a combinational logic lookup table 31 and a charge compensation lookup table memory 32. The combinational logic lookup table 31 receives the digital quantization value as an address and reads the corresponding charge compensation control index from the charge compensation lookup table memory 32. The charge compensation lookup table memory 32 is implemented using SRAM or a register array and supports read operations and feedback-based write update operations.

[0055] The programmable current mirror array 40 is used to perform the function corresponding to step S4 in the above method. Specifically, the programmable current mirror array 40 is configured to decode the charge compensation control index and selectively turn on the internal current mirror branches according to the decoding result, applying quantized compensation charge to the gate node to offset parasitic capacitance transient disturbances. The control input terminal of the programmable current mirror array 40 is connected to the control index output terminal of the clockless asynchronous combinational logic retrieval circuit 30, and the current output terminal is connected to the gate node of the MOS transistor. In one implementation, the programmable current mirror array 40 includes a polarity decoding circuit 41, an amplitude decoding circuit 42, a source current branch group 43, a drain current branch group 44, and multiple weighted current mirror branches. The polarity decoding circuit 41 decodes the polarity control bit in the charge compensation control index, selecting to enable the source current branch group 43 or the drain current branch group 44. The amplitude decoding circuit 42 decodes the amplitude control bit in the charge compensation control index, controlling the selective turn-on of the first weighted current mirror branch 45, the second weighted current mirror branch 46, and other weighted current mirror branches. The currents of each weighted current mirror branch are superimposed at the output node to form a quantized compensation current, which is then applied to the gate node.

[0056] The waveform deviation integration circuit 50 is used to perform the function corresponding to step S5 in the above method. Specifically, the waveform deviation integration circuit 50 is configured to acquire the gate voltage waveform after applying quantization compensation charge, calculate the time-domain waveform deviation integral value of the gate voltage waveform relative to the preset reference voltage waveform after waveform alignment, and dynamically modify the mapping relationship in the charge compensation lookup table based on the time-domain waveform deviation integral value. The waveform sampling input terminal of the waveform deviation integration circuit 50 is connected to the gate node of the MOS transistor, and the feedback output terminal is connected to the lookup table update input terminal of the clockless asynchronous combinational logic lookup circuit 30. In one implementation, the waveform deviation integration circuit 50 includes a sample-and-hold circuit 51, a feature moment detector 52, a difference calculation circuit 53, an integrator 54, a polarity determination circuit 55, and a step size adjustment circuit 56. The sample-and-hold circuit 51 samples the compensated gate voltage waveform. The feature moment detector 52 detects the feature moment of the gate voltage waveform to achieve time-domain synchronization with the preset reference voltage waveform. The difference calculation circuit 53 calculates the difference between the actual waveform and the reference waveform. The integrator 54 integrates the difference to obtain the time-domain waveform deviation integral value. The polarity determination circuit 55 determines the polarity of the integral value to identify over-compensation or under-compensation. The step size adjustment circuit 56 generates a lookup table update instruction based on the polarity determination result and sends it to the clockless asynchronous combinational logic retrieval circuit 30 through the feedback channel to dynamically update the mapping relationship in the charge compensation lookup table memory 32.

[0057] In the above system architecture, the signal flow propagates along the following path: the gate voltage signal is input from the gate node of the MOS transistor into the cascaded analog differentiating circuit 10, and after two stages of differentiating processing, it outputs a second-order derivative characteristic signal; the second-order derivative characteristic signal enters the asynchronous quantization interface circuit 20 and is quantized into a digital quantized value; the digital quantized value is used as an address input to the clockless asynchronous combinational logic retrieval circuit 30 to retrieve the charge compensation control index; the charge compensation control index drives the programmable current mirror array 40 to apply compensation charge to the gate node; the compensated gate voltage waveform is acquired and analyzed by the waveform deviation integrator circuit 50, and the generated lookup table update instruction is fed back to the clockless asynchronous combinational logic retrieval circuit 30 to update the mapping parameters in the charge compensation lookup table memory 32. This signal flow forms a complete closed-loop loop from detection to compensation to feedback correction, and the various modules cooperate to achieve active balance control of the gate charge.

[0058] In practical implementation, the above functional modules can be implemented using analog circuits or analog mixed-signal circuits, or partially using digital circuits. The cascaded analog differentiator circuit 10 is typically implemented using pure analog circuits to ensure the continuity and real-time performance of signal processing. The asynchronous quantization interface circuit 20 uses a mixed-signal architecture of analog comparator array and digital encoder. The digital processing parts of the clockless asynchronous combinational logic retrieval circuit 30 and the waveform deviation integration circuit 50 can be integrated into an FPGA or ASIC. The programmable current mirror array 40 is implemented using analog current mirror circuits in conjunction with digital control logic.

[0059] In summary, the MOS transistor gate charge balancing method and system with parasitic capacitance charge cancellation logic provided in this embodiment can achieve the following technical effects: By employing a cascaded analog differentiating circuit to extract the second derivative characteristic signal of the gate voltage as the basis for disturbance detection, this method effectively distinguishes between parasitic capacitance transient disturbances and normal switching behavior. The second derivative reflects the rate of change of voltage change, exhibiting a high response amplitude for transient disturbances with steep rising or falling edges, while showing a smaller response for relatively gradual changes in normal switching processes. This improves the accuracy and selectivity of disturbance detection. Compared to the prior art's schemes using voltage threshold detection or first derivative detection, which suffer from false detection problems, this scheme achieves more accurate disturbance identification through second derivative characteristics.

[0060] Because it employs a clockless asynchronous combinational logic retrieval circuit for trigger quantization and table lookup operations, the entire processing link is independent of the system clock signal. Its latency depends only on the gate-level propagation delay of the combinational logic, eliminating the latency of waiting for the clock edge in synchronous sampling architectures. Therefore, it can achieve a fast response from disturbance detection to compensation execution, reducing response latency. Compared to the inherent latency problem introduced by the clock cycle in the synchronous sampling architecture of the background technology, this solution achieves a nanosecond-level fast response.

[0061] By employing a programmable current mirror array and utilizing polarity and amplitude control bits in the charge compensation control index for decoding control, it can selectively conduct the source current branch used for current injection or the leakage current branch used for current extraction. Furthermore, by synthesizing compensation charges of different magnitudes through weighted current mirror branches, it can accurately match parasitic capacitance disturbances of different directions and amplitudes, thus improving the matching accuracy between compensation charge and disturbance characteristics. Compared to the problem of inaccurate disturbance matching with fixed compensation amounts or simple graded compensation methods in the background technology, this solution achieves refined charge control through bidirectional programmable compensation.

[0062] By employing a waveform deviation integral circuit to obtain the compensated waveform and calculate the integral value of the time-domain waveform deviation from the reference waveform, and determining over-compensation or under-compensation states based on the polarity of the deviation integral value, and adjusting the mapping relationship in the charge compensation lookup table accordingly, a complete closed-loop feedback mechanism of detection, quantization, compensation, evaluation, and correction is formed. This closed-loop mechanism adopts a cross-cycle adaptive adjustment strategy, performing compensation operations in the current switching cycle, evaluating the compensation effect after the cycle ends, and feeding back the evaluation results to correct the compensation parameters for the next cycle. Iterative optimization of the compensation parameters is achieved by utilizing the periodic repetition of power switching actions. Since the inherent characteristic of closed-loop negative feedback control is to minimize the system error, the compensation parameters can automatically converge to the optimal value under the current operating conditions, realizing online adaptive optimization of the compensation parameters. This makes the detection, quantization, compensation, and correction links form an organic whole, generating an overall synergistic effect and overcoming the limitations of open-loop designs in existing technologies that cannot adapt to changes in operating conditions.

[0063] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for MOS transistor gate charge balancing of parasitic capacitance charge cancellation logic, comprising: The method comprises the following steps: a second-order derivative characteristic signal of a gate voltage of a MOS transistor is continuously captured by using a cascade analog differential circuit, and a trigger pulse signal is generated when an amplitude of the second-order derivative characteristic signal exceeds a preset trigger threshold; in response to the trigger pulse signal, an asynchronous quantization process is performed on the second-order derivative characteristic signal of the gate voltage to generate a digital quantization value; a clockless asynchronous combinational logic retrieval circuit is used to retrieve a charge compensation control index corresponding to the digital quantization value based on a mapping relationship stored in a charge compensation lookup table; a programmable current mirror array is used to decode the charge compensation control index, and an internal current mirror branch is selectively turned on according to a decoding result to apply a quantization compensation charge to a gate node for offsetting a transient disturbance of a parasitic capacitor; a waveform deviation integration circuit is used to obtain a gate voltage waveform after the quantization compensation charge is applied, detect a characteristic time of the gate voltage waveform to achieve time-domain synchronization with a preset reference voltage waveform, calculate a time-domain waveform deviation integration value after synchronization, and dynamically modify the mapping relationship in the charge compensation lookup table based on the time-domain waveform deviation integration value.

2. The method of claim 1, wherein, The second-order derivative characteristic signal of the gate voltage of the MOS transistor is continuously captured by using the cascade analog differential circuit, comprising: a second-order derivative of the gate voltage with respect to time is obtained as the second-order derivative characteristic signal of the gate voltage through a multi-stage series high-pass differential network in the cascade analog differential circuit; the absolute value of the second-order derivative is compared with the preset trigger threshold, and the trigger pulse signal is output when the absolute value is greater than the preset trigger threshold.

3. The method of claim 1, wherein, The clockless asynchronous combinational logic retrieval circuit is used to retrieve the charge compensation control index corresponding to the digital quantization value, comprising: an asynchronous parallel comparator array is used as a quantization front end, and the second-order derivative characteristic signal of the gate voltage is directly converted into the digital quantization value when the trigger pulse signal is received; an internal latch is triggered to latch the digital quantization value and start an asynchronous query operation on an internal charge compensation lookup table; the charge compensation control index corresponding to the digital quantization value is output through the asynchronous query operation independently of a system clock signal.

4. The method of claim 1, wherein, The programmable current mirror array is used to decode the charge compensation control index, comprising: at least two weighted current mirror branches in the programmable current mirror array are used, and the current mirror branches are configured to be able to perform current injection or current extraction operations according to a control signal; a source current branch for current injection or a drain current branch for current extraction is selectively turned on according to a polarity control bit and an amplitude control bit in the charge compensation control index to synthesize the quantization compensation charge corresponding to the charge compensation control index.

5. The method of claim 1, wherein, The time-domain waveform deviation integration value of the gate voltage waveform relative to the preset reference voltage waveform is calculated, comprising: after a switching action of the MOS transistor is completed, a specific characteristic time of an actual gate voltage waveform is detected as a synchronization reference point; determine a time window for integral calculation based on the synchronization reference point; acquire reference data of the preset reference voltage waveform within the time window; calculate a difference between actual gate voltage data within the time window and the reference data, and integrate the difference to obtain a time-domain waveform deviation integral value.

6. The method of claim 5, wherein, The dynamic modification of the mapping relationship in the charge compensation lookup table based on the time-domain waveform deviation integral value includes: determining a polarity of the time-domain waveform deviation integral value; if the polarity indicates that there is an over-compensation state at present, retrieving a current charge compensation control index corresponding to the digital quantization value in the charge compensation lookup table, reducing a numerical value of the current charge compensation control index by a preset fine adjustment step, and updating and storing the reduced charge compensation control index to the charge compensation lookup table; if the polarity indicates that there is an under-compensation state at present, retrieving a current charge compensation control index corresponding to the digital quantization value in the charge compensation lookup table, increasing a numerical value of the current charge compensation control index by a preset fine adjustment step, and updating and storing the increased charge compensation control index to the charge compensation lookup table.

7. The method of claim 1, wherein, The method further includes: continuously monitoring a conduction duration of the programmable current mirror array; if the conduction duration exceeds a preset fusing threshold, forcibly turning off the programmable current mirror array, and resetting a state of the clockless asynchronous combinational logic retrieval circuit.

8. A MOS transistor gate charge balancing system for parasitic capacitance charge cancellation logic, characterized by, including: a cascaded analog differential circuit configured to continuously capture a gate voltage second derivative characteristic signal of a MOS transistor gate voltage due to a parasitic capacitance transient disturbance, and generate a trigger pulse signal when an amplitude of the gate voltage second derivative characteristic signal exceeds a preset trigger threshold; an asynchronous quantization interface circuit configured to convert the gate voltage second derivative characteristic signal into a digital quantization value in response to the trigger pulse signal; a clockless asynchronous combinational logic retrieval circuit configured to retrieve a charge compensation control index corresponding to the digital quantization value based on a mapping relationship currently stored in a charge compensation lookup table; a programmable current mirror array configured to decode the charge compensation control index, and selectively turn on an internal current mirror branch according to a decoding result to apply a quantized compensation charge to a gate node for offsetting the parasitic capacitance transient disturbance; a waveform deviation integral circuit configured to acquire a gate voltage waveform after the quantized compensation charge is applied, calculate a time-domain waveform deviation integral value of the gate voltage waveform relative to a preset reference voltage waveform after performing waveform alignment, and dynamically modify the mapping relationship in the charge compensation lookup table based on the time-domain waveform deviation integral value.

9. The system of claim 8, wherein, It is further configured to perform the method of any one of claims 2 to 7. It is further configured to perform the method of any one of claims 2 to 7.

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