Method and device for zero sequence current suppression of open-winding dual two-level inverter

Abstract

The embodiment of the application discloses a zero sequence current suppression method and device of open-winding double two-level inverter, relates to the modulation field of common DC bus type open-winding permanent magnet synchronous motor, and comprises the following steps: collecting three-phase current to calculate zero sequence current and zero sequence voltage; three-phase reference voltage is formed by superimposing with three-phase voltage and is converted to two-phase stationary coordinate system, and sectors are divided according to phase angles; three-phase reference voltage and zero sequence voltage are normalized, and the maximum conduction phase voltage corresponding to the normalization is extracted; the maximum modulation range is determined in combination with a preset pulse position offset coefficient k, drive pulse signals are formed when power devices are turned on and turned off, and the drive pulse signals are calculated. In a carrier cycle, the motor mutual inductance can be used to offset current pulsation, the current THD can be reduced, the zero sequence current can be suppressed, and the current ripple can be reduced. The modulation strategy can be adjusted only by adjusting the k value, the universality is high, the pulse time overflow can be prevented, the control disorder caused by overmodulation can be avoided, the voltage output range of the motor system is expanded, and the robustness is improved.

Description

Technical Field

[0001] This invention relates to the field of modulation technology for open-winding permanent magnet synchronous motors with common DC bus, and particularly to a method and apparatus for suppressing zero-sequence current in an open-winding dual two-level inverter. Background Technology

[0002] Open-winding motors (or open-circuit motors) are special cascaded power supply methods where the neutral point of the star-connected winding is opened, and an inverter is connected to each end. Driven by two inverters, they offer high flexibility, strong fault tolerance, and high DC voltage utilization, making them suitable for new energy electric vehicles and aerospace applications. The topology of a fully controlled common DC bus open-winding motor system based on two-level inverters is shown in Figure 1. Both sides have a set of two-level inverters, namely inverter P and inverter Q. When using a common DC bus for power supply, compared to an independent DC bus structure, the two inverters only need to share one power source, forming a dual two-level system with two sets of two-level inverters, simplifying the system structure and reducing costs. However, a drawback of this topology is that the direct connection of two inverters sharing the same power source leads to the existence of a zero-sequence path. When a zero-sequence voltage appears in the system, a zero-sequence current will inevitably be generated, causing severe distortion of the three-phase current and resulting in additional energy loss. The motor driven by the inverter simulates the required current by switching at high speed. This switching action causes the actual current to fluctuate up and down like sawtooth around the average value, forming current ripple, which in turn increases the effective value of the current. Ultimately, the motor windings heat up severely, affecting the fluctuation of the motor output torque and deteriorating the system performance. Summary of the Invention

[0003] This invention provides a method and apparatus for suppressing zero-sequence current in an open-winding dual two-level inverter, in order to solve the technical problem of current ripple caused by the formation of zero-sequence current in a dual two-level inverter on the common DC bus of an open-winding motor, which leads to motor winding heating torque fluctuation.

[0004] In a first aspect, embodiments of the present invention provide a method for suppressing zero-sequence current in an open-winding dual two-level inverter, comprising:

[0005] S101: Collect the three-phase current of the open-winding motor and calculate the zero-sequence current; calculate the zero-sequence voltage based on proportional resonance regulation.

[0006] S102, superimposes the zero-sequence voltage with the three-phase voltage output from the dual closed-loop control of the motor to form a three-phase reference voltage;

[0007] S103 converts the three-phase reference voltage to a two-phase stationary coordinate system, and divides the voltage space into sectors based on the phase angle of the three-phase reference voltage and determines the current sector.

[0008] S104, perform per-unit processing on the three-phase reference voltage and zero-sequence voltage. The per-unit range is -1 to 1. Extract the maximum conduction phase voltage of the corresponding per-unit from the three-phase reference voltage after per-unit processing according to the current sector.

[0009] S105 determines the maximum modulation range based on the extracted maximum on-phase voltage, zero-sequence voltage, and preset pulse position offset coefficient k, and calculates the power device turn-on and turn-off time data to form a drive pulse signal.

[0010] Secondly, embodiments of the present invention provide a zero-sequence current suppression device for an open-winding dual two-level inverter, comprising:

[0011] The current acquisition module is used to acquire the three-phase current of the open-winding motor and calculate the zero-sequence current and zero-sequence voltage.

[0012] The reference voltage calculation module is used to superimpose the zero-sequence voltage and the three-phase voltage to form a three-phase reference voltage.

[0013] The sector partitioning module is used to convert the three-phase reference voltage to a two-phase stationary coordinate system and divide the voltage space into sectors based on the phase angle of the three-phase reference voltage.

[0014] The voltage per-unit module is used to standardize the three-phase reference voltage and zero-sequence voltage to per-unit and extract the maximum conducting phase voltage of the corresponding per-unit.

[0015] The drive pulse module is used to determine the maximum modulation range based on the extracted maximum on-phase voltage, zero-sequence voltage and preset pulse position offset coefficient k, and to calculate the power device turn-on and turn-off time data to form a drive pulse signal.

[0016] Thirdly, embodiments of the present invention provide an electronic device, including:

[0017] One or more processors;

[0018] Storage device for storing one or more programs.

[0019] When the one or more programs are executed by the one or more processors, the one or more processors implement the zero-sequence current suppression method for the open-winding dual two-level inverter described above.

[0020] Fourthly, embodiments of the present invention provide a storage medium containing computer-executable instructions, which, when executed by a computer processor, are used to perform the aforementioned zero-sequence current suppression method for an open-winding dual two-level inverter.

[0021] This invention provides a method and apparatus for suppressing zero-sequence current in an open-winding dual two-level inverter. The method involves acquiring the three-phase current of the open-winding motor and calculating the zero-sequence current and zero-sequence voltage. The zero-sequence voltage is injected into the three-phase reference voltage. Then, the three-phase reference voltage is converted to a two-phase stationary coordinate system, and the voltage space is divided into sectors and the current sector is determined based on the phase angle of the three-phase reference voltage. Drive voltage pulse signals are generated based on the maximum conducting phase M, the second conducting phase F, and the last conducting phase L obtained through per-unit processing. A pulse position offset coefficient k, which can continuously change the relative position of the voltage pulses of phase F and phase L, is introduced to participate in the calculation of the drive pulse switching time. Finally, a judgment is made on whether the modulation range of one carrier cycle is exceeded. This system ensures that the voltage pulse polarity of phase M is always opposite to that of phases F and L within a single carrier cycle. Furthermore, the voltage pulses of phases F and L are staggered from phase M on the time axis, preventing the simultaneous positive or negative rates of change of the three-phase current. This utilizes the mutual inductance effect between the motor windings to cancel current pulsation, reducing total harmonic distortion (THD), effectively suppressing zero-sequence current, and reducing current ripple. It also addresses the different optimal current ripple operating points of various motors due to variations in self-inductance and mutual inductance parameters. By simply adjusting the k value, it can approximate the minimum current ripple state of the motor, improving the versatility and engineering applicability of the modulation strategy. Simultaneously, it ensures computational flexibility in the low-modulation region, prevents pulse time overflow in the high-modulation region, ensures the legality of the pulse sequence, avoids control disorder caused by overmodulation, and expands the system's voltage output range and robustness. Attached Figure Description

[0022] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an undue limitation of the invention. In the drawings:

[0023] Figure 1 Topology diagram of a dual two-level inverter system for a permanent magnet synchronous motor with open windings on a common DC bus;

[0024] Figure 2 This is a flowchart of a zero-sequence current suppression method for an open-winding dual two-level inverter according to Embodiment 1 of the present invention;

[0025] Figure 3 The modulation strategy described in Embodiment 1 of the present invention k A schematic diagram of the three-phase voltage pulse when =0;

[0026] Figure 4 The modulation strategy described in Embodiment 1 of the present invention k A schematic diagram of the three-phase voltage pulse when =1;

[0027] Figure 5This is a waveform diagram of the phase voltage and phase current ripple as described in Embodiment 1 of the present invention;

[0028] Figure 6 This is a schematic diagram of the rotor position angle and current ripple as described in Embodiment 1 of the present invention;

[0029] Figure 7 This is a schematic diagram of the zero-sequence current suppression device for an open-winding dual two-level inverter according to Embodiment 2 of the present invention;

[0030] Figure 8 This is a structural diagram of the electronic device described in Embodiment 3 of the present invention. Detailed Implementation

[0031] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0032] In a common DC bus structure, two inverters share a single power supply. A zero-sequence path exists between the two inverters, resulting in zero-sequence voltage and current. Its topology is as follows: Figure 1 As shown in the figure, the power switching device S A1 With S A3 The switching states of the upper and lower bridge arms are reversed for the other phases. Power devices can be set to 1 for on and 0 for off, with each phase outputting a voltage of... V dc - V dc 0. The three-phase windings can be considered as three independent H-bridges, and the voltage of each phase can be expressed as:

[0033]

[0034] Among them, S A1 For the A-phase upper transistor of inverter P, S A2 For the A-phase upper transistor of inverter Q, S B1 For the B-phase upper transistor of inverter P, S B2 For the B-phase upper transistor of inverter Q, S C1 For the C-phase upper transistor of inverter P, S C2 Let be the C-phase upper transistor of inverter Q, and each upper transistor is a power switching device. According to the above equation, the voltage of each phase is determined by the on / off state of the power devices on both sides, and is independent of the power devices in the other two phases. Therefore, changing the switching state of the power device in one phase will not affect the voltage changes in the other two phases. The voltage equation of an open-winding permanent magnet synchronous motor in a three-phase stationary coordinate system can be expressed as:

[0035]

[0036] in, , , It is a three-phase voltage. It is the phase resistance. , , It is a three-phase current. , , Let d / dt represent the three-phase stator flux linkage, and d / dt denote the derivative (the derivative of the three-phase stator flux linkage with respect to time). For a non-salient pole open-winding permanent magnet synchronous motor, the self-inductance and inter-phase mutual inductance of the three-phase windings are constants, and the flux linkage equation is as follows:

[0037]

[0038] in, It is a feeling. It's mutual induction. It is the fundamental magnetic flux linkage of a permanent magnet. It is the third harmonic flux linkage of a permanent magnet. This refers to the rotor position angle. It is evident that due to the self-inductance and mutual inductance effects of the motor, the instantaneous value of the A-phase current is not only affected by the parameters of the A-phase itself, but also coupled with the current states of phases B and C, thus determining the ripple characteristics of the motor current. That is, when the rates of change of the three-phase currents are in the same direction (i.e., simultaneously positive or simultaneously negative), the negative mutual inductance ( The induced voltage generated by a voltage < 0 cancels out the self-inductance voltage, significantly reducing the equivalent inductance of the circuit. This leads to a sharp increase in the rate of current change under the same voltage drive, causing increased current ripple. The main causes of zero-sequence voltage are differential-mode voltage (the common-mode voltage difference between the two inverters) and the motor's third harmonic back electromotive force. A modulation strategy based on mutual inductance can be used to control the differential-mode voltage to cancel out other components, thereby eliminating zero-sequence voltage, suppressing zero-sequence current, reducing current ripple, and enabling stable operation of the motor system. Specific implementation methods are as follows:

[0039] Example 1

[0040] Figure 2 This is a flowchart of a zero-sequence current suppression method for an open-winding dual two-level inverter according to Embodiment 1 of the present invention. This embodiment ensures that the rate of change of the three-phase current is not simultaneously positive or simultaneously negative within one carrier cycle by accurately determining the sector and actively designing and offsetting the phase voltage pulse timing. This utilizes the cancellation effect of the mutual inductance voltage to effectively suppress zero-sequence current while significantly reducing current ripple and total harmonic distortion (THD). Specifically, it includes the following steps:

[0041] S101 collects the three-phase current of the open-winding motor and calculates the zero-sequence current, and calculates the zero-sequence voltage based on proportional resonance regulation.

[0042] Collect the phase currents of each phase of the three-phase windings of the open-winding motor system. , , And calculate the zero-sequence current. The calculated zero-sequence current input proportional resonant (PR) regulator is then combined with the zero-sequence voltage compensation. Forming zero-sequence voltage Zero-sequence voltage compensation and zero sequence voltage The calculation formula is as follows:

[0043]

[0044]

[0045] in, It is the angular velocity of the motor. It is the third harmonic flux linkage of a permanent magnet. It is the rotor position angle. and These are the proportional gain and resonant gain of the zero-sequence current proportional resonant regulator. It is the cutoff frequency. It is the resonant frequency. To achieve zero-sequence current suppression, Usually ,and The speed can be selected as 2-5 rad / s. Set to 0. Zero-sequence voltage. It is used to actively cancel the zero-sequence current path voltage generated by the common DC bus structure in a dual two-level inverter system, thereby suppressing the zero-sequence current.

[0046] S102 superimposes the zero-sequence voltage with the three-phase voltage output from the dual closed-loop control of the motor to form a three-phase reference voltage.

[0047] The motor's dual closed-loop control section will output three-phase voltage commands. , , The three-phase voltage command is superimposed with the zero-sequence voltage to obtain the three-phase reference voltage for modulation. , This refers to the actual three-phase voltage of the motor.

[0048] S103 converts the three-phase reference voltage to a two-phase stationary coordinate system, and divides the voltage space into sectors based on the phase angle of the three-phase reference voltage and determines the current sector.

[0049] Specifically, the three-phase reference voltage is converted to the α-β two-phase stationary coordinate system based on the Clarke transform, and the phase angle θ of the three-phase reference voltage is calculated, with the phase angle ranging from 0 to 2π.

[0050] First, the three-phase reference voltage... , , Perform a Clark transform to convert it to the α-β two-phase stationary coordinate system to obtain the voltage components in the α-β coordinate system. , The formula is as follows:

[0051]

[0052] Using a two-phase stationary coordinate system, the reference voltage is transformed from the α-β domain to the angular domain, allowing us to obtain the amplitude and phase angle of the three-phase reference voltage. The phase angle θ ranges from [0, 2π], and the calculation formula is as follows:

[0053]

[0054] Based on the phase angle θ of the three-phase reference voltage, the voltage space is divided into 6 sectors with π / 3 as a sector, and the current sector is determined.

[0055] Divide the entire voltage vector plane into 6 sectors N=1, 2, 3, 4, 5, 6, each sector being π / 3. The sector number N can be determined based on the phase angle θ of the three-phase reference voltage. The sector determination table is shown in Table 1 below:

[0056] Table 1 Sector Judgment Table

[0057]

[0058] Based on the sector division results, the three-phase reference voltages are mapped to the maximum conducting phase M, the second conducting phase F, and the last conducting phase L, respectively. The voltage of the maximum conducting phase is the phase with the largest absolute value among the three-phase reference voltages, and the voltage polarities of the second conducting phase and the last conducting phase are opposite to those of the maximum conducting phase.

[0059] Based on the sector division results, sector judgment table, and the current sector, the three-phase reference voltage is... , , Mapped to the maximum conducting phase M, the second conducting phase F, and the last conducting phase L respectively, the voltages are respectively , , The phase voltage of the maximum conducting phase M. The phase voltage of the second conducting phase F is the phase with the largest absolute value. and the phase voltage of the last conducting phase L The phase voltage of the maximum conducting phase M The polarities are opposite. The correspondence between the conduction state and the conduction phase of each sector is shown in Table 2:

[0060] Table 2 Correspondence table of different sector conduction states at any given time

[0061]

[0062] At this point, the three phases are in two conduction states. State 1: The phase with the largest absolute value of the three-phase reference voltage has the longest voltage pulse duration among the three phases. This phase is defined as the maximum conduction phase. M State 2: Except for the maximum conducting phase, the polarities of the other two voltages are opposite to those of the maximum conducting phase. Based on their conduction sequence, this is defined as the second conducting phase. F With the last conduction phase L .

[0063] S104, perform per-unit processing on the three-phase reference voltage and zero-sequence voltage. The per-unit range is -1 to 1. Extract the maximum conducting phase voltage of the corresponding per-unit from the three-phase reference voltage after per-unit processing according to the current sector.

[0064] To simplify calculations and generalize the algorithm, the three-phase reference voltage was... and zero sequence voltage Perform per-unit processing, setting the per-unit reference value to the DC bus voltage. Mapping these two values ​​to the range [-1, 1], the formula is as follows:

[0065]

[0066] in, The three-phase reference voltage is the unit number. This is the zero-sequence voltage per unit. Based on the mapping relationship in Table 2, determine the maximum conducting phase M corresponding to the current sector and obtain the corresponding phase voltage. The maximum conduction phase voltage of the corresponding per-unit is obtained using the above per-unit formula. .

[0067] S105 determines the maximum modulation range based on the extracted maximum on-phase voltage, zero-sequence voltage, and preset pulse position offset coefficient k, and calculates the power device turn-on and turn-off time data to form a drive pulse signal.

[0068] One optional implementation of this embodiment is to calculate the maximum modulation range using the extracted maximum on-phase voltage M, zero-sequence voltage, and preset pulse position offset coefficient k.

[0069] To avoid exceeding the modulation range (limited to one carrier cycle) during modulation, the maximum modulation range is first calculated using the extracted maximum on-phase voltage M, zero-sequence voltage, and preset pulse position offset coefficient k. The maximum modulation range is used to determine if the out-of-range judgment is greater than 1 (i.e., exceeding one carrier cycle).

[0070] The maximum modulation range is compared with the 0~1 interval. When it does not exceed the 0~1 interval, the first set of formulas is used to calculate the power device turn-on and turn-off times. When it exceeds the 0~1 interval, the second set of formulas is used to calculate the power device turn-on and turn-off times.

[0071] When the calculated maximum modulation range does not exceed the [0, 1] interval, it indicates that the modulation range is not exceeded, meaning that the modulation is not saturated at this time. The first set of formulas is used to calculate the four key switching time points of the power device's switching on and off. , , , ,in Indicates power devices exist Always on, Indicates power devices exist Always on, Indicates power devices exist Always turn off Indicates power devices exist The formula group for constant shutdown is as follows:

[0072]

[0073] Where k represents the pulse position offset coefficient; , , These represent the phase voltages of the maximum conducting phase M, the second conducting phase F, and the last conducting phase L per unit, respectively. , , These represent the four key switching times for the three phases, and ; Indicates the end time of a carrier cycle; This represents the zero-sequence voltage of a unit. It is the power device of inverter 1 (such as the upper arm of phase A of inverter 1). At this time, the lower bridge arm The switching state is opposite to that of the upper bridge arm. It is the power device of inverter 2 (such as the upper arm of phase A of inverter 2). At this time, the lower bridge arm The switching state is opposite to that of the upper bridge arm); that is... The conduction time is from arrive , The conduction time is from arrive The mapping relationship between each power switch and the three phases M, F, and L will be explained later.

[0074] Optionally, when using the second set of formulas to calculate the turn-on and turn-off times of the power devices, the starting time of the second conducting phase voltage F is set to 0, and the ending time of the last conducting phase voltage L is set to the ending time of the current carrier cycle.

[0075] When the calculated maximum modulation range exceeds the [0, 1] interval, it indicates that the modulation has entered the high-modulation saturation region. To prevent overflow in the pulse timing calculation, the second set of formulas is used to calculate the switching on and off times of the power devices. The formula set is as follows:

[0076]

[0077] To ensure the pulse timing is valid, the start time of the second conducting phase F is set. And the final conduction time of the conducting phase L. , A carrier cycle can also be considered as the end point of a carrier cycle, ensuring that even in the most extreme cases, the voltage pulse sequence can still be completely constrained within a carrier cycle.

[0078] The drive pulse signal is generated based on the turn-on and turn-off times of the power device.

[0079] Based on the power device turn-on and turn-off times calculated using different formula sets under different conditions, and combined with the power device corresponding to the current sector, a drive pulse signal can be generated to control the corresponding power device to turn on or off at a specific time within a carrier cycle.

[0080] Specifically, based on the current sector and the corresponding maximum on-phase voltage M, second on-phase voltage F, and last on-phase voltage L, the corresponding power devices are determined.

[0081] The correspondence between each sector and the power switching transistor is shown in Table 3:

[0082] Table 3: Correspondence of different sector switching transistors at any given time

[0083]

[0084] Table 3 shows that each phase consists of two power devices. In each carrier cycle, the power device connected to the phase with the maximum conduction M is set to S. M1 S M2 The power device connected to the second conducting phase F is set to S. F1 S F2 The power device connected to the last conducting phase L is set to S. L1 S L2 .

[0085] Based on the turn-on and turn-off times of the power devices and the corresponding power devices, a drive pulse signal is generated to drive the corresponding power devices to turn on or off.

[0086] According to the turn-on and turn-off times of the power devices, according to S M1 In T M-1 Always on, in T M-4 Always off; S M2 In T M-2 Always on, in T M-3 Always off. S F1 In T F-1 Always on, in T F-4 Always off; S F2 In T F-2 Always on, in T F-3 Always off. S L1 In T L-1 Always on, in T L-4 Always off; S L2 In T L-2 Always on, in T L-3 The circuit is switched off at specific times. Based on the power switching transistors in the dual three-phase inverter represented by the first column in Table 3, and the aforementioned on / off times, drive pulse signals are generated to drive the corresponding power devices to turn on or off.

[0087] Optionally, the preset pulse position offset coefficient k ranges from 0 to 1, and is determined based on the per-unit ratio of the phase mutual inductance coefficient and the phase self-inductance coefficient of the open-winding motor, as well as the desired current ripple suppression degree. It is used to continuously adjust the offset of the voltage pulses on the time axis of the second conducting phase voltage F and the last conducting phase voltage L.

[0088] The pulse position offset coefficient k can be adjusted based on the ratio of mutual inductance (Ms) to self-inductance (Ls) of the specific motor and the desired degree of current ripple suppression. It represents the degree of offset of the voltage pulse on the horizontal time axis. The value of k can be adjusted online during implementation to find the minimum current ripple, generally around 0.3. The value range of k is [0, 1], where k=0 represents no additional pulse offset. Figure 3As shown in the figure, the three-phase voltages are the phase voltages within one carrier cycle. The yellow line represents the M-phase voltage, the blue line represents the F-phase voltage, and the red line represents the L-phase voltage. It can be seen that when the M-phase voltage is on, the F-phase voltage is also on; when the M-phase voltage is off, the L-phase voltage is also off. k=1 represents the pulse offset to the limit position (i.e., the F-phase and L-phase voltage pulses are adjacent but do not overlap on the time axis), as... Figure 4 As shown in the figure, the three-phase voltage positions are continuously adjusted within one carrier cycle. Specifically, the F-phase voltage pulse position is moved to the left, and the L-phase voltage pulse position is moved to the right, until the three-phase currents do not simultaneously increase or decrease to their limits. At this point, the L-phase voltage turn-on moment is the F-phase voltage turn-off moment. This improved modulation strategy, by adjusting the three-phase voltage pulse positions, prevents the three-phase voltages from being simultaneously positive or negative within one carrier cycle, thus reducing the ripple of the three-phase current. It maintains that within any carrier cycle, one phase voltage is always on one side of the 0 axis, and the other two phase voltages are on the other side. The duration of the voltage of the single phase on the 0 axis side is always greater than the duration of the other two phases.

[0089] Optionally, the preset drive pulse signal is configured to control the voltage pulse polarity of the maximum conducting phase voltage M to be opposite to the voltage pulse polarity of the second conducting phase voltage F and the last conducting phase voltage L within one carrier cycle, and the voltage pulses of the second conducting phase voltage F and the last conducting phase voltage L do not overlap or partially overlap in time, so that the rate of change of the three-phase current is not simultaneously positive or simultaneously negative.

[0090] The preset drive pulse signal is used to generate drive pulses that satisfy the following conditions: within one carrier cycle Within this circuit, the voltage pulse polarity of the largest conducting phase M is opposite to that of the second conducting phase F and the last conducting phase L. Furthermore, by adjusting the parameter k, the voltage pulses of phases F and L can be controlled to gradually change from complete overlap (k=0) to just adjacent or non-overlapping (k=1) on the time axis. This voltage pulse arrangement physically ensures that at any given time, at least one phase current change trend is opposite to the other two, thus utilizing the negative mutual inductance effect to offset the self-inductance voltage drop and suppressing the situation where the three-phase current change rates di / dt are simultaneously positive or simultaneously negative, thereby achieving the core effect of reducing current ripple. Figure 5 The figure shows the ripple of the phase currents and the phase voltage waveforms of phases A, B, and C when the rotor position angle is π / 2. At this time, the phase current of phase A reaches its peak value, and the currents of phases B and C are half of their peak values. The figure also shows the phase current ripple and phase voltage waveforms of phases B and C at the current rotor position angle. Figure 1 Therefore, the three-phase voltages within one carrier cycle are respectively related to and Symmetrical. It can be seen that at this point, all three phase windings of the motor bear positive voltage, the rate of change of the three-phase current is greater than 0, and the ripple of the three-phase current increases simultaneously (within the yellow box). Due to the mutual inductance effect, the rate of rise of the three-phase current will increase, leading to a larger current ripple. This invention, based on the influence of motor mutual inductance, adjusts the pulse position by improving the modulation strategy (e.g., ...). Figure 3 , Figure 4 (As shown) This can reduce current ripple and effectively suppress zero-sequence current in the motor to avoid this situation. Furthermore, compared to the massive computational cost of traditional real-time current calculation followed by calculating the current ripple for each carrier cycle, a minimum current ripple strategy suitable for each motor can be obtained simply by adjusting the k value, such as... Figure 6 As shown, the left side is a schematic diagram of the rotor position angle and current ripple of the traditional modulation strategy, and the right side is a diagram of the current ripple generated by adjusting the rotor position angle in this embodiment. k The diagram illustrates the relationship between rotor position angle and current ripple when minimizing current ripple. It shows that different motors require different values. k With different values, this embodiment can reduce the current ripple more when the mutual inductance of the motor is greater.

[0091] This embodiment acquires the three-phase current of an open-winding motor and calculates the zero-sequence current and zero-sequence voltage. The zero-sequence voltage is injected into the three-phase reference voltage. The three-phase reference voltage is then converted to a two-phase stationary coordinate system, and the voltage space is divided into sectors based on the phase angles of the three-phase reference voltage, and the current sector is determined. Drive voltage pulse signals are generated based on the maximum conducting phase M, the second conducting phase F, and the last conducting phase L, obtained through per-unit processing. A pulse position offset coefficient k, which can continuously change the relative position of the voltage pulses of phase F and phase L, is introduced to participate in the calculation of the drive pulse switching time. A judgment is also made on whether the modulation range exceeds one carrier cycle. This ensures that within one carrier cycle, the polarity of the voltage pulse of phase M is always opposite to that of the voltage pulses of phases F and L, and the voltage pulses of phases F and L are staggered from phase M on the time axis. This avoids the situation where the three-phase current change rate is simultaneously positive or negative, thereby utilizing the mutual inductance effect between the motor windings to cancel current pulsation, reduce total harmonic distortion (THD), effectively suppress zero-sequence current, and reduce current ripple. Furthermore, it can address the different optimal current ripple operating points of various motors due to variations in self-inductance and mutual inductance parameters. By simply adjusting the k value, it can approximate the minimum current ripple state of the motor, improving the versatility and engineering applicability of the modulation strategy. Simultaneously, it ensures computational flexibility in the low-modulation region, prevents pulse time overflow in the high-modulation region, ensures the legality of the pulse sequence, avoids control disorder caused by overmodulation, and expands the system's voltage output range and robustness.

[0092] Example 2

[0093] Figure 7This is a schematic diagram of the zero-sequence current suppression device for an open-winding dual two-level inverter according to Embodiment 2 of the present invention. In this embodiment, the zero-sequence current suppression device for the open-winding dual two-level inverter includes:

[0094] The current acquisition module 810 is used to acquire the three-phase current of the open-winding motor and calculate the zero-sequence current and zero-sequence voltage.

[0095] The reference voltage calculation module 820 is used to superimpose the zero-sequence voltage and the three-phase voltage to form a three-phase reference voltage.

[0096] The sector partitioning module 830 is used to convert the three-phase reference voltage to a two-phase stationary coordinate system and divide the voltage space into sectors according to the phase angle of the three-phase reference voltage.

[0097] The voltage per-unit module 840 is used to standardize the three-phase reference voltage and zero-sequence voltage per unit and extract the maximum conducting phase voltage of the corresponding per unit.

[0098] The drive pulse module 850 is used to determine the maximum modulation range based on the extracted maximum on-phase voltage, zero-sequence voltage and preset pulse position offset coefficient k, and to calculate the power device turn-on and turn-off time data to form a drive pulse signal.

[0099] This embodiment acquires the three-phase current of an open-winding motor using a current acquisition module. A reference voltage calculation module superimposes the zero-sequence voltage with the three-phase voltage to calculate the three-phase reference voltage. A sector division module divides the voltage space into sectors based on the phase angle of the three-phase reference voltage. A per-unit voltage scaling module standardizes the three-phase reference voltage and the zero-sequence voltage. A drive pulse module determines the maximum modulation range and calculates the turn-on and turn-off times of the power devices to form the drive pulse signal. This ensures that within one carrier cycle, the polarity of the voltage pulse in phase M is always opposite to that in phases F and L, and the voltage pulses in phases F and L are staggered from those in phase M on the time axis. This avoids the situation where the three-phase current change rate is simultaneously positive or negative, thereby utilizing the mutual inductance effect between the motor windings to cancel current pulsation, reduce total harmonic distortion (THD), effectively suppress zero-sequence current, and reduce current ripple. Furthermore, it can address the different optimal current ripple operating points of various motors due to variations in self-inductance and mutual inductance parameters. By simply adjusting the k value, it can approximate the minimum current ripple state of the motor, improving the versatility and engineering applicability of the modulation strategy. Simultaneously, it ensures computational flexibility in the low-modulation region, prevents pulse time overflow in the high-modulation region, ensures the legality of the pulse sequence, avoids control disorder caused by overmodulation, and expands the system's voltage output range and robustness.

[0100] The zero-sequence current suppression device for the open-winding dual two-level inverter provided in this embodiment of the invention can execute the zero-sequence current suppression method for the open-winding dual two-level inverter provided in any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the method.

[0101] Example 3

[0102] Figure 8 This is a structural diagram of an electronic device according to Embodiment 3 of the present invention. Figure 8 A block diagram of an exemplary device 12 suitable for implementing embodiments of the present invention is shown. Figure 8 The device 12 shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of the present invention.

[0103] like Figure 8 As shown, device 12 is represented as a general-purpose computing device. Components of device 12 may include, but are not limited to: one or more processors or processing units 16, system memory 28, and a bus 18 connecting different system components (including system memory 28 and processing unit 16).

[0104] Bus 18 represents one or more of several bus architectures, including a memory bus or memory controller, a peripheral bus, a graphics acceleration port, a processor, or a local bus using any of the various bus architectures. For example, these architectures include, but are not limited to, the Industry Standard Architecture (ISA) bus, the Micro Channel Architecture (MAC) bus, the Enhanced ISA bus, the Video Electronics Standards Association (VESA) local bus, and the Peripheral Component Interconnect (PCI) bus.

[0105] Device 12 typically includes a variety of computer system readable media. These media can be any available media that can be accessed by device 12, including volatile and non-volatile media, removable and non-removable media.

[0106] System memory 28 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 30 and / or cache memory 32. Device 12 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, storage system 34 may be used to read and write non-removable, non-volatile magnetic media (… Figure 8 Not shown; usually referred to as a "hard drive"). Although Figure 8Not shown, a disk drive for reading and writing to a removable non-volatile disk (e.g., a "floppy disk") and an optical disk drive for reading and writing to a removable non-volatile optical disk (e.g., a CD-ROM, DVD-ROM, or other optical media) may be provided. In these cases, each drive may be connected to bus 18 via one or more data media interfaces. System memory 28 may include at least one program product having a set (e.g., at least one) of program modules configured to perform the functions of the embodiments of the present invention.

[0107] A program / utility 40 having a set (at least one) of program modules 42 may be stored, for example, in system memory 28. Such program modules 42 include, but are not limited to, an operating system, one or more application programs, other program modules, and program data. Each or some combination of these examples may include an implementation of a network environment. Program modules 42 typically perform the functions and / or methods described in the embodiments of the present invention.

[0108] Device 12 can also communicate with one or more external devices 14 (e.g., keyboard, pointing device, display 24, etc.), and with one or more devices that enable a user to interact with the device 12 / server / computer, and / or with any device that enables the device 12 to communicate with one or more other computing devices (e.g., network card, modem, etc.). This communication can be performed via input / output (I / O) interface 22. Furthermore, device 12 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) via network adapter 20. Figure 8 As shown, network adapter 20 communicates with other modules of device 12 via bus 18. It should be understood that, although... Figure 8 As not shown, other hardware and / or software modules can be used in conjunction with device 12, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0109] The processing unit 16 executes various functional applications and data processing by running programs stored in the system memory 28, such as implementing the zero-sequence current suppression method for open-winding dual two-level inverters provided in this embodiment of the invention.

[0110] Example 4

[0111] Embodiment 4 of the present invention also provides a storage medium containing computer-executable instructions, which, when executed by a computer processor, are used to perform the zero-sequence current suppression method for an open-winding dual two-level inverter as provided in the above embodiments.

[0112] The computer storage medium of this invention can be any combination of one or more computer-readable media. A computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of computer-readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this document, a computer-readable storage medium can be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0113] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. Computer-readable signal media may also be any computer-readable medium other than computer-readable storage media, capable of sending, propagating, or transmitting programs for use by or in connection with an instruction execution system, apparatus, or device.

[0114] Program code contained on a computer-readable medium may be transmitted using any suitable medium, including—but not limited to—wireless, wire, optical fiber, RF, etc., or any suitable combination thereof.

[0115] Computer program code for performing the operations of this invention can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as "C" or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0116] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A method for suppressing zero-sequence current in an open-winding dual two-level inverter, characterized in that, include: S101: Collect the three-phase current of the open-winding motor and calculate the zero-sequence current; calculate the zero-sequence voltage based on proportional resonance regulation. S102, superimposes the zero-sequence voltage with the three-phase voltage output from the dual closed-loop control of the motor to form a three-phase reference voltage; S103 converts the three-phase reference voltage to a two-phase stationary coordinate system, and divides the voltage space into sectors based on the phase angle of the three-phase reference voltage and determines the current sector. S104, perform per-unit processing on the three-phase reference voltage and zero-sequence voltage. The per-unit range is -1 to 1. According to the current sector, extract the phase voltage of the maximum conducting phase corresponding to the per-unit three-phase reference voltage. The phase voltage of the maximum conducting phase is the phase with the largest absolute value among the three-phase reference voltages. S105: Based on the extracted phase voltage and zero-sequence voltage of the maximum conducting phase and the preset pulse position offset coefficient k, determine the maximum modulation range, calculate the power device turn-on and turn-off time data, and form a drive pulse signal. The formula for the maximum modulation range is expressed as follows: ,in This indicates the voltage of the maximum conducting phase after the per-unit designation. The maximum modulation range is zero-sequence voltage. The maximum modulation range is compared with the 0~1 interval to determine if it exceeds the range. If it does not exceed the 0~1 interval, the first formula group is used to calculate the power device turn-on and turn-off times. If it exceeds the 0~1 interval, the second formula group is used to calculate the power device turn-on and turn-off times to form a drive pulse signal. The first set of formulas is: The second set of formulas is: Where k represents the pulse position offset coefficient, which is used to continuously adjust the offset of the voltage pulses of the phase voltage of the second conducting phase and the phase voltage of the last conducting phase on the time axis. , , These represent the phase voltages of the maximum conducting phase M, the second conducting phase F, and the last conducting phase L, respectively. , , These represent the four key switching times for the three phases, and ; Indicates the end time of a carrier cycle; This represents the zero-sequence voltage per unit. , These are the upper arm power devices for the two inverters. The conduction time is from arrive , The conduction time is from arrive ,and .

2. The method according to claim 1, characterized in that, S103 includes: The three-phase reference voltage is converted to the α-β two-phase stationary coordinate system based on the Clarke transform, and the phase angle θ of the three-phase reference voltage is calculated, with the phase angle ranging from 0 to 2π. Based on the phase angle θ of the three-phase reference voltage, the voltage space is divided into 6 sectors with π / 3 as a sector, and the current sector is determined. Based on the sector division results, the three-phase reference voltages are mapped to the maximum conducting phase M, the second conducting phase F, and the last conducting phase L, respectively. The voltage of the maximum conducting phase is the phase with the largest absolute value among the three-phase reference voltages. The second conducting phase and the last conducting phase are determined according to the order of conduction. The voltage polarity of the second conducting phase and the last conducting phase is opposite to that of the maximum conducting phase.

3. The method according to claim 1, characterized in that, The drive pulse signal is generated based on the turn-on and turn-off times of the power device, including: Based on the current sector and the phase voltage of the corresponding maximum conducting phase M, the phase voltage of the second conducting phase F, and the phase voltage of the last conducting phase L, determine the corresponding power device. Based on the turn-on and turn-off times of the power devices and the corresponding power devices, a drive pulse signal is generated to drive the corresponding power devices to turn on or off.

4. The method according to claim 1, characterized in that, The S105 further includes: The preset pulse position offset coefficient k ranges from 0 to 1. It is determined based on the per-unit ratio of the phase mutual inductance coefficient and the phase self-inductance coefficient of the open-winding motor, as well as the desired current ripple suppression degree. It is used to continuously adjust the offset of the voltage pulse on the time axis of the phase voltage of the second conducting phase F and the phase voltage of the last conducting phase L.

5. The method according to claim 1, characterized in that, The S105 further includes: The preset drive pulse signal is configured such that, within one carrier cycle, the voltage pulse polarity of the phase voltage of the maximum conducting phase M is opposite to the voltage pulse polarity of the phase voltage of the second conducting phase F and the phase voltage of the last conducting phase L, and the voltage pulses of the phase voltage of the second conducting phase F and the phase voltage of the last conducting phase L do not overlap or partially overlap in time, so that the rate of change of the three-phase current is not simultaneously positive or not simultaneously negative.

6. A zero-sequence current suppression device for an open-winding dual two-level inverter, used to implement the zero-sequence current suppression method for an open-winding dual two-level inverter as described in any one of claims 1-5, characterized in that, include: The current acquisition module is used to acquire the three-phase current of the open-winding motor and calculate the zero-sequence current and the zero-sequence voltage based on proportional resonance regulation. The reference voltage calculation module is used to superimpose the zero-sequence voltage and the three-phase voltage to form a three-phase reference voltage. The sector partitioning module is used to convert the three-phase reference voltage to a two-phase stationary coordinate system and divide the voltage space into sectors based on the phase angle of the three-phase reference voltage, and determine the current sector. The voltage per-unit module is used to perform per-unit processing on the three-phase reference voltage and zero-sequence voltage within the range of -1 to 1, and extract the phase voltage of the maximum conducting phase from the per-unit three-phase reference voltage according to the current sector. The drive pulse module is used to determine the maximum modulation range based on the extracted phase voltage of the maximum conducting phase, the zero-sequence voltage, and the preset pulse position offset coefficient k. The maximum modulation range is compared with the 0~1 interval to determine if it exceeds the range. If it does not exceed the 0~1 interval, the first formula group is used to calculate the power device turn-on and turn-off times. If it exceeds the 0~1 interval, the second formula group is used to calculate the power device turn-on and turn-off time data to form a drive pulse signal.

7. An electronic device, characterized in that, The device includes: One or more processors; Storage device for storing one or more programs. When the one or more programs are executed by the one or more processors, the one or more processors implement the zero-sequence current suppression method for an open-winding dual two-level inverter as described in any one of claims 1-5.

8. A storage medium containing computer-executable instructions, which, when executed by a computer processor, are used to perform the zero-sequence current suppression method for an open-winding dual two-level inverter as described in any one of claims 1-5.

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