A frequency source with mixing interpolation and its implementation method

Abstract

The application discloses a frequency source of mixed frequency interpolation and an implementation method thereof, and relates to the technical field of radar communication; the frequency source comprises a reference clock, a DDS, a VCO, a frequency mixer, an active N frequency multiplier, a voltage-controlled filter, a 1 / N frequency divider and a FPGA controller. In the initial stage of frequency switching, the FPGA controller controls a radio frequency switch to access the active N frequency multiplier link, simultaneously N multiplies the target frequency fo and the mirror frequency fy+fx, suppresses the mirror frequency by using the voltage-controlled filter, and then recovers fo by the 1 / N frequency division to complete the error-free lock capture; after locking, the straight-through path is switched to and the frequency multiplier power supply is disconnected. The application effectively prevents the error lock, does not introduce additional phase noise and spurs in the steady state operation, and realizes high-performance frequency synthesis.

Description

Technical Field

[0001] This invention belongs to the field of frequency synthesis technology, specifically, it relates to a frequency source with mixing interpolation and its implementation method. Background Technology

[0002] Frequency sources, as the core signal generation unit of electronic systems, are widely used in key fields such as radar, communication, measurement and control, electronic countermeasures, and navigation. With the ever-increasing performance requirements of modern electronic systems, frequency sources need to achieve a balance between multiple indicators, including miniaturization, ultra-wideband, low phase noise, low spurious emissions, high frequency stability, fine frequency stepping, frequency agility, and fast startup. These indicators are often mutually restrictive and difficult to optimize simultaneously. Currently, mainstream frequency synthesis technologies mainly include phase-locked loop (PLL) type, direct digital frequency synthesis (DDS) type, and DDS-excited PLL schemes. While PLL structures possess good phase noise performance and high-frequency output capability, their frequency resolution is limited, making it difficult to achieve fine-step frequency hopping. DDS, although capable of extremely fine frequency stepping and fast switching, is limited by the operating bandwidth and nonlinear characteristics of the digital-to-analog converter (DAC), resulting in weak high-frequency output capability, poor spurious suppression, and its inherent phase truncation and quantization errors further deteriorate the output signal quality. If the DDS is used directly to excite the PLL, the spurious and phase noise in the DDS output will be transmitted or even amplified by the PLL loop, which will seriously affect the purity of the final output signal.

[0003] To address these shortcomings, a mixing interpolation phase-locked loop (PLL) was developed. However, with wideband mixing interpolation PLLs, the output frequency mirror frequency of the PLL falls within the output frequency band of the VCO, which can lead to frequency mislocking.

[0004] To address the issue of mislocking, traditional broadband mixing phase-locked loops employ a broadband voltage-controlled oscillator (VCO) with a DAC for capture. However, due to the poor output noise of the DAC, this noise is directly superimposed on the VCO output, leading to a deterioration of the output phase noise when using the DAC capture method.

[0005] Chinese patent CN117411478A discloses a low-phase-noise mixer phase-locked loop (PLL) circuit with anti-mislocking function. The anti-mislocking method is as follows: After the product is powered on, the reference signal provided by the crystal oscillator gradually stabilizes. To prevent logic errors and abnormal power-on timing, the main controller needs to be reset once, reloading the programmed code. Then, according to usage requirements, the final output frequency is set. Next, control commands are sequentially sent to PLS1, PLS2, the switching filter bank, the DDS unit, and the PLL phase-locked loop. After the output signal is locked, the main controller checks for mislocking. If mislocking occurs, the control command for the PLL phase-locked loop is sent again, and the PLL register configuration is reconfigured for correction until the lock is correct. This patent relies on reconfiguring the PLL register configuration for correction, but it does not eliminate the mirror frequency. Reconfiguring the registers does not guarantee a second lock; it is possible that the second lock will fail, the third lock will fail, and so on, potentially causing a software dead loop and control paralysis. Summary of the Invention

[0006] The purpose of this invention is to provide a frequency source with interpolation mixing, which mainly solves the problem of mislocking caused by the image frequency falling into the tuning band of the voltage-controlled oscillator (VCO) during the broadband tuning process of existing frequency sources with interpolation mixing.

[0007] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0008] A frequency source with mixing and interpolation capabilities includes:

[0009] FPGA controller, used for operating control of frequency source circuit;

[0010] The reference clock, after being split into two paths by the first power divider, provides two reference clock signals for the frequency source.

[0011] A phase-locked loop (PLL) enables the frequency and phase of the output signal to accurately track the input reference signal.

[0012] The DDS circuit receives a reference clock signal from the first power divider and processes it to provide a clock signal for the phase-locked loop.

[0013] The mixer circuit receives another reference clock signal from the first power divider and, after mixing, provides a loopback signal for the phase-locked loop.

[0014] The error-prevention lockout circuit receives one signal from the phase-locked loop (PLL) output after it has been divided by the second power divider. This signal is used to prevent the PLL from erroneously locking to a non-target frequency. The other output signal from the second power divider is output externally.

[0015] Furthermore, in this invention, the DDS circuit includes a DDS clock generation unit and a DDS unit; wherein the DDS clock generation unit receives one reference clock signal from the first power divider and generates a high-frequency reference clock signal required by the DDS unit, and the DDS generates an adjustable low-frequency reference clock signal based on the high-frequency reference clock signal as a reference input for the phase-locked loop.

[0016] Furthermore, in this invention, the phase-locked loop includes a phase detector, a loop filter, and a voltage-controlled oscillator (VCO). The phase detector receives an adjustable low-frequency reference clock signal from the DDS unit at its reference signal input terminal and outputs a differential signal to the loop filter. The differential signal is filtered and amplified by the loop filter to generate a VCO control voltage Vt. The control voltage Vt adjusts the output frequency of the VCO, forming a negative feedback control loop, ultimately achieving phase locking between the output signal and the reference signal.

[0017] Furthermore, in this invention, the error-proof lockout circuit includes a first radio frequency switch, an active N-frequency multiplier, an analog switch, a voltage-controlled filter, and a second operational amplifier. The system consists of a frequency divider, a second RF switch, a digital-to-analog converter (DAC), and resistors R6-R8. The two switching terminals of the first RF switch are respectively connected to one switching terminal of the second RF switch and one output terminal of the second power divider. The input terminal of the active N-multiplier is connected to one freely switching terminal of the analog switch. The fixed terminal of the analog switch is connected to the power supply, and the other freely switching terminal is grounded through resistor R6. A voltage-controlled filter is connected to the active N-multiplier. The second operational amplifier, resistors R7 and R8 together form an operational amplifier circuit to adjust the amplification factor to M times. The DAC is connected to the non-inverting input terminal of the second operational amplifier and is controlled by the FPGA controller. The frequency divider converts the frequency back to the output signal frequency of the second power divider after frequency division. The other freely switching terminal of the second RF switch is connected to… The output of the frequency divider is connected, and the fixed terminal of the second RF switch is connected to the mixer circuit.

[0018] Furthermore, in this invention, the mixing circuit includes a mixer whose RF input terminal is connected to the fixed terminal of the second RF switch, a mixing local oscillator circuit connected to the local oscillator input terminal of the mixer, a low-pass filter connected to the intermediate frequency output terminal of the mixer, and a first amplifier connected to the low-pass filter; wherein, the mixing local oscillator circuit receives another reference clock signal from the first power divider; and the output terminal of the first amplifier is connected to the RF input terminal of the phase detector.

[0019] Furthermore, in this invention, the mixing local oscillator circuit includes a harmonic generator, a switching filter, and a second amplifier connected in sequence; wherein the harmonic generator uses another reference clock signal received from the first power divider as a reference to obtain multiple harmonic signals by frequency multiplication; the switching filter selects the frequency of the multiple harmonic signals according to the setting to obtain a low phase noise local oscillator signal, which is then amplified by the second amplifier and sent to the local oscillator input terminal of the mixer.

[0020] Based on the above-mentioned frequency source with mixing and interpolation, the present invention also provides a method for implementing the frequency source with mixing and interpolation, comprising the following steps:

[0021] S1, after the reference clock signal is input, it is divided into two completely identical reference clock signals by the first power divider and sent to the DDS circuit and the mixer circuit respectively.

[0022] S2, the DDS circuit generates a phase-locked loop reference signal, which serves as the reference input signal for the phase detector of the phase-locked loop;

[0023] S3, the second reference clock enters the mixer circuit, and after being mixed with the phase-locked loop output signal and judged by the error prevention lock, it generates a loopback signal and feeds it back to the phase detector of the phase-locked loop to participate in phase comparison and loop adjustment;

[0024] S4, the phase-locked loop achieves phase locking, ultimately realizing precise phase locking between the output signal and the reference signal.

[0025] Furthermore, in step S3, the process for determining the error-proof lock is as follows:

[0026] S31, the first RF switch selects the output signal to the active N-frequency multiplier for frequency multiplication;

[0027] S32, the frequency multiplier selects the power supply through an analog switch controlled by the FPGA controller, multiplies the input signal, and then enters the voltage-controlled filter. The FPGA controller outputs a control signal to the non-inverting input of the second operational amplifier through a digital-to-analog converter. The operational amplifier outputs power to control the voltage-controlled filter for filtering.

[0028] S33, the filtered signal is amplified by the operational amplifier circuit and then sent to the ÷N frequency divider for frequency division;

[0029] S34, the frequency-divided signal passes through the second RF switch and is selected to be output to the mixer to participate in mixing and form an internal loop;

[0030] When the lock indicator of the FPGA monitoring phase detector is high (S35), it indicates that the phase-locked loop has locked to the target frequency. The FPGA controls the output signal of the first RF switch to the input of the second RF switch to suppress image frequency interference and prevent the phase-locked loop from locking to a non-target frequency. It also controls the analog switch to select ground and de-energizes the frequency multiplier to prevent the output signal from introducing frequency multiplication spurious signals.

[0031] Compared with the prior art, the present invention has the following beneficial effects:

[0032] (1) This invention introduces an active N-multiplier-voltage-controlled filter-÷N divider link in the early stage of frequency switching, multiplying the target frequency and the image frequency signal by N times at the same time, so that the frequency gap between the two is increased by N times (e.g., when N=4, the gap between 2100MHz and 2700MHz increases from 600MHz to 2400MHz), which breaks through the bandwidth limitation of the voltage-controlled filter and can achieve a deep suppression of the image frequency of >40dB; after the target frequency is recovered by frequency division, phase locking is completed, which eliminates the possibility of the phase-locked loop accidentally locking to the image frequency from the physical level, and solves the core technical pain point of broadband mixing interpolation frequency source.

[0033] (2) After the phase-locked loop of the present invention is locked, the FPGA automatically controls the RF switch to switch to the low-loss through path and disconnects the power supply of the active N-frequency multiplier: the feedback link only inserts the RF switch with a loss of <0.5dB, and no nonlinear active devices introduce additional phase noise and spurious signals; the frequency multiplier completely stops working after power-off, and does not generate harmonics, intermodulation or thermal noise, so that the phase noise of the output signal is determined only by the core devices such as VCO and phase detector, achieving the best performance level among similar solutions.

[0034] (3) The present invention does not require the use of DAC preset VCO frequency anti-error lock method, which completely eliminates the phase noise degradation caused by the direct superposition of DAC output noise to VCO; at the same time, it abandons the error correction mechanism that relies on repeated software configuration of registers, avoids reliability problems such as software dead loop and control paralysis, and improves the system response speed by more than 30%. It is suitable for scenarios with strict requirements for signal purity and reliability, such as radar and electronic countermeasures.

[0035] (4) The error prevention lock mechanism of the present invention is only briefly activated in the initial stage of frequency switching (typical time <10ms). After locking, it automatically bypasses the frequency multiplier link and shuts down the power supply of the frequency multiplier. There is no additional power consumption during steady-state operation. The FPGA can automatically complete the link switching and parameter configuration according to the frequency control code, support millisecond-level frequency agility, and the entire process does not require manual intervention, taking into account both high performance and intelligent requirements. Attached Figure Description

[0036] Figure 1 This is the circuit schematic diagram of the present invention.

[0037] Figure 2This is a diagram illustrating the frequency source implementation method in this invention.

[0038] Figure 3 This is a flowchart of the error-prevention lock judgment process in this invention. Detailed Implementation

[0039] The present invention will be further described below with reference to the accompanying drawings and embodiments. The embodiments of the present invention include, but are not limited to, the following embodiments.

[0040] like Figure 1 As shown, this invention discloses a frequency source with a mixing interpolation. This embodiment takes an output frequency fo = 2100 MHz as an example to illustrate in detail how the system completes the error prevention lock-in process after receiving the frequency control code, and finally achieves a stable output with low phase noise and low spurious emissions.

[0041] When an external input frequency control code requires the frequency source to output a signal fo = 2100 MHz, the FPGA first determines the required local oscillator frequency fy and loopback frequency fx according to a pre-stored mapping table. In this example, the DDS output reference frequency is set to fx = 300MHz, the harmonic generator generates higher harmonics based on a 100 MHz reference clock, and the output signal fy = 2400MHz is selected by a switching filter. Since the mixer uses a down-conversion structure, i.e., fx = fy - fo, then fo = fy - fx = 2400 MHz - 300 MHz = 2100 MHz, which meets the target output. However, the VCO (voltage-controlled oscillator) tuning range covers f1~f2 = 2100MHz~2700 MHz, and the mirror frequency signal fmirror = fy + fx = 2400 MHz + 300 MHz = 2700 MHz happens to fall within the VCO frequency band. If it directly enters the phase-locked loop feedback path, there is a risk that the phase-locked loop may be mistakenly locked to 2700 MHz.

[0042] like Figure 2 As shown, to avoid this problem, this invention introduces a fault-prevention lockout circuit. The FPGA controls the analog switch to turn on, supplying power to the active N-multiplier. In this embodiment, N = 4. Since 2100 MHz × 4 = 8400 MHz and 2700 MHz × 4 = 10800 MHz, the interval between the two is 2400 MHz, which is much larger than the effective suppression bandwidth of the voltage-controlled filter (typically 500 MHz), ensuring that the image frequency is effectively filtered out. Subsequently, the FPGA controls the first RF switch (i.e., Figure 1 RF switch 1) and second RF switch (i.e. Figure 1 The RF switch 2) in the middle is switched to the active N-multiplier link. At this time, the VCO output signal is switched through the second power divider (i.e., Figure 1The power divider 2) has one output to the outside and the other enters the active N frequency multiplier through RF switch 1. After frequency multiplication, the output contains a composite signal of 8400 MHz (target) and 10800 MHz (image frequency).

[0043] Next, the FPGA calculates N·fo = 8400 MHz based on the target frequency fo = 2100 MHz, and consults the internally stored voltage-frequency mapping table of the voltage-controlled filter to determine the control voltage V required to align the passband center of the voltage-controlled filter to 8400 MHz. This voltage V needs to be passed through the second operational amplifier (i.e., Figure 1 The amplified voltage is applied to the voltage-controlled filter after being amplified by op-amp 2. Op-amp 2, resistors R7 and R8 form an inverting or non-inverting amplification structure. The gain is set to M = R8 / R7 (for example, M = 2). Therefore, the output voltage of the digital-to-analog converter controlled by the FPGA is V / M. After being amplified by op-amp 2, the accurate value of V is obtained, which drives the voltage-controlled filter to set its passband to 8400 MHz and its stopband to cover the 10800 MHz region.

[0044] After being filtered by a voltage-controlled filter, the 10800 MHz image frequency is strongly suppressed (typical suppression >40 dB), retaining only the pure 8400 MHz signal. This signal is fed into a ÷N divider (N=4), and after division, it is restored to a 2100 MHz signal, which is then sent to the RF port of the mixer as a feedback signal without image frequency interference. Simultaneously, the 2400 MHz signal output from the harmonic generator is selected by a switching filter and then amplified by a second amplifier (i.e.,...). Figure 1 Amplified by amplifier 2), the signal is used as the local oscillator signal fy and input to the LO port of the mixer. The mixer outputs an intermediate frequency signal fx = |fy - f_RF| = |2400 - 2100| = 300 MHz. This signal is filtered by a low-pass filter to remove high-frequency components (such as 2100 MHz, 2400 MHz and their combinations), and then amplified by the first amplifier (i.e., Figure 1 Amplifier 1) amplifies the signal to the power level required by the phase detector (e.g., 0 dBm) and sends it to the second input of the phase detector. The DDS unit outputs a 300 MHz signal driven by the DDS clock generation circuit (multiplied to 1.2 GHz by a phase-locked loop from a 100 MHz reference) as the reference signal for the first input of the phase detector.

[0045] A phase detector (such as HMC3716LP4E) compares the phases of two 300 MHz signals, and the output error voltage passes through capacitors C1-C5, resistors R1-R5, and the first operational amplifier (i.e., Figure 1The operational amplifier 1) forms a fifth-order active loop filter to generate a smooth tuning voltage to control the VCO frequency. The loop continues to adjust until the VCO output stabilizes at 2100 MHz and the phase detector output lock-in indicator signal goes high. The FPGA continuously monitors this lock-in indicator signal through its GPIO pins. Once a high level is detected, it confirms that the phase-locked loop has stably locked to the target frequency. Then, it controls RF switch 1 and RF switch 2 to switch back to the direct path, so that the VCO output signal is directly sent to the RF terminal of the mixer through RF switch 1 and RF switch 2; at the same time, it controls the analog switch to open, cutting off the power supply to the active N-multiplier.

[0046] During steady-state operation, the feedback path contains only RF switch 1 and RF switch 2. Since the selected RF switches have an insertion loss of less than 0.5 dB, isolation greater than 40 dB, and no nonlinear active devices are involved, no additional phase noise or spurious signals are introduced. The active N-multiplier is completely de-energized after locking, generating no harmonics, intermodulation, or thermal noise, thus ensuring that the phase noise performance of the output signal is determined solely by the VCO, phase detector, and loop filter, achieving optimal levels. Furthermore, since the entire error-proof locking mechanism is only briefly activated during the initial locking phase, and the multiplier-filter-divider path is physically bypassed after locking, the final output quality is not affected by the non-ideal characteristics of the multiplier (such as amplitude imbalance or phase distortion).

[0047] In this embodiment, all module parameters are managed uniformly by the FPGA: the channel selection of the switching filter, the DDS frequency word configuration, the output voltage of the digital-to-analog converter, the RF switch status, and the analog switch enable signal are all automatically calculated and configured based on the input frequency control code. For example, when the frequency control code changes to require an output fo = 2300 MHz, the FPGA recalculates fy = 2600 MHz (fx remains 300 MHz), with a mirror frequency of 2900 MHz. If this is still within the VCO range, the N=4 multiplication path is activated, the voltage-controlled filter is tuned to 9200 MHz, and after frequency division, it recovers to 2300 MHz, completing error-free lock-on acquisition. The entire process requires no manual intervention and does not rely on a high-noise DAC for VCO preset, avoiding the phase noise degradation caused by DAC noise directly modulating the VCO in traditional solutions.

[0048] In summary, this invention dynamically introduces a temporary frequency multiplication-filtering-frequency division link into the phase-locked loop (PLL) feedback path. During the initial frequency switching phase, the frequency multiplication expands the gap between the target frequency and the image frequency, enabling the voltage-controlled filter to effectively suppress the image frequency and ensuring that the PLL locks only the target frequency. After locking is complete, it automatically switches to a low-loss direct path and shuts down the frequency multiplier power supply. This results in the system ultimately requiring only two additional RF switches, completely eliminating the risk of mis-locking while maintaining optimal phase noise and spurious performance. This invention is suitable for applications such as radar and electronic countermeasures, where stringent requirements for frequency agility, reliability, and signal purity are necessary.

[0049] The above embodiments are merely one of the preferred embodiments of the present invention and should not be used to limit the scope of protection of the present invention. Any modifications or refinements made to the main design concept and spirit of the present invention that are not of substantial significance, but solve the same technical problem as the present invention, should be included within the scope of protection of the present invention.

Claims

1. A frequency source with mixing and interpolation, characterized in that, include: FPGA controller, used for operating control of frequency source circuit; The reference clock, after being split into two paths by the first power divider, provides two reference clock signals for the frequency source. A phase-locked loop (PLL) enables the frequency and phase of the output signal to accurately track the input reference signal. The DDS circuit receives a reference clock signal from the first power divider and processes it to provide a clock signal for the phase-locked loop. The mixer circuit receives another reference clock signal from the first power divider and, after mixing, provides a loopback signal for the phase-locked loop. The error-prevention lockout circuit receives one signal from the phase-locked loop (PLL) output after being divided by a second power divider, to prevent the PLL from erroneously locking to a non-target frequency; the other output signal from the second power divider is output externally. The error-prevention lockout circuit includes a first RF switch, an active N-multiplier, an analog switch, a voltage-controlled filter, and a second operational amplifier. The system consists of a frequency divider, a second RF switch, a digital-to-analog converter (DAC), and resistors R6-R8. The fixed terminal of the first RF switch is connected to one output of the second power divider. The two switching terminals of the first RF switch are respectively connected to one switching terminal of the second RF switch and one input of an active N-multiplier. The other input of the active N-multiplier is connected to one freely switching terminal of the analog switch. The fixed terminal of the analog switch is connected to a power supply, and the other freely switching terminal is grounded via resistor R6. A voltage-controlled filter is connected to the active N-multiplier. The second operational amplifier, resistors R7 and R8 together form an operational amplifier circuit to adjust the amplification factor to M. The DAC is connected to the non-inverting input of the second operational amplifier and is controlled by an FPGA controller. The frequency divider converts the frequency back to the output signal frequency of the second power divider after frequency division. The other freely switching terminal of the second RF switch is connected to… The output of the frequency divider is connected, and the fixed terminal of the second RF switch is connected to the mixer circuit.

2. The frequency source with mixing and interpolation according to claim 1, characterized in that, The DDS circuit includes a DDS clock generation unit and a DDS unit; wherein the DDS clock generation unit receives one reference clock signal from the first power divider and generates a high-frequency reference clock signal required by the DDS unit, and the DDS generates an adjustable low-frequency reference clock signal based on the high-frequency reference clock signal as the reference input of the phase-locked loop.

3. A frequency source with mixing and interpolation according to claim 2, characterized in that, The phase-locked loop includes a phase detector, a loop filter, and a voltage-controlled oscillator (VCO). The phase detector receives an adjustable low-frequency reference clock signal from the DDS unit at its reference signal input terminal and outputs a differential signal to the loop filter. The differential signal is filtered and amplified by the loop filter to generate a VCO control voltage Vt. The control voltage Vt adjusts the output frequency of the VCO, forming a negative feedback control loop, and ultimately achieving phase locking between the output signal and the reference signal.

4. A frequency source with mixing and interpolation according to claim 3, characterized in that, The mixing circuit includes a mixer whose RF input is connected to the fixed terminal of the second RF switch, a mixing local oscillator circuit connected to the local oscillator input of the mixer, a low-pass filter connected to the intermediate frequency output of the mixer, and a first amplifier connected to the low-pass filter; wherein the mixing local oscillator circuit receives another reference clock signal from the first power divider; the output of the first amplifier is connected to the RF input of the phase detector.

5. A frequency source with mixing and interpolation according to claim 4, characterized in that, The mixing local oscillator circuit includes a harmonic generator, a switching filter, and a second amplifier connected in sequence. The harmonic generator uses another reference clock signal from the first power divider as a reference and obtains multiple harmonic signals by frequency multiplication. The switching filter selects the frequency of the multiple harmonic signals according to the settings to obtain a low phase noise local oscillator signal, which is then amplified by the second amplifier and sent to the local oscillator input of the mixer.

6. A method for implementing a frequency source using a mixing interpolation method, characterized in that, The frequency source employing the mixing interpolation method as described in claim 5 includes the following steps: S1, after the reference clock signal is input, it is divided into two completely identical reference clock signals by the first power divider and sent to the DDS circuit and the mixer circuit respectively. S2, the DDS circuit generates a phase-locked loop reference signal, which serves as the reference input signal for the phase detector of the phase-locked loop; S3, the second reference clock enters the mixer circuit, and after being mixed with the phase-locked loop output signal and judged by the error prevention lock, it generates a loopback signal and feeds it back to the phase detector of the phase-locked loop to participate in phase comparison and loop adjustment; S4, the phase-locked loop achieves phase locking, ultimately realizing precise phase locking between the output signal and the reference signal.

7. The method for implementing a frequency source with mixing interpolation according to claim 6, characterized in that, In step S3, the process for determining the error-proof lock is as follows: S31, the first RF switch selects the output signal to the active N-frequency multiplier for frequency multiplication; S32, the frequency multiplier selects the power supply through an analog switch controlled by the FPGA controller, multiplies the input signal, and then enters the voltage-controlled filter. The FPGA controller outputs a control signal to the non-inverting input of the second operational amplifier through a digital-to-analog converter. The operational amplifier outputs power to control the voltage-controlled filter for filtering. S33, the filtered signal is amplified by the operational amplifier circuit and then sent to the ÷N frequency divider for frequency division; S34, the frequency-divided signal passes through the second RF switch and is selected to be output to the mixer to participate in mixing and form an internal loop; When the lock indicator of the FPGA monitoring phase detector is high (S35), it indicates that the phase-locked loop has locked to the target frequency. The FPGA controls the output signal of the first RF switch to the input of the second RF switch to suppress image frequency interference and prevent the phase-locked loop from locking to a non-target frequency. It also controls the analog switch to select ground and de-energizes the frequency multiplier to prevent the output signal from introducing frequency multiplication spurious signals.

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