Semiconductor device

Abstract

The invention provides a semiconductor device which is applied to the technical field of semiconductors. According to the semiconductor device, the first insulating plug is arranged between the first bit line and the second bit line, so that a new semiconductor device structure is formed.

Description

[0001] This invention is a divisional application of the invention application with application number "202510058388.9", application date "January 14, 2025", and application title "A Semiconductor Device". Technical Field

[0002] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device. Background Technology

[0003] With the trend towards miniaturization in various electronic products, the design of semiconductor devices must also meet the requirements of high integration and high density. For Dynamic Random Access Memory (DRAM) with a recessed gate structure, it can achieve a longer carrier channel length within the same semiconductor substrate, reducing leakage current caused by capacitor structures. Therefore, under the current mainstream development trend, it has gradually replaced DRAM with only planar gate structures. Generally, DRAM with a recessed gate structure consists of a large number of memory cells arranged in an array to store information. Each memory cell can be composed of transistor components and capacitor components connected in series to receive voltage information from the word line (WL) and bit line (BL). Therefore, existing technologies or structures still need further improvement to effectively enhance the performance and reliability of related memory devices. Summary of the Invention

[0004] The purpose of this invention is to provide a new structure for semiconductor devices to improve their performance and reliability.

[0005] In a first aspect, to solve the above-mentioned technical problems, one embodiment of the present invention provides a semiconductor device, comprising:

[0006] The substrate includes an active region and a shallow trench isolation region adjacent to the active region;

[0007] Multiple bit lines, including multiple first bit lines and at least one second bit line disposed on the substrate and spaced apart from each other, the at least one second bit line being disposed outside all the first bit lines;

[0008] Contact holes are located within the substrate;

[0009] The bit line contact is located inside the contact hole, with its bottom contacting the active area and its top contacting the first bit line;

[0010] The sidewall layer includes a sidewall layer located on both sides of the first bit line and a sidewall layer located inside the contact hole;

[0011] The first conductive plug is located between adjacent first bit lines, and the first conductive plug is also electrically connected to the active region.

[0012] A first insulating plug is located between adjacent first bit lines and second bit lines, wherein in the vertical direction, the first insulating plug overlaps with the projection of the sidewall layer located within the contact hole onto the substrate.

[0013] Secondly, based on the same inventive concept, another embodiment of the present invention provides a semiconductor device, comprising:

[0014] The substrate includes an active region and a shallow trench isolation region adjacent to the active region;

[0015] Multiple bit lines, including multiple first bit lines and at least one second bit line disposed on the substrate and spaced apart from each other, the at least one second bit line being disposed outside all the first bit lines;

[0016] Contact holes are located within the substrate;

[0017] The bit line contact is located inside the contact hole, with its bottom contacting the active area and its top contacting the first bit line;

[0018] The sidewall layer includes a sidewall layer located on both sides of the first line and a sidewall layer located inside the contact hole;

[0019] The first conductive plug is located between adjacent first bit lines, and the first conductive plug is also electrically connected to the active region.

[0020] A first insulating plug is located between adjacent first bit lines and second bit lines, wherein in the vertical direction, the first insulating plug overlaps with the projection of the sidewall layer located in the contact hole onto the substrate;

[0021] The first insulating plug is electrically insulated from the active area.

[0022] Thirdly, based on the same inventive concept, another embodiment of the present invention provides a semiconductor device, comprising:

[0023] The substrate includes an active region and a shallow trench isolation region adjacent to the active region;

[0024] Multiple bit lines, including multiple first bit lines and at least one second bit line disposed on the substrate and spaced apart from each other, the at least one second bit line being disposed outside all the first bit lines;

[0025] Contact holes are located within the substrate;

[0026] The bit line contact is located inside the contact hole, with its bottom contacting the active area and its top contacting the first bit line;

[0027] A first insulating plug, the bottom of which is located inside the contact hole and directly contacts the active area.

[0028] Fourthly, based on the same inventive concept, another embodiment of the present invention provides a semiconductor device, comprising:

[0029] The substrate includes an active region and a shallow trench isolation region adjacent to the active region;

[0030] Multiple bit lines, including multiple first bit lines and at least one second bit line disposed on the substrate and spaced apart from each other, the at least one second bit line being disposed outside all the first bit lines;

[0031] Contact holes are located within the substrate;

[0032] The bit line contact is located inside the contact hole, with its bottom contacting the active area and its top contacting the first bit line;

[0033] A first insulating plug, the bottom of which is located within the contact hole, and the bottom surface of the first insulating plug being lower than the top surface of the substrate.

[0034] Fifthly, based on the same inventive concept, another embodiment of the present invention provides a semiconductor device, comprising:

[0035] The substrate includes an active region and a shallow trench isolation region adjacent to the active region;

[0036] Multiple bit lines, including multiple first bit lines and at least one second bit line disposed on the substrate and spaced apart from each other, the at least one second bit line being disposed outside all the first bit lines;

[0037] Contact holes are located within the substrate;

[0038] The bit line contact is located inside the contact hole, with its bottom contacting the active area and its top contacting the first bit line;

[0039] The first insulating plug includes

[0040] The first part is located inside the contact hole;

[0041] The second part is located on the first part and is situated between the adjacent first bit line and the second bit line;

[0042] The first part is in direct contact with the bit line contact.

[0043] As described above, in the semiconductor device provided by the present invention, the first insulating plug located between the first bit line and the second bit line may include two parts, wherein the first part fills the contact hole (inside the substrate) where the bit line plug is located below the first bit line adjacent to the second bit line or further directly contacts the sidewall layer remaining in the contact hole, and the second part is located on the first part (on the substrate) and between the adjacent first bit line and the second bit line, thereby forming a new structure of the semiconductor device in which the first insulating plug is located between the first bit line and the second bit line and its part is also in direct contact with the bit line plug and the sidewall layer. Attached Figure Description

[0044] The accompanying drawings are provided to further illustrate the present application and form part of the specification. They are used together with the following detailed description to explain the present application, but do not constitute a limitation thereof. In the drawings:

[0045] Figures 1-20 This is a schematic diagram of the semiconductor device provided in the embodiment of the present invention during the fabrication process.

[0046] The attached figures are labeled as follows:

[0047] 100 - Substrate; AR - Active region; 110 - Shallow trench isolation region; 120 - Isolation layer; 130 - Bit line material layer; 131 - Semiconductor layer; 132 - Barrier layer; 133 - Conductive layer; 134 - Insulating cap layer; 130a - Bit line contact; 101 - Contact hole; 141 - Sidewall structure; 150 - Etching barrier layer; 160 - Interlayer insulating layer; 161 - Bit line mask pattern; BL - Bit line; BL1 - First bit line; BL2 - Second bit line; 170 - Sidewall layer; 171 - First... Sidewall layer, 172-Second sidewall layer, 173-Third sidewall layer, 170.1-Sidewall layer located on the first sidewall, 170.2-Sidewall layer located on the second sidewall, 170'-Sidewall layer located inside the contact hole, 180-First plug material layer, 190-Photoresist layer, 181-First insulating plug (first plug), 181.1-First part of the first insulating plug, 181.2-Second part of the first insulating plug, 182-First conductive plug (second plug), 190-Conductive pad.

[0048] In the accompanying drawings, the same parts are referred to by the same reference numerals, and the drawings are not drawn to scale. Detailed Implementation

[0049] To make the technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary implementation methods of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0050] The invention is described more specifically by way of example in the following paragraphs with reference to the accompanying drawings. The advantages and features of the invention will become clearer from the following description and claims. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, used only to facilitate and clarify the illustration of the embodiments of the invention. It is understood that the terms "on," "above," and "over" in this invention should be interpreted in the broadest sense, such that "on" not only means "on" something without any intervening feature or layer (i.e., directly on something), but also includes "on" something with an intervening feature or layer. In the embodiments of the invention, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be noted that the technical solutions described in the embodiments of the invention can be arbitrarily combined without conflict.

[0051] Please refer to Figure 10 The illustration shows a schematic diagram of a semiconductor device according to the first embodiment of the present invention. The semiconductor device of the present invention can be used to manufacture dynamic random access memory (DRAM), and the present invention can also be applied to other types of memory without departing from the spirit of the present invention.

[0052] like Figure 10 As shown, the semiconductor device may include a substrate 100, multiple bit lines BL, multiple contact holes 101, bit line contacts 130a, a first insulating plug 181, and a first conductive plug 182. The substrate 100 includes active regions AR and shallow trench isolation regions 110 adjacent to the active regions AR. Specifically, the multiple shallow trench isolation regions 110 may be disposed within the substrate 100 to define multiple active regions AR on the substrate 100; in other words, the shallow trench isolation regions 110 surround all the active regions AR. For example, the shallow trench isolation regions 110 may be elongated strips extending in a direction perpendicular to the surface of the substrate 100 (hereinafter referred to as the vertical direction), and one of the shallow trench isolation regions 110 has a larger width in a direction parallel to the surface of the substrate 100 (hereinafter referred to as the horizontal direction) than the other shallow trench isolation regions 110 and is located on one side of all the other shallow trench isolation regions 110, for example, located on... Figure 10The rightmost shallow trench isolation zone 110 is wider in the horizontal direction than the other shallow trench isolation zones 110, but this is not a limitation. In addition, an isolation layer 120 may be provided on part of the surface of the substrate 100.

[0053] In one embodiment, the substrate 100 is any suitable substrate material known in the art, such as a silicon substrate, a silicon-containing substrate, or a silicon-on-insulator substrate or a substrate made of other suitable materials, but not limited thereto; the shallow trench isolation region 110 and / or the isolation layer 120 may each include a single layer or multiple layers of dielectric material, and suitable dielectric materials may include, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, nitrogen-doped silicon carbide, low dielectric constant dielectric materials such as fluorosilicone glass, silicon carbide oxide, spin-coated silicon glass, porous low dielectric constant dielectric materials, or combinations of the above materials, but not limited thereto.

[0054] Furthermore, in combination Figure 3 As shown, the plurality of bit lines BL may include a plurality of first bit lines BL1 and at least one second bit line BL2 disposed on the substrate 100, spaced apart from each other. The at least one second bit line BL2 is disposed outside all the first bit lines BL1. Specifically, the widths of the first bit lines BL1 and the second bit lines BL2 in the horizontal direction may be different. For example, the first bit lines BL1 may have a first width in the horizontal direction, while the second bit lines BL2 may have a second width in the horizontal direction. The first width is smaller than the second width. Specifically, the second width may be N times the first width, where N≥2. The second bit line BL2 is disposed outside all the first bit lines BL1, for example... Figure 10 The second bit line BL2 shown is located at the rightmost position of all the first bit lines BL1, but is not limited thereto. The contact hole 101 is located within the substrate 100, and the bit line contact 130a is located within the contact hole 101. The bottom of the bit line contact 130a is in direct contact with the active region AR, while its top is in direct contact with the first bit line BL1. That is, the bit line contact 130a is located within the contact hole 101 located within the substrate 100 below the first bit line BL1. Furthermore, the isolation layer 120 is provided between the bottom of the first bit line BL1 and the second bit line BL2 and the substrate 100.

[0055] In one embodiment, both the first bit line BL1 and the second bit line BL2 are composite structures. For example, they may each include a semiconductor layer 131, a barrier layer 132, a conductive layer 133, and an insulating capping layer 134 stacked from bottom to top along a vertical direction. The material of the semiconductor layer 131 may include monocrystalline silicon, polycrystalline silicon, amorphous silicon, doped silicon, silicon germanium, or other suitable semiconductor materials, but is not limited thereto. The material of the barrier layer 132 may include metals, metal silicides, or metal nitrides, such as titanium, titanium nitride, tungsten silicide, cobalt silicide, and tungsten nitride, but is not limited thereto. The material of the conductive layer 133 may include tungsten, copper, aluminum, titanium, tantalum, or compounds or alloys of the aforementioned metal materials, and / or composite layers, but is not limited thereto. The insulating capping layer 134 may include dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or combinations of the above materials, but is not limited thereto. Preferably, in this embodiment of the invention, the semiconductor layer 131 is made of polycrystalline silicon, the barrier layer 132 is made of titanium nitride, the conductive layer 133 is made of tungsten, and the insulating capping layer 134 is made of silicon nitride. Furthermore, the material of the semiconductor layer 131 in the first bit line BL1 may be the same as the material of the bit line contact 130a located below the first bit line BL1, but is not limited thereto.

[0056] It should be noted that the contact holes 101 located within the substrate 100 and used to provide different bit line contacts 130a below the first bit line BL1 may have different widths in the horizontal direction, for example, as shown below. Figure 10 In the first embodiment of the present invention shown, the width of the contact hole 101 below the first bit line BL1 adjacent to the second bit line BL2 in the horizontal direction is greater than the width of other contact holes 101; and the width of each contact hole 101 in the horizontal direction must be greater than the width of the first bit line BL1 in the horizontal direction, but is not limited thereto.

[0057] Furthermore, the first insulating plug 181 may include: a first portion 181.1 and a second portion 181.2; the first portion 181.1 is located within the contact hole 101 of the bit line contact 130a below the adjacent first bit line BL1, and the second portion 181.2 is located on the first portion 181.1 and is situated between the adjacent first bit line BL1 and the second bit line BL2; in one embodiment, the material of the first portion 181.1 may be an insulating material, and since the material of the first portion 181.1 is an insulating material, it will not affect the performance of the first bit line BL1 above the bit line contact 130a or the semiconductor device; the material of the second portion 181.2 may be an insulating material, such as... Figure 7 or Figure 9 and Figure 10As shown, insulating and conductive materials can also be stacked sequentially from bottom to top, such as... Figure 8 As shown. The conductive material may be, for example, titanium and / or titanium nitride (TiN), tantalum (Ta) and / or tantalum oxide (TaN), and the insulating material may include dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, or combinations thereof, but is not limited thereto.

[0058] Furthermore, the semiconductor device in the first embodiment of the present invention may include a plurality of first conductive plugs 182, and the plurality of first conductive plugs 182 may be respectively located on the substrate 100 between any two adjacent first bit lines BL1; in one embodiment, the top surface of the first conductive plug 182 may be flush with the top surface of the interlayer insulating layer 160 located on the top surface of the first bit lines BL1 on both sides thereof, but is not limited thereto, and the material of each first conductive plug 182 may be a conductive material to meet the requirements of semiconductor devices such as DRAM, for example, by electrically leading out components and / or devices such as transistors within the substrate 100 through the first conductive plugs 182. In addition, the semiconductor device may also include a plurality of conductive pads 190, the plurality of conductive pads 190 may be respectively located on a first conductive plug 182 to realize their electrical lead-out.

[0059] Furthermore, the semiconductor device in the first embodiment of the present invention may further include a plurality of sidewall layers 170; wherein the plurality of sidewall layers 170 may be respectively disposed on the two sidewalls of each first bit line BL1 and extend in the vertical direction to the two sidewalls of the bit line contact 130a, and on at least one sidewall of the second bit line BL2, for example, on the sidewall of the second bit line BL2 near the side of the first bit line BL1 adjacent to it, and a protective sidewall layer may also be formed on the other sidewall of the second bit line BL2 (the side away from all the first bit lines BL1), and the structure of the sidewall layers on the two sidewalls of the second bit line BL2 may be different. Specifically, the sidewall layer 170 located on the sidewall of the second bit line BL2 near the adjacent first bit line BL1 and the sidewall layers 170 on the sidewalls of all other first bit lines BL1 have the same structure. For example, it may include a first sidewall layer 171, a second sidewall layer 172, and a third sidewall layer 173 stacked sequentially in the horizontal direction; wherein the first sidewall layer 171 is in direct contact with the sidewall of the first bit line BL1 or the second bit line BL2. For ease of distinction, the sidewall layer located on the sidewall of the second bit line BL2 away from all first bit lines BL1 is identified as sidewall structure 141 in the first embodiment of the present invention. The sidewall structure 141 may be a single-layer structure, such as a silicon dioxide layer or a silicon nitride layer, or a composite structure (not shown), but is not limited thereto. Furthermore, an etching barrier layer 150 is also provided on the outer surface of the sidewall structure 141 to protect the second bit line BL2 and its sidewall structure 141 during the semiconductor device fabrication process, but is not limited thereto.

[0060] In one embodiment, the sidewall layer 170 located on both sides of the first bit line BL1 adjacent to the second bit line BL2 extends vertically to the contact hole 101 below the first bit line BL1. Because the width (in the horizontal direction) and depth (in the vertical direction) of the gaps on both sides of the contact hole 101 located on the bit line contact member 130a are different, the width and depth of the portion of the sidewall layer 170 extending vertically into the contact hole 101 (indicated by reference numeral 170') are also different, but not limited thereto. Specifically, in conjunction with... Figure 5 As shown, if the two side walls of the first bit line BL1 adjacent to the second bit line BL2 are referred to as the first side wall and the second side wall (not shown) from left to right in the horizontal direction, then the portion of the side wall layer 170 on the first side wall extending vertically into the lower contact hole 101 ( Figure 10 The width of the left-hand area marked 170' in the horizontal direction is smaller than the portion of the sidewall layer 170 located on the second sidewall that extends vertically into the lower contact hole 101. Figure 10The width of the right-hand area (marked by 170') in the horizontal direction; and, the top surface of the portion of the sidewall layer 170 on the first sidewall extending vertically into the lower contact hole 101 is higher than the top surface of the portion of the sidewall layer 170 on the second sidewall extending vertically into the lower contact hole 101, so that the top surface profile of the portion of the sidewall layer 170 on the second sidewall extending vertically into the lower contact hole 101 is a regular or irregular arc shape that is recessed toward the bottom surface of the base 100, but not limited thereto; furthermore, the bottom surface of the portion of the sidewall layer 170 on the first sidewall extending vertically into the lower contact hole 101 is higher than the bottom surface of the portion of the sidewall layer 170 on the second sidewall extending vertically into the lower contact hole 101, but not limited thereto. The sidewall layers 170 (first sidewall layers 171 to third sidewall layers 173) may include dielectric materials, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), or combinations thereof, but are not limited thereto. Furthermore, the sidewall layers 170 may also be a single-layer structure, such as a silicon dioxide layer or a silicon nitride layer, but in the embodiments of the present invention, a multilayer structure is preferred.

[0061] Furthermore, the first insulating plug 181 may include: a first portion 181.1 and a second portion 181.2; the first portion 181.1 of the first insulating plug 181 extends into the groove of the contact hole 101 where the bit line contact 130a is located below the first bit line BL1, such that the bottom surface of the first portion 181.1 is completely covered by the sidewall layer 170' with the groove (also referred to as the sidewall layer 170' remaining in the contact hole 101); in other words, the bottom surface of the first portion 181.1 is higher than the bottom surface of the portion of the sidewall layer 170 on the second sidewall that extends vertically into the lower contact hole 101; the second portion 181.2 is located vertically above the first portion 181.1, and the outer edge of the second portion 181.2 overlaps with the outer edge of the first portion 181.1 in the vertical direction, that is, the projection of the first insulating plug 181 and the sidewall layer 170' onto the substrate 100 in the vertical direction overlaps. Furthermore, the first portion 181.1 is made of an insulating material, and because the first portion 181.1 is made of an insulating material, it will not affect the performance of the first bit line BL1 above the bit line contact 130a or the semiconductor device. The second portion 181.2 of the first insulating plug 181 is located on the substrate 100 between the adjacent first bit line BL1 and second bit line BL2, and its material can be an insulating material, such as... Figure 7 or Figure 9 and Figure 10As shown, insulating and conductive materials can also be stacked sequentially from bottom to top, such as... Figure 8 As shown. In one embodiment, the conductive material may be, for example, titanium and / or titanium nitride (TiN), tantalum (Ta) and / or tantalum oxide (TaN), and the insulating material may include dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, or combinations thereof, but is not limited thereto.

[0062] Furthermore, the semiconductor device may include a plurality of first conductive plugs 182 (also referred to as second plugs). The plurality of first conductive plugs 182 or second plugs 182 may be located on the substrate 100 between any two adjacent first bit lines BL1, with their top surfaces flush with the top surfaces of the first bit lines BL1 on both sides of each first conductive plug 182, but this is not a limitation. Each first conductive plug 182 is made of a conductive material to meet the requirements of semiconductor devices such as DRAM, for example, by electrically leading out components and / or devices such as transistors within the substrate 100 through the first conductive plugs 182. In addition, the semiconductor device may include a plurality of conductive pads 190, which may be located on a first conductive plug 182 to electrically lead out its components.

[0063] It should be understood that, in this embodiment of the invention, an interlayer insulating layer 160 (material such as silicon dioxide or silicon nitride) with a top surface higher than the top surface of the second bit line BL2 is further formed on the etching barrier layer 150 on the other side of the second bit line BL2, so as to protect the second bit line BL2 in this embodiment of the invention. Therefore, the interlayer insulating layer 160 also extends laterally to cover the top surface of the second bit line BL2, and in order to simplify the manufacturing process and protect the first bit line BL1, it can also extend to cover the top surface of all the first bit lines BL1, but is not limited thereto.

[0064] Those skilled in the art will readily understand that, to meet actual product requirements, the semiconductor device of this invention may have other forms and is not limited to those described above. Further descriptions will follow regarding other embodiments or variations of the semiconductor device of this invention. For the sake of simplicity, identical components in the various embodiments of this invention are designated with the same reference numerals to facilitate comparison between embodiments.

[0065] For example Figure 10As shown, the semiconductor device in the second embodiment of the present invention includes the substrate 100, multiple bit lines BL, contact holes 101, bit line contacts 130a, sidewall layers 170, a first insulating plug 181, and a first conductive plug 182. The substrate 100 (material such as silicon) includes active regions AR and shallow trench isolation regions 110 (material such as dielectric material) adjacent to the active regions AR. Specifically, the plurality of shallow trench isolation regions 110 may be disposed within the substrate 100 to define a plurality of active regions AR on the substrate 100; in other words, the shallow trench isolation regions 110 surround all the active regions AR. For example, the shallow trench isolation regions 110 may be elongated strips extending in the vertical direction, and one of the shallow trench isolation regions 110 has a larger horizontal width than the other shallow trench isolation regions 110 and is located on one side of all the other shallow trench isolation regions 110, for example, located on... Figure 10 The rightmost shallow trench isolation area 110 has a horizontal width greater than the other shallow trench isolation areas 110, but this is not a limitation. In addition, an isolation layer 120 (made of, for example, a dielectric material) may be provided on a portion of the surface of the substrate 100.

[0066] Furthermore, the plurality of bit lines BL may include a plurality of first bit lines BL1 and at least one second bit line BL2 disposed on the substrate 100, which are spaced apart from each other. The at least one second bit line BL2 is disposed outside all the first bit lines BL1. In detail, the first bit lines BL1 and the second bit lines BL2 may both be composite structures, for example, both may include, from bottom to top, a semiconductor layer 131 (material for example, polycrystalline silicon), a barrier layer 132 (material for example, titanium nitride), a conductive layer 133 (material for example, tungsten metal), and an insulating capping layer 134 (material for example, silicon nitride), but are not limited thereto. In one embodiment, the widths of the first bit line BL1 and the second bit line BL2 in the horizontal direction may be different. For example, the first bit line BL1 may have a first width in the horizontal direction, while the second bit line BL2 may have a second width in the horizontal direction. The first width is less than the second width; specifically, the second width may be N times the first width, where N ≥ 2. The contact hole 101 is located within the substrate 100, and the bit line contact 130a is located within the contact hole 101. The bottom of the bit line contact 130a is in direct contact with the active region AR, while its top is in direct contact with the first bit line BL1. That is, the bit line contact 130a is located within the contact hole 101 located below the first bit line BL1 within the substrate 100. Furthermore, the isolation layer 120 is provided between the bottoms of the first bit line BL1 and the second bit line BL2 and the substrate 100.

[0067] Furthermore, the sidewall layer 170 may be disposed on both side walls of each of the first bit lines BL1 and extend vertically to both side walls of the bit line contact 130a, and on at least one side wall of the second bit line BL2, for example, on the side wall of the second bit line BL2 near the adjacent first bit line BL1. A protective sidewall layer may also be formed on the other side wall of the second bit line BL2 (the side away from all the first bit lines BL1). The structure of the sidewall layer on the two side walls of the second bit line BL2 may be different, for example, the sidewall structure indicated by reference numeral 141. In one embodiment, the sidewall layer 170 located on the sidewall of the second bit line BL2 near the adjacent first bit line BL1 and the sidewall layers 170 on all other sidewalls of the first bit line BL1 have the same structure. For example, it may include a first sidewall layer 171, a second sidewall layer 172, and a third sidewall layer 173 stacked sequentially in the horizontal direction. The first sidewall layer 171 is in direct contact with the sidewall of the first bit line BL1 or the second bit line BL2. The sidewall structure 141 may be a single-layer structure, such as a silicon dioxide layer or a silicon nitride layer, or a composite structure (not shown), but is not limited thereto. Furthermore, an etching barrier layer 150 is provided on the outer surface of the sidewall structure 141 to protect the second bit line BL2 and its sidewall structure 141 during the semiconductor device fabrication process, but is not limited thereto.

[0068] Furthermore, the sidewall layer 170 located on both sides of the first bit line BL1 adjacent to the second bit line BL2 extends vertically to the contact hole 101 below the first bit line BL1. Since the width (horizontal direction) and depth (vertical direction) of the gaps on both sides of the contact hole 101 located on the bit line contact member 130a are different, the width and depth of the portion of the sidewall layer 170 extending vertically into the contact hole 101 (indicated by reference numeral 170') are also different, but not limited thereto. Specifically, if the two sides of the first bit line BL1 adjacent to the second bit line BL2 are referred to horizontally from left to right as the first sidewall and the second sidewall (not shown), then the portion of the sidewall layer 170 located on the first sidewall extending vertically into the lower contact hole 101 (…) Figure 10 The width of the left-hand area marked 170' in the horizontal direction is smaller than the portion of the sidewall layer 170 located on the second sidewall that extends vertically into the lower contact hole 101. Figure 10The width of the right-hand area (marked by 170') in the horizontal direction; the bottom surface of the portion of the sidewall layer 170 located on the first sidewall extending vertically into the lower contact hole 101 is higher than the bottom surface of the portion of the sidewall layer 170 located on the second sidewall extending vertically into the lower contact hole 101, but is not limited thereto. The sidewall layers 170 (first sidewall layer 171 to third sidewall layer 173) may include dielectric materials, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), or combinations thereof, but are not limited thereto. Furthermore, the sidewall layer 170 may also be a single-layer structure, such as a silicon dioxide layer or a silicon nitride layer, but in this embodiment of the invention, a multi-layer structure is preferred.

[0069] Furthermore, the first insulating plug 181 is located between adjacent first bit line BL1 and second bit line BL2, and in the vertical direction, the first insulating plug 181 overlaps with the projection of the sidewall layer 170' within the contact hole 101 below the adjacent first bit line BL1 onto the substrate 100; more specifically, the first insulating plug 181 may include a first portion 181.1 and a second portion 181.2 that are generally distributed vertically; wherein, the first portion 181.1 is located below the bit line contact 1 adjacent to the first bit line BL1. The first portion 181.1 is located within the contact hole 101, such that the bottom surface of the first portion 181.1 is completely enclosed by the sidewall layer 170' (also referred to as the sidewall layer 170' remaining in the contact hole 101) located within the contact hole 101. The second portion 181.2 is located on the first portion 181.1 and is situated between the adjacent first bit line BL1 and the second bit line BL2. In one embodiment, the material of the first portion 181.1 may be an insulating material, and the material of the second portion 181.2 may be an insulating material or may be an insulating material and a conductive material stacked sequentially from bottom to top, such as... Figure 8 As shown. The conductive material may be, for example, titanium and / or titanium nitride (TiN), tantalum (Ta) and / or tantalum oxide (TaN), and the insulating material may include dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, or combinations thereof, but is not limited thereto.

[0070] Furthermore, the first conductive plug 182 may be located on the substrate 100 between any two adjacent first bit lines BL1. In one embodiment, the top surface of the first conductive plug 182 may be flush with the top surface of the interlayer insulating layer 160 on the top surface of the first bit lines BL1 located on both sides thereon, but this is not a limitation. Each first conductive plug 182 may be made of a conductive material to meet the requirements of semiconductor devices such as DRAM, for example, by electrically leading out components and / or devices such as transistors within the substrate 100 through the first conductive plug 182. In addition, the semiconductor device may also include a plurality of conductive pads 190, which may be respectively located on a first conductive plug 182 to electrically lead out its components.

[0071] Those skilled in the art will readily understand that, to meet actual product requirements, the semiconductor device of this invention may have other forms and is not limited to those described above. Further descriptions will follow regarding other embodiments or variations of the semiconductor device of this invention. For the sake of simplicity, identical components in the various embodiments of this invention are designated with the same reference numerals to facilitate comparison between embodiments.

[0072] For example Figure 10 As shown, the semiconductor device in the third embodiment of the present invention includes the substrate 100, multiple bit lines BL, contact hole 101, bit line contact 130a, sidewall layer 170 and first plug 181, wherein the first plug 181 is the first insulating plug in the aforementioned two embodiments.

[0073] Specifically, the substrate 100 (material such as silicon) includes active regions AR and shallow trench isolation regions 110 (material such as dielectric material) disposed adjacent to the active regions AR. More specifically, the plurality of shallow trench isolation regions 110 may be disposed within the substrate 100 to define a plurality of active regions AR on the substrate 100; in other words, the shallow trench isolation regions 110 surround all the active regions AR. For example, the shallow trench isolation regions 110 may be elongated strips extending in the vertical direction, and one of the shallow trench isolation regions 110 has a larger horizontal width than the others and is located on one side of all the other shallow trench isolation regions 110, for example, located on... Figure 10 The rightmost shallow trench isolation area 110 has a horizontal width greater than the other shallow trench isolation areas 110, but this is not a limitation. In addition, an isolation layer 120 (made of, for example, a dielectric material) may be provided on a portion of the surface of the substrate 100.

[0074] Furthermore, the plurality of bit lines BL may include a plurality of first bit lines BL1 and at least one second bit line BL2 disposed on the substrate 100, which are spaced apart from each other. The at least one second bit line BL2 is disposed outside all the first bit lines BL1. In detail, the first bit lines BL1 and the second bit lines BL2 may both be composite structures, for example, both may include, from bottom to top, a semiconductor layer 131 (material for example, polycrystalline silicon), a barrier layer 132 (material for example, titanium nitride), a conductive layer 133 (material for example, tungsten metal), and an insulating capping layer 134 (material for example, silicon nitride), but are not limited thereto. In one embodiment, the widths of the first bit line BL1 and the second bit line BL2 in the horizontal direction may be different. For example, the first bit line BL1 may have a first width in the horizontal direction, while the second bit line BL2 may have a second width in the horizontal direction. The first width is less than the second width; specifically, the second width may be N times the first width, where N ≥ 2. The contact hole 101 is located within the substrate 100, and the bit line contact 130a is located within the contact hole 101. The bottom of the bit line contact 130a is in direct contact with the active region AR, while its top is in direct contact with the first bit line BL1. That is, the bit line contact 130a is located within the contact hole 101 located below the first bit line BL1 within the substrate 100. Furthermore, the isolation layer 120 is provided between the bottoms of the first bit line BL1 and the second bit line BL2 and the substrate 100.

[0075] Furthermore, the sidewall layer 170 may be disposed on both side walls of each of the first bit lines BL1 and extend vertically to both side walls of the bit line contact 130a, and on at least one side wall of the second bit line BL2, for example, on the side wall of the second bit line BL2 near the adjacent first bit line BL1. A protective sidewall layer may also be formed on the other side wall of the second bit line BL2 (the side away from all the first bit lines BL1). The structure of the sidewall layer on the two side walls of the second bit line BL2 may be different, for example, the sidewall structure indicated by reference numeral 141. In one embodiment, the sidewall layer 170 located on the sidewall of the second bit line BL2 near the adjacent first bit line BL1 and the sidewall layers 170 on all other sidewalls of the first bit line BL1 have the same structure. For example, it may include a first sidewall layer 171, a second sidewall layer 172, and a third sidewall layer 173 stacked sequentially in the horizontal direction. The first sidewall layer 171 is in direct contact with the sidewall of the first bit line BL1 or the second bit line BL2. The sidewall structure 141 may be a single-layer structure, such as a silicon dioxide layer or a silicon nitride layer, or a composite structure (not shown), but is not limited thereto. Furthermore, an etching barrier layer 150 is provided on the outer surface of the sidewall structure 141 to protect the second bit line BL2 and its sidewall structure 141 during the semiconductor device fabrication process, but is not limited thereto.

[0076] Furthermore, the sidewall layer 170 located on both sides of the first bit line BL1 adjacent to the second bit line BL2 extends vertically to the contact hole 101 below the first bit line BL1. Since the width (horizontal direction) and depth (vertical direction) of the gaps on both sides of the contact hole 101 located on the bit line contact member 130a are different, the width and depth of the portion of the sidewall layer 170 extending vertically into the contact hole 101 (indicated by reference numeral 170') are also different, but not limited thereto. Specifically, if the two sides of the first bit line BL1 adjacent to the second bit line BL2 are referred to horizontally from left to right as the first sidewall and the second sidewall (not shown), then the portion of the sidewall layer 170 located on the first sidewall extending vertically into the lower contact hole 101 (…) Figure 10 The width of the left-hand area marked 170' in the horizontal direction is smaller than the portion of the sidewall layer 170 located on the second sidewall that extends vertically into the lower contact hole 101. Figure 10The width of the right side region (marked by 170') in the horizontal direction; and, the top surface of the portion of the sidewall layer 170 on the first sidewall extending vertically into the lower contact hole 101 is higher than the top surface of the portion of the sidewall layer 170 on the second sidewall extending vertically into the lower contact hole 101, so that the top surface profile of the portion of the sidewall layer 170 on the second sidewall extending vertically into the lower contact hole 101 is a regular or irregular arc shape recessed towards the bottom surface of the base 100, that is, the top of the portion of the sidewall layer 170 on the second sidewall extending vertically into the lower contact hole 101 has a groove (not shown), but is not limited thereto; in addition, the bottom surface of the portion of the sidewall layer 170 on the first sidewall extending vertically into the lower contact hole 101 is higher than the bottom surface of the portion of the sidewall layer 170 on the second sidewall extending vertically into the lower contact hole 101, but is not limited thereto. The sidewall layers 170 (first sidewall layers 171 to third sidewall layers 173) may include dielectric materials, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), or combinations thereof, but are not limited thereto. Furthermore, the sidewall layers 170 may also be a single-layer structure, such as a silicon dioxide layer or a silicon nitride layer, but in the embodiments of the present invention, a multilayer structure is preferred.

[0077] Furthermore, the first plug 181 may include a first portion 181.1 and a second portion 181.2. Specifically, the first portion 181.1 is located in the groove of the contact hole 101 where the bit line contact 130a is located below the adjacent first bit line BL1. The bottom of the groove is higher than the bottom of the contact hole 101 and lower than the surface of the base 100, so that the bottom surface of the first portion 181.1 is completely covered by the sidewall layer 170' with the groove (also referred to as the sidewall layer 170' remaining in the contact hole 101). In other words, the bottom surface of the first portion 181.1 is higher than the bottom surface of the portion of the sidewall layer 170 on the second sidewall that extends vertically into the lower contact hole 101; the second portion 181.2 is located vertically above the first portion 181.1 and is situated between adjacent first bit line BL1 and second bit line BL2; in one embodiment, the material of the first portion 181.1 may be an insulating material, and the material of the second portion 181.2 may be an insulating material or may be an insulating material and a conductive material stacked sequentially from bottom to top, such as... Figure 8 As shown. The conductive material may be, for example, titanium and / or titanium nitride (TiN), tantalum (Ta) and / or tantalum oxide (TaN), and the insulating material may include dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, or combinations thereof, but is not limited thereto.

[0078] Furthermore, the first conductive plug 182 may be located on the substrate 100 between any two adjacent first bit lines BL1. In one embodiment, the top surface of the first conductive plug 182 may be flush with the top surface of the interlayer insulating layer 160 on the top surface of the first bit lines BL1 located on both sides thereon, but this is not a limitation. Each first conductive plug 182 may be made of a conductive material to meet the requirements of semiconductor devices such as DRAM, for example, by electrically leading out components and / or devices such as transistors within the substrate 100 through the first conductive plug 182. In addition, the semiconductor device may also include a plurality of conductive pads 190, which may be respectively located on a first conductive plug 182 to electrically lead out its components.

[0079] Those skilled in the art will readily understand that, to meet actual product requirements, the semiconductor device of this invention may have other forms and is not limited to those described above. Further descriptions will follow regarding other embodiments or variations of the semiconductor device of this invention. For simplicity, the following description focuses on the differences between the embodiments, without repeating the similarities. Furthermore, identical components in the embodiments of this invention are designated with the same reference numerals to facilitate comparison between embodiments.

[0080] Those skilled in the art will readily understand that, to meet actual product requirements, the semiconductor device of this invention may have other forms and is not limited to those described above. Further descriptions will follow regarding other embodiments or variations of the semiconductor device of this invention. For the sake of simplicity, identical components in the various embodiments of this invention are designated with the same reference numerals to facilitate comparison between embodiments.

[0081] Please see Figure 20 The illustration shown is a schematic diagram of a semiconductor device according to the fourth embodiment of the present invention. Figure 20As shown, the structure of the semiconductor device in this embodiment is largely the same as that of the semiconductor device in the first embodiment described above. For example, the semiconductor device also includes multiple bit lines BL. These multiple bit lines BL may include multiple first bit lines BL1 and a second bit line BL2 arranged horizontally from left to right on the substrate 100, with different widths along the horizontal direction. The plug located between adjacent first bit lines BL1 and second bit lines BL2 is a first insulating plug 181, while the plug located between any two adjacent first bit lines BL1 is a first conductive plug 182, etc. Similarities will not be repeated here. The main difference between the semiconductor device in this embodiment and the first embodiment is the shape and specific position of the first portion 181.1 of the first insulating plug 181, and the shape and specific position of the sidewall layers 170 on both sides of the bit line contact 130a below the first bit line BL1 adjacent to the second bit line BL2.

[0082] Specifically, in the fourth embodiment of the present invention, the first insulating plug 181 includes a first part 181.1 and a second part 181.2; wherein, the area within the contact hole 101 where the first part 181.1 is located does not have a sidewall layer 170', that is, the first part 181.1 is in direct contact with the sidewall of the bit line contact 130a within the contact hole 101, and the bottom surface of the first part 181.1 is in direct contact with the active region AR below the contact hole 101; under this configuration, the bottom surface of the first part 181.1 is lower than the sidewall layer on the other sidewall of the bit line contact 130a within the contact hole 101 ( Figure 20 The bottom surface (identified by reference numeral 170.1 in the attached drawing), and the width of the first portion 181.1 in the horizontal direction may also be greater than the width of the sidewall layer 170.1 on the other sidewall of the bit line contact 130a in the contact hole 101 in the horizontal direction.

[0083] Those skilled in the art will readily understand that, to meet actual product requirements, the semiconductor device of this invention may have other forms and is not limited to those described above. Further descriptions will follow regarding other embodiments or variations of the semiconductor device of this invention. For the sake of simplicity, identical components in the various embodiments of this invention are designated with the same reference numerals to facilitate comparison between embodiments.

[0084] For example Figure 20 The illustration shown is a schematic diagram of a semiconductor device according to the fifth embodiment of the present invention. Figure 20As shown, the structure of the semiconductor device in this embodiment is largely the same as that in the second embodiment described above. For example, the semiconductor device also includes multiple bit lines BL, contact holes 101, bit line contacts 130a, sidewall layers 170, a first insulating plug 181, and a first conductive plug 182, etc. The similarities will not be repeated here. The main difference between the semiconductor device in this embodiment and the second embodiment lies in the shape and specific position of the first portion 181.1 of the first insulating plug 181, and the shape and specific position of the sidewall layers 170 on both sides of the bit line contact 130a below the first bit line BL1 adjacent to the second bit line BL2.

[0085] Specifically, in the fifth embodiment of the present invention, the first insulating plug 181 includes a first part 181.1 and a second part 181.2; wherein, the area within the contact hole 101 where the first part 181.1 is located does not have a sidewall layer 170', that is, the first part 181.1 is in direct contact with the sidewall of the bit line contact 130a within the contact hole 101, and the bottom surface of the first part 181.1 is in direct contact with the active region AR below the contact hole 101; under this configuration, the bottom surface of the first part 181.1 is lower than the sidewall layer on the other sidewall of the bit line contact 130a within the contact hole 101 ( Figure 20 The bottom surface (identified by reference numeral 170.1 in the attached drawing) and the width of the first portion 181.1 in the horizontal direction may also be greater than the width of the sidewall layer 170.1 on the other sidewall of the bit line contact 130a within the contact hole 101 in the horizontal direction. However, in the fifth embodiment of the present invention, the outer edge of the first portion 181.1 of the first insulating plug 181 does not overlap with the outer edge of its second portion 181.2 in the vertical direction. For example, the outer edge of the first portion 181.1 may be located between adjacent first bit lines BL1 and second bit lines BL2. Similarly, in the vertical direction, the projection of the first insulating plug 181 and the sidewall layer 170' within the contact hole 101 below the adjacent first bit line BL1 onto the substrate 100 also does not overlap.

[0086] Those skilled in the art will readily understand that, to meet actual product requirements, the semiconductor device of this invention may have other forms and is not limited to those described above. Further descriptions will follow regarding other embodiments or variations of the semiconductor device of this invention. For the sake of simplicity, identical components in the various embodiments of this invention are designated with the same reference numerals to facilitate comparison between embodiments.

[0087] For example Figure 20 The illustration shown is a schematic diagram of a semiconductor device according to the sixth embodiment of the present invention. Figure 20As shown, the structure of the semiconductor device in this embodiment is largely the same as that in the third embodiment described above. For example, the semiconductor device also includes multiple bit lines BL, contact holes 101, bit line contacts 130a, sidewall layers 170, and a first plug 181. The first plug 181 is the same as the first insulating plug in the two embodiments described above, and the similarities will not be repeated here. The main difference between the semiconductor device in this embodiment and the third embodiment is the shape and specific position of the first portion 181.1 of the first plug 181, and the shape and specific position of the sidewall layers 170 on both sides of the bit line contact 130a below the first bit line BL1 adjacent to the second bit line BL2.

[0088] Specifically, in the sixth embodiment of the present invention, the first plug 181 includes a first part 181.1 and a second part 181.2. In the region within the contact hole 101 where the first part 181.1 is located, no sidewall layer 170' is provided. That is, the bottom surfaces of the sidewall layers 170 formed on the opposing sidewalls between adjacent first bit lines BL1 and second bit lines BL2 are all higher than the surface of the substrate 100. Furthermore, the first part 181.1 directly contacts the sidewall of the bit line contact 130a within the contact hole 101, and the bottom surface of the first part 181.1 directly contacts the active region AR below the contact hole 101. Under this configuration, the bottom surface of the first part 181.1 is lower than the sidewall layer on the other sidewall of the bit line contact 130a within the contact hole 101. Figure 20 The bottom surface (identified by reference numeral 170.1 in the attached drawing), and the width of the first portion 181.1 in the horizontal direction may also be greater than the width of the sidewall layer 170.1 on the other sidewall of the bit line contact 130a in the contact hole 101 in the horizontal direction.

[0089] In order to enable those skilled in the art to easily understand the semiconductor devices in the first to third embodiments of the present invention, the present invention also provides a method for preparing the semiconductor device. The following will further explain the method for preparing the semiconductor device proposed in the present invention with reference to the various structural schematic diagrams in the preparation process of the semiconductor device.

[0090] in, Figures 1-10 This is a schematic diagram of the structure of the semiconductor device fabrication method provided in the first to third embodiments of the present invention during the fabrication process.

[0091] Please see Figure 1First, a substrate 100 (material such as a silicon substrate) is provided. Then, multiple trenches (not shown) are formed in the substrate 100 using an etching method. An insulating material (material such as silicon oxide or silicon oxynitride) is then filled into the trenches to form multiple shallow trench isolation regions 110 and multiple active regions AR defined by the shallow trench isolation regions 110 within the substrate 100. For example, the shallow trench isolation regions 110 may be elongated strips extending in a vertical direction, and one of the shallow trench isolation regions 110 may have a larger width in the parallel direction than the other shallow trench isolation regions 110 and be located on one side of all the other shallow trench isolation regions 110, but this is not a limitation. Then, an isolation layer 120 may be formed on the surface of the substrate 100 using at least one deposition process such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc. Next, multiple trenches, i.e., contact holes 101, are formed in the isolation layer 120 and the substrate 100. Figure 1 Two contact holes 101 are formed in the substrate 100 at intervals, and the contact holes 101 are the corresponding positions of the bit line contact 130a formed later in the substrate 100. Next, a material layer (material, for example, polysilicon) of bit line contact 130a can be formed in the contact hole 101 using the above deposition process. Then, a bit line material layer 130 consisting of a semiconductor layer 131 (material, for example, polysilicon), a barrier layer 132 (material, for example, titanium nitride), a conductive layer 133 (material, for example, tungsten), and an insulating capping layer 134 (material, for example, silicon nitride) stacked sequentially from bottom to top is formed on the material layer of the bit line contact 130. A sidewall structure 141 (material, for example, silicon nitride) and an etch barrier layer 150 (material, for example, silicon dioxide) are formed on the sidewall of the bit line material layer 130 near the exposed surface of the substrate 100.

[0092] It should be noted that, since a residual sidewall layer 170' is provided between the first insulating plug 181 or the first portion 181.1 of the first plug 181 in the first to third embodiments of the present invention and the bit line contact 130a below the first bit line BL1 adjacent thereto, when forming the contact hole 101 in this step, at least one contact hole 101 in the first to third embodiments of the present invention needs to have a larger width in the horizontal direction, for example, it can be larger than the width of other contact holes 101 in the horizontal direction, but is not limited thereto.

[0093] Please see Figure 2First, an etching process can be used to remove the etch barrier layer 150 on the top surface of the bit line material layer 130, so that the remaining etch barrier layer 150 only covers the surface of the sidewall structure 141 and the exposed substrate 100. Then, a deposition process can be used to form an interlayer insulating layer 160 (material such as silicon nitride or silicon oxide) and multiple bit line mask patterns 161 on the bit line material layer 130, the sidewall structure 141 and the remaining etch barrier layer 150, burying them all. The bit line mask patterns 161 are used to define the positions of the first bit line BL1 and the second bit line BL2, that is, to prepare for the subsequent formation of multiple first bit lines BL1 and a second bit line BL2 that are spaced apart from each other.

[0094] Please see Figure 3 Next, using the plurality of bit line mask patterns 161 as masks, a portion of the bit line material layer 130 and a portion of the interlayer insulating layer 160 are etched downwards in the vertical direction to form a plurality of first bit lines BL1 and a second bit line BL2 that are horizontally separated on the substrate 100. It should be noted that during the etching of the bit line material layer 130 to form the first bit line BL1 and the second bit line BL2 in this step, bit line contacts 130a are simultaneously formed within the contact holes 101; wherein, the bit line contacts 130a are located within the contact holes 101 below the first bit line BL1, and since the width of the contact holes 101 in the horizontal direction is greater than the width of the bit line contacts 130a in the horizontal direction, the corresponding bit lines BL1 are simultaneously exposed during the formation of the plurality of independent first bit lines BL1. The contact hole area of ​​the bit line contact 130a within the contact hole 101. Since the width of the contact hole 101 below the first bit line BL1 adjacent to the second bit line BL2 in the first embodiment of the present invention is larger than the width of other contact holes 101, the contact hole 101 below the first bit line BL1 adjacent to the second bit line BL2 in the first to third embodiments of the present invention will undergo further partial etching after the bit line material layer 130 is etched in this step, resulting in a change in its shape. For example... Figure 3 As shown.

[0095] Please see Figure 4Next, a sidewall layer 170 can be formed on both sides of the first bit line BL1, on one side wall of the second bit line BL2 near the remaining first bit lines BL1, and on the isolation layer 120 between adjacent first bit lines BL1 and adjacent first bit lines BL1 and second bit lines BL2 using a deposition process. The sidewall layer 170 may include a first sidewall layer 171 (material for example, silicon dioxide), a second sidewall layer 172 (material for example, silicon nitride), and a third sidewall layer 173 (material for example, silicon dioxide) stacked sequentially in a vertical direction, with the first sidewall layer 171 in direct contact with the sidewall of the first bit line BL1 or the second bit line BL2. In this configuration, the sidewall layer 170 will simultaneously fill the remaining space in the contact hole 101. Since the shape of the contact hole 101 below the first bit line BL1 adjacent to the second bit line BL2 has changed, the sidewall layer filled vertically into the contact hole 101 has a different shape than the sidewall layers in other contact holes 101. For ease of distinction, this invention exemplarily identifies the sidewall layers formed in this step on both sides of the first bit line BL1 adjacent to the second bit line BL2 using reference numerals 170.1 and 170.2 from left to right, but this is not a limitation. It should be understood that the top surfaces of the sidewall layers identified by reference numerals 170.1 and 170.2 formed in this step are at the same horizontal height, i.e., the groove is not formed at this time.

[0096] Please see Figure 5 Next, the sidewall layer 170 and the isolation layer 120 between adjacent first bit lines BL1 and between adjacent first bit lines BL1 and second bit lines BL2 are etched away in the vertical direction to expose the substrate 100 between adjacent bit lines BL. It should be noted that, since the sidewall layer 170.2 on the sidewall of the first bit line BL1 adjacent to the second bit line BL2 was not covered when the sidewall layer 170 was etched away in this step in the first to third embodiments of the present invention, a portion of the sidewall layer 170.2 will also be removed in this step to form a groove with an arc-shaped top surface profile extending vertically toward the bottom surface of the substrate 100. In this case, the sidewall layer remaining in the contact hole 101 after the groove is formed is exemplarily identified by reference numeral 170' in the figure drawing.

[0097] Please see Figure 6Subsequently, a first plug material layer 180 can be filled between adjacent bit lines BL, and a photoresist layer 190 can be used to shield the interlayer dielectric layer 160 above the second bit line BL2 and the first plug material layer 180 adjacent to it. The first plug material layer 180 can be a single-layer structure, such as using insulating materials like silicon dioxide or silicon nitride, or a composite structure, such as insulating and conductive materials stacked sequentially from bottom to top. The conductive material can be, for example, titanium and / or titanium nitride (TiN), tantalum (Ta) and / or tantalum oxide (TaN). The insulating material can include dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or combinations thereof, but is not limited thereto. In this configuration, it is sufficient that at least the lower half of the first insulating plug 181, such as the first portion 181.1, is made of insulating material.

[0098] Please see Figure 7 or Figure 8 The first plug material layer 180 between adjacent first bit lines BL1 is removed by etching (e.g., dry etching process), so that the remaining first plug material layer 180 between adjacent first bit lines BL1 and second bit lines BL2 serves as the first insulating plug 181. Specifically, the first plug material layer 180 located within the shaped contact hole 101 serves as the first portion 181.1 of the first insulating plug 181, and the first plug material layer 180 located on the substrate 100 and between adjacent first bit lines BL1 and second bit lines BL2 serves as the first insulating plug 181 or the second portion 181.2 of the first plug 181. Figure 7 and Figure 8 The first insulating plug 181 or the second part 181.2 of the first plug 181 shown in the embodiments of the present invention may be made of insulating material or different examples of insulating and conductive materials.

[0099] Please see Figure 9 Then, a deposition process can be used to fill the gap between adjacent first bit lines BL1 with at least one of conductive materials such as titanium and / or titanium nitride (TiN), tantalum (Ta) and / or tantalum oxide (TaN) to form first conductive plugs 182 located between the first bit lines BL1 respectively.

[0100] Please see Figure 10 Finally, a conductive pad 190 is formed on each of the plurality of first conductive plugs 182 using deposition, photolithography, and etching processes. The material of the conductive pad 190 may be a metal, such as tungsten, but is not limited thereto.

[0101] In order to enable those skilled in the art to easily understand the semiconductor devices in the fourth to sixth embodiments of the present invention, the present invention also provides a method for preparing the semiconductor device. The following will further explain the method for preparing the semiconductor device proposed in the present invention with reference to the various structural schematic diagrams in the preparation process of the semiconductor device.

[0102] in, Figures 11-20 This is a schematic diagram illustrating the fabrication process of the semiconductor device provided in the fourth to sixth embodiments of the present invention. Since the semiconductor devices in the fourth to sixth embodiments of the present invention are substantially the same as those in the first to third embodiments described above, the fabrication methods for their corresponding components and / or devices are also the same. Therefore, the parts of the fabrication methods in the fourth to sixth embodiments of the present invention that are the same as those in the first to third embodiments will not be described again below; only the different fabrication processes will be explained.

[0103] Specifically, such as Figure 13 As shown, during the process of etching and removing a portion of the bit line material layer 130 and a portion of the interlayer insulating layer 160 downwards in the vertical direction using the plurality of bit line mask patterns 161 as masks to form a plurality of first bit lines BL1 and a second bit line BL2 arranged horizontally and mutually separated on the substrate 100, a portion of the material layer of the bit line contact 130a in the contact hole 101 below the first bit line BL1 adjacent to the second bit line BL2 in the fourth to sixth embodiments of the present invention is also simultaneously removed to expose the contact holes 101 on both sides of the bit line contact 130a in each contact hole 101, that is, a gap is formed on both sides of the edge region of each contact hole 101 to expose a portion of the substrate 100 below. Further, as... Figure 14 As shown, in the fourth to sixth embodiments of the present invention, the sidewall layer 170 formed on both sides of the first bit line BL1 adjacent to the second bit line BL2 also extends vertically into the contact hole 101 below it. However, since the contact hole 101 is in Figure 13 The gap difference between the two sides of the bit line contact 130a formed after the etching step is small. Therefore, the sidewall layer 170 formed in this step has a roughly the same shape on both sides of the bit line contact 130a in the contact hole 101.

[0104] Furthermore, such as Figure 15As shown, in the fourth to sixth embodiments of the present invention, during the process of etching away the sidewall layer 170 and the isolation layer 120 between adjacent first bit lines BL1 and between adjacent first bit lines BL1 and second bit lines BL2 in the vertical direction to expose the substrate 100 between adjacent bit lines BL, the sidewall layer 170.2 inside the contact hole 101 below the first bit line BL1 adjacent to the second bit line BL2 is simultaneously removed to re-expose the side gap of the contact hole 101. The bottom surface of the sidewall layer 170.2 covering the sidewall of the first bit line BL1 near the second bit line BL2 is higher than the bottom surface of the sidewall layer 170.1 of the first bit line BL1 near all other first bit lines BL1, but this is not a limitation.

[0105] In summary, in the semiconductor device provided by the present invention, the first insulating plug located between the first bit line and the second bit line may include two parts, wherein the first part fills the contact hole (inside the substrate) where the bit line plug is located below the first bit line adjacent to the second bit line or further directly contacts the sidewall layer remaining in the contact hole, and the second part is located on the first part (on the substrate) and between the adjacent first bit line and the second bit line, thereby forming a new structure of the semiconductor device in which the first insulating plug is located between the first bit line and the second bit line and its part is also in direct contact with the bit line plug and the sidewall layer.

[0106] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A semiconductor device, characterized by, The application relates to a semiconductor memory device, comprising: a substrate comprising an active region and a shallow trench isolation region disposed adjacent to the active region; a plurality of bit lines comprising a plurality of first bit lines and at least one second bit line disposed on the substrate separately from each other, the at least one second bit line being disposed outside all of the first bit lines; a contact hole in the substrate; a bit line contact in the contact hole, the bottom of the bit line contact contacting the active region and the top of the bit line contact contacting the first bit line; a sidewall layer comprising a sidewall layer on both sidewalls of the first bit line and a sidewall layer in the contact hole; a first conductive plug between adjacent first bit lines, the first conductive plug also electrically connected to the active region; a first insulating plug between adjacent first bit lines and the second bit line, wherein in a vertical direction, the first insulating plug overlaps a projection of the sidewall layer in the contact hole on the substrate.

2. The semiconductor device of claim 1, wherein, The bottommost part of the first insulating plug is lower than the bottommost part of the first conductive plug.

3. The semiconductor device of claim 1, wherein, The first insulating plug directly contacts the sidewall layer in the contact hole.

4. The semiconductor device of claim 1, wherein, The first insulating plug comprises a first part and a second part, the material of the first part being insulating, and the material of the second part comprising insulating material and conductive material stacked in order from bottom to top.

5. The semiconductor device of claim 1, wherein, The first insulating plug comprises a first part and a second part, the material of the first part being insulating, and the material of the second part being insulating.

6. The semiconductor device according to claim 4 or 5, wherein The first part is in the contact hole, and the second part is on the first part and between adjacent first bit lines and the second bit line.

7. The semiconductor device of claim 5, wherein, The bit line comprises a semiconductor layer, a barrier layer, a conductive layer and an insulating cover layer stacked in order from bottom to top, wherein the top surface of the insulating material in the first insulating plug is higher than the top surface of the metal layer in the bit line.

8. The semiconductor device of claim 4, wherein, The bit line comprises a semiconductor layer, a barrier layer, a conductive layer and an insulating cover layer stacked in order from bottom to top, wherein the top surface of the conductive material in the first insulating plug is higher than the top surface of the metal layer in the bit line.

9. The semiconductor device of claim 1, wherein, The sidewall layer in the contact hole directly contacts the inner sidewall of the contact hole and the bit line contact.

10. The semiconductor device of claim 1, wherein, The first insulating plug is electrically insulated from the active region.

11. The semiconductor device of claim 1, wherein, The bottom surface of the first insulating plug is completely wrapped by the sidewall layer with a groove in the contact hole.

12. The semiconductor device of claim 6, wherein, The width of the first part in the horizontal direction is greater than the width of the sidewall layer on the other sidewall of the bit line contact in the contact hole in which the first part is located.

13. The semiconductor device of claim 1, wherein, The bottom surface of the sidewall layer on the side of the bit line contact close to the first insulating plug is lower than the bottom surface of the sidewall layer on the side away from the first insulating plug.

14. The semiconductor device of claim 1, wherein, The width of the sidewall layer on the side of the bit line contact close to the first insulating plug in the horizontal direction is greater than the width of the sidewall layer on the side away from the first insulating plug in the horizontal direction.

15. The semiconductor device of claim 1, wherein, The width of the second bit line in the horizontal direction is N times the width of the first bit line in the horizontal direction, wherein N>=2.

16. The semiconductor device of claim 1, wherein, The sidewall layer on the sidewall of the first bit line adjacent to the second bit line close to the first insulating plug directly contacts the sidewall layer in the contact hole.

17. A semiconductor device, characterized by comprising: The application relates to a semiconductor memory device, comprising: a substrate including an active region and a shallow trench isolation region disposed adjacent to the active region; a plurality of bit lines including a plurality of first bit lines and at least one second bit line disposed on the substrate separately from each other, the at least one second bit line disposed outside of all of the first bit lines; a contact hole located in the substrate; a bit line contact located in the contact hole, a bottom portion of the bit line contact contacting the active region, and a top portion of the bit line contact contacting the first bit line; a sidewall layer including a sidewall layer located on sidewalls of the first bit line and a sidewall layer located in the contact hole; a first conductive plug located between adjacent first bit lines, the first conductive plug also electrically connected to the active region; a first insulating plug located between adjacent first bit lines and the second bit line, wherein in a vertical direction, the first insulating plug overlaps a projection of the sidewall layer located in the contact hole on the substrate; the first insulating plug is electrically insulated from the active region.

18. A semiconductor device, characterized by comprising: comprising: a substrate including an active region and a shallow trench isolation region disposed adjacent to the active region; a plurality of bit lines including a plurality of first bit lines and at least one second bit line disposed on the substrate separately from each other, the at least one second bit line disposed outside of all of the first bit lines; a contact hole located in the substrate; a bit line contact located in the contact hole, a bottom portion of the bit line contact contacting the active region, and a top portion of the bit line contact contacting the first bit line; a first insulating plug, a bottom portion of the first insulating plug located in the contact hole, and the bottom portion of the first insulating plug directly contacting the active region.

19. A semiconductor device, characterized by comprising: comprising: a substrate including an active region and a shallow trench isolation region disposed adjacent to the active region; a plurality of bit lines including a plurality of first bit lines and at least one second bit line disposed on the substrate separately from each other, the at least one second bit line disposed outside of all of the first bit lines; a contact hole located in the substrate; a bit line contact located in the contact hole, a bottom portion of the bit line contact contacting the active region, and a top portion of the bit line contact contacting the first bit line; a first insulating plug, a bottom portion of the first insulating plug located in the contact hole, and a bottom surface of the first insulating plug lower than a top surface of the substrate.

20. A semiconductor device, characterized by comprising: comprising: a substrate including an active region and a shallow trench isolation region disposed adjacent to the active region; a plurality of bit lines including a plurality of first bit lines and at least one second bit line disposed on the substrate separately from each other, the at least one second bit line disposed outside of all of the first bit lines; a contact hole located in the substrate; a bit line contact located in the contact hole, a bottom portion of the bit line contact contacting the active region, and a top portion of the bit line contact contacting the first bit line; a first insulating plug including a first portion located in the contact hole; a second portion located on the first portion and located between adjacent first bit lines and the second bit line; wherein the first portion directly contacts the bit line contact.

21. The semiconductor device of claim 20, wherein, a bottom portion of the first portion directly contacts the active region.

22. The semiconductor device of claim 20, wherein, a bottom surface of the first portion is lower than a bottom surface of a sidewall layer on another sidewall of the bit line contact in the contact hole in which the first portion is located.

23. The semiconductor device of claim 20, wherein, the first insulating plug is electrically insulated from the active region.

24. The semiconductor device of claim 20, wherein, The first portion has a width in a horizontal direction that is greater than a width in a horizontal direction of a sidewall layer on another sidewall of the bit line contact within the contact hole.

25. The semiconductor device of claim 20, wherein, The bottom surface of the sidewall layer of the bit line contact on a side closer to the first insulating plug is lower than the bottom surface of the sidewall layer on a side farther from the first insulating plug.

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