Solar cell and preparation method thereof
By printing aluminum-free silver paste on an N-type silicon wafer to form a fine grid and depositing a perovskite composite layer, the problem of low utilization rate of perovskite solar cells was solved, and the photoelectric conversion efficiency was improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-27
- Publication Date
- 2026-03-06
AI Technical Summary
Perovskite solar cells have low solar energy utilization, which affects their photoelectric conversion efficiency.
A fine grid is formed by printing aluminum-free silver paste on the first contact area of an N-type silicon wafer, and a perovskite composite layer is deposited therebetween. The perovskite composite layer is formed by using a gridless design, combined with laser-induced sintering and low-temperature conductive silver paste printing.
It saves on paste usage, reduces the area occupied by the main grid, improves the utilization rate of solar energy by N-type silicon wafers, and enhances photoelectric conversion efficiency.
Smart Images
Figure CN121619986A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of solar cells, and more particularly to a solar cell and a method for its fabrication. Background Technology
[0002] Perovskite solar cells are a type of solar cell that is easy to fabricate and has low production costs.
[0003] In related technologies, perovskite solar cells have low solar energy utilization, which affects the photoelectric conversion efficiency of solar cells. Summary of the Invention
[0004] To overcome the shortcomings of the prior art, this application provides a solar cell and a method for its fabrication.
[0005] In a first aspect, this application provides a method for fabricating a solar cell, comprising: obtaining an N-type silicon wafer, and sequentially depositing a first mask layer and a second mask layer on a first contact area of the N-type silicon wafer; performing a first screen printing process on the N-type silicon wafer to print a first paste on a first preset area on the first contact area and form a plurality of fine grids; sequentially performing a first sintering process and a second sintering process on the N-type silicon wafer; depositing a perovskite composite layer on the first contact area and positioning the perovskite composite layer between each of the fine grids; and performing a second screen printing process on the N-type silicon wafer to print a second paste on a second preset area on the first contact area.
[0006] In conjunction with the first aspect, in one possible implementation, the N-type silicon wafer includes a first contact area and a second contact area disposed opposite to each other, the first contact area being the front side of the N-type silicon wafer, the second contact area being the back side of the N-type silicon wafer, and the first paste being an aluminum-free silver paste.
[0007] In conjunction with the first aspect, in one possible implementation, the perovskite composite layer includes a first conductive layer, a second conductive layer, a perovskite layer, a first electron transport layer, a second electron transport layer, and a third conductive layer stacked sequentially.
[0008] In conjunction with the first aspect, in one possible implementation, the second paste is silver paste, the second paste has a preset curing temperature, and the second paste is printed on the third conductive layer.
[0009] In conjunction with the first aspect, in one possible implementation, the first conductive layer is an ITO layer, the first conductive layer is located between the fine gates, and the first conductive layer has a first preset thickness; the second conductive layer includes a NiO layer, the second conductive layer has a second preset thickness; the third conductive layer is an ITO layer, the third conductive layer has a third preset thickness, and the second preset thickness is greater than the third preset thickness.
[0010] In conjunction with the first aspect, in one possible implementation, the second preset region is located between two adjacent first preset regions, the fine grid is arranged along a first preset direction, and the length of the second preset region along a second preset direction is greater than the length of the first preset region along the second preset direction, and the second preset direction is perpendicular to the first preset direction.
[0011] In conjunction with the first aspect, in one possible implementation, the second sintering process is a laser-induced sintering process, and the second sintering process is performed at a preset laser power.
[0012] In conjunction with the first aspect, in one possible implementation, the first sintering process is performed at a first preset temperature, and before performing the second sintering process on the N-type silicon wafer, the N-type silicon wafer needs to undergo a light injection process, which is performed at a second preset temperature and a preset light intensity, wherein the second preset temperature is lower than the first preset temperature.
[0013] In conjunction with the first aspect, in one possible implementation, the first mask layer is an aluminum oxide layer, the second mask layer is a silicon nitride layer, and a passivation contact layer and a polysilicon layer are sequentially deposited on the second contact area before the first mask layer is deposited on the first contact area.
[0014] Secondly, this application provides a solar cell prepared using the solar cell preparation method described above.
[0015] Compared with the prior art, the beneficial effects of this application are:
[0016] The method for fabricating a solar cell provided in this application involves printing a first paste on a first contact area of an N-type silicon wafer to form a plurality of fine grids. This method employs a gridless design, which saves on the amount of first paste used and reduces production costs. Furthermore, it reduces the area of the first contact area occupied by the grid, increases the area of the N-type silicon wafer that effectively utilizes solar energy, and improves the utilization rate of solar energy by the N-type silicon wafer, thereby enhancing the photoelectric conversion efficiency of the cell. Attached Figure Description
[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0018] Figure 1 A schematic diagram of the process for fabricating a solar cell is shown. Detailed Implementation
[0019] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.
[0020] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.
[0021] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.
[0022] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.
[0023] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.
[0024] Example 1
[0025] Please see Figure 1 This application provides a method for preparing a solar cell, which includes the following steps:
[0026] S100: Obtain an N-type silicon wafer, and sequentially deposit a first mask layer and a second mask layer on the first contact area of the N-type silicon wafer;
[0027] S200: Perform a first screen printing process on the N-type silicon wafer to print a first paste on a first preset area on the first contact area and form a plurality of fine grids;
[0028] S300: After performing a first sintering process, a light injection process, and a second sintering process on the N-type silicon wafer in sequence, a perovskite composite layer is deposited on the first contact area, and the perovskite composite layer is located between each of the fine gates.
[0029] S400: Perform a second screen printing process on the N-type silicon wafer to print a second paste on a second preset area on the first contact area.
[0030] In some embodiments, the N-type silicon wafer in S100 includes a first contact surface and a second contact surface disposed opposite to each other. The first contact surface is the front side of the N-type silicon wafer. The second contact surface is the back side of the N-type silicon wafer. The first contact area is located on the first contact surface. The second contact area is located on the second contact surface.
[0031] In some embodiments, the N-type silicon wafer in S100 has a size of 182mm*183.75mm.
[0032] In some embodiments, before depositing the first mask layer on the first contact area of the N-type silicon wafer in S100, the second contact area needs to be subjected to low-pressure chemical vapor deposition to sequentially deposit a passivation contact layer and a polycrystalline silicon layer on the second contact area.
[0033] In some embodiments, the passivation contact layer includes a silicon oxide layer and a doped silicon layer. The silicon oxide layer is located on the second contact region. The doped silicon layer is located on the side of the silicon oxide layer opposite to the second contact region, and the thickness of the doped silicon layer is greater than the thickness of the silicon oxide layer.
[0034] In some embodiments, the specific process for preparing the silicon oxide layer is as follows: placing the N-type silicon wafer in a reactor, introducing oxygen into the reactor at a flow rate of 20,000 sccm, while simultaneously adjusting the temperature of the reactor to 605°C and the pressure of the reactor to 860 N, to complete the preparation of the silicon oxide layer.
[0035] In some embodiments, the specific process for preparing the doped silicon layer is as follows: after the silicon oxide layer on the second contact region is prepared, silane is introduced into the reactor at a flow rate of 240 sccm, while the temperature of the reactor is adjusted to 620°C and maintained for 32 minutes to complete the preparation of the doped silicon layer. The silicon oxide layer and the doped silicon layer together form a passivated contact structure, which can effectively reduce surface recombination and metal-to-surface recombination.
[0036] In some embodiments, the specific process for preparing the polycrystalline silicon layer is as follows: the N-type silicon wafer is placed in a diffusion furnace, and POCl3, O2, and N2 are introduced into the diffusion furnace, with the POCl3 flow rate at 130 sccm / min, the O2 flow rate at 700 sccm / min, and the N2 flow rate at 1800 sccm / min. The temperature of the diffusion furnace is adjusted to 920°C, and the pressure is maintained at 170 mbar for 12 minutes. Then, the temperature of the N-type silicon wafer is raised to 980°C, and the O2 flow rate in the diffusion furnace is increased to 12000 sccm / min, and the pressure in the diffusion furnace is maintained at 920 mbar for 55 minutes to complete the phosphorus diffusion treatment, thereby completing the preparation of the polycrystalline silicon layer.
[0037] In some embodiments, the sheet resistance of the N-type silicon wafer after the phosphorus diffusion treatment is 42 Ω / sq, and the junction depth of the N-type silicon wafer is 1.05 μm. The phosphorus diffusion treatment reduces the sheet resistance and resistivity of the N-type silicon wafer.
[0038] In some embodiments, before depositing the first mask layer on the first contact area of the N-type silicon wafer in S100, the second contact area needs to be subjected to texturing, boron diffusion, oxidation degradation, first acid pickling, and first alkaline polishing in sequence.
[0039] In some embodiments, the texturing process is as follows: the N-type silicon wafer is placed in a texturing reagent at 70°C to perform double-sided texturing, so that both the first contact area and the second contact area are texturized surfaces, and the texturized surfaces have a preset reflectivity.
[0040] In some embodiments, the preset reflectivity is 9.1%, and the morphology of the velvet surface is pyramidal when tested under a microscope.
[0041] In some embodiments, the texturing reagent is a mixture of 24L concentrated KOH, 8L texturing additive and 455L pure water, and the temperature of the texturing reagent is 70°C, and the reaction time of the N-type silicon wafer in the texturing reagent is 275s.
[0042] In some embodiments, the specific process of the boron diffusion treatment is as follows: the N-type silicon wafer after texturing is placed in a boron diffusion tube at 980°C, and 340 sccm of BCl3, 920 sccm of O2 and 3500 sccm of N2 are introduced into the boron diffusion tube, and the reaction is carried out for 620 s to form the P+ layer, which can effectively increase the doping of the P+ doped region and improve the passivation effect of the battery.
[0043] In some embodiments, the specific process of the oxidation degradation treatment is as follows: the N-type silicon wafer after the boron diffusion treatment is placed in an annealing furnace, and O2 at 2300 sccm is introduced into the annealing furnace and reacted for 12 minutes to complete the oxidation degradation treatment.
[0044] In some embodiments, the sheet resistance of the N-type silicon wafer subjected to the oxidation degradation treatment is 180 Ω / sq, and the junction depth of the N-type silicon wafer is 0.95 μm. The oxidation degradation treatment allows the diffused boron to redistribute under high temperature processing on the N-type silicon wafer, while also serving as an oxide layer to provide protection during subsequent alkaline polishing.
[0045] In some embodiments, the specific process of the first pickling treatment is as follows: the N-type silicon wafer, after the oxidation degradation treatment, is placed in a first pickling reagent for chain-like back-side pickling, and the first pickling reagent is a mixture of 1.2% concentrated hydrochloric acid and 1.5% hydrofluoric acid. Because the borosilicate glass on the surface of the oxidized N-type silicon wafer will prevent the N-type silicon wafer from reacting with alkali, the N-type silicon wafer after the first pickling treatment can better remove the borosilicate glass, thereby improving the cleanliness of the N-type silicon wafer surface.
[0046] In some embodiments, the specific process of the first alkaline polishing treatment is as follows: the N-type silicon wafer after the first acid washing treatment is placed in the first alkaline polishing reagent and reacted for 285 seconds.
[0047] In some embodiments, the first alkaline polishing reagent is a mixture of 25L concentrated KOH, 8L additive and 450L water, wherein the additive is BP52 and the temperature of the first alkaline polishing reagent is 65°C.
[0048] In some embodiments, a second acid pickling process is required after the polycrystalline silicon layer is prepared to remove the phosphosilicate glass and oxide layer on the surface of the N-type silicon wafer, thereby ensuring the cleanliness of the N-type silicon wafer surface and preventing impurities from being carried into subsequent processes.
[0049] In some embodiments, the specific process of the second pickling treatment is as follows: the N-type silicon wafer after phosphorus expansion is placed in a second pickling reagent for chain-type back pickling, and the second pickling reagent is a mixture of 1.5% concentrated hydrochloric acid and 1.5% hydrofluoric acid.
[0050] In some embodiments, the N-type silicon wafer after the second acid pickling treatment needs to undergo a second alkaline polishing treatment. The specific process of the second alkaline polishing treatment is as follows: the N-type silicon wafer after the second acid pickling treatment is placed in a second alkaline polishing reagent and reacted for 270 seconds.
[0051] In some embodiments, the second alkaline polishing reagent is a mixture of 24L concentrated KOH, 5L additive and 440L water, wherein the additive is BP65 and the temperature of the first alkaline polishing reagent is 65°C.
[0052] In some embodiments, after the second alkaline polishing process is completed, the first mask layer and the second mask layer are sequentially deposited on the first contact area of the N-type silicon wafer. The first mask layer is an aluminum oxide layer. The second mask layer is a silicon nitride layer.
[0053] In some embodiments, the specific process for preparing the first mask layer is as follows: the N-type silicon wafer is placed in an atomic layer deposition furnace, and 7 sccm of O2 and 18 sccm of TMA (trimethylaluminum) are introduced into the atomic layer deposition furnace. The temperature of the atomic layer deposition furnace is adjusted to 280°C, the reaction is carried out for 30 seconds, and the deposition is repeated 20 times to form an aluminum oxide layer on the first contact area, which can effectively improve the pressure and passivation effect.
[0054] In some embodiments, while depositing the second mask layer in the first contact area, it is necessary to deposit the second mask layer in the second contact area. That is, the N-type silicon wafer is placed in a vapor deposition furnace, and NO2 at 1000 sccm, silane at 1800 sccm, and ammonia at 1000 sccm are introduced, the temperature is adjusted to 510°C, and the reaction is carried out for 510 seconds to form the silicon nitride layer.
[0055] In some embodiments, the specific process of performing the first screen printing process on the N-type silicon wafer in S200 is as follows: the first paste is spread on the screen of the screen printing machine, and under pressure, the first paste is printed onto the N-type silicon wafer so that the fine grid is printed on the first preset area.
[0056] In some embodiments, the first paste is an aluminum-free silver paste. The screen printing machine has a grid-less design, which saves the amount of the first paste and reduces production costs. The grid occupies the front area of the solar cell, affecting the utilization of solar energy and reducing the effective utilization area of the cell. The grid-less design increases the effective utilization area of the N-type silicon wafer, increases the current of the cell, and improves the efficiency of the solar cell.
[0057] In some embodiments, the first sintering process in S300 is performed at a first preset temperature. The light injection process is performed at a second preset temperature and a preset light intensity. The second preset temperature is lower than the first preset temperature.
[0058] In some embodiments, the first preset temperature is 742°C. The first preset temperature is 532°C. The preset light intensity is 5500 W / m². 2 .
[0059] In some embodiments, the second sintering process is a laser-induced sintering process, and the second sintering process is performed at a preset laser power.
[0060] In some embodiments, the preset laser power is 14W, and a reverse voltage of 45V needs to be applied to the battery terminal during the second sintering process.
[0061] In some embodiments, the perovskite composite layer includes a first conductive layer, a second conductive layer, a perovskite layer, a first electron transport layer, a second electron transport layer, and a third conductive layer stacked sequentially. Stacking the perovskite composite layer on the front side of the solar cell can effectively improve the cell's short-wavelength response and low-light performance.
[0062] In some embodiments, the first conductive layer is an electron-conductive layer, the first conductive layer is an ITO layer, the first conductive layer has a first preset thickness, and the specific process for preparing the conductive layer is: using a magnetron sputtering device to sputter an ITO target onto the second preset area to form an ITO thin film layer between each of the fine gates.
[0063] In some embodiments, the second preset region is located between two adjacent first preset regions. The fine grid is disposed along a first preset direction, and the length of the second preset region along a second preset direction is greater than the length of the first preset region along the second preset direction. The second preset direction is perpendicular to the first preset direction.
[0064] In some embodiments, the second conductive layer is a hole transport layer, the second conductive layer is prepared by vacuum deposition of copper oxide, the second conductive layer has a second preset thickness, and the second conductive layer includes a NiO layer and a PVK (polyvinylcarbazole) layer.
[0065] In some embodiments, the perovskite layer is used to absorb solar energy to generate electron-hole pairs and convert solar energy into electrical energy. The perovskite layer is 450 nm thick CH3NH3PbCl3.
[0066] In some embodiments, the first electron transport layer is prepared by thermal evaporation, and the first electron transport layer plays a good electron transport role. The thickness of the first electron transport layer is 40 nm, and the first electron transport layer is C60.
[0067] In some embodiments, the second electron transport layer is prepared by atomic layer deposition, and the second electron transport layer is a dense ZnO layer.
[0068] In some embodiments, the third conductive layer is an ITO layer, which is fabricated by sputtering an ITO layer onto the second electron transport layer using magnetron sputtering. The third conductive layer has a third preset thickness. The second preset thickness is greater than the third preset thickness.
[0069] In some embodiments, the first preset thickness is 230 nm. The second preset thickness is 20 nm. The third preset thickness is 200 nm.
[0070] In some embodiments, the second paste in S400 is printed onto the third conductive layer. The second paste has a preset curing temperature and is a low-temperature conductive silver paste. Printing the low-temperature conductive silver paste onto the perovskite composite layer can adequately maintain the electrical properties of the N-type silicon wafer.
[0071] To better illustrate how the solar cell fabrication method described in this embodiment improves the photoelectric conversion efficiency of solar cells, the following verification experiments were conducted:
[0072] Experimental Group 1: Obtain a first N-type silicon wafer and fabricate a first solar cell using the first N-type silicon wafer according to the above-described method for preparing solar cells, which includes the following steps: sequentially performing texturing, boron diffusion, oxidation degradation, first acid washing, first alkaline polishing, depositing a passivation contact layer, depositing a polycrystalline silicon layer, second acid washing, second alkaline polishing, depositing a first mask layer, depositing a second mask layer, first screen printing, first sintering, light injection, second sintering, depositing a perovskite composite layer, and second screen printing.
[0073] Experimental Group 2: A second N-type silicon wafer was obtained, and the second N-type silicon wafer was used to sequentially perform texturing, boron diffusion, oxidation degradation, first acid pickling, first alkaline polishing, deposition of a passivation contact layer, deposition of a polycrystalline silicon layer, second acid pickling, second alkaline polishing, deposition of a first mask layer, deposition of a second mask layer, first screen printing, first sintering, light injection, and second sintering to obtain a second solar cell. The difference between the second solar cell obtained in Experimental Group 2 and the first solar cell obtained in Experimental Group 1 is that the second solar cell does not include the steps of depositing a perovskite composite layer and the second screen printing process.
[0074] Experiment Group 3: Obtain a third N-type silicon wafer, and perform a perovskite composite layer deposition and a second screen printing process on the third N-type silicon wafer to obtain a third solar cell.
[0075] The electrical performance IV tests were performed on the first solar cell prepared in Experiment 1, the second solar cell prepared in Experiment 2, and the third solar cell prepared in Experiment 3 to obtain the electrical performance comparison table of open circuit voltage (Voc), current density (Jsc), fill factor (FF), and photoelectric conversion efficiency (Eff) as shown in Table 1.
[0076] Table 1. Comparison of Electrical Performance
[0077] Group Voc(V) <![CDATA[Jsc(mA / cm 2 )]]> FF (%) Eff(%) Experimental Group 1 35.35 Experimental Group 2 0.738 31.42 83.55 19.38 Experimental Group 3 1.18 18.5 73.2 15.97
[0078] Due to the difficulty in ensuring completely consistent experimental conditions, the above experimental data contains certain errors, but these do not affect the final experimental results. As shown in Table 1, the photoelectric conversion efficiency of the first solar cell in Experimental Group 1 is significantly higher than that of the second solar cell in Experimental Group 2 and the third solar cell in Experimental Group 3. This application, through a gridless design, saves the amount of the first paste, reduces production costs, and reduces the area occupied by the grid on the front side of the cell, thereby increasing the effective utilization area of the cell and improving the photoelectric conversion efficiency. Furthermore, stacking the perovskite composite layer on the front side of the cell effectively improves the cell's short-wavelength response and weak light effect. In addition, printing low-temperature conductive silver paste on the perovskite composite layer can fully maintain the cell's electrical performance.
[0079] Example 2
[0080] This application provides a solar cell (not shown in the figure). The solar cell is prepared by the method of preparing the solar cell in the above embodiment 1. Therefore, it has all the beneficial effects of the method of preparing the solar cell in the above embodiment, which will not be described in detail here.
[0081] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.
[0082] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.
Claims
1. A method for producing a solar cell, characterized by, The application relates to a preparation method of a solar cell. The application relates to a preparation method of a solar cell. The application relates to a preparation method of a solar cell. The application relates to a preparation method of a solar cell. The application relates to a preparation method of a solar cell.
2. The method of producing a solar cell according to claim 1, wherein The application relates to a preparation method of a solar cell.
3. The method of producing a solar cell according to claim 2, wherein The application relates to a preparation method of a solar cell.
4. The method of producing a solar cell according to claim 3, wherein The application relates to a preparation method of a solar cell.
5. The method of producing a solar cell according to claim 3, wherein The application relates to a preparation method of a solar cell.
6. The method of producing a solar cell according to claim 1, wherein The application relates to a preparation method of a solar cell.
7. The method of producing a solar cell according to claim 1, wherein The application relates to a preparation method of a solar cell.
8. The method of producing a solar cell according to claim 7, wherein The application relates to a preparation method of a solar cell.
9. The method of producing a solar cell according to any one of claims 1 to 8, wherein The application relates to a preparation method of a solar cell.
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