High-density three-dimensional integrated digital transceiver module and preparation method thereof

Abstract

The invention discloses a high-density three-dimensional integrated digital transceiver module and a preparation method thereof. The module comprises a bottom solder ball, a sealing substrate, a first dielectric layer, an internal solder ball, a switching substrate, a second dielectric layer, an inverted bump, a chip, a passive device, a third dielectric layer and a sealing cover plate. The passive device is arranged on the upper surface of the switching substrate or integrated in the switching substrate; the switching substrate is connected to the upper surface of the sealing substrate through an internal solder ball; the chip is inversely arranged on the upper surface or the lower surface of the switching substrate through the inverted salient points; a gap between the switching substrate and the sealing substrate is filled with the first dielectric layer; a gap between the chip and the switching substrate is filled with the second dielectric layer; the third dielectric layer is filled between the chip and the lower surface of the sealing cover plate; the bottom solder balls are arranged on the lower surface of the sealing substrate. According to the invention, the integration level of the module can be effectively improved, the weight and the size of the module are greatly reduced, and the lightness and the miniaturization of the multi-channel digital transceiver module are realized.

Description

Technical Field

[0001] This invention belongs to the field of digital transceiver technology, specifically relating to a high-density three-dimensional integrated digital transceiver module and its preparation method. Background Technology

[0002] Given the increasing demand for multifunctional and miniaturized radar systems, digital transceiver modules (DVRs), as crucial components of phased array radar DVR systems, require small size, light weight, integrated design, and high reliability. Most existing DVRs employ discrete component integration schemes, resulting in large size and poor signal interference immunity. Therefore, high-density integrated DVRs have become a vital solution for miniaturizing and lightening these modules. Summary of the Invention

[0003] The purpose of this invention is to provide a high-density three-dimensional integrated digital transceiver module and its fabrication method, which can achieve high integration and miniaturization of the module, and solve the difficulty of miniaturizing multi-channel digital transceiver modules.

[0004] To achieve the above objectives, one aspect of the present invention provides a high-density three-dimensional integrated digital transceiver module, including bottom solder balls, a sealing substrate, a first dielectric layer, internal solder balls, an adapter substrate, a second dielectric layer, flip-chip bumps, a chip, passive devices, a third dielectric layer, and a sealing cover. Passive components are disposed on the upper surface of the adapter substrate or integrated inside the adapter substrate; the adapter substrate is connected to the upper surface of the sealing substrate through internal solder balls; the chip is flip-chip disposed on the upper or lower surface of the adapter substrate through flip-chip bumps. The chip includes an FPGA chip, a DDS chip, an ADC chip, a DAC chip, and an RF transceiver chip, wherein the FPGA chip, DDS chip, ADC chip, and RF transceiver chip are disposed on the upper surface of the adapter substrate, and the DAC chip is disposed on the lower surface of the adapter substrate. The first dielectric layer fills the gap between the adapter substrate and the sealing substrate; the second dielectric layer fills the gap between the chip and the adapter substrate; the third dielectric layer fills the space between the chip and the lower surface of the sealing cover; and the bottom solder balls are disposed on the lower surface of the sealing substrate.

[0005] Another aspect of the present invention provides a method for fabricating the above-described high-density three-dimensional integrated digital transceiver module, comprising: Step 1: Solder the FPGA chip and passive components to the upper surface of the adapter substrate using a flip-chip soldering process and then clean them. Step 2: Gold balls are implanted on the chip PAD as flip-chip bumps using a ball-planting process to attach the RF transceiver chip, DDS chip, ADC chip, and DAC chip. Step 3: The chip with the gold balls implanted is bonded to the upper or lower surface of the adapter substrate using a flip-chip bonding process. Step four: Fill the second dielectric layer on the chip that has completed the flip-chip process using the bottom fill process; Step 5: Place solder balls as internal solder balls on the adapter substrate. The diameter of the solder balls is 0.3mm-0.5mm. Step 6: Solder the adapter board with solder balls onto the sealing board using a flip-chip soldering process and then clean it. Step 7: Fill the first dielectric layer on the adapter substrate that has completed the flip-chip bonding process using a bottom fill process; Step 8: Apply thermally conductive adhesive to the back of the chip as a third dielectric layer, and then use parallel seam welding to hermetically seal the sealing cover.

[0006] According to the high-density three-dimensional integrated digital transceiver module and its fabrication method described above, FPGA, ADC, DAC, DDS and RF transceiver chips and passive components are integrated on the adapter substrate, which can effectively improve the integration of the module, greatly reduce the weight and volume of the module, and realize the miniaturization of multi-channel digital transceiver modules. Attached Figure Description

[0007] To more clearly illustrate the technical solutions of the present invention, the accompanying drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort: Figure 1 This is a cross-sectional structural diagram of a high-density three-dimensional integrated digital transceiver module according to an embodiment of the present invention. Detailed Implementation

[0008] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0009] One embodiment of the present invention provides a high-density three-dimensional integrated digital transceiver module, such as... Figure 1 As shown, the high-density three-dimensional integrated digital transceiver module of this embodiment includes bottom solder balls 1, a sealing substrate 2, a first dielectric layer 3, internal solder balls 4, an adapter substrate 5, a second dielectric layer 6, flip-chip bumps 7, a chip 8, passive components 9, a third dielectric layer 10, and a sealing cover plate 11. The bottom solder balls 1 and the internal solder balls 4 can also be solder pillars.

[0010] The passive component 9 can be disposed on the upper surface of the adapter substrate 5 or integrated into the interior of the adapter substrate 5 through IPD integration process, or it can be disposed on the upper surface of the sealing substrate 2. When the passive component 9 is disposed on the upper surface of the adapter substrate 5, it can balance minimizing integration and difficulty; when the passive component 9 is disposed on the upper surface of the sealing substrate 2, the integration level is poor, but the difficulty is the lowest; when the passive component 9 is integrated into the interior of the adapter substrate 5, the integration level is the highest, but the difficulty is the greatest.

[0011] The adapter substrate 5 is connected to the upper surface of the sealing substrate 2 via internal solder balls 1. Chip 8 is flip-chip mounted on the upper or lower surface of the adapter substrate via flip-chip bumps 7. Chip 8 includes FPGA, ADC, DAC, DDS, and RF transceiver chips. Currently, FPGA-controlled DDS (Direct Digital Synthesis) is the mainstream method for generating radar waveforms, supporting flexible adjustment of parameters such as waveform mode, bandwidth, and pulse width, achieving waveform agility. With the increase in operating frequency, DDS can directly output RF signals, eliminating the need for analog up-conversion circuitry. The increased sampling rate of the analog-to-digital converter (ADC) supports direct sampling of intermediate frequency and even RF signals, simplifying the RF signal analog conditioning circuitry and improving quadrature consistency.

[0012] The third dielectric layer 10 is filled between the lower surfaces of the chip 8 and the sealing cover plate 11; the second dielectric layer 6 is filled between the chip 8 and the adapter substrate 5; and the first dielectric layer 3 is filled between the adapter substrate 5 and the sealing substrate 2.

[0013] Bottom solder balls 1 are disposed on the lower surface of the sealing substrate 2. The sealing substrate 2 includes a TSV silicon substrate, a TCV glass substrate, and a DPC ceramic substrate. The adapter substrate 5 completes vertical signal communication through a through-hole structure. The adapter substrate 5 includes a TSV silicon substrate, a TCV glass substrate, and a DPC ceramic substrate. Chip flip-chip bonding includes solder ball bump flip-chip bonding and gold bump flip-chip bonding. The third dielectric layer 10 uses thermally conductive materials such as thermally conductive adhesive. The first dielectric layer 3 and the second dielectric layer 6 use underfill materials such as underfill adhesive. The sealing substrate 2 and the sealing cover plate 11 are sealed by a parallel seam welding process.

[0014] The manufacturing process of the high-density three-dimensional integrated digital transceiver module according to an embodiment of the present invention is as follows: Step 1: The FPGA chip and passive device 9 are soldered to the upper surface of the adapter substrate 5 using a flip-chip soldering process and then cleaned. Preferably, in this step, the chip and passive device with solder ball bumps are integrated to the upper surface of the adapter substrate by reflow soldering. Step 2: Gold balls are implanted on the chip PAD as flip-chip bumps for the RF transceiver, DDS, ADC, and DAC chips using a ball-planting process. Step 3: The chip with gold balls attached is bonded to the upper or lower surface of the adapter substrate 5 using a flip-chip bonding process. Preferably, in this step, the chip with gold bumps is integrated to the upper and lower surfaces of the adapter substrate by a hot-pressing process or a hot-pressing ultrasonic process. Step four: The chip that has completed the flip-chip process is underfilled with the second dielectric layer 6. Preferably, in this step, underfilling technology is used, and the second dielectric layer 6 is underfilled to different positions according to different filling heights through a curing process. Step 5: Place solder balls as internal solder balls 4 on the adapter substrate 5. The diameter of the solder balls is 0.3mm-0.5mm. Step 6: After the solder balls are attached to the adapter substrate 5, the substrate is soldered to the sealing substrate 2 using a flip-chip soldering process and then cleaned. Preferably, in this step, surface mount technology is used to stack the adapter substrate with integrated chips onto the upper surface of the sealing substrate using a reflow soldering process. Step 7: The adapter substrate 5 that has completed the flip-chip bonding process is filled with the first dielectric layer 3. Preferably, in this step, the first dielectric layer 3 is filled to different positions according to different filling heights through a curing process. Step 8: After applying thermally conductive adhesive to the back of the topmost chip as the third dielectric layer 10, the module is sealed. Preferably, in this step, a coating technique is used to coat the third dielectric layer 10 onto the upper surface of the chip, and the sealing cover is hermetically sealed by a parallel seam welding process.

[0015] In summary, the high-density three-dimensional integrated digital transceiver module of this invention utilizes a high-density three-dimensional integrated architecture. A transceiver substrate with vertical signal connectivity is stacked on a sealed substrate using solder balls / pillars. FPGA, ADC, DAC, DDS, and RF transceiver chips, along with passive components, are integrated on the transceiver substrate using flip-chip technology. The integrated transceiver substrate is then stacked onto the sealed substrate surface using a reflow soldering process. Multiple dielectric layers are used as bottom fillers or thermal conductive materials within the module. This fully leverages the advantages of the transceiver substrate's high integration, shortened signal transmission path, reduced power consumption, and increased data transmission bandwidth. The resulting digital transceiver module boasts high integration, miniaturization, high bandwidth, high heat dissipation, and high reliability, with a transmission frequency range of 10MHz to 18GHz, making it widely applicable in digital signal transceiver systems.

[0016] The foregoing has only described certain exemplary embodiments of the present invention by way of illustration. Undoubtedly, those skilled in the art can modify the described embodiments in various ways without departing from the spirit and scope of the present invention. Therefore, the foregoing drawings and descriptions are illustrative in nature and should not be construed as limiting the scope of protection of the claims of the present invention.

Claims

1. A high-density three-dimensional integrated digital transceiver module, characterized by, The bottom solder ball, the sealing substrate, the first dielectric layer, the internal solder ball, the adapter substrate, the second dielectric layer, the flip chip, the passive device, the third dielectric layer and the sealing cover plate are included. The passive device is arranged on the upper surface of the adapter substrate or integrated in the interior of the adapter substrate; the adapter substrate is connected to the upper surface of the sealing substrate through the internal solder ball; The chip is arranged on the upper surface or the lower surface of the adapter substrate through the flip chip; The chip includes the FPGA chip, the DDS chip, the ADC chip, the DAC chip and the radio frequency transceiver chip, wherein the FPGA chip, the DDS chip, the ADC chip and the radio frequency transceiver chip are arranged on the upper surface of the adapter substrate, and the DAC chip is arranged on the lower surface of the adapter substrate; The first dielectric layer is filled in the gap between the adapter substrate and the sealing substrate; the second dielectric layer is filled in the gap between the chip and the adapter substrate; and the third dielectric layer is filled between the chip and the lower surface of the sealing cover plate; The bottom solder ball is arranged on the lower surface of the sealing substrate.

2. The high-density three-dimensional integrated digital transceiver module of claim 1, wherein, The chip includes the FPGA, the ADC, the DAC and the radio frequency transceiver chip.

3. The high-density three-dimensional integrated digital transceiver module of claim 1 or 2, wherein, The sealing substrate and the adapter substrate include the TSV silicon substrate, the TCV glass substrate and the DPC ceramic substrate.

4. The high-density three-dimensional integrated digital transceiver module of claim 1 or 2, wherein, The adapter substrate realizes the signal communication in the vertical direction through the via structure.

5. The high-density three-dimensional integrated digital transceiver module of claim 1 or 2, wherein, The flip chip includes the tin ball bump and the gold bump.

6. The high-density three-dimensional integrated digital transceiver module of claim 1 or 2, wherein, The first dielectric layer adopts the heat-conducting glue, and the second dielectric layer and the third dielectric layer adopt the bottom filling glue.

7. A high-density three-dimensional integrated digital transceiver module according to claim 1 or 2, wherein The sealing substrate and the sealing cover plate are sealed through the parallel seam welding process.

8. A method of manufacturing a high-density three-dimensional integrated digital transceiver module according to any one of claims 1-7, characterized by, The method includes the following steps: Step one, the FPGA chip and the passive device are welded to the upper surface of the adapter substrate through the flip welding process and cleaned; Step two, the radio frequency transceiver chip, the DDS chip, the ADC chip and the DAC chip are planted with gold balls as flip bumps on the chip PAD through the ball planting process; Step three, the chip with the planted gold ball is bonded to the upper surface or the lower surface of the adapter substrate through the flip bonding process; Step four, the second dielectric layer is filled through the bottom filling process for the chip after the flip process is completed; Step five, the tin ball is planted on the adapter substrate as the internal solder ball, and the diameter of the tin ball is 0.3mm-0.5mm; Step six, the adapter substrate with the planted tin ball is welded to the sealing substrate through the flip welding process and cleaned; Step seven, the first dielectric layer is filled through the bottom filling process for the adapter substrate after the flip welding process is completed; Step eight, the heat-conducting glue is coated as the third dielectric layer on the back of the chip, and the sealing cover plate is airtightly packaged through the parallel seam welding process.

9. The production method according to claim 8, characterized by, In step three, the chip with the planted gold ball is integrated into the upper surface or the lower surface of the adapter substrate through the hot pressing process or the hot pressing ultrasonic process.

10. The method of claim 9, wherein, In step six, the adapter substrate with the integrated chip is stacked to the upper surface of the sealing substrate through the reflow welding process by using the surface mounting technology.

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