Systems and methods for assessing scalability of quantum computing systems

Abstract

Systems and methods for assessing scalability of a quantum system are provided. In one example, a method may include obtaining benchmark performance data for a candidate quantum system architecture. The benchmark performance data may describe one or more performance characteristics of the candidate quantum system architecture for a plurality of processor sizes. The method may include obtaining one or more scaling parameters based on the benchmark performance data, the one or more scaling parameters including a quantum scaling model that associates a processor size of the candidate quantum system architecture with the one or more performance characteristics. The method may include determining, by the quantum scaling model, one or more scaling metrics for the candidate quantum system architecture at a scaled processor size that is greater than the plurality of processor sizes. The method may include determining one or more control actions for the operational quantum system based on the one or more scaling indicators.

Description

Technical Field

[0001] This disclosure generally relates to systems and methods for evaluating the scalability of quantum computing systems.

[0002] Cross-references to related applications

[0003] This application is based on and claims priority to U.S. Patent Application No. 18 / 364,305, filed August 2, 2023, the disclosure of which is hereby incorporated herein by reference in its entirety for all purposes. Background Technology

[0004] Quantum computing is a method of computation that utilizes quantum effects, such as superposition of ground states and entanglement, to perform specific calculations more efficiently than classical digital computers. Unlike digital computers that store and process information in bits (e.g., "1" or "0"), quantum computing systems can process information using qubits. A qubit can refer to a quantum device that enables the superposition of multiple states, such as data in "0" and "1" states, and / or to the superposition of data itself in multiple states. In conventional terms, the superposition of "0" and "1" states in a quantum system can be represented as, for example... The "0" and "1" states of a digital computer are similar to those of a qubit. and Ground state. Summary of the Invention

[0005] Various aspects and advantages of embodiments of this disclosure will be set forth in part in the description which follows, or may be learned from the description, or may be learned by practice of the embodiments.

[0006] One example aspect of this disclosure relates to a method for evaluating the scalability of a quantum system. The method may include obtaining benchmark performance data for a candidate quantum system architecture. The benchmark performance data may describe one or more performance characteristics of the candidate quantum system architecture for multiple processor sizes. The method may include obtaining one or more scaling parameters based on the benchmark performance data. The one or more quantum scaling parameters may include a quantum scaling model that correlates the processor size of the candidate quantum system architecture with one or more performance characteristics of the candidate quantum system architecture. The method may include determining one or more scaling metrics for the candidate quantum system architecture at scaled processor sizes greater than multiple processor sizes using the quantum scaling model. The method may include determining one or more control actions for an operational quantum system based on the one or more scaling metrics.

[0007] These and other features, aspects, and advantages of the various embodiments of this disclosure will be better understood with reference to the following description and the appended claims. The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the disclosure and, together with the description, explain the relevant principles. Attached Figure Description

[0008] Referring to the accompanying drawings, a detailed discussion of embodiments is set forth in this specification for those skilled in the art, in which:

[0009] Figure 1 An example of a quantum computing system according to an exemplary aspect of this disclosure is depicted;

[0010] Figure 2 A schematic diagram of an example system for evaluating the scalability of candidate quantum system architectures, according to aspects of this disclosure, is depicted;

[0011] Figure 3 A diagram depicts examples of baseline performance data for a given performance benchmark and corresponding scaling models according to aspects of this disclosure;

[0012] Figure 4 A flowchart is depicted illustrating an example method for evaluating the scalability of candidate quantum system architectures according to an example aspect of this disclosure;

[0013] Figure 5A A block diagram of an example computational system for implementing calibration model evaluation is depicted according to an example aspect of this disclosure;

[0014] Figure 5B A block diagram of an example computing device for implementing calibration model evaluation according to an example aspect of this disclosure is depicted; and

[0015] Figure 5C A block diagram of an example computing device for implementing calibration model evaluation is depicted according to an example aspect of this disclosure. Detailed Implementation

[0016] Example embodiments of some aspects of this disclosure relate to systems and methods for evaluating the scalability of quantum computing systems. Evaluating the scalability of a quantum computing system can be challenging, as quantum computing systems typically include quantum processors configured according to the architecture and control system. For example, building larger quantum systems to measure the performance of those systems at scales including tens, hundreds, or even thousands of qubits can be costly and / or infeasible. Therefore, it is beneficial to simulate or build smaller-scale quantum systems and infer the performance of larger quantum systems from those smaller-scale quantum systems.

[0017] However, extrapolating the performance of large systems from relatively small systems can be challenging because increasingly larger quantum systems may be affected by a growing number of degradation sources. For example, as the scale of a quantum system increases, both the hardware architecture and / or control sources can contribute to the degradation of quantum operations. For instance, the hardware system may be affected by increased control crosstalk, where one qubit's control line is weakly coupled to another qubit, potentially leading to control errors. Alternatively, the hardware system may be affected by increased quantum crosstalk, such as frequency collisions and / or qubit parasitic couplings, which can lead to control errors such as swapping errors, phase errors, and / or leakage errors. Alternatively, the hardware system may be affected by increased fabrication non-uniformity, which can lead to variations in qubit circuit parameters, such as maximum frequency, flux sensitivity, and / or other qubit circuit parameters. Furthermore, due to the complex interactions between various components, the distinction between different sources of error may not always be clearly determined.

[0018] Furthermore, controlling larger quantum systems can be difficult because progressively scaling quantum systems can lead to frequency configurations that typically increase exponentially and frequency constraints that typically increase linearly, which can be computationally challenging to optimize. Additionally, larger quantum systems may experience more catastrophic performance anomaly gates due to drift during calibration. For example, a defective frequency transition in a two-level system (TLS) can fluctuate into the path of the gate frequency trajectory. Moreover, larger systems may be more sensitive to constraint propagation on the processor. For instance, a single anomalous frequency constraint or performance outlier can degrade several nearby gates. As a concrete example, a single qubit with an abnormally low maximum frequency can “pull down” the frequencies of surrounding qubits, thereby minimizing frequency shifts during two-qubit gates. This can potentially help dephase those surrounding qubits.

[0019] The inventors have discovered that, due to these complex sources of degradation as the size of quantum systems increases, it is currently impossible to infer the scalability of a quantum computing system by measuring the performance metrics of a fixed-size system. To address these issues, this disclosure provides systems and methods for evaluating the scalability of a quantum computing system architecture (e.g., quantum hardware architecture and / or control strategy) based on benchmark performance measurements of progressively larger quantum systems, according to the quantum computing system architecture. For example, aspects of this disclosure can utilize scalability models that accurately model the performance of a quantum computing system architecture at scales, such as those used to implement practical quantum algorithms (e.g., approximately tens or hundreds of qubits). Furthermore, determining the scalability model can be performed using data from real or simulated quantum systems much smaller than those used to implement practical quantum algorithms, such as those of approximately ten or fewer qubits. In this way, the scalability of a given quantum computing system architecture can be evaluated at scale without scaling up the operational quantum computing system.

[0020] A quantum computing system architecture (or quantum system architecture) can define a hardware architecture or procedural architecture and a control strategy. The hardware architecture can specify, describe, or otherwise represent the structural characteristics of the quantum computing system, such as the qubits of the quantum computing system. For example, an example hardware architecture can define frequency-tunable superconducting transmon qubits. Alternatively or concurrently, the hardware architecture can define ion qubits, neutral atom qubits, photon qubits, semiconductor defect qubits, quantum dots, and so on. The hardware architecture can also define structural characteristics such as qubit type characteristics (e.g., defining the type of qubits), qubit arrangement characteristics (e.g., defining an arrangement of one or more qubits), control signal line arrangement characteristics (e.g., defining an arrangement of one or more control signal lines coupled to one or more qubits), fabrication characteristics, and / or dependency characteristics (e.g., defining known dependencies between multiple qubits). Furthermore, the control strategy can specify, describe, or otherwise represent the operational characteristics of the quantum system, such as, for example, operating frequency, optimization, calibration interventions, and / or other suitable aspects of controlling the quantum hardware.

[0021] Example embodiments based on some aspects of this disclosure can provide numerous technical effects and benefits, such as improvements to computing techniques (e.g., quantum computing techniques). For example, evaluating candidate quantum computing system architectures at the scale required to implement practical quantum algorithms using a scalability model allows for accurate evaluation of those candidate architectures while avoiding the costs associated with building large-scale quantum computing systems. Alternatively or additionally, using a scalability model can save computational resources associated with simulating large-scale quantum computing systems and / or provide options for evaluating computationally difficult-to-simulate systems. Furthermore, example aspects of this disclosure can provide for designing and / or implementing quantum computing system architectures with improved scalability. This, in turn, can provide improvements in the performance of quantum computing systems, such as reduced gate errors.

[0022] Exemplary embodiments of this disclosure will now be discussed in further detail with reference to the accompanying drawings.

[0023] Figure 1 An example quantum computing system 100 is depicted. Example system 100 is an example of a system on one or more classical computers or quantum computing devices at one or more locations in which the systems, components, and techniques described below can be implemented. Those skilled in the art will understand using the disclosure provided herein that other quantum computing structures or systems can be used without departing from the scope of this disclosure.

[0024] System 100 includes quantum hardware 102 that communicates data with one or more classical processors 104. Quantum hardware 102 includes components for performing quantum computing. For example, quantum hardware 102 includes a quantum system 110, a control device 112, and a readout device 114 (e.g., a readout resonator). Quantum system 110 may include one or more multilevel quantum subsystems, such as registers of qubits. In some implementations, the multilevel quantum subsystem may include superconducting qubits, such as flux qubits, charge qubits, transmon qubits, gmon qubits, etc.

[0025] The type of multilevel quantum system used in system 100 may vary. For example, in some cases, it may be convenient to include one or more readout devices 114 attached to one or more superconducting qubits (e.g., transmon qubits, flux qubits, gmon qubits, xmon qubits, or other qubits). In other cases, ion traps, photonic devices, or superconducting cavities may be used (e.g., which allow for state preparation without the need for qubits). Further examples of implementations of multilevel quantum systems include fluxmon qubits, silicon quantum dots, or phosphorus-impurity qubits.

[0026] Quantum circuits can be constructed and applied to registers of qubits included in the quantum system 110 via multiple control lines coupled to one or more control devices 112. Example control devices 112 operating on the qubit registers can be used to implement quantum gates or quantum circuits with multiple quantum gates, such as Pauli gates, Hadamard gates, controlled-NOT (CNOT) gates, controlled-phase gates, T-gates, multi-qubit quantum gates, coupler quantum gates, etc. One or more control devices 112 can be configured to operate the quantum system 110 via one or more corresponding control parameters (e.g., one or more physical control parameters). For example, in some implementations, the multi-level quantum subsystem may be superconducting qubits, and the control devices 112 may be configured to provide control pulses to the control lines to generate magnetic fields to adjust the frequency of the qubits.

[0027] Quantum hardware 102 may further include a readout device 114 (e.g., a readout resonator). Measurement results 108 obtained via the measurement device can be provided to classical processor 104 for processing and analysis. In some implementations, quantum hardware 102 may include quantum circuits, and control device 112 and readout device 114 may implement one or more quantum logic gates that operate the quantum system 102 via physical control parameters (e.g., microwave pulses) transmitted via wires included in quantum hardware 102. Further examples of the control device include an arbitrary waveform generator, where a DAC (digital-to-analog converter) creates the signal.

[0028] The readout device 114 can be configured to perform a quantum measurement on the quantum system 110 and send the measurement result 108 to the classical processor 104. Additionally, the quantum hardware 102 can be configured to receive data from the classical processor 104 specifying physical control qubit parameter values ​​106. The quantum hardware 102 can use the received physical control qubit parameter values ​​106 to update the actions of the control device 112 and the readout device 114 on the quantum system 110. For example, the quantum hardware 102 can receive data specifying a new value representing the voltage intensity of one or more DACs included in the control device 112, and the quantum hardware can update the actions of the DACs on the quantum system 110 accordingly. The classical processor 104 can be configured, for example, to initialize the quantum system 110 in an initial quantum state by sending data specifying an initial parameter set 106 to the quantum hardware 102.

[0029] Readout device 114 can utilize elements of a quantum system (such as qubits). and The impedance difference between states is used to measure the state of an element (e.g., a qubit). For example, due to the nonlinearity of the qubit, when the qubit is in a state... or state The resonant frequency of the readout resonator can be different. Therefore, the microwave pulse reflected from the readout device 114 carries an amplitude and phase shift that depends on the qubit state. In some implementations, a Purcell filter can be used in conjunction with the readout device 114 to block microwave propagation at the qubit frequency.

[0030] In some implementations, the quantum system 110 may include, for example, a plurality of qubits 120 arranged in a two-dimensional grid 122. For clarity, Figure 1 The two-dimensional grid 122 depicted includes 16 qubits arranged in a square pattern; however, in some implementations, system 110 may include fewer or more qubits. In some embodiments, the multiple qubits 120 may interact with each other through multiple qubit couplers (e.g., qubit coupler 124). The qubit couplers may define the nearest-neighbor interactions between the multiple qubits 120. In some implementations, the strength of the multiple qubit couplers is an adjustable parameter. In some cases, the multiple qubit couplers included in the quantum computing system 100 may be couplers with a fixed coupling strength. In some implementations, the multiple qubits 120 may include data qubits (such as qubit 126) and measurement qubits (such as qubit 128). Data qubits are qubits that participate in the computation performed by system 100. Measurement qubits are qubits that can be used to determine the result of the computation performed by the data qubits. That is, during computation, the unknown state of the data qubits is transferred to the measurement qubits using appropriate physical operations and measured via appropriate measurement operations performed on the measurement qubits.

[0031] In some implementations, each of the multiple qubits 120 can operate using a corresponding operating frequency, such as an idle frequency and / or an interaction frequency and / or a readout frequency and / or a reset frequency. Different qubits may operate at different frequencies. For example, each qubit may be idle at a different operating frequency. The operating frequencies of the qubits 120 can be selected before the calibration system performs computations. Some operating frequencies are better than others. One measure of the merits of a particular operating frequency for a particular qubit is the energy relaxation time (T1) of the qubit at that frequency. A lower energy relaxation time can lead to larger quantum computation errors.

[0032] In various implementations, example system 100 can be implemented as a client device, a server device, or both. Example system 100 can be implemented as part of a distributed computing system. Example system 100 can be implemented with other example systems, which may be the same or different. Example system 100 can be implemented in a server farm or other facility that operates multiple computing systems to provide computing services to or on behalf of multiple client systems. Advantageously, the techniques according to the example aspects of this disclosure can provide improved calibration and maintenance of computing facilities, increased service uptime, reduced failure rates, etc.

[0033] Figure 2 A diagram depicts an example system 200 for evaluating the scalability of candidate quantum system architectures according to aspects of this disclosure. System 200 can be configured to evaluate one or more candidate quantum system architectures 202. Each of the candidate quantum system architectures 202 can specify, represent, or otherwise define a different configuration of the quantum computing system. Each candidate quantum system architecture 202 can specify a quantum hardware architecture 203 and a control policy 204.

[0034] System 200 can select a candidate quantum system architecture 202 for scalability evaluation. For example, in some implementations, evaluating the scalability of a candidate quantum system architecture 202 may include selecting a hardware architecture 203 and / or a control policy 204 for the candidate quantum system architecture 202. In some implementations, a user (e.g., a quantum programmer or quantum system designer) may manually select the hardware architecture 203 and / or control policy 204 to be tested. Alternatively, in some implementations, the hardware architecture 203 and / or control policy 204 may be selected iteratively or automatically. For example, in some implementations, the candidate quantum system architecture 202 may be periodically selected and / or tested as an optimization loop to gradually improve the scalability of the quantum computing system over time. For example, system 200 may repeatedly test variable hardware architectures 203 and / or control policies 204 to optimize relevant scaling metrics and / or algorithms in deployment.

[0035] The hardware architecture 204 of the candidate quantum system architecture 202 can define or specify structural characteristics of the candidate quantum system architecture 202 (e.g., one or more qubits of the candidate quantum system architecture 202). Structural characteristics can relate to aspects of the candidate quantum system architecture 202 that are fixed for a given qubit type and / or architecture, such as, for example, qubit type characteristics, qubit arrangement characteristics, control signal line arrangement characteristics, fabrication characteristics, and / or dependency characteristics. Example structural characteristics may include, but are not limited to: capacitance (e.g., self-capacitance), Josephson junction resistance, qubit anharmonicity, qubit-controlled mutual inductance distribution, maximum frequency, readout resonator frequency, Josephson junction asymmetry, two-level system (TLS) TLS number density, TLS frequency, TLS coherence, TLS qubit decoupling, qubit quality, qubit-controlled mutual inductance prime number distribution, driving impedance, resonator internal quality, resonator coupling quality, resonator-qubit coupling efficiency, bandpass filter frequency, bandpass filter quality, transporter frequency, T1 spectrum, single-qubit frequency, or qubit grid frequency.

[0036] Control strategy 204 can define or specify operational characteristics of candidate quantum system architecture 202 (e.g., one or more qubits of candidate quantum system architecture 202). For example, control strategy 204 may include data describing the operational characteristics of classical or quantum hardware of quantum computing system 100, such as qubit operational characteristics (e.g., including qubits and qubit couplers) and readout resonator characteristics. Alternatively or additionally, control strategy 204 may instruct one or more calibration interventions or one or more optimization interventions. Calibration interventions can provide or describe instructions for calibrating one or more aspects of the quantum computing system. Different calibration interventions can reflect or embody different calibration strategies, such as by manipulating different parameters, implementing different timelines for adjusting parameters, determining whether to fully implement the intervention, etc. For example, different calibration interventions can be configured with different responses to a given set of input characteristics. For example, threshold-based heuristics can be configured with different trigger points (e.g., for identifying components with anomalous characteristics). For example, for a given quantum system architecture 202 describing multiple qubits, different calibration models can identify different qubits for calibration, different gate frequencies for adjustment, or other different operational characteristics for calibration.

[0037] Operating characteristics may include data describing both controlled and / or uncontrolled characteristics. As an example, the operating characteristics of one or more qubits may include one or more operating frequencies of the qubits in candidate quantum system architecture 202. As another example, operating characteristics may include data describing environmental conditions or other characteristics that are not directly controlled or cannot be directly controlled. As a further example, operating characteristics may include one or more of the following: single-qubit gate frequency trajectory, two-qubit gate frequency trajectory, readout frequency trajectory, maximum / minimum operating frequency, frequency anharmonicity, bias voltage, coupling efficiency, Ramsey coherence time, spin echo coherence time, CPMG dephasing time, energy relaxation time, Rabi oscillation, pulse amplitude, pulse length, pulse frequency, single-qubit random benchmark (RB) error, single-qubit cross-entropy benchmark (XEB) error, two-qubit RB error, two-qubit XEB error, or two-qubit XEB purity error.

[0038] Example quantum systems can be designed, constructed, and / or simulated based on candidate quantum system architecture 202 to generate benchmark performance data 216, which represents the performance of those systems at different numbers of qubits. For example, a small-scale quantum computing system 206 can be designed and / or constructed based on candidate quantum system architecture 202. Small-scale quantum computing system 206 can be a physical (e.g., real-world) quantum computing system constructed according to the candidate quantum system architecture, such that system 206 can perform quantum gate operations. Small-scale quantum computing system 206 may include one or more qubits, but may include only a limited number of qubits (e.g., fewer than 10 qubits, fewer than 20 qubits, etc.).

[0039] Alternatively, the simulated quantum computing system 209 may be generated by one or more simulated quantum system generation models 208. Depending on the candidate quantum system architecture 202, the simulated quantum computing system 209 may be or may include data, models, or other virtual (e.g., in classical computing) representations of a quantum computing system. For example, in one instance, parameters of the candidate quantum system architecture 202 may be input into the simulated quantum system generation model 208, which is configured to generate samples of quantum hardware (e.g., quantum processors) based on architecture 202.

[0040] In one example implementation, the simulated quantum system generation model 208 is configured to model the statistical distribution of the quantum system based on parameters specified by architecture 202 (e.g., manufacturing variations, operational variations, etc.). For example, the simulated quantum system generation model 208 may model a distribution of quantum hardware parameters, such as circuit parameters, one or more electrical parameters, one or more manufacturing parameters, or one or more defect parameters. In some implementations, the quantum hardware parameter distribution may include at least one of a qubit distribution, a qubit circuit distribution, a qubit relaxation distribution, or a background loss distribution. In some implementations, one or more quantum hardware parameter distributions may include at least one of the following: capacitance (e.g., qubit self-capacitance), junction resistance (e.g., Josephson junction resistance), qubit anharmonicity, qubit-controlled mutual inductance distribution, maximum frequency, readout resonator frequency, Josephson junction asymmetry, two-level system (TLS) TLS number density, TLS frequency, TLS coherence, TLS qubit decoupling, qubit quality, qubit-controlled mutual inductance prime number distribution, driving impedance, resonator internal quality, resonator coupling quality, resonator-qubit coupling efficiency, bandpass filter frequency, bandpass filter quality, transporter frequency, T1 spectrum, single-qubit frequency, or qubit grid frequency. In some implementations, the simulated quantum system generation model 208 may be or may include a joint probability distribution over the quantum hardware parameter distributions.

[0041] In some implementations, the quantum hardware parameter distribution can be a “simple distribution” that returns one or more numbers corresponding to some parameters of the quantum hardware (such as circuit parameters, manufacturing parameters, TLS, etc.). The quantum hardware parameter distribution can be sampled to generate parameter distribution samples. Distribution samples can be propagated via a simulated quantum system generation model 208 (e.g., through a statistical network). For example, an example Josephson junction resistance distribution of an example quantum hardware parameter distribution can be sampled to generate resistance values ​​in the parameter distribution samples. The resistance values ​​in the parameter distribution samples can indicate the Josephson junction resistance of example quantum hardware samples, such as example quantum hardware samples generated by propagating parameter distribution samples via the simulated quantum system generation model 208. Alternatively or additionally, the simulated quantum system generation model 208 can learn dependencies in the quantum hardware and / or otherwise model dependencies in the quantum hardware to simulate the operation of a real quantum computing system.

[0042] The quantum system scalability evaluator 210 can determine one or more performance benchmarks 212. Performance benchmarks 212 can establish test conditions for a given quantum system to evaluate its performance relative to other quantum systems. Performance benchmarks 212 can be designed to measure one or more performance characteristics of the quantum system. For example, a performance characteristic can be or may include gate error.

[0043] In some implementations, the performance benchmark 212 can be designed with respect to a given quantum algorithm of interest. For example, a performance benchmark 212 can be selected to represent the quantum algorithm. As an example, the quantum system scalability evaluator 210 can select a quantum algorithm and then select one or more performance benchmarks 212 to represent that quantum algorithm.

[0044] The quantum system scalability evaluator 210 can obtain benchmark performance data 214. Benchmark performance data 214 can be obtained with respect to the candidate quantum system architecture 202. For example, performance benchmark 212 can be used to measure the performance of a small-scale quantum computing system 206 and / or a simulated quantum computing system 209 configured according to the quantum system architecture 202, thereby generating benchmark performance data 214. Benchmark performance data 214 can describe one or more performance characteristics of the candidate quantum system architecture. For example, performance characteristics can be or may include gate errors, and benchmark performance data 214 can be gate error benchmark performance data.

[0045] Furthermore, benchmark performance data 214 can be obtained for multiple processor sizes of candidate quantum system architecture 202. As used herein, processor size refers to the number of qubits in a processor. For example, small-scale quantum computing systems 206 and / or 209 can be designed and / or simulated for multiple processor sizes. Each processor size may include multiple qubits in the quantum processor of quantum systems 206, 209. For example, quantum systems 206, 209 with a variable number of qubits can be tested to assess how the performance of quantum systems 206, 209 is affected as the processor size of systems 206, 209 expands. As an example, systems 206, 209 can be evaluated at multiple processor sizes ranging from a first number of qubits (e.g., one qubit, two qubits, etc.) to a second number of qubits (e.g., ten qubits). Although systems 206 and 209 can be tested on a variable number of qubits to evaluate scalability, the number of qubits in systems 206 and 209 may be less than the number of qubits used to implement practical quantum algorithms, such as more than about 20 qubits.

[0046] The quantum system scalability evaluator 210 can obtain a quantum scaling model 216, including one or more scaling parameters 217, based on benchmark performance data 214. For example, the quantum scaling parameters 217 can define the quantum scaling model 216. The quantum scaling model 216 can correlate the processor size of a candidate quantum system architecture 202 with one or more performance characteristics of the candidate quantum system architecture 202. For example, the quantum scaling model 216 can define how the performance of a quantum computing system varies with increasing processor size according to the quantum system architecture 202 (e.g., systems 206, 209). The quantum scaling model 216 can be an algebraic model, such as an equation including multiple scaling parameters 217, one or more independent variables (e.g., multiple qubits), and / or one or more dependent variables (e.g., performance characteristics such as gate error).

[0047] For example, an example quantum scaling model 216 includes scaling parameters 217, such as a qubit saturation constant, a saturation gate error, and a scaling logic error penalty. The qubit saturation constant represents the number of qubits beyond which performance does not significantly degrade. The saturation gate error represents the limit of performance degradation as the number of qubits increases. For example, when the number of qubits in a quantum system increases beyond the qubit saturation constant, the quantum system typically reaches or approaches the saturation gate error. Additionally, the scaling logic error penalty represents the penalty incurred when scaling logic from a relatively small system to a relatively large system. Specifically, an example quantum scaling model 216 associates the average gate error at multiple qubits with a quantity consisting of the scaling logic error penalty multiplied by an exponential function of the number of qubits divided by the qubit saturation constant, minus this quantity from the saturation gate error. For example, the example quantum scaling model 216 can be represented by:

[0048]

[0049] in It is the number of qubits. yes Average gate error at each qubit It is the saturation gate error. It is a scaling logic error penalty, and This refers to the qubit saturation constant. While the model is relatively simple mathematically, it can be applied to various practical scenarios and even the scalability of models for relatively complex quantum computing systems. Specifically, these parameters can even embed complex interactions between multiple sources of degradation.

[0050] In some implementations, obtaining one or more quantum scaling parameters 217 may include fitting a quantum scaling model 216 to benchmark performance data 214. For example, the quantum scaling model 216 may be a performance algorithm model that can be tuned by adjusting the values ​​of one or more quantum scaling parameters 217. The quantum scaling model 216 can be fitted to the benchmark performance data 214 using any suitable curve fitting algorithm (e.g., regression, least squares, or other suitable algorithm) to determine the values ​​of one or more quantum scaling parameters 217 that cause the quantum scaling model 216 to approximately fit the benchmark performance data 214.

[0051] Figure 3 Figure 300 illustrates examples of baseline performance data 214 and a corresponding scaling model 216 for a given performance baseline 212. Figure 300 includes first baseline performance data 302 based on a first quantum hardware architecture and second baseline performance data 304 based on a second quantum hardware architecture and / or a second control strategy. Additionally, a first scaling model 312 is fitted to the first baseline performance data 302, and a second scaling model 314 is fitted to the second baseline performance data 304. In Figure 300, the x-axis represents the number of qubits added, and the y-axis represents the performance on the performance baseline. For example, the y-axis could represent the number of gate errors for a given candidate quantum system architecture with a given number of qubits.

[0052] like Figure 3 As shown, the performance of a given candidate quantum system architecture typically follows a curve represented by scaling models 312 and 314. Furthermore, the performance of the quantum system architecture typically saturates at levels represented by saturation gate errors 322 and 324. Saturation gate errors 322 and 324 can represent the amount of gate error to which the performance of the quantum system tends as the number of qubits increases. Generally, it may be desirable to choose a quantum system with lower saturation gate errors rather than higher saturation gate errors, as a lower saturation gate error can provide reduced gate errors when executing practical quantum algorithms. By comparing scaling models 312 and 314 (e.g., saturation gate errors 322 and 324), the performance of a given candidate quantum architecture with a large number of qubits can be evaluated.

[0053] Return to Figure 2The quantum system scalability evaluator 210 can determine one or more scaling metrics 218 for the candidate quantum system architecture 202 using a quantum scaling model 216. Specifically, the scaling metrics 218 can be, or can be included, the performance of the quantum system based on the candidate quantum system architecture 202 at a scaled processor size larger than the multiple processor sizes used to obtain the quantum scaling model 216. For example, the quantum system scalability evaluator 210 can use the quantum scaling model 216 to infer the performance of the quantum system based on architecture 202 at a processor size much larger than that of quantum computing systems 206, 209. As an example, the scaled processor size can be provided as input to the quantum scaling model 216. The scaling metrics 218 can be the output of the scaling model 216 in response to receiving the scaled processor size as input. The scaling metrics 218 can be baseline performance data for predictions of the candidate quantum system architecture at the scaled processor size. Alternatively, in some implementations, the scaling metrics 218 can be some or all of the quantum scaling parameters 217 themselves (e.g., saturation gate error). Alternatively, in some implementations, scaling metrics 218 may include data describing a comparison of the outputs of quantum scaling model 216 and / or its outputs for multiple candidate quantum system architectures.

[0054] System 200 may include determining one or more control actions for operational quantum system 220 based on one or more scaling metrics 218. For example, in some implementations, if system 200 identifies a candidate quantum system architecture 202 with improved scalability, operational quantum system 220 may be configured according to that architecture 202. For example, in some implementations, one or more control actions may be determined to implement one or more operational characteristics of candidate quantum system architecture 202 in operational quantum system 220.

[0055] Alternatively, system 200 may compare scaling metrics 218 of two or more candidate quantum system architectures 202 to configure operational quantum system 220 according to an architecture 202 that provides improved scalability. For example, in some implementations, quantum system scalability evaluator 210 may obtain second benchmark performance data for a second candidate quantum system architecture; obtain one or more second scaling parameters based on the second benchmark performance data; determine one or more second scaling metrics for the second candidate quantum system architecture based on the one or more second scaling parameters; and compare the one or more scaling metrics with the one or more second scaling metrics. Based on the comparison, system 200 and / or the user may select one of the candidate quantum system architectures or the second quantum system. Operational quantum system 220 may be configured according to one or more operational characteristics of a selected candidate quantum system architecture or the second candidate quantum system architecture. For example, operational quantum system 220 may be configured according to a candidate quantum system architecture that provides improved scalability.

[0056] Furthermore, in some implementations, scaling metrics 218 and / or scaling model 216 can be used to modify the future design and development of the quantum processor. For example, a test quantum processor can be repeatedly designed, manufactured, benchmarked, and modified. It may be desirable to increase the speed and / or reduce the cost of performing these processes to reduce the resources dedicated to future development. To achieve this, it may be beneficial to use a smaller quantum processor. Scaling metrics 218 and / or scaling model 216 can inform the test processor of sufficient size to capture the scalability of the quantum processor. For example, if several given quantum computing systems saturate at a common qubit saturation constant, future test quantum systems can be tested up to that common qubit saturation constant (or some small multiple, such as two or three times that qubit saturation constant) to limit the size of future test processors without compromising scalability testing.

[0057] Figure 4 A flowchart depicts a method 400 for evaluating the scalability of a quantum system according to aspects of this disclosure. One or more portions of method 400 may be implemented by a computing system comprising one or more computing devices, such as the computing system described, for example, with reference to other figures (e.g., Figure 1 , Figure 2 , Figures 5A to 5C (Systems and apparatuses, etc.). Each corresponding part of method 400 can be performed by any one (or any combination of one or more computing devices). Furthermore, one or more parts of method 400 can be implemented on the hardware components of the apparatus described herein. Figure 4For illustrative and discussion purposes, elements executed in a specific order are depicted. Those skilled in the art will understand using the disclosure provided herein that elements of any method discussed herein can be adapted, rearranged, extended, omitted, combined, or modified in various ways without departing from the scope of this disclosure. Figure 4 The elements / terms described are for illustrative purposes only and with reference to other systems and figures, and are not intended to be limiting. Alternatively or additionally, one or more portions of method 400 may be performed by other systems.

[0058] At 402, method 400 may include obtaining one or more candidate quantum system architectures. Each of the candidate quantum system architectures may specify, represent, or otherwise define a different configuration of the quantum computing system. Each candidate quantum system architecture may specify a quantum hardware architecture and a control strategy.

[0059] The system can select candidate quantum system architectures for scalability evaluation. For example, in some implementations, evaluating the scalability of a candidate quantum system architecture may include selecting the hardware architecture and / or the control strategy for that architecture. In some implementations, a user (e.g., a quantum programmer or quantum system designer) may manually select the hardware architecture and / or control strategy to be tested. Alternatively, in some implementations, the hardware architecture and / or control strategy may be selected iteratively or automatically. For example, in some implementations, candidate quantum system architectures may be periodically selected and / or tested as an optimization loop to gradually improve the scalability of the quantum computing system over time. For example, the system may repeatedly test variable hardware architectures and / or control strategies to optimize relevant scaling metrics and / or algorithms in deployment.

[0060] The hardware architecture of a candidate quantum system architecture can define or specify structural characteristics of the candidate quantum system architecture (e.g., one or more qubits of the candidate quantum system architecture). Structural characteristics can relate to aspects of the candidate quantum system architecture that are fixed for a given qubit type and / or architecture, such as, for example, qubit type characteristics, qubit arrangement characteristics, control signal line arrangement characteristics, fabrication characteristics, and / or dependency characteristics. Example structural characteristics may include, but are not limited to: capacitance (e.g., self-capacitance), Josephson junction resistance, qubit anharmonicity, qubit-controlled mutual inductance distribution, maximum frequency, readout resonator frequency, Josephson junction asymmetry, two-level system (TLS) TLS number density, TLS frequency, TLS coherence, TLS qubit decoupling, qubit quality, qubit-controlled mutual inductance prime number distribution, driving impedance, resonator internal quality, resonator coupling quality, resonator-qubit coupling efficiency, bandpass filter frequency, bandpass filter quality, transporter frequency, T1 spectrum, single-qubit frequency, or qubit grid frequency.

[0061] A control strategy can define or specify operational characteristics of a candidate quantum system architecture (e.g., one or more qubits of the candidate quantum system architecture). For example, a control strategy may include data describing the operational characteristics of the classical or quantum hardware of a quantum computing system 100, such as qubit operational characteristics (e.g., including qubits and qubit couplers) and readout resonator characteristics. Alternatively, the control strategy may instruct one or more calibration interventions or one or more optimization interventions. Calibration interventions can provide or describe instructions for calibrating one or more aspects of the quantum computing system. Different calibration interventions may reflect or embody different calibration strategies, such as by manipulating different parameters, implementing different timelines for adjusting parameters, determining whether to fully implement the intervention, etc. For example, different calibration interventions may be configured with different responses to a given set of input characteristics. For example, threshold-based heuristics may be configured with different trigger points (e.g., for identifying components with anomalous characteristics). For example, for a given quantum system architecture describing multiple qubits, different calibration models may identify different qubits for calibration, different gate frequencies for adjustment, or other different operational characteristics for calibration.

[0062] Operational characteristics may include data describing both controlled and / or uncontrolled characteristics. As an example, the operational characteristics of one or more qubits may include one or more operating frequencies of qubits in a candidate quantum system architecture. As another example, operational characteristics may include data describing environmental conditions or other characteristics that are not directly controlled or cannot be directly controlled. As a further example, operational characteristics may include one or more of the following: single-qubit gate frequency trajectory, two-qubit gate frequency trajectory, readout frequency trajectory, maximum / minimum operating frequency, frequency anharmonicity, bias voltage, coupling efficiency, Ramsey coherence time, spin echo coherence time, CPMG dephasing time, energy relaxation time, Rabi oscillation, pulse amplitude, pulse length, pulse frequency, single-qubit random benchmark (RB) error, single-qubit cross-entropy benchmark (XEB) error, two-qubit RB error, two-qubit XEB error, or two-qubit XEB purity error.

[0063] Example quantum systems can be designed, built, and / or simulated based on candidate quantum system architectures to generate benchmark performance data representing the performance of those systems at different numbers of qubits. For example, small-scale quantum computing systems can be designed and / or built based on candidate quantum system architectures. Small-scale quantum computing systems can be physical (e.g., real-world) quantum computing systems built according to candidate quantum system architectures, enabling the system to perform quantum gate operations. Small-scale quantum computing systems may include one or more qubits, but may include only a limited number of qubits (e.g., fewer than 10 qubits, fewer than 10 qubits, etc.).

[0064] Alternatively, a simulated quantum computing system can be generated by one or more simulated quantum system generation models. Depending on the candidate quantum system architecture, the simulated quantum computing system can be or may include data, models, or other virtual (e.g., in classical computing) representations of the quantum computing system. For example, in one instance, parameters of the candidate quantum system architecture can be input into a simulated quantum system generation model configured to produce samples of quantum hardware (e.g., quantum processors) based on the architecture.

[0065] In one example implementation, the simulated quantum system generation model is configured to model the statistical distribution of the quantum system based on parameters specified by the architecture (e.g., manufacturing variations, operational variations, etc.). For example, the simulated quantum system generation model may model a distribution of quantum hardware parameters, such as circuit parameters, one or more electrical parameters, one or more manufacturing parameters, or one or more defect parameters. In some implementations, the quantum hardware parameter distribution may include at least one of a qubit distribution, a qubit circuit distribution, a qubit relaxation distribution, or a background loss distribution. In some implementations, one or more quantum hardware parameter distributions may include at least one of the following: capacitance (e.g., qubit self-capacitance), junction resistance (e.g., Josephson junction resistance), qubit anharmonicity, qubit-controlled mutual inductance distribution, maximum frequency, readout resonator frequency, Josephson junction asymmetry, two-level system (TLS) TLS number density, TLS frequency, TLS coherence, TLS qubit decoupling, qubit quality, qubit-controlled mutual inductance prime number distribution, driving impedance, resonator internal quality, resonator coupling quality, resonator-qubit coupling efficiency, bandpass filter frequency, bandpass filter quality, transporter frequency, T1 spectrum, single-qubit frequency, or qubit grid frequency. In some implementations, the model simulating the generation of the quantum system may be or may include a joint probability distribution over the quantum hardware parameter distributions.

[0066] In some implementations, the quantum hardware parameter distribution can be a “simple distribution” that returns one or more numbers corresponding to some parameters of the quantum hardware (such as circuit parameters, manufacturing parameters, TLS, etc.). The quantum hardware parameter distribution can be sampled to generate parameter distribution samples. These distribution samples can be propagated via a simulated quantum system generation model (e.g., through a statistical network). For example, an example Josephson junction resistance distribution of an example quantum hardware parameter distribution can be sampled to generate resistance values ​​in the parameter distribution samples. The resistance values ​​in the parameter distribution samples can indicate the Josephson junction resistance of example quantum hardware samples, such as example quantum hardware samples generated by propagating parameter distribution samples via a simulated quantum system generation model. Alternatively or additionally, the simulated quantum system generation model can learn dependencies in the quantum hardware and / or otherwise model dependencies in the quantum hardware to simulate the operation of a real quantum computing system.

[0067] At 404, method 400 may include obtaining benchmark performance data. Benchmark performance data may be obtained with respect to the candidate quantum system architecture. In some implementations, obtaining benchmark performance data may include determining one or more performance benchmarks. Performance benchmarks can establish test conditions for a given quantum system to evaluate the performance of that quantum system relative to other quantum systems. Performance benchmarks may be designed to measure one or more performance characteristics of the quantum system. For example, a performance characteristic may be or may include gate error.

[0068] In some implementations, performance benchmarks can be designed with respect to a given quantum algorithm of interest. For example, a performance benchmark can be chosen to represent the quantum algorithm. As an example, the system can select a quantum algorithm and then select one or more performance benchmarks to represent that algorithm. For instance, performance benchmarks can be used to measure the performance of small-scale quantum computing systems and / or simulated quantum computing systems configured according to a quantum system architecture, thereby generating benchmark performance data. Benchmark performance data can describe one or more performance characteristics of a candidate quantum system architecture. For example, a performance characteristic can be or may include gate errors, and benchmark performance data can be gate error benchmark performance data.

[0069] Furthermore, benchmark performance data can be obtained for multiple processor sizes of candidate quantum system architectures. For example, small-scale quantum computing systems and / or simulated quantum computing systems can be designed and / or simulated for various processor sizes. Each processor size can include multiple qubits in the quantum processor of the quantum system. For example, quantum systems with a variable number of qubits can be tested to assess how the performance of the quantum system is affected as the system scales to a larger processor size. As an example, the system can be evaluated at multiple processor sizes ranging from a first number of qubits (e.g., one qubit, two qubits, etc.) to a second number of qubits (e.g., ten qubits). Although the system can be tested at a variable number of qubits to assess scalability, the number of qubits in the system may be less than the number of qubits used to implement practical quantum algorithms, such as more than approximately [number missing] qubits.

[0070] In some implementations, obtaining one or more quantum scaling parameters may include determining a quantum scaling model that includes one or more scaling parameters based on benchmark performance data. For example, the quantum scaling parameters can define a quantum scaling model. A quantum scaling model can correlate the processor size of a candidate quantum system architecture with one or more performance characteristics of the candidate quantum system architecture. For example, a quantum scaling model can define how the performance of a quantum computing system varies with the processor size as the quantum system architecture increases. A quantum scaling model can be an algebraic model, such as an equation that includes multiple scaling parameters, one or more independent variables (e.g., multiple qubits), and / or one or more dependent variables (e.g., performance characteristics such as gate error).

[0071] For example, an example quantum scaling model includes scaling parameters such as the qubit saturation constant, saturation gate error, and scaling logic error penalty. The qubit saturation constant represents the number of qubits beyond which performance does not significantly degrade. The saturation gate error represents the limit of performance degradation as the number of qubits increases. For example, when the number of qubits in a quantum system increases beyond the qubit saturation constant, the quantum system typically reaches or approaches the saturation gate error. Additionally, the scaling logic error penalty represents the penalty incurred when scaling logic from a relatively small system to a relatively large system. Specifically, an example quantum scaling model associates the average gate error across multiple qubits with a quantity consisting of the scaling logic error penalty multiplied by an exponential function of the number of qubits divided by the qubit saturation constant, minus this quantity from the saturation gate error. For example, an example quantum scaling model can be represented by:

[0072]

[0073] in It is the number of qubits. yes Average gate error at each qubit It is the saturation gate error. It is a scaling logic error penalty, and This refers to the qubit saturation constant. While the model is relatively simple mathematically, it can be applied to various practical scenarios and even the scalability of models for relatively complex quantum computing systems. Specifically, these parameters can even embed complex interactions between multiple sources of degradation.

[0074] In some implementations, obtaining one or more quantum scaling parameters may include fitting a quantum scaling model to benchmark performance data. For example, the quantum scaling model may be a performance algorithm model that can be tuned by adjusting the values ​​of one or more quantum scaling parameters. The quantum scaling model can be fitted to the benchmark performance data using any suitable curve fitting algorithm (e.g., regression, least squares, or other suitable algorithm) to determine the values ​​of one or more quantum scaling parameters that make the quantum scaling model approximately fit the benchmark performance data. Figure 3 Figure 300 shows an example of baseline performance data for a given performance benchmark and the corresponding scaling model.

[0075] At 406, method 400 may include determining one or more scaling metrics for candidate quantum system architectures using a quantum scaling model. Specifically, the scaling metrics may be, or may include, the performance of the quantum system based on the candidate quantum system architecture at a scaled processor size larger than the multiple processor sizes used to obtain the quantum scaling model. For example, determining the scaling metrics may include using the quantum scaling model to infer the performance of the quantum system based on the architecture at a processor size much larger than that of the quantum computing system. As an example, the scaled processor size may be provided as input to the quantum scaling model. The scaling metrics may be the output of the scaling model in response to receiving the scaled processor size as input. Alternatively or additionally, in some implementations, the scaling metrics may be some or all of the quantum scaling parameters themselves (e.g., saturation gate error). Alternatively or additionally, in some implementations, the scaling metrics may include data describing a comparison of the output of the quantum scaling model and / or its output for multiple candidate quantum system architectures.

[0076] At 408, method 400 may include determining one or more control actions for the operational quantum system based on one or more scaling metrics. For example, in some implementations, if the system identifies a candidate quantum system architecture with improved scalability, the operational quantum system can be configured according to that architecture. For example, in some implementations, one or more control actions are determined to implement one or more operational properties of the candidate quantum system architecture in the operational quantum system.

[0077] Alternatively, in some implementations, method 400 may further include comparing scaling metrics of two or more candidate quantum system architectures to configure the operational quantum system according to an architecture that provides improved scalability. For example, in some implementations, method 400 may further include obtaining second benchmark performance data for a second candidate quantum system architecture; obtaining one or more second scaling parameters based on the second benchmark performance data; determining one or more second scaling metrics for the second candidate quantum system architecture based on the one or more second scaling parameters; and comparing the one or more scaling metrics with the one or more second scaling metrics. Based on the comparison, the system and / or user may select either a candidate quantum system architecture or a second quantum system. The operational quantum system can be configured according to one or more operational characteristics of a selected candidate quantum system architecture or a second candidate quantum system architecture. For example, the operational quantum system can be configured according to a candidate quantum system architecture that provides improved scalability.

[0078] Figure 5A A block diagram of an example computing system 1, which can perform aspects of exemplary embodiments of the present disclosure, is depicted. System 1 includes a control computing device 2, a quantum computing system 30, and a training computing system 50, which are communicatively coupled via a network 70.

[0079] The control computing device 2 can be any type of computing device (e.g., a classic computing device), such as, for example, a mobile computing device (e.g., a smartphone or tablet), a personal computing device (e.g., a laptop or desktop computer), a workstation, a cluster, a game console or controller, a wearable computing device, an embedded computing device, or any other type of computing device. In some embodiments, the computing device 2 can be a client computing device. The computing device 2 can include one or more processors 12 and memory 14. The one or more processors 12 can be any suitable processing device (e.g., a processor core, a microprocessor, an ASIC, an FPGA, a controller, a microcontroller, etc.), and can be a single processor or multiple processors operatively connected. The memory 14 can include one or more non-transitory computer-readable storage media, such as RAM, ROM, EEPROM, EPROM, flash memory devices, disks, etc., and combinations thereof. The memory 14 can store data 16 and instructions 18, which are executed by the processor 12 to cause the user computing device 2 to perform the operations described herein.

[0080] In some implementations, the control computing device 2 may store or include one or more models 20. Model 20 may be a calibration model for calibrating one or more components (e.g., qubits, etc.) of the quantum computing system 20. For example, model 20 may or may otherwise include various machine learning models, such as neural networks (e.g., deep neural networks) or other types of machine learning models, including nonlinear or linear models. Neural networks may include feedforward neural networks, recurrent neural networks (e.g., long short-term memory recurrent neural networks), convolutional neural networks, or other forms of neural networks. Some example machine learning models may utilize attention mechanisms, such as self-attention. For example, some example machine learning models may include multi-head self-attention models (e.g., transformer models).

[0081] In some implementations, one or more models 20 may be sent to or received from the quantum computing system 30 via the network 70, stored in the computing device memory 14, and used or otherwise implemented by one or more processors 12. In some implementations, the computing device 2 may implement multiple parallel instances of model 20.

[0082] Alternatively or concurrently, one or more models 40 may be included in, or otherwise stored and implemented by, a quantum computing system 30 communicating with the computing device 2. For example, model 40 may be implemented by the quantum computing system 40 for use in calibrating the quantum computing system 30.

[0083] The computing device 2 may also include one or more input components for receiving user input. For example, the user input component may be a touch-sensitive component (e.g., a touch-sensitive display or touchpad) that is sensitive to the touch of a user input object (e.g., a finger or stylus). Touch-sensitive components can be used to implement a virtual keyboard. Other example user input components include a microphone, a conventional keyboard, or other components through which the user can provide input.

[0084] The quantum computing system 30 may include one or more processors 32 (e.g., classical processor 104) and memory 34. The one or more processors 32 may be any suitable processing device (e.g., processor core, microprocessor, ASIC, FPGA, controller, microcontroller, etc.) and may be a single processor or multiple processors operatively connected. The memory 34 may include one or more non-transitory computer-readable storage media, such as RAM, ROM, EEPROM, EPROM, flash memory devices, disks, etc., and combinations thereof. The memory 34 may store data 36 and instructions 38, which are executed by the processor 32 to cause the server computing system 30 to perform the operations described herein.

[0085] The quantum computing system 30 may also include the above references. Figure 1 The quantum hardware 102 described is used to perform quantum computing.

[0086] In some implementations, the quantum computing system 30 includes one or more server computing devices or is otherwise implemented by one or more server computing devices. Where the quantum computing system 30 includes multiple server computing devices, such server computing devices can operate according to sequential computing architectures, parallel computing architectures, or some combination thereof.

[0087] As described above, the quantum computing system 30 can store or otherwise include one or more models 40. For example, model 40 can be, or can otherwise include, various machine learning models. Example machine learning models include neural networks or other multi-layer nonlinear models. Example neural networks include feedforward neural networks, deep neural networks, recurrent neural networks, and convolutional neural networks. Some example machine learning models can utilize attention mechanisms, such as self-attention. For example, some example machine learning models can include multi-head self-attention models (e.g., transformer models).

[0088] Computing device 2 or quantum computing system 30 may select, update, train, or otherwise iterate on an example embodiment of a model (e.g., including model 20 or 40). In some embodiments, computing device 2 or quantum computing system 30 may train an example embodiment of a machine learning model (e.g., including model 20 or 40) via interaction with training computing system 50. In some embodiments, training computing system 50 may be communicatively coupled via network 70. Training computing system 50 may be separate from quantum computing system 30 or may be part of quantum computing system 30 or control computing device 2.

[0089] The training computing system 50 may include one or more processors 52 and memory 54. The one or more processors 52 may be any suitable processing device (e.g., processor core, microprocessor, ASIC, FPGA, controller, microcontroller, etc.) and may be a single processor or multiple processors operatively connected. The memory 54 may include one or more non-transitory computer-readable storage media, such as RAM, ROM, EEPROM, EPROM, flash memory devices, disks, etc., and combinations thereof. The memory 54 may store data 56 and instructions 58, which are executed by the processor 52 to cause the training computing system 50 to perform operations. In some implementations, the training computing system 50 includes one or more server computing devices or is otherwise implemented by one or more server computing devices.

[0090] In some embodiments, the parameters of the model can be trained using various training or learning techniques, such as, for example, backpropagation of error. For example, the objective or loss can be backpropagated through a pre-training, general training, or fine-tuning pipeline to update one or more parameters of the model (e.g., gradients based on the loss function). Various losses can be determined, such as mean squared error, likelihood loss, cross-entropy loss, hinge loss, or various other loss functions. Gradient descent techniques can be used to iteratively update the parameters across multiple training iterations. In some implementations, performing backpropagation of error may include performing truncated backpropagation over time. The pipeline can perform various generalization techniques (e.g., weight decay, backoff, etc.) to improve the generalization ability of the model being trained.

[0091] Model trainer 60 may include computer logic for providing desired functionality. Model trainer 60 may be implemented in hardware, firmware, or software that controls a general-purpose processor. For example, in some implementations, model trainer 60 includes a program file stored on a storage device, loaded into memory, and executed by one or more processors. In other implementations, model trainer 60 includes one or more sets of computer-executable instructions stored in a tangible computer-readable storage medium, such as RAM, a hard disk, or an optical or magnetic medium.

[0092] Network 70 can be any type of communication network (e.g., classical or quantum), such as a local area network (e.g., intranet), a wide area network (e.g., the Internet), or some combination thereof, and can include any number of wired or wireless links. Typically, communication conducted through network 70 can be carried over any type of wired or wireless connection using various communication protocols (e.g., TCP / IP, HTTP, SMTP, FTP), encodings or formats (e.g., HTML, XML), or protection schemes (e.g., VPN, Secure HTTP, SSL).

[0093] Figure 5A An example computing system that can be used to implement this disclosure is shown. Other computing systems may also be used. For example, in some implementations, computing device 2 may include a model trainer 60. In such an implementation, the training pipeline may be used locally at computing device 2.

[0094] Figure 5B A block diagram of an example computing device 80, implemented according to an example embodiment of the present disclosure, is depicted. The computing device 80 may be a client computing device or a server computing device. The computing device 80 may include multiple applications (e.g., application 1 to application N). Each application may contain its own machine learning library and machine learning model. For example, each application may include a machine learning model. Example applications include text messaging applications, email applications, dictation applications, virtual keyboard applications, browser applications, etc. Figure 5B As shown, each application can communicate with multiple other components of the computing device, such as one or more sensors, a context manager, a device state component, or additional components. In some implementations, each application can communicate with each device component using an API (e.g., a public API). In some implementations, the API used by each application is application-specific.

[0095] Figure 5C A block diagram of an example computing device 80, implemented according to an example embodiment of the present disclosure, is depicted. The computing device 80 may be a user computing device or a server computing device. The computing device 80 may include multiple applications (e.g., application 1 to application N). Each application communicates with a central intelligence layer. Example applications include a text messaging application, an email application, a dictation application, a virtual keyboard application, a browser application, etc. In some implementations, each application may use an API (e.g., a common API across all applications) to communicate with the central intelligence layer (and the models stored therein).

[0096] The central intelligence layer can include multiple machine learning models. For example, such as Figure 5C As shown, a corresponding machine learning model can be provided for each application, and the corresponding machine learning model can be managed by a central intelligent layer. In other implementations, two or more applications can share a single machine learning model. For example, in some implementations, the central intelligent layer can provide a single model for all applications. In some implementations, the central intelligent layer is included within or otherwise implemented by the operating system of the computing device 80.

[0097] The central intelligence layer can communicate with the central device data layer. The central device data layer can be a centralized data repository for computing device 80. For example... Figure 5C As shown, the central device data layer can communicate with multiple other components of the computing device, such as one or more sensors, a context manager, a device state component, or additional components. In some implementations, the central device data layer can communicate with each device component using an API (e.g., a private API).

[0098] The implementations of the digital, classical, and / or quantum themes, as well as digital function operations and quantum operations described in this specification, may be implemented in digital electronic circuit systems, suitable quantum circuit systems, or more generally in quantum computing systems, in tangibly implemented digital and / or quantum computer software or firmware, in digital and / or quantum computer hardware (including the structures disclosed in this specification and their structural equivalents), or in a combination of one or more of these. The term "quantum computing system" may include, but is not limited to, quantum computers / computing systems, quantum information processing systems, quantum cryptography systems, or quantum simulators.

[0099] The implementation of the digital and / or quantum themes described in this specification can be implemented as one or more digital and / or quantum computer programs (e.g., one or more modules of digital and / or quantum computer program instructions encoded on a tangible, non-transitory storage medium for execution by a data processing device or for controlling the operation of a data processing device). The digital and / or quantum computer storage medium can be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, one or more qubit / qubit structures, or a combination thereof. Alternatively or additionally, program instructions can be encoded on an artificially generated propagation signal (e.g., a machine-generated electrical, optical, or electromagnetic signal) capable of encoding digital and / or quantum information, which is then transmitted to a suitable receiver device for execution by the data processing device.

[0100] The terms quantum information and quantum data refer to information or data carried, stored, or housed in quantum systems, the smallest nontrivial system being a qubit (i.e., a system that defines a unit of quantum information). It should be understood that the term "qubit" encompasses all quantum systems that can be appropriately approximated as two-level systems in the corresponding context. Such quantum systems can include multi-level systems, for example, systems with two or more energy levels. Examples of such systems include atoms, electrons, photons, ions, or superconducting qubits. In many implementations, the computational ground state is considered as the ground state and the first excited state; however, it should be understood that other settings where the computational state is considered as a higher-level excited state (e.g., a qubit) are also possible.

[0101] The term "data processing device" refers to digital and / or quantum data processing hardware and encompasses all kinds of devices, apparatuses, and machines for processing digital and / or quantum data, including, for example, programmable digital processors, programmable quantum processors, digital computers, quantum computers, or multiple digital and quantum processors or computers, and combinations thereof. The device may also be or include dedicated logic circuit systems, such as FPGAs (Field-Programmable Gate Arrays) or ASICs (Application-Specific Integrated Circuits), or quantum simulators, i.e., quantum data processing devices designed to simulate or generate information about a particular quantum system. Specifically, a quantum simulator is a dedicated quantum computer that does not have the capability to perform general-purpose quantum computing. In addition to hardware, the device may optionally include code that creates an execution environment for digital and / or quantum computer programs, such as code constituting processor firmware, protocol stacks, database management systems, operating systems, or combinations thereof.

[0102] Digital or classical computer programs, which can also be referred to or described as programs, software, software applications, modules, software modules, scripts, or code, can be written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and can be deployed in any form, including as standalone programs or as modules, components, subroutines, or other units suitable for use in a digital computing environment. Quantum computer programs, which can also be referred to or described as programs, software, software applications, modules, software modules, scripts, or code, can be written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages) and translated into a suitable quantum programming language, or can be written in quantum programming languages ​​such as QCL, Quipper, Cirq, etc.

[0103] Digital and / or quantum computer programs may, but do not necessarily, correspond to files in a file system. Programs may be stored as a portion of a file containing other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinating files (e.g., files storing one or more modules, subroutines, or code sections). Digital and / or quantum computer programs may be deployed to execute on a single digital or quantum computer, or on multiple digital and / or quantum computers located at a single site or distributed across multiple sites and interconnected via digital and / or quantum data communication networks. A quantum data communication network is understood as a network that can transmit quantum data using quantum systems (e.g., qubits). Generally, digital data communication networks cannot transmit quantum data; however, quantum data communication networks can transmit both quantum data and digital data.

[0104] The processes and logic flows described in this specification can be executed by one or more programmable digital and / or quantum computers (which may operate using one or more digital and / or quantum processors, as appropriate) executing one or more digital and / or quantum computer programs to perform functions by manipulating input digital and quantum data and generating outputs. The processes and logic flows can also be executed by a dedicated logic circuit system (e.g., an FPGA or ASIC or a quantum simulator) or by a combination of a dedicated logic circuit system or a quantum simulator and one or more programmable digital and / or quantum computers, and the device can also be implemented as said dedicated logic circuit system or said combination.

[0105] For a system of one or more digital and / or quantum computers or processors that is “configured” or “operable to” perform a specific operation or action, it means that the system has software, firmware, hardware, or a combination thereof installed thereon that causes the system to perform the operation or action in operation. For one or more digital and / or quantum computer programs configured to perform a specific operation or action, it means that the one or more programs include instructions that cause the device to perform the operation or action when executed by a digital and / or quantum data processing device. A quantum computer can receive instructions from a digital computer that cause the device to perform the operation or action when executed by a quantum computing device.

[0106] Digital and / or quantum computers suitable for executing digital and / or quantum computer programs may be based on general-purpose or special-purpose digital and / or quantum microprocessors or both, or any other kind of central digital and / or quantum processing unit. Generally, the central digital and / or quantum processing unit receives instructions and digital and / or quantum data from read-only memory, or random access memory, or a quantum system suitable for transmitting quantum data (e.g., photons), or a combination thereof.

[0107] Some example elements of a digital and / or quantum computer are a central processing unit (CPU) that makes or executes instructions and one or more memory devices for storing instructions and digital and / or quantum data. The CPU and memory may be supplemented by or incorporated into a dedicated logic circuit system or quantum simulator. Generally, a digital and / or quantum computer will also include one or more mass storage devices for storing digital and / or quantum data, such as magnetic disks, magneto-optical disks, or optical disks, or quantum systems suitable for storing quantum information, or operatively coupled to receive digital and / or quantum data from or to said one or more mass storage devices, or both. However, a digital and / or quantum computer need not have such devices.

[0108] Digital and / or quantum computer-readable media suitable for storing digital and / or quantum computer program instructions and digital and / or quantum data include all forms of non-volatile digital and / or quantum memories, media, and memory devices, including, for example, semiconductor memory devices, such as EPROM, EEPROM, and flash memory devices; magnetic disks, such as internal hard disks or removable hard disks; magneto-optical disks; and CD-ROM and DVD-ROM disks; and quantum systems, such as trapped atoms or electrons. It should be understood that quantum memory is a device capable of storing quantum data for a long period with high fidelity and high efficiency, for example, using light for transmission and using matter for storage and preservation of quantum characteristics (such as superposition or quantum coherence) of the quantum data at an optical-material interface.

[0109] Control of the various systems or portions thereof described in this specification may be implemented using digital and / or quantum computer program products, which include instructions stored on one or more tangible, non-transitory, machine-readable storage media and executable on one or more digital and / or quantum processing devices. The systems or portions thereof described in this specification may each be implemented as an apparatus, method, or electronic system, which may include one or more digital and / or quantum processing devices and memory for storing executable instructions to perform the operations described in this specification.

[0110] While this specification contains numerous specific implementation details, these details should not be construed as limiting the scope of what may be claimed, but rather as descriptions of features that may be specific to a particular implementation. Certain features described in the context of individual implementations may also be implemented in combination within a single implementation. Conversely, individual features described in the context of a single implementation may also be implemented individually or in any suitable sub-combination in multiple implementations. Furthermore, while features are described above as functioning in certain combinations, and even initially claimed to be so, one or more features from a claimed combination may, in some cases, be removed from said combination, and the claimed combination may be for a sub-combination or a variation thereof.

[0111] Similarly, although operations are depicted in a specific order in the accompanying drawings, this should not be construed as requiring such operations to be performed in the specific order shown or in sequential order, or requiring all shown operations to achieve the desired result. In some cases, multitasking and parallel processing can be advantageous. Furthermore, the separation of the various system modules and components in the implementation described above should not be construed as requiring such separation in all implementations, and it should be understood that the described program components and systems can generally be integrated together in a single software product or encapsulated in multiple software products.

[0112] Specific implementations of this subject matter have been described. Other implementations are within the scope of the appended claims. For example, the actions described in the claims can be performed in different orders and still achieve the desired result. As an example, the processes depicted in the figures do not necessarily require a specific order or sequence shown to achieve the desired result. In some cases, multitasking and parallel processing can be advantageous.

[0113] Various aspects of this disclosure have been described with respect to their illustrative implementations. Numerous other implementations, modifications, and alterations within the scope and spirit of the appended claims will arise in those skilled in the art upon careful reading of this disclosure. Any and all features of the following claims can be combined or rearranged in any possible manner. Therefore, the scope of this disclosure is illustrative rather than limiting, and this disclosure does not exclude such modifications, alterations, and / or additions to the subject matter that will be readily understood by those skilled in the art. Furthermore, terms are described herein using a list of example elements connected by conjunctions such as “and,” “or,” and “however.” It should be understood that such conjunctions are provided for illustrative purposes only. For example, a list connected by a specific conjunction such as “or” may refer to “at least one” or “any combination” of the example elements listed therein, where “or” should be understood as “and / or” unless otherwise indicated. Furthermore, terms such as “based on” should be understood as “at least partially based on.”

[0114] Those skilled in the art will understand using the disclosure provided herein that elements of any claim, operation, or process discussed herein can be adjusted, rearranged, expanded, omitted, combined, or modified in various ways without departing from the scope of this disclosure. Some claims are described with letter references to claim elements for illustrative purposes and are not intended to be limiting. Letter references do not imply a particular order of operations. For example, letter identifiers such as (a), (b), (c)..., (i), (ii), (iii)... may be used to describe operations. Such identifiers are provided for the convenience of the reader and do not indicate a particular order of steps or operations. Operations indicated by list identifiers (a), (i), etc., may be performed before, after, or in parallel with another operation indicated by list identifiers (b), (ii), etc.

Claims

1. A method for evaluating scalability of a quantum system, the method comprising: obtaining benchmark performance data for a candidate quantum system architecture, the benchmark performance data describing one or more performance characteristics of the candidate quantum system architecture for a plurality of processor sizes of the candidate quantum system architecture; obtaining one or more scaling parameters based on the benchmark performance data, one or more quantum scaling parameters including a quantum scaling model that relates processor sizes of the candidate quantum system architecture to the one or more performance characteristics of the candidate quantum system architecture; determining one or more scaling indicators for the candidate quantum system architecture at scaled processor sizes greater than the plurality of processor sizes by the quantum scaling model; and determining one or more control actions for an operational quantum system based on the one or more scaling indicators.

2. The method of claim 1, wherein obtaining the benchmark performance data comprises: selecting a quantum algorithm; selecting one or more performance benchmarks to represent the quantum algorithm; and obtaining the benchmark performance data based on the one or more performance benchmarks.

3. The method of claim 1, wherein obtaining the benchmark performance data comprises: selecting a hardware architecture of the candidate quantum system architecture, the hardware architecture of the candidate quantum system architecture defining structural characteristics of one or more qubits of the candidate quantum system architecture; selecting a control strategy of the candidate quantum system architecture, the control strategy defining operational characteristics of the one or more qubits of the candidate quantum system architecture; and obtaining the benchmark performance data for the candidate quantum system architecture, the candidate quantum system architecture including the one or more qubits configured according to the hardware architecture and the control strategy.

4. The method of claim 3, wherein the structural characteristics of the one or more qubits include qubit type characteristics, qubit arrangement characteristics, control signal line arrangement characteristics, fabrication characteristics, and / or dependency characteristics.

5. The method of claim 3, wherein the structural characteristics of the one or more qubits include at least one of: self-capacitance, junction resistance, qubit anharmonicity, qubit control mutual inductance distribution, maximum frequency, readout resonator frequency, Josephson junction asymmetry, two-level system TLS TLS number density, TLS frequency, TLS coherence, TLS qubit decoupling, qubit mass, qubit control mutual inductance prime distribution, drive impedance, resonator internal mass, resonator coupling mass, resonator-qubit coupling efficiency, bandpass filter frequency, bandpass filter mass, phonon frequency, Tl frequency spectrum, single qubit frequency, or qubit grid frequency.

6. The method of claim 3, wherein the operational characteristics of the one or more qubits include one or more operational frequencies of the one or more qubits. ​ 7. The method of claim 3, wherein the operational characteristics of the one or more qubits comprise one or more of: single-qubit gate frequency trajectory, two-qubit gate frequency trajectory, readout frequency trajectory, maximum / minimum operational frequency, frequency anharmonicity, bias voltage, coupling efficiency, Ramsey coherence time, spin echo coherence time, CPMG dephasing time, energy relaxation time, Rabi oscillation, pulse amplitude, pulse length, pulse frequency, single-qubit random-benchmark test (RB) error, single-qubit cross-entropy benchmark test (XEB) error, two-qubit RB error, two-qubit XEB error, or two-qubit XEB purity error.

8. The method of claim 3, wherein the operational characteristics of the one or more qubits comprise one or more uncontrolled characteristics.

9. The method of claim 3, wherein the control policy indicates one or more calibration interventions or one or more optimization interventions.

10. The method of claim 1, wherein the benchmark performance data comprises gate error benchmark performance data, and wherein the performance characteristic of the candidate quantum system architecture comprises a gate error.

11. The method of claim 1, wherein the quantum scaling parameters comprise a qubit saturation constant, a saturation gate error, and a scaling logical error penalty.

12. The method of claim 11, wherein the quantum scaling model relates an average gate error at a plurality of qubits to a quantity comprising the scaling logical error penalty multiplied by an exponential function of a number of qubits divided by the qubit saturation constant, the quantity being subtracted from the saturation gate error.

13. The method of claim 1, wherein obtaining the one or more quantum scaling parameters comprises fitting the quantum scaling model to the benchmark performance data.

14. The method of claim 1, wherein determining the one or more control actions comprises implementing one or more operational characteristics of the candidate quantum system architecture in an operational quantum system.

15. The method of claim 1, further comprising: obtaining second benchmark performance data for a second candidate quantum system architecture; obtaining one or more second scaling parameters based on the second benchmark performance data; determining one or more second scaling indicators for the second candidate quantum system architecture based on the one or more second scaling parameters; comparing the one or more scaling indicators to the one or more second scaling indicators, and based on the comparison, selecting one of the candidate quantum system architecture or a second quantum system architecture; and configuring the operational quantum system according to one or more operational characteristics of the selected one of the candidate quantum system architecture or the second candidate quantum system architecture.

16. A quantum computing system, comprising: quantum hardware; one or more classical processors; one or more non-transitory computer-readable media storing instructions that, when implemented, cause the one or more classical processors to perform operations comprising: obtaining benchmark performance data for a candidate quantum system architecture, the benchmark performance data describing one or more performance characteristics of the candidate quantum system architecture for a plurality of processor sizes of the candidate quantum system architecture; obtaining one or more scaling parameters based on the benchmark performance data, one or more quantum scaling parameters including a scaling model that relates processor sizes of the candidate quantum system architecture to the one or more performance characteristics of the candidate quantum system architecture; determining one or more scaling indicators for the candidate quantum system architecture at scaled processor sizes greater than the plurality of processor sizes via the scaling model; and determining one or more control actions for the quantum hardware based on the one or more scaling indicators.

17. The quantum computing system of claim 16, wherein obtaining the benchmark performance data comprises: selecting a hardware architecture of the candidate quantum system architecture, the hardware architecture of the candidate quantum system architecture defining structural characteristics of one or more qubits of the candidate quantum system architecture; selecting a control strategy of the candidate quantum system architecture, the control strategy defining operational characteristics of the one or more qubits of the candidate quantum system architecture; and obtaining the benchmark performance data for the candidate quantum system architecture, the candidate quantum system architecture including the one or more qubits configured according to the hardware architecture and the control strategy.

18. The quantum computing system of claim 16, wherein obtaining the one or more quantum scaling parameters comprises fitting the scaling model to the benchmark performance data.

19. The quantum computing system of claim 16, wherein the quantum scaling parameters include a qubit saturation constant, a saturation gate error, and a scaling logical error penalty; and wherein the scaling model relates an average gate error at a plurality of qubits to a quantity that includes the scaling logical error penalty multiplied by an exponential function that is exponential in a quantity of qubits divided by the qubit saturation constant, the quantity subtracted from the saturation gate error.

20. One or more non-transitory computer-readable media storing instructions that, when implemented, cause one or more processors to perform operations comprising: obtaining benchmark performance data for a candidate quantum system architecture, the benchmark performance data describing one or more performance characteristics of the candidate quantum system architecture for a plurality of processor sizes of the candidate quantum system architecture; obtaining one or more scaling parameters based on the benchmark performance data, one or more quantum scaling parameters including a scaling model that relates processor sizes of the candidate quantum system architecture to the one or more performance characteristics of the candidate quantum system architecture; determining one or more scaling indicators for the candidate quantum system architecture at scaled processor sizes greater than the plurality of processor sizes via the scaling model; and determining one or more control actions for an operational quantum system based on the one or more scaling indicators.

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