Quick-start crystal oscillator stability test method

Abstract

The invention discloses a quick-start crystal oscillator stability test method, which comprises the following steps of: installing a tested crystal oscillator on an adaptive clamp, and electrifying to output a clock signal as a phase-locked loop reference input; the power supply receives an instruction of the upper computer and synchronously outputs a power-on time sequence signal as a timing starting point; the phase-locked loop tracks the reference clock through negative feedback, and outputs a locking time sequence signal when the frequency stability reaches a preset threshold value; and the time measuring unit records stable time, uploads the stable time to the upper computer for data verification and statistical analysis, and automatically powers off after a report is generated. According to the method, a phase-locked loop is taken as a core, an Arron variance statistical mechanism is combined, and the frequency jitter sensitivity reaches a ppb level; in cooperation with a vernier method and Butterworth filtering, the time measurement precision reaches a microsecond level, and the problem that the precision of a traditional method is insufficient is effectively solved. Parameterized configuration and automatic testing are supported, waveform acquisition and data tracing functions are achieved, and the testing efficiency and reproducibility are remarkably improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of crystal oscillator performance testing, and particularly relates to a rapid start crystal oscillator stability testing method. BACKGROUND

[0002] As a core clock frequency generating device of an electronic device, the stability speed of the output frequency of a crystal oscillator directly determines the response efficiency of the device after being powered on to enter a normal working state. In an application scenario requiring rapid start and target locking, the device usually adopts a temperature-compensated crystal oscillator or a constant-temperature crystal oscillator. Although such a crystal oscillator can quickly start to output a frequency signal, it needs to complete temperature-frequency calibration through an internal compensation circuit or maintain the stability of the working environment temperature through a constant-temperature control unit, resulting in a long time for the output frequency to reach the stability degree required by the application, and the time is measured in milliseconds. The difference between different crystal oscillator individuals is significant, and it is necessary to accurately test whether the crystal oscillator meets the device use requirements.

[0003] The existing crystal oscillator testing technology has obvious technical limitations: first, the test target is single, and only whether the crystal oscillator outputs a signal or the time from power-on to start can be detected, and the key time for the frequency to gradually converge to a stable state after starting cannot be quantified, and the time is the core index for determining whether the device can quickly complete target locking; second, the stability decision precision is low, and there is a lack of high-sensitivity detection mechanism for frequency micro-dithering. The traditional method mainly uses the frequency deviation falling into the ppm level range as the stability criterion, which is difficult to match the evaluation demand of ppb level stability for high-precision crystal oscillators; third, the test process has low automation degree, and manual recording of test data and manual adjustment of device parameters are required, which not only has low test efficiency, but also is easy to introduce errors due to human operation; fourth, the test process lacks traceability, and only a single numerical result can be output, and the dynamic adjustment process of the crystal oscillator frequency from starting to stability cannot be reviewed, which is not conducive to subsequent fault troubleshooting and crystal oscillator performance optimization.

[0004] In view of the above technical problems, a crystal oscillator stability testing method with high precision, automation and traceability is needed to solve the core problems that the existing technology cannot accurately measure the frequency stability time, has low test efficiency and the process is not traceable. SUMMARY

[0005] The purpose of the present application is to provide a rapid start crystal oscillator stability testing method to solve the problems of the existing technology that cannot accurately measure the frequency stability time, has low test efficiency and the process is not traceable.

[0006] To solve the above technical problems, the technical solution adopted by the present application is:

[0007] A rapid start crystal oscillator stability testing method, comprising the following steps:

[0008] Crystal clock source construction step: the tested crystal is fixed on the adaptive tool fixture, and the tested crystal outputs a continuous clock signal after being powered on, which is input as a reference clock of the phase-locked loop module;

[0009] Timing reference generation step: after the crystal power supply receives the power-on control instruction issued by the upper computer, it outputs a stable working voltage to the tested crystal, and simultaneously outputs a power-on timing signal to the time measurement unit; the power-on timing signal serves as the starting reference for testing timing;

[0010] Frequency stability decision step: the phase-locked loop module receives the reference clock of the tested crystal, and forms a negative feedback loop through the built-in voltage-controlled clock device and the loop filter unit, dynamically adjusts the output frequency of the voltage-controlled clock device to track the reference clock; when the frequency variation rate of the reference clock meets the statistical characteristics of the relative frequency deviation calculated by continuous sampling, so that the frequency stability reaches the preset threshold, the phase-locked loop module enters the locked state and outputs the locked timing signal;

[0011] Test process control step: the upper computer receives the frequency stability time data uploaded by the time measurement unit, performs validity check on the single test data, eliminates obviously abnormal data, completes statistical analysis of multiple test data and generates a test report; after the test is completed, the upper computer issues a power-off instruction to the crystal power supply to cut off the working power supply of the tested crystal, and completes a single test cycle.

[0012] According to the above technical solution, in the crystal clock source construction step, the tool fixture is differentiated and adapted based on the working principle and physical characteristics of the tested crystal, specifically including:

[0013] If the tested crystal is a temperature-compensated crystal, the tool fixture uses low-thermal-potential contact materials to construct the signal transmission path, suppressing the additional frequency drift introduced by the temperature difference at the contact point; at the same time, an impedance matching network is built in to make the reflection coefficient of the reference clock transmission satisfy |Γ|≤0.03, and the reflection coefficient calculation formula is:

[0014]

[0015] Where Z L is the actual load impedance, and Z0 is the system characteristic impedance; if the tested crystal is a constant-temperature crystal, the tool fixture integrates an active thermal management subsystem, which maintains the crystal working environment temperature fluctuation ≤±0.1℃ through a heat conduction control algorithm, and the heat conduction control algorithm is constructed based on the heat diffusion equation:

[0016]

[0017] Where α is the thermal diffusivity of the thermal management material, P is the working power consumption of the crystal, and C pρ is the specific heat capacity of the material, and ρ is the density of the material. If the crystal oscillator being tested is a passive crystal oscillator: the tooling fixture integrates a π-type matching network, and the matching parameters are configured according to the equivalent series resistance of the crystal oscillator and the load capacitance requirements to ensure that the crystal oscillator has a start-up margin of ≥6dB.

[0018] According to the above technical solution, in the timing reference generation step, the stability design of the crystal oscillator power supply is based on the frequency domain analysis of the control system, and the power transfer function model is:

[0019]

[0020] Where K is the DC gain of the power supply, and τ1 and τ2 are the system time constants; by adjusting the feedback network parameters, the power supply meets the following performance requirements: the output voltage accuracy is determined by the resolution of the feedback network resistor, ensuring that the impact of voltage fluctuations on the crystal oscillator frequency does not exceed 1 / 5 of the preset frequency stability threshold; the voltage rise time and the power supply bandwidth satisfy t r ≈0.35 / BW, where W is the power supply bandwidth, to avoid abnormal crystal oscillator startup caused by rising edge overshoot; the output ripple is lower than the power supply noise suppression threshold in the crystal oscillator sensitive frequency band, and the power-on timing signal is output through electromagnetic isolation units such as optocouplers, with an isolation voltage ≥2kVrms to avoid common ground noise interference.

[0021] According to the above technical solution, the stability criterion in the frequency stability decision step is as follows:

[0022] The reference clock is continuously sampled by the built-in sampling unit of the phase-locked loop module, and the Allan variance of frequency stability is calculated. Frequency stability is determined when the Allan variance is less than or equal to a preset threshold. The formula for calculating the Allan variance is:

[0023]

[0024] in The frequency stability of the reference clock is given by τ, the sampling interval is given by N, and the number of samples is given by y. i Let be the relative frequency deviation of the i-th sample; and the loop design of the phase-locked loop module is based on the phase margin optimization principle, with the loop filter transfer function H(s) and phase margin φ being related. m satisfy:

[0025]

[0026] Where ω c ω is the loop cutoff frequency. z ω is the zero-point angular frequency of the loop. p The loop pole angular frequency is used to maintain the phase margin between 45° and 65° to ensure locking stability.

[0027] According to the above technical solution, in the steady-state time measurement step, the timing uncertainty of the time measurement unit satisfies:

[0028]

[0029] Where f clk σ is the clock frequency of the timing module. jitter The clock jitter variance is used; the digital filtering algorithm is the Butterworth low-pass filter algorithm based on the Z-transform, and the filter transfer function is:

[0030]

[0031] The timing measurement unit adopts a multi-edge verification mechanism: timing stops only after ≥3 valid edges of the lock timing signal are detected consecutively, further avoiding false triggering caused by single noise.

[0032] Based on the above technical solution, the data validity verification step in the test process control process specifically includes:

[0033] The confidence level of time measurement data is assessed based on a Bayesian inference model, and data with a confidence level below 95% are removed. The Bayesian inference expression is as follows:

[0034]

[0035] Where θ is the frequency stability time parameter to be evaluated, D is the measurement data, P(θ) is the prior probability, and P(D|θ) is the likelihood function;

[0036] Automated linkage: Communicates with automated clamping equipment and uses a discrete event control model to achieve seamless coordination between test completion, crystal oscillator unloading, new crystal oscillator clamping, and the start of the next test round. The discrete event control model is defined as follows:

[0037] G=(X,E,f,Γ,x0)

[0038] Where X is the system state set, E is the event set, f is the state transition function, Γ is the active event set, and x0 is the initial state.

[0039] Based on the above technical solution, in the waveform verification and tracing steps, the design of the acquisition parameters and the waveform analysis logic of the waveform acquisition unit are as follows:

[0040] Data acquisition parameters: Based on Shannon's sampling theorem, sampling rate f s Satisfy f s >2f max f max The highest frequency of the crystal oscillator under test is used to avoid aliasing of the reference clock signal; the storage depth is determined based on the maximum test duration and sampling rate to ensure complete recording of the entire process from power-on, oscillation start-up, to stabilization.

[0041] Waveform analysis: Key time points are extracted using an instantaneous frequency calculation model. The instantaneous frequency calculation formula is as follows:

[0042]

[0043] Where φ is the phase of the reference clock; automatically identify the start-up and stabilization times.

[0044] The start-up time is when the instantaneous frequency first enters the range of ±10% of the crystal oscillator's rated frequency, and the stabilization time is when the instantaneous frequency change rate is ≤ the preset frequency stabilization threshold and lasts for ≥10ms. These values ​​are marked in the waveform graph and cross-validated with the data from the time measurement unit.

[0045] According to the above technical solution, the preset frequency stability threshold can be dynamically adjusted according to the accuracy level of the crystal oscillator being tested:

[0046] For high-precision temperature-controlled crystal oscillators: the preset frequency stability threshold is adjusted to ≤0.5ppb / s, and the phase-locked loop bandwidth is simultaneously reduced to 50Hz~200Hz to improve the phase difference detection accuracy;

[0047] For ordinary temperature-compensated crystal oscillators: the preset frequency stability threshold is adjusted to ≤2ppb / s, and the loop bandwidth is configured to 200Hz~1kHz;

[0048] For passive crystal oscillators: the preset frequency stability threshold is adjusted to ≤5ppb / s, and the loop filter is simplified to a second-order RC structure to balance test accuracy and efficiency.

[0049] According to the above technical solution, a system calibration step is also included before testing to ensure the accuracy of each unit test:

[0050] Phase-locked loop module calibration: Use a standard signal generator with a frequency stability ≤0.1ppb / s to output a reference signal, adjust the phase-locked loop locking detection parameters, and make the error of the stability criterion ≤1 / 10 of the preset frequency stability threshold;

[0051] Time measurement unit calibration: Standard timing signals are output from high-precision clock sources such as rubidium atomic clocks to calibrate the clock frequency deviation of the timing module of the time measurement unit, so that the timing error is ≤1μs;

[0052] Waveform acquisition unit calibration: The sampling rate and trigger accuracy are calibrated using an oscilloscope calibrator to ensure that the waveform time axis error is ≤ 5% of the sampling period.

[0053] According to the above technical solution, it also includes a test environment control step to suppress the impact of external interference on the test:

[0054] Temperature control: The test environment temperature is maintained at 25℃±2℃ by a constant temperature chamber, and the temperature fluctuation during the constant temperature crystal oscillator test is further controlled to ≤±0.1℃;

[0055] Electromagnetic interference control: Electromagnetic shielding measures are adopted in the test area to ensure that electromagnetic radiation in the 10kHz~1GHz frequency band is ≤30dBμV / m; the crystal oscillator power supply, phase-locked loop module, and time measurement unit adopt independent grounding and independent voltage regulation to avoid power supply noise coupling;

[0056] Humidity control: Maintain the test environment humidity at 40% to 60% to avoid oxidation of tooling and fixture contacts due to high humidity or electrostatic interference due to low humidity.

[0057] Compared with the prior art, the present invention has the following beneficial effects:

[0058] In this invention, a phase-locked loop module is used as the core of frequency stability decision. The statistical decision mechanism based on Allan variance can achieve a sensitivity of ppb level to frequency jitter. Combined with the microcontroller vernier method timing and Butterworth digital filtering algorithm, the time difference measurement accuracy is better than microsecond level. This effectively solves the technical bottleneck of low decision accuracy and large timing error of traditional methods and meets the testing requirements of high-precision crystal oscillators.

[0059] Furthermore, through parameterized configuration and automated linkage with the host computer, the process of power-on, testing, data statistics, and the next round of startup is automated, significantly reducing testing costs. The testing process is also traceable, and an optional oscilloscope can be used to acquire waveforms and mark key nodes, generating complete waveform spectra of oscillation, adjustment, and stabilization, which are stored in association with numerical data. This not only provides an intuitive basis for crystal oscillator performance optimization, but also allows for review of the entire process when test anomalies occur, quickly locating the cause of the fault. Attached Figure Description

[0060] Figure 1 This is a flowchart of the crystal oscillator testing method of the present invention. Detailed Implementation

[0061] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0062] Example 1

[0063] like Figure 1 As shown, the solution of this invention is based on a closed-loop architecture of clock source construction, timing reference generation, frequency stability determination, time measurement, and process control. It achieves efficient testing of crystal oscillator stability through modular collaboration and precise timing control. The specific technical solution is as follows:

[0064] First, the crystal clock source construction step is performed. The crystal under test is fixed in the appropriate fixture to ensure that it can output a continuous, interference-free clock signal after being powered on. This clock signal serves as the reference clock input for the phase-locked loop (PLL) module. The fixture must simultaneously meet the dual design requirements of impedance matching and noise suppression: impedance matching design avoids reflection interference caused by impedance discontinuities during signal transmission, while noise suppression design ensures that the phase noise of the reference clock is below a preset threshold through the selection of low-interference materials and structural optimization, providing a clean signal foundation for subsequent frequency stability determination.

[0065] Next, the timing reference generation step begins. After receiving the power-on control command from the host computer, the crystal oscillator power supply outputs a stable operating voltage to the crystal oscillator under test, and simultaneously outputs a power-on timing signal to the microcontroller (i.e., the time measurement unit). This power-on timing signal serves as the timing start reference for the entire test process. Its edge steepness must meet the requirement that the timing error does not exceed 1% of the timing cycle, thereby ensuring the accuracy of the starting timing point and avoiding measurement deviations caused by timing signal drift.

[0066] The frequency stability determination process then begins. The phase-locked loop (PLL) module receives the reference clock output from the crystal oscillator under test. Through a built-in voltage-controlled clock (VCC) device and a loop filter unit, a negative feedback loop is formed, dynamically adjusting the output frequency of the VCC device to track the reference clock. When the rate of change of the reference clock's frequency satisfies the stability criterion defined based on Allan variance, the PLL module enters a locked state and outputs a lock timing signal. This stability criterion, calculated through continuous sampling, determines the statistical characteristics of the relative frequency deviation, accurately reflecting the actual stable state of the crystal oscillator frequency rather than instantaneous fluctuations, thus ensuring the reliability of the determination result.

[0067] In the stabilization time measurement step, the microcontroller synchronously acquires the power-on timing signal and the lock-in timing signal, and records the time difference between the two signals through a high-frequency timing module. This time difference is the frequency stabilization time of the crystal oscillator under test. To avoid timing misjudgments caused by glitches and noise, the microcontroller needs to integrate a digital filtering algorithm to suppress noise in the timing signal, ensuring that the time difference measurement accuracy is better than the preset accuracy threshold and meets the microsecond-level testing requirements.

[0068] As a core control step, the test process management steps involve the host computer receiving the frequency stabilization time data uploaded by the microcontroller. First, it verifies the validity of the single test data to remove obvious abnormal data. Then, it performs statistical analysis on multiple sets of test data (such as calculating the average value and standard deviation) and generates a test report. After the test is completed, the host computer sends a power-off command to the crystal oscillator power supply to cut off the working power of the crystal oscillator under test, completing a single test cycle and providing closed-loop support for batch crystal oscillator testing.

[0069] In addition, this solution can selectively perform waveform verification and traceability steps: an oscilloscope (i.e., waveform acquisition unit) is used to synchronously receive the power-on timing signal, the reference clock signal of the crystal oscillator under test, and the locking timing signal of the phase-locked loop module. Based on signal sampling theory, the three signals are acquired without aliasing to generate a complete waveform spectrum including the crystal oscillator start-up stage, frequency adjustment stage, and frequency stabilization stage. After the spectrum is uploaded to the host computer, it is associated with the frequency stabilization time data for storage, realizing the visualization and traceability of the test process and data cross-verification, further improving the credibility of the test results.

[0070] To ensure the practicality and adaptability of the technical solution, the design details of the core modules were further optimized: In the tooling fixture design, differentiated adaptations were adopted for the working principles and physical characteristics of different types of crystal oscillators. For temperature-compensated crystal oscillators, low thermoelectric potential contact materials (such as beryllium copper) were used to construct the signal transmission path to suppress additional frequency drift introduced by the temperature difference at the contact point. At the same time, an impedance matching network was built-in, and the impedance matching effect was quantified by the reflection coefficient calculation formula, which is shown below:

[0071]

[0072] Among them, Z L Z0 is the system characteristic impedance, where Z is the actual load impedance. The impedance matching effect is quantified using the reflection coefficient calculation formula to ensure that the reflection coefficient |Γ| of the reference clock transmission is ≤0.03 (corresponding to a reflection power ≤0.1%). For the temperature-controlled crystal oscillator, the fixture integrates an active thermal management subsystem. A thermal conduction control algorithm is constructed based on the thermal diffusion equation to maintain the temperature fluctuation of the crystal oscillator's operating environment ≤±0.1℃. The thermal conduction control algorithm is as follows:

[0073]

[0074] Where α is the thermal diffusivity of the thermal management material, P is the crystal oscillator power consumption, and C p ρ is the specific heat capacity of the material, and ρ is the density of the material. For passive crystal oscillators, the fixture integrates a π-type matching network. The matching parameters are configured according to the equivalent series resistance of the crystal oscillator and the load capacitance requirements to ensure that the crystal oscillator has an oscillation margin of ≥6dB and avoid oscillation failure or oscillation delay.

[0075] The stability design of the crystal oscillator power supply is based on frequency domain analysis of the control system, and its transfer function model is as follows:

[0076]

[0077] Where K is the DC gain of the power supply, and τ1 and τ2 are the system time constants; by adjusting the feedback network parameters, the influence of power supply output voltage fluctuations on the crystal oscillator frequency is ensured to not exceed 1 / 5 of the preset frequency stability threshold, and the voltage rise time and power supply bandwidth satisfy t rThe output ripple is approximately 0.35 / BW (BW is the power supply bandwidth) and there is no overshoot. The output ripple in the 10Hz to 1MHz frequency band is lower than the power supply noise suppression threshold. At the same time, the power-on timing signal is output through an optocoupler (such as model TLP181) with an isolation voltage ≥2kVrms to avoid common ground noise interfering with the timing reference.

[0078] In the specific implementation of the frequency stability criterion, the phase-locked loop module has a built-in sampling unit that continuously samples the reference clock. The frequency stability is calculated using the Allan variance calculation formula, which is shown below:

[0079]

[0080] in The frequency stability of the reference clock, τ is the sampling interval, N is the number of samples, and y i The relative frequency deviation of the i-th sample is considered stable when this value is less than or equal to a preset threshold. The phase-locked loop design is based on the phase margin optimization principle, and the loop filter transfer function H(s) and phase margin φ are related. m satisfy:

[0081]

[0082] Where ω c For loop cutoff frequency, ω z For the loop zero-point angular frequency, ω p The loop pole angular frequency is used to maintain the phase margin between 45° and 65° to ensure the locking stability of the phase-locked loop when the reference clock fluctuates. When the frequency of the voltage-controlled clock device is inconsistent with that of the crystal oscillator under test, frequency matching is achieved by using the integer / fractional frequency division configuration of the frequency division unit built into the phase-locked loop. That is, the frequency of the voltage-controlled clock device = the frequency of the crystal oscillator under test × the frequency division coefficient N / the frequency division coefficient M (N and M are positive integers).

[0083] The high-precision timing function of the microcontroller is implemented based on the vernier method, and the timing uncertainty satisfies the following formula:

[0084]

[0085] Where f clk σ is the clock frequency of the timing module. jitter The clock jitter variance is used; the digital filtering algorithm adopts the Butterworth low-pass filtering algorithm based on Z-transform, and its transfer function is shown in the following equation:

[0086]

[0087] The low-pass filtering algorithm can effectively suppress glitches and noise in the timing signal; at the same time, the microcontroller adopts a multi-edge verification mechanism, and stops timing only after detecting ≥3 valid edges of the lock timing signal, further avoiding false triggering caused by single noise.

[0088] The intelligent management and control functions of the host computer mainly include three parts: First, data validity verification, based on a Bayesian inference model, as shown in the following formula:

[0089]

[0090] Where θ is the frequency stability time parameter to be evaluated, D is the measurement data, P(θ) is the prior probability, and P(D|θ) is the likelihood function. The measurement data are evaluated for confidence based on a Bayesian inference model, and data with a confidence level below 95% are discarded.

[0091] Secondly, it features parameterized configuration, allowing users to input parameters such as the crystal oscillator's rated frequency, preset frequency stability threshold, and number of tests. It automatically derives hardware configuration parameters such as the phase-locked loop division ratio and timing sampling interval, eliminating the need for manual adjustments.

[0092] Thirdly, it features automated linkage, communicating with automated clamping equipment and using a discrete event control model to achieve seamless transitions between test completion, crystal oscillator unloading, new crystal oscillator clamping, and the start of the next round of testing, thereby improving batch testing efficiency. The discrete event control model is defined as follows:

[0093] G=(X,E,f,Γ,x0)

[0094] Where X is the system state set, E is the event set, f is the state transition function, Γ is the active event set, and x0 is the initial state.

[0095] The waveform acquisition and analysis function of the oscilloscope is designed based on Shannon's sampling theorem, with a sampling rate f. s Satisfy f s >2f max (f max The highest frequency of the crystal oscillator under test is used to avoid signal aliasing. The storage depth is determined based on the maximum test duration and sampling rate to ensure complete recording of the entire process from power-on, oscillation start-up, to stabilization. Waveform analysis extracts key time nodes through an instantaneous frequency calculation model, automatically identifying the start-up moment (when the instantaneous frequency first enters the range of ±10% of the crystal oscillator's rated frequency) and the stabilization moment (when the instantaneous frequency change rate is ≤ a preset threshold and lasts ≥ 10ms). These are marked on the waveform graph and cross-validated with the microcontroller's measurement data to further ensure test accuracy. The instantaneous frequency calculation formula is:

[0096]

[0097] In addition, the preset frequency stability threshold can be dynamically adjusted according to the crystal oscillator accuracy level: for high-precision temperature-compensated crystal oscillators, the threshold is adjusted to ≤0.5ppb / s, simultaneously reducing the phase-locked loop bandwidth to 50Hz~200Hz and improving the phase difference detection accuracy to ≤0.05°; for ordinary temperature-compensated crystal oscillators, the threshold is adjusted to ≤2ppb / s, and the loop bandwidth is configured to 200Hz~1kHz; for passive crystal oscillators, the threshold is adjusted to ≤5ppb / s, simplifying the loop filter to a second-order RC structure, balancing test efficiency while ensuring test accuracy.

[0098] To further ensure the reliability of the test results, system calibration must be completed before testing: The phase-locked loop (PLL) locking detection parameters are calibrated using a standard signal generator with a frequency stability ≤ 0.1 ppb / s, ensuring the stability criterion error is ≤ 1 / 10 of the preset threshold; the microcontroller timing module is calibrated using a rubidium atomic clock, ensuring the timing error is ≤ 1 μs; and the sampling rate and trigger accuracy are calibrated using an oscilloscope calibrator, ensuring the waveform time axis error is ≤ 5% of the sampling period. Environmental interference must also be controlled during testing: the temperature is maintained at 25℃±2℃ (further controlled to ≤ ±0.1℃ for isothermal crystal oscillator testing); electromagnetic shielding measures are used in the test area to ensure electromagnetic radiation in the 10kHz~1GHz frequency band is ≤ 30dBμV / m; each device uses independent grounding and independent regulated power supply to avoid power supply noise coupling; humidity is controlled at 40%~60% to prevent oxidation of tooling contacts or electrostatic interference caused by low humidity.

[0099] Example 2

[0100] This embodiment is a further refinement of Embodiment 1. To make the technical solution of the present invention clearer and more operable, the implementation process of the present invention will be described in detail below with reference to specific embodiments.

[0101] This embodiment uses a temperature-compensated crystal oscillator (TCXO-100MHz) as the test object. The oscillator has a rated frequency of 100MHz, a target stability of 0.5ppm, and a preset frequency stability threshold of 2ppb / s. The core test equipment is selected as follows: The fixture is a low-thermal-potential fixture adapted to the TCXO, with a built-in 50Ω impedance matching network and a contact resistance ≤50mΩ; the crystal oscillator power supply output voltage is 5V±1%, rise time ≤100μs, and ripple ≤20mVpp in the 10Hz~1MHz frequency band; signal isolation is achieved using a TLP181 optocoupler; the phase-locked loop module is an ADF4351. The phase-locked loop (PLL) chip incorporates a third-order RC loop filter (parameters: R1 = 2kΩ, R2 = 10kΩ, C1 = 10nF, C2 = 1nF, C3 = 100pF) with a phase margin of 50°. The microcontroller used is an STM32F407 with a TIM2 timer clock frequency of 84MHz, a prescaler of 83, and a timing accuracy of 1μs. The oscilloscope used is a Tektronix MDO3054 with a bandwidth of 500MHz, a sampling rate of 2.5GSa / s, and a storage depth of 1Mpts. Customized testing software is installed on the host computer, supporting parameter configuration, data statistics, and report generation. The specific implementation steps include the following:

[0102] First, system calibration and environmental preparation were performed: A 100MHz standard signal was output through a standard signal generator, and the lock detection register (address 0x07) of the ADF4351 phase-locked loop chip was adjusted so that the lock signal was triggered when the Allan variance calculation result was ≤2ppb / s; a 1ms standard timing signal was output using a rubidium atomic clock to calibrate the microcontroller's TIM2 timer, ensuring that the timing error was ≤1μs; the constant temperature chamber was turned on and the temperature was set to 25℃±0.5℃, the humidity controller was started to maintain the humidity at 50%, and the electromagnetic shielding device was turned on to ensure that the electromagnetic radiation in the 10kHz~1GHz frequency band of the test area was ≤30dBμV / m.

[0103] After calibration, the crystal clock source construction operation is performed: the TCXO-100MHz temperature compensated crystal oscillator is installed on the adapter fixture, ensuring that the alignment deviation between the crystal oscillator pins and the fixture contacts is ≤0.1mm. Then, the crystal oscillator output pins are connected to the reference clock input terminal of the phase-locked loop module. The reflection coefficient |Γ| of the transmission path is verified to be ≤0.03 by an impedance tester, which meets the signal integrity requirements.

[0104] Next, the equipment is connected and parameters are configured: the voltage output terminal of the crystal oscillator power supply is connected to the crystal oscillator power supply pin, and the timing signal output terminal is connected to the microcontroller GPIO1 interface and oscilloscope channel 1 respectively; the lock signal output terminal of the phase-locked loop module is connected to the microcontroller GPIO2 interface and oscilloscope channel 3 respectively; the frequency output terminal of the crystal oscillator is connected to oscilloscope channel 2; the host computer establishes communication with the crystal oscillator power supply, microcontroller, and phase-locked loop module through the serial port, and inputs parameters (crystal type: temperature compensated crystal oscillator, rated frequency: 100MHz, stability threshold: 2ppb / s, number of tests: 5) into the test software. The software automatically derives parameters such as the phase-locked loop frequency division ratio (N=1, M=1) and the microcontroller sampling interval (1μs), and sends the configuration command to the corresponding device.

[0105] The test process was then initiated: the host computer sent a test start command, the crystal oscillator power supply output 5V to the crystal oscillator, and the measured voltage rise time was 80μs. At the same time, a TTL high-level power-on signal was output to the microcontroller and oscilloscope. After the microcontroller's GPIO1 interface detected the rising edge of the power-on signal, it immediately started the TIM2 timer to begin timing. After the crystal oscillator was powered on, it quickly started oscillating, and the measured initial frequency deviation was -12ppm. The internal temperature compensation circuit started and sampled the ambient temperature parameter, dynamically adjusting the output frequency, and the frequency change rate gradually decreased. The phase-locked loop module received the 100MHz reference clock output from the crystal oscillator and dynamically adjusted the output frequency of the voltage-controlled clock device through the built-in negative feedback loop. When the crystal oscillator frequency change rate dropped to below 2ppb / s, the Allan variance calculation result met the stability criterion, and the phase-locked loop module output a high-level lock signal, with a measured lock delay of ≤10μs.

[0106] In the stabilization time measurement stage, after the microcontroller's GPIO2 interface detects the rising edge of the lock signal three times consecutively (with an interval of 10μs), it stops the TIM2 timer, calculates the timing difference (in this embodiment, the difference for a single test is 120μs), and reports the data to the host computer via the UART interface; the oscilloscope captures three signals at a sampling rate of 2.5GSa / s, automatically identifies the oscillation start time (the moment when the signal amplitude reaches 0.9Vpp, which is measured to be 3ms) and the stabilization time (which is measured to be 120ms), marks the key nodes in the waveform graph, and then uploads the data to the host computer.

[0107] During the data processing phase, the host computer uses the 3σ criterion to remove anomalies from five test data sets (118ms, 120ms, 122ms, 150ms, and 121ms, respectively). The average value of the valid data is calculated to be 120.25ms, and the standard deviation is 1.5ms. Subsequently, a PDF report containing test environment parameters (temperature 25.2℃, humidity 49%), raw data, waveform screenshots, and statistical results is generated and stored in the local database. After the test, the host computer sends a power-off command to the crystal oscillator power supply, which cuts off the crystal oscillator power supply. The fixture ejects the crystal oscillator under test, completing a single test. If batch testing is required, a new crystal oscillator can be grabbed by an automatic clamping device and the next round of testing can be started.

[0108] In this embodiment, the frequency stabilization time of the temperature-compensated crystal oscillator was measured to be 120.25 ms. The oscilloscope waveform verification showed that the deviation between the stabilization time and the microcontroller measurement result was ≤3 ms, which met the test accuracy requirements. The standard deviation of 5 repeated tests was ≤1.5 ms, indicating that the test repeatability of this method is good and can effectively distinguish the stabilization time differences of different crystal oscillators, providing reliable data support for the selection of crystal oscillators for equipment.

[0109] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0110] Finally, it should be noted that the above descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for testing the stability of a fast-start crystal oscillator, characterized by: The method comprises the following steps: crystal clock source construction step: fix the tested crystal oscillator in the adaptive tool clamp, and make the tested crystal oscillator output continuous clock signal after being powered on, which is used as the reference clock input of the phase-locked loop module; timing reference generation step: the crystal oscillator power supply outputs stable working voltage to the tested crystal oscillator after receiving the power-on control instruction issued by the upper computer, and synchronously outputs the power-on timing signal to the time measurement unit; the power-on timing signal is used as the starting reference of the test timing; frequency stability decision step: the phase-locked loop module receives the reference clock of the tested crystal oscillator, and forms a negative feedback loop through the built-in voltage-controlled clock device and the loop filter unit, so as to dynamically adjust the output frequency of the voltage-controlled clock device to track the reference clock; when the frequency variation rate of the reference clock satisfies the statistical characteristics of the relative frequency deviation calculated by continuous sampling, so that the frequency stability reaches the preset threshold, the phase-locked loop module enters the locked state and outputs the locked timing signal; test process control step: the upper computer receives the frequency stability time data uploaded by the time measurement unit, performs validity check on the single test data, eliminates obviously abnormal data, completes statistical analysis of multiple test data and generates a test report; after the test is completed, the upper computer issues a power-off instruction to the crystal oscillator power supply to cut off the working power supply of the tested crystal oscillator, and completes a single test cycle.

2. The method of claim 1, wherein: In the crystal clock source construction step, the tool clamp is differentiated and adapted based on the working principle and physical characteristics of the tested crystal oscillator, specifically including: If the tested crystal oscillator is a temperature compensation crystal oscillator: the tool clamp uses low-thermal-potential contact materials to construct the signal transmission path, so as to suppress the additional frequency drift introduced by the temperature difference of the contact point; at the same time, an impedance matching network is built in, so that the reflection coefficient of the reference clock transmission satisfies |Γ|≤0.03, and the reflection coefficient calculation formula is: wherein Z L is the actual load impedance, Z0 is the system characteristic impedance; if the tested crystal oscillator is a constant temperature crystal oscillator: the tooling fixture integrates an active thermal management subsystem, which maintains the temperature fluctuation of the working environment of the crystal oscillator ≤±0.1℃ through a heat conduction control algorithm, and the heat conduction control algorithm is constructed based on a heat diffusion equation: wherein a is the thermal diffusivity of the thermal management material, P is the operating power dissipation of the crystal, C p is the specific heat capacity of the material, and p is the density of the material; if the crystal being tested is a passive crystal: the tooling fixture integrates a pi-type matching network, the matching parameters are configured according to the equivalent series resistance of the crystal and the load capacitance requirement, to ensure that the crystal start-up margin is > 6 dB.

3. The method of claim 1 or 2, wherein: In the timing reference generation step, the stability design of the crystal oscillator power supply is realized based on the frequency domain analysis of the control system, and the power supply transfer function model is: Wherein K is the power DC gain, τ1, τ2 is the system time constant; by adjusting the feedback network parameters to meet the following performance requirements: output voltage precision is determined by the feedback network resistance resolution, ensure that the impact of the voltage fluctuation on the frequency of the crystal oscillator is not more than 1 / 5 of the preset frequency stability threshold; the voltage rise time and the power bandwidth satisfy t r ≈0.35 / BW, W is the power bandwidth, to avoid the overshoot of the rising edge leading to the abnormal start of the crystal oscillator; the output ripple is lower than the power noise suppression threshold in the sensitive frequency band of the crystal oscillator, and the power-on timing signal is output through an electromagnetic isolation unit such as an optical coupler, and the isolation voltage is greater than or equal to 2kVrms to avoid common ground noise interference.

4. The method of claim 3, wherein: In the frequency stability decision step, the stability criterion is specifically: The built-in sampling unit of the phase-locked loop module continuously samples the reference clock, calculates the Allan variance of the frequency stability, and determines that the frequency is stable when the Allan variance is less than or equal to the preset threshold, and the Allan variance calculation formula is: wherein is the frequency stability of the reference clock, τ is the sampling interval, N is the number of samples, y i is the relative frequency deviation of the i-th sample; and the loop design of the phase-locked loop module is based on the phase margin optimization principle, the loop filter transfer function H(s) and the phase margin φ m satisfies: where ω c is the loop cutoff frequency, ω z is the loop zero angular frequency, and ω p is the loop pole angular frequency. The phase margin needs to be maintained between 45° and 65° to ensure lock stability.

5. The method of claim 4, wherein: In the stability time measurement step, the timing uncertainty of the time measurement unit satisfies: where f clk is the clock frequency of the timing module, σ jitter is the clock jitter variance; the digital filtering algorithm is a Butterworth low-pass filter algorithm based on Z-transform, and the filter transfer function is: The time measurement unit uses a multi-edge verification mechanism: it stops timing only after continuously detecting ≥3 valid edges of the locked timing signal, further avoiding false triggering caused by single noise.

6. The method of claim 1, wherein: In the test process control step, the data validity check is specifically: Based on the Bayesian inference model, the confidence of the time measurement data is evaluated, and the data with a confidence lower than 95% is eliminated, and the Bayesian inference expression is: Where θ is the frequency stability time parameter to be evaluated, D is the measurement data, P(θ) is the prior probability, and P(D|θ) is the likelihood function; Automatic linkage: communicate with the automatic clamping equipment, realize the connection of test end, crystal unloading, new crystal clamping and next round test start through the discrete event control model, and the discrete event control model is defined as: G=(X,E,f,Γ,x0) Where X is the system state set, E is the event set, f is the state transition function, Γ is the active event set, x0 is the initial state.

7. The method of claim 1, wherein: In the waveform verification and tracing step, the waveform acquisition unit's acquisition parameter design and waveform analysis logic are: Acquisition parameters: based on Shannon sampling theorem, sampling rate f s Satisfies f s > 2f max , f max is the highest frequency of the tested crystal oscillator, avoiding aliasing of the reference clock signal; the storage depth is determined according to the maximum test duration and the sampling rate, ensuring complete recording of the power-on, start-up, and stable whole process; Waveform analysis: extract key time nodes through the instantaneous frequency calculation model, and the instantaneous frequency calculation formula is: Where φ is the phase of the reference clock; automatically identify the starting time and stable time Where the starting time is when the instantaneous frequency first enters the rated frequency ± 10% range of the crystal oscillator, and the stable time is when the instantaneous frequency change rate ≤ preset frequency stability threshold and lasts ≥ 10ms, which is marked in the waveform atlas and cross-verified with the data of the time measurement unit.

8. The method of claim 7, wherein: The preset frequency stability threshold can be dynamically adjusted according to the accuracy level of the tested crystal oscillator: For high-precision constant-temperature crystal oscillators: adjust the preset frequency stability threshold to ≤0.5ppb / s, simultaneously reduce the phase-locked loop bandwidth to 50Hz-200Hz, and improve the phase difference detection accuracy; For ordinary temperature-compensated crystal oscillators: adjust the preset frequency stability threshold to ≤2ppb / s, and configure the loop bandwidth to 200Hz-1kHz; For passive crystal oscillators: adjust the preset frequency stability threshold to ≤5ppb / s, and simplify the loop filter to a 2-order RC structure to balance the test accuracy and efficiency.

9. The method of claim 1, wherein: It also includes a system calibration step before testing to ensure the accuracy of each unit: Phase-locked loop module calibration: use a standard signal generator with a frequency stability of ≤0.1ppb / s to output a reference signal, adjust the phase-locked loop locking detection parameters, and make the error of the stability criterion ≤1 / 10 of the preset frequency stability threshold; Time measurement unit calibration: use a high-precision clock source such as a rubidium atomic clock to output a standard time sequence signal, calibrate the clock frequency deviation of the time measurement unit's timing module, and make the timing error ≤1μs; Waveform acquisition unit calibration: use an oscilloscope calibrator to calibrate the sampling rate and trigger accuracy, and ensure that the waveform time axis error ≤5% of the sampling period.

10. The method of claim 1, wherein: It also includes a test environment control step to suppress the influence of external interference on the test: Temperature control: maintain the test environment temperature at 25℃±2℃ through a thermostat, and further control the temperature fluctuation to ≤±0.1℃ when testing constant-temperature crystal oscillators; Electromagnetic interference control: use electromagnetic shielding measures in the test area to make the electromagnetic radiation in the 10kHz-1GHz frequency band ≤30dBμV / m; use independent grounding and independent voltage-stabilized power supply for the crystal oscillator power supply, phase-locked loop module, and time measurement unit to avoid power supply noise coupling; Humidity control: maintain the test environment humidity at 40%-60% to avoid high humidity causing tooling fixture contact oxidation or low humidity causing static interference.

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