Silicon carbide device state detection circuit based on threshold voltage variation

Abstract

The application discloses a silicon carbide device state detection circuit based on threshold voltage change, relates to the technical field of power electronics, and is oriented to online threshold voltage extraction and state evaluation of SiC power devices. The circuit takes a half-bridge structure as a carrier, forms an integral voltage at an integral node of a lower tube through the transconductance operational amplifier integration of a lower tube gate-source voltage, and converts a midpoint node voltage mutation in the half-bridge into a comparator inversion signal of a drain-source event detection node through a high-voltage diode and a current-limiting resistor, so as to limit an integral time window and trigger a reset switch MOS tube to discharge and reset the integral capacitor, and obtain an integral voltage peak value and an event time delay. A control unit only collects the two variables of the event time delay and the integral voltage peak value, carries out gating and subdivides output abnormal types according to a calibrated consistency relationship, realizes effective measurement screening, false trigger and integral / reset abnormality diagnosis and threshold voltage drift statistics, and improves the stability and engineering usability of online detection.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power electronics, in particular to a circuit and method for threshold voltage online detection, aging evaluation and abnormality diagnosis of silicon carbide power devices. BACKGROUND

[0002] Silicon carbide (SiC) power devices have been widely used in new energy vehicles, industrial power supplies and smart grids due to their high switching speed, low conduction loss and high voltage resistance. The gate threshold voltage (Vth) of SiC devices may drift during long-term operation due to electric field stress, temperature cycling and switching stress, which may change the conduction and switching behavior of the devices and cause reliability risks. Existing Vth measurement methods are mostly offline testing methods that require stopping the system and using special equipment to extract parameters, which cannot meet the continuity and real-time requirements of online monitoring in engineering systems. Existing online detection methods usually rely on a voltage point, time point or slope feature in the on or off transient to indirectly infer Vth. However, the switching transient is significantly affected by parasitic parameters, driving conditions, load changes and electromagnetic interference, and there are Miller platforms and ringing phenomena, making it difficult to define and repeat the feature points, resulting in fluctuations and even misjudgments in online measurement under complex working conditions. Therefore, the single technical problem to be solved by the present application is how to realize a SiC power device Vth online detection method that is not sensitive to working condition disturbances and has better repeatability without stopping the system, to reduce the risk of measurement errors caused by transient uncertainties. SUMMARY

[0003] In order to overcome the above-mentioned defects of the prior art, the embodiments of the present application provide a silicon carbide device state detection circuit based on threshold voltage change to solve the problems raised in the background art.

[0004] To achieve the above-mentioned purpose, the present application provides the following technical solutions:

[0005] The silicon carbide device state detection circuit based on threshold voltage change comprises:

[0006] The direct current bus voltage source UDC is connected in parallel with the bus capacitor C3 between the direct current bus positive node NDC+ and the direct current bus negative node NDC-; the drain of the upper transistor S1 is connected to NDC+, and the source is connected to the half-bridge midpoint node NSW; the drain of the lower transistor S2 is connected to NSW, and the source is connected to NDC-; the lower transistor drive source V2 is connected to the lower transistor S2 gate node NG2 through the lower transistor gate resistor R4; the input of the transconductance operational amplifier OTA2 is connected to NG2 and the lower transistor source node NS2, and the output of the transconductance operational amplifier OTA2 is connected to the lower transistor integration node NINT2; the lower transistor integration capacitor C2 is connected between NINT2 and NDC- to form the integration voltage VC2; the high-voltage diode D6 and the lower transistor current-limiting resistor R3 are connected in series between NSW and the lower transistor drain-source event detection node NSEN2; the micro-current source I2 is connected between VDD and NSEN2; the clamping diode D4 and the clamping diode D5 are connected between NSEN2 and VCLAMP+, VCLAMP- respectively; the input of the comparator U2 is connected to NSEN2 and the comparator reference voltage node VREF, and the output is the lower transistor comparator output node COMP2; the input of the buffer BUF2 is connected to COMP2, and the output is connected to the gate of the lower transistor reset switch MOS transistor M2, which is connected in parallel between NINT2 and NDC-; the control unit is electrically connected to V2, COMP2 and NINT2 respectively, for recording the turn-on instruction timestamp t0 and the comparator flip timestamp t2 to obtain the event delay Δt, collecting the integration voltage peak value VC_peak at t2, calculating the residual error r=VC_peak-f(Δt), outputting the valid measurement flag when |the residual error r|≤ε, and obtaining the gate threshold voltage Vth according to the conversion relationship g(VC_peak), outputting the abnormal type 1 flag when the residual error r<-ε, and outputting the abnormal type 2 flag when the residual error r>+ε.

[0007] In a preferred embodiment, the lower transistor S2 source node NS2 and the direct current bus negative node NDC- are the same node or are connected equivalently.

[0008] In a preferred embodiment, the cathode of the high-voltage diode D6 is connected to the half-bridge midpoint node NSW, and the anode is connected to the lower transistor drain-source event detection node NSEN2 through the lower transistor current-limiting resistor R3.

[0009] In a preferred embodiment, the buffer BUF2 is an inverting or non-inverting buffer, so that when the lower transistor comparator output node COMP2 is at the first logic level, the lower transistor reset switch MOS transistor M2 is off, and when the lower transistor comparator output node COMP2 flips to the second logic level, the lower transistor reset switch MOS transistor M2 is turned on to discharge the lower transistor integration capacitor C2 and reset the integration voltage VC2.

[0010] In a preferred embodiment, the consistency function f(Δt) is stored in the control unit in a piecewise linear look-up table manner, and the conversion relationship g(VC_peak) is stored in the control unit in a piecewise linear look-up table manner and segmented by ambient temperature or temperature compensated.

[0011] In a preferred embodiment, the control unit controls the down tube driving source V2 to apply an on voltage to the down tube S2 gate node NG2 through the down tube gate resistor R4 under the control of the on instruction timestamp t0, so that the transconductance operational amplifier OTA2 integrates the down tube integration capacitor C2 and makes the integration voltage VC2 rise; when the down tube comparator output node COMP2 of the comparator U2 flips at the comparator flip timestamp t2, the control unit obtains the event time delay Δt=t2-t0 and collects the integration voltage peak value VC_peak before the down tube reset switch MOS tube M2 discharges; the control unit calculates the residual error r=VC_peak-f(Δt) and compares it with the residual error threshold ε, outputs the valid measurement flag when |the residual error r|≤ε, and obtains the gate threshold voltage Vth according to the conversion relationship g(VC_peak), outputs the abnormal type 1 flag when the residual error r<-ε, and outputs the abnormal type 2 flag when the residual error r>+ε.

[0012] In a preferred embodiment, a voltage follower buffer or a sample and hold circuit is arranged between the down tube integration node NINT2 and the sampling channel of the control unit, so that the integration voltage peak value VC_peak is maintained for a time not less than τ_hold after the down tube comparator output node COMP2 flips.

[0013] In a preferred embodiment, when the residual error r<-ε and the abnormal type 1 flag is output, the control unit confirms the second logic level holding time of the down tube comparator output node COMP2, and if the holding time is insufficient for a preset threshold, the abnormal type 1 flag is maintained and the gate threshold voltage Vth of this time is discarded.

[0014] In a preferred embodiment, when the residual error r>+ε and the abnormal type 2 flag is output, the control unit collects the potential of the down tube integration node NINT2 during the idle period and judges whether the integration voltage VC2 returns to a preset near-zero range, as a self-checking basis for the reset state of the down tube reset switch MOS tube M2.

[0015] In a preferred embodiment, only when the valid measurement flag is output, the control unit adds the gate threshold voltage Vth to the threshold sequence and compares it with the baseline Vth_base to obtain the drift amount, and outputs the aging trend or failure conclusion according to the preset drift rule.

[0016] The technical effects and advantages of the silicon carbide device state detection circuit based on threshold voltage change are as follows:

[0017] The application converts the key switching event of the power device opening process into a trigger signal that can be captured on the low-voltage side in the detection link, and uses an integral voltage as a reading carrier, so that the extraction of threshold-related information is completed by the measurement window defined by the trigger event, instead of relying on the selection of a certain waveform feature point by a person. Since the trigger, integration and reset form fixed timing constraints in the circuit connection, each detection starts from a consistent initial state and terminates the integration and completes the reset when the trigger event occurs, thereby reducing the influence of parasitic parameter changes, driving condition fluctuations, bus voltage fluctuations and electromagnetic interference on the stability of the reading, improving the repeatability and anti-interference of online detection, and reducing the cumulative error caused by residual charge or baseline drift, suitable for continuous monitoring in long-term operation scenarios.

[0018] The application performs consistency discrimination based on two different detection variables obtained in the same opening process, thereby providing credibility screening capability for online measurement. When the trigger link is affected by glitches, dv / dt coupling or parameter drift to produce false triggering, early / late triggering, or when the integration / reset link has incomplete reset, integration bias and other abnormalities, the control logic can identify and reject the untrusted results into the threshold drift statistics, avoiding the misjudgment of the measurement link abnormality as device aging; and different diagnostic indications can be output according to the abnormal direction, facilitating the differentiation between trigger-type abnormalities and integration / reset-type abnormalities, improving the maintenance positioning efficiency, reducing the false alarm and missed detection risk, and enhancing the engineering usability and reliability. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 The application is a silicon carbide device state detection circuit principle diagram based on threshold voltage change.

[0020] Figure 2 The application is a timing diagram of the detection circuit. DETAILED DESCRIPTION

[0021] In order to facilitate explanation and uniform reference, the key nodes in this embodiment are named as follows:

[0022] NDC+: Positive DC bus node; NDC-: Negative DC bus node; NSW: Midpoint node of half-bridge; NG1: Gate node of upper MOSFET S1; NG2: Gate node of lower MOSFET S2; NS1: Source node of upper MOSFET S1; NS2: Source node of lower MOSFET S2; VGS1: Gate-source voltage of upper MOSFET; VGS2: Gate-source voltage of lower MOSFET; NINT1: Integrator node of upper MOSFET; NINT2: Integrator node of lower MOSFET; VC1: Integrator voltage of upper MOSFET; VC2: Integrator voltage of lower MOSFET; M1: Reset switch MOSFET of upper MOSFET; M2: Reset switch MOSFET of lower MOSFET; NSEN1: Drain-source event detection node of upper MOSFET; NSEN2: Drain-source event detection node of lower MOSFET; VREF: Comparator reference voltage node; COMP1: Comparator output node of upper MOSFET; COMP2: Comparator output node of lower MOSFET; BUF1: Buffer output node of upper MOSFET; BUF2: Buffer output node of lower MOSFET; UDC: Bus voltage source; C3: Bus voltage source. Capacitors; S1: Upper transistor; S2: Lower transistor; V1: Upper transistor drive source; V2: Lower transistor drive source; R2: Upper transistor gate resistor; R4: Lower transistor gate resistor; A1: Upper transistor transconductance op-amp; A2: Lower transistor transconductance op-amp; C1: Upper transistor integrating capacitor; C2: Lower transistor integrating capacitor; D3: Upper transistor high-voltage diode; D6: Lower transistor high-voltage diode; R1: Upper transistor current-limiting resistor; R3: Lower transistor current-limiting resistor; I1: Upper transistor micro-current source; I2: Lower transistor micro-current source; D1 D1: Positive terminal of upper MOSFET clamping diode; D2: Negative terminal of upper MOSFET clamping diode; D4: Positive terminal of lower MOSFET clamping diode; D5: Negative terminal of lower MOSFET clamping diode; U1: Upper MOSFET comparator; U2: Lower MOSFET comparator; VDD: Low-voltage supply node; VCLAMP+: Upper clamping limit potential node; VCLAMP-: Lower clamping limit potential node; t0: Turn-on command timestamp; t2: Comparator toggle timestamp; VC_peak: Peak value of integrated voltage; Δt: Event delay.

[0023] Furthermore, specifically including:

[0024] (a) High-voltage side power circuit node:

[0025] NDC+: Positive terminal of DC bus, connected to the positive terminal of DC bus voltage source UDC, the positive terminal of bus capacitor C3, and the drain of upper transistor S1.

[0026] NDC-: Negative terminal of the DC bus, connected to the negative terminal of the DC bus voltage source UDC, the negative terminal of the bus capacitor C3, and the source of the lower transistor S2. This terminal also serves as the low-voltage reference ground.

[0027] NSW: Midpoint node of the half-bridge, connecting the source of the upper transistor S1 and the drain of the lower transistor S2. The voltage at this node is close to NDC+ when it is off, close to NDC- when the lower transistor S2 is on, and close to NDC+ when the upper transistor S1 is on.

[0028] (II) Low voltage side but strongly coupled to the gate drive and sampling nodes of the power devices:

[0029] NG1: Upper transistor S1 gate node, connecting the driving source V1 through gate resistor R2 to the S1 gate.

[0030] NG2: Lower transistor S2 gate node, connecting the driving source V2 through gate resistor R4 to the S2 gate.

[0031] NS1: Upper transistor S1 source node, same node or equivalent connection with NSW.

[0032] NS2: Lower transistor S2 source node, same node or equivalent connection with NDC-.

[0033] VGS1: Upper transistor gate-source voltage, equal to the voltage of NG1 relative to NS1.

[0034] VGS2: Lower transistor gate-source voltage, equal to the voltage of NG2 relative to NS2.

[0035] (III) Integration and reset nodes:

[0036] NINT1: Upper transistor integration node, connecting the output of transconductance op-amp A1 and the first end of integration capacitor C1.

[0037] NINT2: Lower transistor integration node, connecting the output of transconductance op-amp A2 and the first end of integration capacitor C2.

[0038] VC1: Upper transistor integration voltage, equal to the voltage of NINT1 relative to NS1 or equivalent reference.

[0039] VC2: Lower transistor integration voltage, equal to the voltage of NINT2 relative to NDC- or equivalent reference.

[0040] M1 / M2: Reset switch MOSFET, connected in parallel between NINT1-reference and NINT2-reference respectively, for fast discharge reset.

[0041] (IV) Drain-source voltage detection nodes:

[0042] NSEN1: Upper transistor drain-source event detection node, connected to the detection point on the power side through high-voltage diode D3 and current-limiting resistor R1, and pulled up by a small current source I1, clamped by diode DCL1±.

[0043] NSEN2: Lower transistor drain-source event detection node, connected to the power side NSW through high-voltage diode D6 and current-limiting resistor R3, and pulled up by a small current source I2, clamped by diode DCL2±.

[0044] VREF: Comparator reference voltage node, for example 5V.

[0045] COMP1 / COMP2: Comparator output nodes, the comparator outputs the number after comparing NSENx with VREF.

[0046] BUF1 / BUF2: Buffer output nodes, used to drive the gate of the reset switch MOSFET.

[0047] Example 1: The technical solution of this embodiment of the invention will be clearly and completely described below with reference to the accompanying drawings. Example 1 mainly uses the lower transistor S2 in the half-bridge structure as the device under test for detailed description. The upper transistor S1 channel can be reserved for symmetry or the detection function can be disabled. Obviously, the described embodiments are only some embodiments of this invention, and not all embodiments.

[0048] This invention provides a silicon carbide device state detection circuit based on threshold voltage variation, aiming to realize online threshold voltage (Vth) extraction, aging assessment, and anomaly diagnosis of SiC power devices. This embodiment uses a SiC MOSFET half-bridge structure as an example, but the invention is not limited to this and can also be applied to other types of power devices or topologies.

[0049] like Figure 1 As shown, the bus voltage source UDC is connected between NDC+ and NDC-; the bus capacitor C3 is connected in parallel between NDC+ and NDC- to provide DC bus voltage support and absorb transient switching energy. The drain of the upper transistor S1 is connected to NDC+, and the source is connected to NSW; the drain of the lower transistor S2 is connected to NSW, and the source is connected to NDC-.

[0050] In this embodiment, no external load is connected in detection mode, so that the voltage transition of the NSW node is mainly determined by the device output capacitance, bus capacitance, and parasitic parameters. This makes the initial conduction current controllable and small, enhancing the stability of the relationship between the Miller plateau voltage and the threshold voltage. During the detection cycle, the DC bus voltage UDC should be kept within a preset range, and the ambient temperature should be within a preset range or the temperature should be sampled for calibration.

[0051] The upper-side drive source V1 is connected to NG1 via gate resistor R2; the lower-side drive source V2 is connected to NG2 via gate resistor R4. Gate resistors R2 / R4 are used to limit the gate charging and discharging current, set the VGS rising slope, and suppress ringing. During turn-off, the drive source outputs a turn-off voltage to ensure reliable device turn-off; during turn-on, the drive source outputs a turn-on voltage to drive the device into the turn-on process.

[0052] As an alternative example, the shutdown voltage can be -5V to 0V, and the turn-on voltage can be 10V to 20V.

[0053] This invention employs an alternating conduction strategy: during any detection cycle, only the device under test (DUT) is turned on, while the other device remains off, to avoid shoot-through between the upper and lower transistors and interference with the NSW node waveform. The values ​​of the gate resistors R2 / R4 determine the rise slope of VGS, which in turn affects the calibrability of the event delay Δt and the integral voltage VC_peak, forming the basis for subsequent gating logic.

[0054] In one optional example, let's take the S2 channel:

[0055] The transconductance operational amplifier A2 samples VGS2 at its input, meaning its input is connected to NG2 and NS2 (or with NS2 as a reference), so that A2 obtains a VGS2 that increases as it is turned on. The output of A2 is connected to NINT2; the integrating capacitor C2 is connected between NINT2 and NDC-, so that the current output by A2 is integrated with respect to C2, forming an integrated voltage VC2 at NINT2.

[0056] During the period from t0 to t2, VGS2 gradually increases from 0, the output current of A2 changes with VGS2 and accumulates on C2, and VC2 shows a monotonically increasing trend; therefore, the pre-discharge peak value of VC2, VC2_peak, can be used as a characterizing quantity of this turn-on process. In this invention, VC2 is not directly sampled from VGS, but rather the evolution of VGS is integrated within a window. This method has stronger resistance to transient disturbances and is more suitable for consistency verification.

[0057] For the detection of the upper transistor's S1 channel, since NS1 and NSW share the same node, their source potential exhibits a high common-mode swing during switching. Possible implementation methods include:

[0058] 1. Threshold extraction is only performed on the lower S2 channel, while the upper S1 channel is used for normal half-bridge complementary drive and the detection function is not enabled.

[0059] 2. The upper tube S1 detection channel uses isolated power supply and isolated signal transmission (such as isolation amplifier or digital isolator) to make low voltage devices such as A1 and U1 work in a floating ground reference system, thereby achieving symmetrical detection with the lower tube S2.

[0060] In an optional example, let's still use the S2 channel:

[0061] The cathode of the high-voltage diode D6 is connected to NSW, and the anode is connected to one end of the current-limiting resistor R3; the other end of R3 is connected to the drain-source event detection node NSEN2. This connection direction ensures that D6 reverse-biasedly blocks the high voltage when NSW is under high voltage, and forward-biasedly provides a discharge path when NSW drops rapidly.

[0062] One end of the micro-current source I2 is connected to VDD, and the other end is connected to NSEN2. It is used to provide a stable micro-current to NSEN2 when D6 is reverse cut off, thus pulling NSEN2 up. VDD is a low-voltage power supply node, such as 5V or 12V, used to power the comparator, buffer, and micro-current source.

[0063] Clamping diodes D4 and D5 are connected between NSEN2 and VCLAMP+ and VCLAMP-, respectively, limiting the voltage of NSEN2 to the range of VCLAMP- to VCLAMP+, thereby suppressing parasitic coupling spikes and protecting the comparator input. VCLAMP+ and VCLAMP- are the upper and lower clamping potential nodes, such as 10V and 0V, which can be generated by a reference source or a Zener diode.

[0064] The positive input of comparator U2 is connected to NSEN2, and the negative input is connected to the reference voltage VREF. When NSEN2 is higher than VREF, COMP2 outputs the first logic level; when NSEN2 is lower than VREF, COMP2 toggles and outputs the second logic level, forming a digital trigger for the Vds drop event.

[0065] In the off state, NSW is approximately equal to NDC+, and D6 is reverse-biased and cut off. I2 pulls NSEN2 up and clamps it to near VCLAMP+, for example, ≈10V. Therefore, NSEN2 is higher than VREF, for example, 5V, and COMP2 maintains the first logic level. When S2 enters the Miller plateau and conducts, causing NSW to drop rapidly to approximately equal to NDC-, D6 conducts forward. NSEN2 discharges to NSW through R3 and D6, and is quickly pulled low to below VREF, for example, ≈1V. COMP2 then toggles to the second logic level.

[0066] This link converts the high-voltage side Vds sudden drop event into a digital signal of low-voltage side COMP flipping, and through the design of pulling up +VCLAMP- to VCLAMP+ with a small current source, it achieves strong anti-coupling capability and is the only source for subsequent Δt event capture.

[0067] In an optional example, the input of buffer BUF2 is connected to COMP2, and the output is connected to the gate of reset switch M2; the drain and source of M2 are connected in parallel between NINT2 and NDC-.

[0068] The buffer BUF2 can be an inverting or non-inverting driver to achieve the following: when COMP2 is at the first logic level, BUF2 drives M2 to remain off, and NINT2 is in the integration state; when COMP2 flips to the second logic level, BUF2 drives M2 to switch to conduction, so that NINT2 is quickly pulled to NDC-, the integration capacitor C2 discharges rapidly, and the integration voltage VC2 is reset to 0V.

[0069] Therefore, the flip of COMP2 accomplishes two things at the same time: first, it outputs the trigger event to the outside world; second, it cuts off the integration window internally and resets it, providing consistent initial conditions for the next cycle.

[0070] Using S2 as the device under test, combined with Figure 2 The timing diagram shown illustrates the detection process as follows:

[0071] 1. Preset stage (before t0): The driver source V2 outputs the turn-off voltage, and S2 is in the off state; the integral voltage VC2 is approximately 0; the drain-source event detection node NSEN2 is pulled up and clamped to a high level by the small current source I2, the comparator COMP2 maintains the first logic level, and the reset switch M2 is turned off.

[0072] 2. Integration phase (t0 to t2): The control unit or drive source applies the turn-on voltage at time t0, and the gate-source voltage VGS2 begins to rise; the transconductance operational amplifier A2 integrates the integrating capacitor C2, and the integrating voltage VC2 rises monotonically.

[0073] 3. Trigger and Reset (t2): When VGS2 enters the Miller plateau and causes the NSW voltage to drop rapidly, the drain-source event detection node NSEN2 is quickly pulled low and comparator COMP2 flips; this flip signal drives the reset switch M2 to turn on through the buffer BUF2, and the integrated voltage VC2 is quickly discharged and reset.

[0074] 4. Reading definition: The peak value of the integrated voltage VC2 before M2 is turned on is defined as VC2_peak. If the channels are not distinguished, it is collectively referred to as VC_peak, which is used as the reading for this detection. The time interval t2 relative to t0 is defined as Δt, which is used as the event delay reading for this detection.

[0075] Example 2: This invention introduces a software control method strongly associated with the hardware structure: taking two input variables (Δt and VC_peak) as inputs, it performs a consistency judgment on the measurement reliability and outputs diagnostic indicators for two types of abnormal directions. Specifically, as follows:

[0076] (a) Collection of two input variables:

[0077] 1. Δt (event delay): The control unit records timestamp t0 when issuing the power-on command or power-on pulse; records timestamp t2 when capturing the toggling edge of comparator COMP2, and calculates Δt = t2 - t0.

[0078] 2. VC_peak (Integral Peak Value): The control unit synchronously samples the voltage value of NINT2 when capturing the topping edge of comparator COMP2, obtaining VC_peak. To ensure that sampling is completed before M2 discharges, a voltage follower buffer or sample-and-hold circuit is set between NINT2 and the sampling terminal, so that the holding time of VC_peak after COMP2 topping is not less than τ_hold, for example, several microseconds to tens of microseconds, to meet the ADC sampling setup time. Specific implementation methods can include:

[0079] ADC sampling is triggered immediately upon the COMP2 toggle interrupt entry;

[0080] NINT2 is buffered with high impedance before sampling;

[0081] A sample-and-hold circuit is used to latch VC_peak.

[0082] None of the above methods change the hardware closed-loop mechanism of COMP flip-driven MRESET discharge.

[0083] (ii) Consistency function f and residual r:

[0084] The control unit pre-stores a consistency function f(Δt) to describe the correspondence between VC_peak and Δt under normal conditions. This function f can be obtained through calibration and implemented using a piecewise linear list. The control unit calculates:

[0085] VC_exp=f(Δt); r=VC_peak-VC_exp;

[0086] The residual r is signed and used for subsequent subdivision of anomaly types.

[0087] (III) Gating and anomaly segmentation output:

[0088] The control unit sets the residual threshold ε and outputs three types of results:

[0089] 1. Output A: Accepted:

[0090] When |r|≤ε, the measurement is deemed reliable, a valid measurement flag is output, and VC_peak is converted into threshold voltage Vth through the conversion relationship g(VC), which is then used for subsequent drift statistics and aging determination.

[0091] Explanation: |r|≤ε means that the Δt given by the trigger chain (NSEN2 / COMP2) is consistent with the VC_peak given by the integral chain (A2 / C2), which is consistent with the homology of the same opening process under this topology.

[0092] 2. Output B: Anomaly type 1, i.e., suspected false triggering / premature triggering;

[0093] When r < −ε, output an anomaly type 1 flag, indicating that VC_peak is significantly smaller than the expected value that Δt should correspond to, that is, the triggering event is relatively early or there is a glitch flip.

[0094] When COMP2 flips, the control unit briefly confirms the holding state of COMP2 without changing the hardware reset link. If the holding time of the second logic level of COMP2 is less than the preset threshold, it is still handled as an exception type 1.

[0095] This is because the NSEN2 end may be affected by the parasitic coupling of high dv / dt of NSW, which may produce transient spikes / valleys. Even with VCLAMP- to VCLAMP+ clamping, a short-term transient that crosses VREF may still occur at the edge, causing COMP2 to flip prematurely.

[0096] The reverse recovery / parasitic capacitance coupling of the high-voltage diode D6 causes a short-term undershoot in NSEN2;

[0097] The drift of parameters in the current-limiting resistor R3, the micro-current source I2, or the clamping branch can cause abnormalities in the pull-up preset or discharge path of NSEN2, resulting in the comparator trigger point being advanced.

[0098] The common feature of the above anomalies is that Δt is shortened, but the integral chain does not accumulate accordingly (VC_peak is too small), so r is negative and exceeds the limit.

[0099] Therefore, this measurement is discarded at this point, the Vth sequence is not updated, and the measurement frequency can be reduced or the idle preset time can be extended before the next measurement.

[0100] 3. Output C: Anomaly type 2, i.e., suspected integration / reset chain anomaly or late triggering:

[0101] When r>+ε, output the exception type 2 flag, indicating that VC_peak is significantly greater than the expected value that Δt should correspond to, that is, the integral accumulation is too large or there is an anomaly in the reset / integral chain, or the triggering event is too late.

[0102] This is because the reset branch M2 has a leakage conduction / insufficient drive, resulting in an incomplete reset. In the next cycle, the initial VC2 is not 0, causing VC_peak to be too large.

[0103] The transconductance operational amplifier A2 bias drift or saturation causes abnormal integration current and excessive VC growth rate.

[0104] The failure or hysteresis of the comparator COMP2 trigger chain causes t2 to be delayed (triggering is too late), which in turn prolongs the integration window and makes VC_peak larger.

[0105] An abnormal conduction path of the current-limiting resistor R3 / high-voltage diode D6 causes NSEN2 to be pulled low more slowly, delaying the comparator flip-off.

[0106] The common feature of the above anomalies is that the cumulative result of the integral chain is too large or the window is extended, but the Δt given by the event chain is inconsistent with its expected relationship, so r is positive and exceeds the limit.

[0107] Therefore, at this point, the measurement is discarded, the Vth sequence is not updated, and a reset self-test or hardware anomaly can be performed, such as sampling NINT2 during the idle period to see if it returns to near 0.

[0108] Furthermore, to ensure the feasibility of this invention, the following calibrations and parameter settings are required:

[0109] 1. Calibrating the consistency function f(Δt):

[0110] Under device health conditions or reference device conditions, the detection is repeatedly performed with fixed turn-on voltage, fixed gate resistance R4, fixed DC bus voltage UDC, and fixed ambient temperature to collect multiple sets of (Δt, VC_peak) samples. Statistical analysis is performed on these samples to obtain the consistency function f(Δt). The function f can be implemented using a piecewise linear lookup table: divide Δt into several intervals, store the endpoints (Δt_i, VC_i) for each interval, and then calculate VC_exp through interpolation.

[0111] 2. Calibration of the threshold conversion relation g(VC):

[0112] A mapping relationship g(VC) between VC_peak and Vth is established using external standard threshold measurements or devices with known Vth. This mapping relationship can also be implemented using a lookup table or a piecewise linear function. Multiple mapping tables can be established for temperature segments, or a temperature compensation coefficient can be introduced to accommodate device characteristics at different operating temperatures.

[0113] 3. Setting the residual threshold ε:

[0114] By statistically analyzing the residual r distribution of normal samples, a threshold ε that can cover the normal fluctuation range is selected, such that when |r|≤ε, the measurement is likely to be normal; when |r|>ε, the measurement is likely to be abnormal, thus achieving robust gating.

[0115] Therefore, when the control unit outputs A, it indicates that the Vth measurement result is reliable. The control unit adds this Vth measurement value to the Vth sequence and compares it with the baseline Vth_base to calculate the relative drift. Based on preset drift rules, such as if the drift exceeds 20%, it outputs an aging trend or failure conclusion, thereby realizing online aging evaluation of SiC devices.

[0116] When the control unit outputs B or C, it indicates that the measurement is unreliable and the Vth sequence is not updated. Simultaneously, the control unit counts the anomaly types for subsequent fault location or maintenance strategies. For example, an increase in the proportion of anomaly type 1 may indicate a coupling problem in the detection chain; an increase in the proportion of anomaly type 2 may indicate a lag problem in the integration / reset chain or trigger chain. This granular anomaly diagnosis helps engineers quickly identify and resolve potential problems in the system.

[0117] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

[0118] In conclusion, the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A state detection circuit for a silicon carbide device based on threshold voltage variation, characterized in that, include: A DC bus voltage source UDC and bus capacitor C3 are connected in parallel between the positive node NDC+ and the negative node NDC- of the DC bus. The drain of the upper transistor S1 is connected to NDC+, and the source is connected to the midpoint node NSW of the half-bridge. The drain of the lower transistor S2 is connected to NSW, and the source is connected to NDC-. The lower transistor drive source V2 is connected to the gate node NG2 of the lower transistor S2 via the gate resistor R4. The input of the transconductance operational amplifier OTA2 is connected to NG2 and the source node NS2 of the lower transistor S2. The output of the transconductance operational amplifier OTA2 is connected to the integrating node NINT2 of the lower transistor. The integrating capacitor C2 of the lower transistor is connected between NINT2 and NDC- to form the integrating voltage VC2. The high-voltage diode D6 and the current-limiting resistor R3 of the lower transistor are connected in series between NSW and the drain-source event detection node NSEN2 of the lower transistor. The small current source I2 is connected between VDD and NSEN2. The clamping diodes D4 and D5 are connected to NSEN2 and... Between VCLAMP+ and VCLAMP-; the input of comparator U2 is connected to NSEN2 and the comparator reference voltage node VREF, and its output is the output node COMP2 of the lower MOSFET comparator; the input of buffer BUF2 is connected to COMP2, and its output is connected to the gate of the lower MOSFET reset switch M2. M2 is connected in parallel between NINT2 and NDC-; the control unit is electrically connected to V2, COMP2 and NINT2 respectively, and is used to record the turn-on command timestamp t0 and the comparator toggle timestamp t2 to obtain the event delay Δt. At t2, the peak value of the integral voltage VC_peak is collected, the residual r=VC_peak-f(Δt) is calculated, and when |residual r|≤ε, a valid measurement flag is output and the gate threshold voltage Vth is obtained according to the conversion relationship g(VC_peak). When the residual r<-ε, an abnormality type 1 flag is output, and when the residual r>+ε, an abnormality type 2 flag is output.

2. The silicon carbide device state detection circuit based on threshold voltage change according to claim 1, characterized in that: The source node NS2 of the lower tube S2 and the negative node NDC- of the DC bus are the same node or equivalently connected.

3. The silicon carbide device state detection circuit based on threshold voltage change according to claim 1, characterized in that: The cathode of the high-voltage diode D6 is connected to the midpoint node NSW of the half-bridge, and the anode is connected to the drain-source event detection node NSEN2 of the lower diode via the current-limiting resistor R3.

4. The silicon carbide device state detection circuit based on threshold voltage change according to claim 1, Its characteristics are: The buffer BUF2 is an inverting or non-inverting buffer. When the output node COMP2 of the lower transistor comparator is at the first logic level, the lower transistor reset switch MOS transistor M2 is turned off. When the output node COMP2 of the lower transistor comparator flips to the second logic level, the lower transistor reset switch MOS transistor M2 is turned on to discharge the lower transistor integrating capacitor C2 and reset the integrating voltage VC2.

5. The silicon carbide device state detection circuit based on threshold voltage change according to claim 1, characterized in that: The consistency function f(Δt) is stored in the control unit in a piecewise linear lookup table manner, and the conversion relationship g(VC_peak) is stored in the control unit in a piecewise linear lookup table manner and is segmented according to the ambient temperature or temperature compensation.

6. The silicon carbide device state detection circuit based on threshold voltage change according to claim 1, characterized in that: The control unit controls the lower transistor drive source V2 to apply an on-state voltage to the gate node NG2 of the lower transistor S2 through the gate resistor R4 at the turn-on command timestamp t0, causing the transconductance operational amplifier OTA2 to integrate the lower transistor integrating capacitor C2 and causing the integrating voltage VC2 to rise. When the lower transistor comparator output node COMP2 of comparator U2 flips at the comparator toggling timestamp t2, the control unit obtains the event delay Δt=t2-t0 and collects the peak value of the integrating voltage VC_peak before the lower transistor reset switch MOS transistor M2 discharges. The control unit calculates the residual r=VC_peak-f(Δt) and compares it with the residual threshold ε. When |the residual r|≤ε, it outputs a valid measurement flag and obtains the gate threshold voltage Vth according to the conversion relationship g(VC_peak). When the residual r<-ε, it outputs an abnormality type 1 flag, and when the residual r>+ε, it outputs an abnormality type 2 flag.

7. The silicon carbide device state detection circuit based on threshold voltage change according to claim 6, characterized in that: A voltage follower buffer or sample-and-hold circuit is set between the integrator node NINT2 of the lower transistor and the sampling channel of the control unit so that the peak value of the integrated voltage VC_peak is held for no less than τ_hold after the output node COMP2 of the lower transistor comparator flips.

8. The silicon carbide device state detection circuit based on threshold voltage change according to claim 6, characterized in that: When the residual r < −ε and an abnormality type 1 flag is output, the control unit confirms the second logic level holding time of the lower comparator output node COMP2. If the holding time is less than the preset threshold, the abnormality type 1 flag is maintained and the gate threshold voltage Vth is discarded.

9. The silicon carbide device state detection circuit based on threshold voltage change according to claim 6, characterized in that: When the residual r > + ε and an abnormality type 2 flag is output, the control unit collects the potential of the lower transistor integral node NINT2 during the idle period and determines whether the integral voltage VC2 returns to the preset near-zero range, as a self-test basis for the reset state of the lower transistor reset switch MOS transistor M2.

10. The silicon carbide device state detection circuit based on threshold voltage change according to claim 6, characterized in that: Only when a valid measurement flag is output, the control unit adds the gate threshold voltage Vth to the threshold sequence and compares it with the baseline Vth_base to obtain the drift amount, and outputs the aging trend or failure conclusion according to the preset drift rule.

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