Clock burr detection circuit and detection method

Abstract

The invention discloses a clock burr detection circuit and detection method, and belongs to the technical field of integrated circuits. The clock burr detection circuit comprises a rising edge sampling module and a falling edge sampling module; the sampling output ends of the rising edge sampling module and the falling edge sampling module are connected with the level period calculation module, the output end of the level period calculation module is connected with the clock burr detection module, and the output end of the clock burr detection module is connected with the automatic judgment unit; the invention further discloses a clock burr detection method. According to the clock burr detection circuit and the detection method, the detected clock is used for sampling the edge of the detected clock and obtaining the clock period without counting, so that missing detection and error detection of clock burrs are avoided.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology and relates to clock signal calibration, specifically to a clock glitch detection circuit and detection method. Background Technology

[0002] Clock glitches in chip development can lead to instability in chip circuits and even logic failures, causing the chip to malfunction. Therefore, avoiding clock glitches is crucial during chip development. However, as chip development scales up and clock circuits become more complex, the requirements for the efficiency and reliability of clock glitch detection become even higher.

[0003] In existing technologies, a common method is to simulate clock test cases and then manually examine the waveform of the clock simulation results to analyze whether clock glitches are generated during clock configuration. This method is not only inefficient but also introduces the risk of detection errors, making it unsuitable for large-scale integrated circuit verification. Another method is to build a clock glitch detection circuit using the System Verilog hardware programming language. This involves introducing a high-frequency sampling clock externally to count the adjacent edges of the clock to be tested, and then comparing the count value with the frequency ratio of the high-frequency sampling clock and the detection clock at the rising or falling edge of the detection clock to detect clock glitches. While this method can automate clock glitch detection, it requires an externally introduced high-frequency clock proportional to the detection clock, and the implementation circuit is relatively complex. Furthermore, glitches cannot be detected if the period of the clock glitch is shorter than the period of the high-frequency sampling clock.

[0004] In summary, traditional clock glitch detection technologies cannot meet the requirements of high reliability, high efficiency, and simple and rapid glitch location in automated detection circuits. Summary of the Invention

[0005] To overcome the technical defects of the existing technology, this invention discloses a clock glitch detection circuit and detection method.

[0006] The clock glitch detection circuit of the present invention includes a rising edge sampling module and a falling edge sampling module; the sampling output terminals of the rising edge sampling module and the falling edge sampling module are connected to a level period calculation module, the output terminal of the level period calculation module is connected to the clock glitch detection module, and the output terminal of the clock glitch detection module is connected to an automatic judgment unit. The rising edge sampling module and falling edge sampling module are used to sample and output the occurrence time of the rising edge and falling edge; the level period calculation module is used to calculate the difference between the occurrence time of adjacent rising edges and falling edges; the clock glitch detection module determines whether it is a glitch based on the difference; and the automatic judgment unit outputs glitch information.

[0007] Preferably, the rising edge sampling module and the falling edge sampling module are implemented using System Verilog language, and the system function $realtime provided by System Verilog language is used to capture the time of the rising edge and the falling edge.

[0008] Preferably, the automatic judgment unit is implemented by the SVA assertion function of System Verilog.

[0009] A clock glitch detection method, based on the detection circuit, includes the following steps: Step 1. Detect the rising edge and falling edge times of the clock; Step 2. Subtract the adjacent rising edge time points from the falling edge time points to obtain the duration period value TH and save it; Step 3. Clock glitch detection, specifically: Step 31. Set the stable quantity threshold D1 and the stable difference threshold D2, and start detection from the second clock cycle; Step 32. Compare the current stable level period with the previous stable level period value. If the difference between the two is less than the stability difference threshold D2, the clock signal is considered to be output stably. When the number of consecutive stable clock signals reaches the stability number threshold D1, calculate the average value MA of these consecutive D1 stable level periods, and use it as the current stable level period value MS. In step 32, if the difference between adjacent stable level periods is greater than the stable difference threshold D2 before reaching the stable quantity threshold D1, the counting restarts until the number of continuously stable clock signals reaches the stable quantity threshold D1. Step 33. After reaching the stable quantity threshold D1 and the stable level period of continuous operation is greater than the pre-exemption threshold D3, the subsequent stable level periods are continuously compared. If the difference between the subsequent stable level period value and the current stable level period value MS is found to be greater than the stable difference threshold D2, then proceed to step 34; otherwise, continue with step 33. Step 34. For stable level period T(N) where the difference between the stable level period value and the current stable level period value MS is greater than the stable difference threshold D2, continue to detect subsequent stable level periods of stable level period T(N); Step 341. If the difference between the subsequent stable level period value and the stable level period value of the stable level period T(N) is greater than the stable difference threshold D2, then the stable level period T(N) is determined to be a glitch; Step 342. If the difference between the subsequent stable level period value and the stable level period value of the stable level period T(N) is less than the stable difference threshold D2, the clock signal is considered to be output stably. When the number of consecutive stable clock signals reaches the stable number threshold D1, the average value MA of these consecutive D1 stable level periods is calculated as the updated stable level period value MS. In step 342, if after the clock signal is determined to be output stably, the number of continuously output clock signals does not reach the stable number threshold D1 and the difference is greater than the stable difference threshold D2 again, then the stable level period T(N) and the subsequent stable level period before reaching the stable number threshold D1 are still regarded as glitches. After detecting a glitch or updating the stable level period value MS, return to step 33 to continue detection; Set the stable voltage level to high and low respectively, and repeat step 3; Step 4. Output burr information.

[0010] Preferably, step 31 further includes a pre-exemption threshold D3, during which no glitch detection is performed within the initial D3 stable level cycles.

[0011] The clock glitch detection circuit and method described in this invention use the clock being detected to sample its own edges without counting to obtain the clock period, thus avoiding missed or false detections of clock glitch and simplifying the clock detection circuit. This invention uses the SVA assertion method to automatically detect clock glitch and output glitch information, improving detection efficiency and facilitating the location of the time point and cause of clock glitch occurrence. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of a specific embodiment of the clock glitch detection circuit described in this invention; Figure 2 This is a schematic diagram of a specific embodiment of the clock glitch detection method of the present invention; Figure 3 This is a schematic diagram of a specific embodiment of step 3 of the present invention. Detailed Implementation

[0013] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0014] The clock glitch detection circuit of the present invention includes a rising edge sampling module and a falling edge sampling module; the sampling output terminals of the rising edge sampling module and the falling edge sampling module are connected to a level period calculation module, the output terminal of the level period calculation module is connected to the clock glitch detection module, and the output terminal of the clock glitch detection module is connected to an automatic judgment unit.

[0015] The rising edge sampling module uses the clock being detected itself to sample the rising edge of the clock being detected, thereby obtaining the rising edge time point of the clock being detected. There is no need to introduce a high-frequency clock to sample the rising edge of the detection clock, which ensures that every rising edge of the detection clock is sampled and that no glitches of the clock being detected are missed.

[0016] The falling edge sampling module uses the clock being detected itself to sample the falling edge of the clock being detected, thereby obtaining the falling edge time point of the clock being detected. There is no need to introduce a high-frequency clock to sample the falling edge of the clock being detected, ensuring that every falling edge of the clock being detected is sampled and that no glitches of the clock being detected are missed.

[0017] The rising edge sampling module and falling edge sampling module are implemented using System Verilog. The built-in System Verilog function `$realtime` captures and saves the time point of each rising and falling edge. Both normal clock signals and clock glitches generate rising and falling edges simultaneously. By capturing each rising and falling edge, every high-low level change of the clock signal can be detected.

[0018] The level period calculation module performs a difference calculation on the rising edge time point TR of the detected clock sampled by the adjacent rising edge sampling module and the falling edge time point TF of the detected clock sampled by the falling edge sampling module to obtain the duration of each stable level of the sampled clock, that is, the duration of the high level or low level; if the TR time point comes first and the TF time point comes later, the difference obtained is the duration of the low level, and if the TF time point comes first and the TR time point comes later, the difference obtained is the duration of the high level.

[0019] The level period calculation module is implemented using System Verilog software. Its function is to calculate the difference between the time point data output by the rising edge sampling module and the falling edge sampling module. It does not require the use of the counter value to estimate the high level period of the detection clock, thus avoiding the generation of high level period errors and simplifying the clock glitch detection circuit.

[0020] The clock glitch detection module is triggered by the clock being detected. When the rising or falling edge of the clock being detected arrives, it compares and analyzes the adjacent stable level cycles of the calculation result of the level period calculation module, and outputs the detection result to ensure the reliability of the detection.

[0021] The SVA assertion auto-judgment unit is triggered by the detected clock. When the rising or falling edge of the detected clock arrives, it automatically judges the analysis results output by the clock glitch detection module, and reports and outputs errors for periods identified as glitch, ensuring detection efficiency and rapid location of glitch problems. Both the clock glitch detection module and the SVA assertion auto-judgment unit are implemented using System Verilog.

[0022] Specific testing methods include: Step 1. Detect the rising edge and falling edge times of the clock, as shown below: When the rising and falling edges of the clock are detected, the current time can be obtained and saved using the System Verilog system function $realtime.

[0023] Step 2. Detect the duration of the clock level, which is manifested as follows: The duration of the stable level is obtained by subtracting the rising edge time from the falling edge time of the acquired detection clock and then saving it.

[0024] The level period calculation module performs a difference calculation on the rising edge time point TR of the detected clock sampled by the adjacent rising edge sampling module and the falling edge time point TF of the detected clock sampled by the falling edge sampling module to obtain the duration of each stable level of the sampled clock, that is, the duration of the high level or low level; if the TR time point comes first and the TF time point comes later, the difference obtained is the duration of the low level, and if the TF time point comes first and the TR time point comes later, the difference obtained is the duration of the high level.

[0025] The following explanation will use the duration of a stable level as an example of the duration of a high level.

[0026] Step 3. Clock glitch detection, manifested as: The calculated high-level period value is stored in a multi-level clock register under the detection clock to compare and analyze the high-level periods of adjacent periods. If a high-level period is inconsistent with the previous few high-level periods and also inconsistent with the subsequent few high-level periods, then the high level is considered a glitch.

[0027] Taking a stable high level as an example, the specific implementation method is as follows: Step 31. Set the stable quantity threshold D1 and the stable difference threshold D2, and start detection from the second high-level cycle; A threshold D3 for the number of items exempted from inspection can also be set. During the first D3 high-level cycles, since the clock is still being established, no glitches are detected. D3 is usually 1.5 to 3 times D1. Step 32. Compare the current high-level cycle value with the previous high-level cycle value. If the difference between the two is less than the stable difference threshold D2, the clock signal is considered to be output stably. When the number of consecutive stable clock signals reaches the stable number threshold D1, calculate the average value MA of these D1 consecutive high-level cycles, and use it as the current high-level cycle stable value MS. In step 32, if the difference between adjacent high-level cycles is greater than the stable difference threshold D2 before reaching the stable quantity threshold D1, the counting restarts until the number of continuously stable clock signals reaches the stable quantity threshold D1. Step 33. After reaching the stable quantity threshold D1 and the continuous high-level period is greater than the pre-exemption threshold D3, the subsequent high-level periods are continuously compared. If the difference between the subsequent high-level period value and the current stable high-level period value MS is found to be greater than the stable difference threshold D2, then proceed to step 34; otherwise, continue with step 33. Step 34. For high-level periods T(N) where the difference between the high-level period value and the current stable high-level period value MS is greater than the stable difference threshold D2, continue to detect subsequent high-level periods of high-level periods T(N); Step 341. If the difference between the subsequent high-level period value and the high-level period value of high-level period T(N) is greater than the stable difference threshold D2, then the high-level period T(N) is determined to be a glitch; Step 342. If the difference between the subsequent high-level period value and the high-level period value of high-level period T(N) is less than the stability difference threshold D2, then the clock signal is considered to be output stably. When the number of consecutive stable clock signals reaches the stability number threshold D1, it indicates that the clock period itself has undergone controlled adjustment starting from the high-level period T(N), rather than glitches. In this case, the average value MA of these consecutive D1 high-level periods is calculated as the updated high-level period stability value MS. In step 342, if after the clock signal is determined to be output stably, the number of continuously output clock signals does not reach the stable number threshold D1 and the difference is greater than the stable difference threshold D2 again, then the high-level period T(N) and the subsequent high-level period before reaching the stable number threshold D1 are still regarded as glitches. After detecting a glitch or updating the stable value of the high-level period MS, return to step 33 to continue the detection.

[0028] For example, set a stable quantity threshold D1=3, a stable difference threshold D2=0.4, and a pre-exemption quantity threshold D3=6. Figure 3As shown, the horizontal axis represents the number of cycles, and the vertical axis represents the high-level cycle value. The high-level cycle values ​​for the first 7 cycles T1 to T7 are all equal to 2. The high-level cycle values ​​for the 8th and 9th cycles T8 and T9 are both 2.5. After the 10th cycle T10, the high-level cycle values ​​are all equal to 3.

[0029] Replace the high level with a low level and repeat step 3. When detecting either level, either detection is judged as a glitch.

[0030] In step 32, the current high-level period is compared with the previous high-level period in the first 4 cycles. When the difference between the two is less than the stable difference threshold D2=0.4 and the number of clock signals that are continuously and stably output reaches the stable number threshold D1=3, the average value of these 3 consecutive high-level periods, 2, is taken as the current high-level period stable value MS=2.

[0031] In step 33, after the continuous high-level period is greater than the pre-exemption threshold D3=6, starting from the seventh period, it is detected whether the difference between the current high-level period value and the current high-level period stable value MS=2 is greater than the stable difference threshold D2. If it is not greater in the seventh period, then step 33 is repeated. If the high-level period value of the 8th cycle is 2.5, which is greater than the stability difference threshold D2, then proceed to step 34 to continue detecting the subsequent high-level periods of the high-level period T(N). If the difference between the 9th cycle and the 8th cycle is not greater than the stability difference threshold D2, then the clock signal is considered to be output stably, and proceed to step 342. Since the high-level period value of the 10th cycle is 3, the difference is again greater than the stability difference threshold D2, so the 8th and 9th cycles are still considered as glitches. Starting from the 10th cycle, if the difference between the 11th and 10th cycles is not greater than the stable difference threshold D2, the clock signal is considered to be output stably, and the process continues to step 342. Since the high-level cycle value of each cycle after the 10th cycle is 3, when the number of continuously stable clock signals reaches the stable number threshold D1, it indicates that the clock cycle itself has undergone controlled adjustment since the 10th cycle, rather than glitches. In this case, starting from the 10th cycle, the average value of the 10th, 11th, and 12th consecutive high-level cycles is calculated to be 3, which is used as the updated high-level cycle stability value MS=3, thereby eliminating glitches and updating the MS value when the clock signal itself changes.

[0032] Replace the high level with a low level and repeat step 3.

[0033] Step 4. Detection result determination: By using SVA assertions under the trigger of the detection clock, the detection result of each clock glitch can be determined and output. The output includes information such as the occurrence time of the clock glitch and the glitch width.

[0034] Based on traditional clock glitch detection solutions, this solution demonstrates significant improvements in reliability, efficiency, circuit simplification, and rapid clock glitch location. This invention uses the clock being tested as the sampling clock, enabling glitches to be detected on clocks of any frequency. It can accurately sample each rising and falling edge of the clock being tested and obtain the corresponding time point, then calculate each high-level period of the clock being tested, and then determine whether clock glitches are generated by analyzing the differences between multiple adjacent high-level periods, ensuring that clock glitches are not missed or falsely detected, thus guaranteeing the reliability of clock glitches detection.

[0035] The clock detection circuit samples and detects at each edge of the clock. The detection results are determined using SVA assertions. It can achieve fully automated real-time detection and determination without manual intervention and print out the results, ensuring high efficiency in clock glitch detection.

[0036] Using the detection clock as the sampling clock eliminates the need to manually generate a high-frequency sampling clock when detecting clock glitches. The high-level period is calculated by directly sampling the rising and falling edges of the detection clock, without using a counter to estimate the high-level period. The existing mature SVA assertion is used for result determination, which simplifies the implementation of the automated clock glitch detection circuit and allows for quick start-up, thus ensuring the simplification of the automated clock glitch detection circuit.

[0037] SVA assertions are used to determine the clock glitch detection results. When a clock glitch is detected, it will output in real time that a glitch has occurred at the current time point. Furthermore, the specific cause can be quickly located by viewing and analyzing the SVA assertion simulation waveform, ensuring that clock glitch problems can be quickly identified.

[0038] The foregoing descriptions are preferred embodiments of the present invention. Unless there is a clear contradiction between the preferred embodiments or a prerequisite for a particular preferred embodiment, the preferred embodiments can be arbitrarily combined and used. The embodiments and specific parameters described are only for clearly illustrating the inventor's invention verification process and are not intended to limit the scope of patent protection of the present invention. The scope of patent protection of the present invention shall still be determined by its claims. Similarly, any equivalent structural changes made based on the description and drawings of the present invention shall also be included within the scope of protection of the present invention.

Claims

1. A clock spurs detection circuit, characterized by, The detection circuit comprises a rising edge sampling module and a falling edge sampling module; sampling output ends of the rising edge sampling module and the falling edge sampling module are connected with a level period calculation module; an output end of the level period calculation module is connected with a clock glitch detection module; and an output end of the clock glitch detection module is connected with an automatic judgment unit. The rising edge sampling module and the falling edge sampling module are used to sample and output the time points of the rising edge and the falling edge. The level period calculation module is used to calculate the difference between the time points of the adjacent rising edge and the falling edge; the clock glitch detection module is used to judge whether it is a glitch according to the difference; and the automatic judgment unit outputs the glitch information.

2. The clock glitch detection circuit of claim 1, wherein, The rising edge sampling module and the falling edge sampling module are programmed by using the System Verilog language, and the time points of the rising edge and the falling edge are captured by using the system function $realtime of the System Verilog language.

3. The clock spurs detection circuit of claim 1, wherein, The automatic judgment unit is realized by using the SVA assertion function of the System Verilog.

4. A clock spurs detection method, characterized by, Based on the detection circuit of claim 1, the following steps are included: Step 1: detecting the time points of the rising edge and the falling edge of the clock; Step 2: subtracting the time points of the adjacent rising edge and the falling edge to obtain the continuous level period value TH and saving the value; Step 3: detecting the clock glitch, specifically as follows: Step 31: setting a stable quantity threshold D1 and a stable difference threshold D2, and starting to detect from the second clock period; Step 32: comparing the current stable level period with the previous stable level period value, and if the difference between the two is less than the stable difference threshold D2, it is considered that the clock signal is stable, and when the number of the continuously stable output clock signals reaches the stable quantity threshold D1, the average MA of the continuous D1 stable level periods is calculated as the stable value MS of the current stable level period; In step 32, if the difference between the adjacent stable level periods is greater than the stable difference threshold D2 before the stable quantity threshold D1 is reached, the counting is restarted until the number of the continuously stable output clock signals reaches the stable quantity threshold D1; Step 33: after the stable quantity threshold D1 is reached and the continuously running stable level period is greater than the pre-set exempt threshold D3, the subsequent stable level periods are continuously compared, and if the difference between the subsequent stable level period value and the stable value MS of the current stable level period is greater than the stable difference threshold D2, step 34 is entered; otherwise, step 33 is continuously performed; Step 34: for the stable level period T(N) whose difference with the stable value MS of the current stable level period is greater than the stable difference threshold D2, the subsequent stable level periods of the stable level period T(N) are continuously detected; Step 341: if the difference between the subsequent stable level period value and the stable level period value of the stable level period T(N) is greater than the stable difference threshold D2, the stable level period T(N) is determined as a glitch. Step 342. If the difference between the subsequent stable level period value and the stable level period value of the stable level period T(N) is less than the stable difference threshold D2, it is considered that the clock signal is stable output, when the number of continuously stable output clock signals reaches the stable number threshold D1, the average MA of the D1 continuous stable level periods is calculated as the updated stable level period stable value MS; In step 342, if it is determined that the clock signal is stable output, and the number of continuously stable output clock signals does not reach the stable number threshold D1 again, the difference is greater than the stable difference threshold D2, the stable level period T(N) and the stable level period before reaching the stable number threshold D1 are still considered as glitches; After detecting the glitch or updating the stable level period stable value MS, return to step 33 to continue detecting; Repeat step 3 by setting the stable level to high and low respectively; Step 4. Output the glitch information.

5. The clock spurs detection method of claim 4, wherein, In step 31, a pre-NFC number threshold D3 is also set. In the first D3 stable level periods, no glitch judgment is performed.

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