Automatic switching device and switching method for multi-processor JTAG debugging mode

Abstract

The invention relates to the field of circuit board testing, in particular to an automatic switching device and switching method for a multi-processor JTAG debugging mode. A micro control unit MCU; the multi-path electronic switch comprises a plurality of control input ends and a plurality of signal channels, and the plurality of control input ends are electrically connected with GPIO (General Purpose Input / Output) pins of the MCU and are used for receiving level control signals; each processor is provided with a JTAG (Joint Test Action Group) signal pin; jTAG signal pins of the plurality of processors are connected with a plurality of signal channels of the multipath electronic switch; the multipath electronic switch switches the connection state of an internal signal channel by responding to a level control signal, and dynamically reconfigures JTAG signal pins of the plurality of processors into a cascade mode and an independent mode; through cooperative control of the micro-control unit and the multi-path electronic switch, dynamic switching of the multi-processor JTAG between a cascade mode and an independent mode is realized, the debugging efficiency and the system reliability are improved, and the area of a circuit board and interface resources are remarkably saved.

Description

Technical Field

[0001] This invention relates to the field of circuit board testing, and more specifically to an automatic switching device and method for multiprocessor JTAG debugging modes. Background Technology

[0002] Currently, embedded hardware boards commonly use DSPs, MCUs, ARMs, or FPGAs as processors. With the increasing demands of various hardware circuit applications, multi-processor hardware designs are becoming mainstream to improve the processing performance of embedded hardware boards. During the debugging process of multi-processor hardware boards, JTAG technology based on the IEEE 1149.1 protocol is required. This protocol is an international standard testing protocol used for applications such as chip internal testing, boundary scan, debugging, and in-circuit programming. For multi-processor hardware circuits, the traditional approach is to use independent JTAG mode or cascaded daisy-chain JTAG mode.

[0003] Existing standalone JTAG modes require JTAG pins to be routed to each processor and placed in a single row of headers nearby. This approach occupies PCB layout space, wastes interface resources, affects signal routing between processors, and increases the number of PCB traces due to routing difficulties, significantly raising costs. Traditional cascaded daisy-chain JTAG modes can connect multiple processors in series through a single interface, optimizing layout and facilitating debugging. However, if a processor in the daisy chain fails, the entire JTAG chain will fail. While reserving 0-ohm resistors, jumpers, or DIP switches at each branch point allows for individual processor debugging by disconnecting the resistor and using jumper wires, this requires hardware rework, is complex, and can introduce potential hazards during the jumper wire process. Alternatively, replacing jumper caps or toggle switches can be used, but this requires manual hardware modification, necessitating complex disassembly and reassembly for assembled circuit boards and complex machined devices. Summary of the Invention

[0004] To address the problems mentioned in the prior art, this invention proposes an automatic switching device and method for multi-processor JTAG debugging modes. Through a daisy-chain configuration of electronic switches and a microcontroller, and using a pre-configured switch table, the daisy chain of the hardware circuit board can be flexibly configured. This method features fast configuration speed, flexibility, low power consumption, safety, reliability, and convenient operation. It solves the problems in the prior art where multi-processor hardware circuits, when used for simulation, waste interface resources, occupy PCB area, and suffer from inflexible configuration in daisy-chain mode, as well as operational risks and complex procedures when switching to independent simulation modes.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: This invention provides an automatic switching device for multiprocessor JTAG debugging modes, comprising: The microcontroller unit (MCU) is used to define the switch configuration table for JTAG signal paths and output level control signals through GPIO pins according to the switch configuration table or external instructions. At least one multiplexer electronic switch includes multiple control inputs and multiple signal channels, wherein the multiple control inputs are electrically connected to the GPIO pins of a microcontroller unit (MCU) for receiving level control signals; Multiple processors, each with a JTAG signal pin, including TDI pin, TDO pin, TMS pin, and TCK pin; the JTAG signal pins of the multiple processors are electrically connected to multiple signal channels of a multiplexer. Among them, the multi-channel electronic switch switches the connection state of its internal signal channels by responding to the level control signal, and can dynamically reconstruct the JTAG signal pins of multiple processors into cascade mode and independent mode.

[0006] As a further improvement of the present invention, the cascading mode includes: The processor's TMS pin and TCK pin are connected in parallel to a common TMS signal line and TCK signal line, respectively. The multiplexer connects the TDO pin of the first processor to the TDI pin of the second processor, connects the TDO pin of the second processor to the TDI pin of the third processor, and so on, connecting the JTAG signals of all processors in series to form a daisy chain.

[0007] As a further improvement of the present invention, both the start and end ends of the daisy chain are connected to an external JTAG interface.

[0008] As a further improvement to the present invention, the independent mode includes: Each processor's TMS pin, TCK pin, TDI pin, and TDO pin are routed to an independent JTAG signal channel via multiplex electronic switches.

[0009] As a further improvement of the present invention, in independent mode, the TMS pins of all processors are connected to a set of independent TMS common signal lines, and the TCK pins of all processors are connected to a set of independent TCK common signal lines. The TDI and TDO pins of each processor are routed independently.

[0010] As a further improvement of the present invention, the multi-channel electronic switch is a four-channel double-throw analog electronic switch.

[0011] As a further improvement of the present invention, the four signal channels in the four-way double-throw analog switch are respectively used to switch the processor's TDI signal, TDO signal, TMS signal and TCK signal.

[0012] As a further improvement of the present invention, the model of the four-way double-throw analog electronic switch is CH445P.

[0013] This invention proposes a method for switching JTAG debugging modes in a multi-processor system, using the aforementioned automatic switching device for processor JTAG debugging modes, comprising the following steps: The microcontroller unit (MCU) generates corresponding level control signals based on a pre-stored switch configuration table or external instructions. The microcontroller unit (MCU) outputs level control signals to the control input terminal of the multi-channel electronic switch via GPIO pins; The multi-channel electronic switch responds to the level control signal and switches the connection state of its multiple internal signal channels; by switching the signal channels, the JTAG signal pins of multiple processors are dynamically reconstructed between cascaded mode and independent mode; As a further improvement to the present invention, in cascaded mode, all processors form a JTAG daisy chain; in standalone mode, each processor has an independent JTAG signal channel.

[0014] Compared with the prior art, the present invention achieves the following technical effects: This invention achieves dynamic switching between cascaded and independent modes of a multi-processor JTAG link through the coordinated control of a microcontroller unit (MCU) and multiple electronic switches. It solves the problems of excessive interface resource consumption, difficult PCB layout, complex mode switching operations, and potential safety hazards in traditional debugging methods. This device eliminates the need for manual hardware modifications; it uses only the MCU's output level control signal to drive the electronic switches, thus significantly improving debugging efficiency and system reliability. It also significantly saves circuit board area and interface resources, and features fast configuration, flexibility, low power consumption, safety, reliability, and ease of operation.

[0015] This invention employs a four-way double-throw analog electronic switch as the signal routing component, enabling channel control of the TDI, TDO, TMS, and TCK signals of each processor. This ensures the integrity and timing stability of the JTAG signal during path switching, avoiding signal quality degradation caused by the introduction of switching circuits. In cascaded mode, this device connects the JTAG signals of multiple processors in series to form a unified daisy chain, which not only greatly simplifies the operation process of the host computer debugging software but also allows multiple processors to be identified as a unified logical entity for access, significantly reducing the number of pins on external connectors and the complexity of circuit board routing. Furthermore, in independent mode, this device can route the TMS and TCK pins of all processors to independent common signal lines, while routing the TDI and TDO pins of each processor completely independently, achieving flexible debugging and convenient operation. Attached Figure Description

[0016] Figure 1 This is a block diagram of the daisy-chain debugging interface based on switch selection of the present invention; Figure 2 This is a diagram of the internal structure of the CH445P type 4-channel double-throw 2-to-1 electronic switch of the present invention; Figure 3 This is the truth table for the CH445P type 4-channel double-throw 2-to-1 electronic switch of the present invention; Figure 4 This invention relates to the design principle of a 3-FPGA daisy chain based on the CH445P electronic switch. Figure 5 This is a block diagram of the MCU-based intelligent daisy-chain debugging interface design of the present invention. Detailed Implementation

[0017] In the following description, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of the invention. Therefore, the drawings and description are considered to be exemplary in nature and not restrictive.

[0018] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0019] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0020] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a communication connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0021] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0022] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0023] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0024] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0025] The accompanying drawings illustrate various structural schematic diagrams according to embodiments disclosed in this invention. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0026] It should be noted that an electronic switch is a device that controls the on / off state of a circuit through electronic signals. It is widely used in modern electronic devices. Compared to traditional mechanical switches, electronic switches are typically composed of semiconductor devices and have no moving mechanical parts, offering advantages such as fast response speed, long lifespan, and small size. Commonly used ST-series microcontrollers offer balanced performance, rich peripherals, a mature development ecosystem, and low cost, providing high cost-effectiveness. Furthermore, there are fully domestically produced alternatives available. This embodiment, by combining a microcontroller with an electronic switch, effectively solves the problems mentioned in the background technology.

[0027] See Figure 1 This embodiment provides an automatic switching device for multi-processor JTAG debugging modes, including: The microcontroller unit (MCU) is used to define the switch configuration table for JTAG signal paths and output level control signals through GPIO pins according to the switch configuration table or external instructions. At least one multiplexer electronic switch includes multiple control inputs and multiple signal channels, wherein the multiple control inputs are electrically connected to the GPIO pins of a microcontroller unit (MCU) for receiving level control signals; Multiple processors, each with a JTAG signal pin, including TDI pin, TDO pin, TMS pin, and TCK pin; the JTAG signal pins of the multiple processors are electrically connected to multiple signal channels of a multiplexer. Among them, the multi-channel electronic switch switches the connection state of its internal signal channels by responding to the level control signal, and can dynamically reconstruct the JTAG signal pins of multiple processors into cascade mode and independent mode.

[0028] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0029] Example 1 like Figure 1 As shown, this embodiment employs multiple multi-channel electronic switches, preferably the CH445P four-pole double-throw 3.3V low-impedance analog switch developed by Nanjing Qinheng Microelectronics Co., Ltd., with a typical switch response speed of less than 5ns; the specific structure of the above switches is as follows. Figure 2 As shown.

[0030] In this embodiment, the CH445P four-pole double-throw 3.3V low-impedance analog switch includes four independent double-throw switches (corresponding to four channels A / B / C / D). Each switch has two inputs (S1x and S2x, such as S1A / S2A) and one output (Dx, such as DA). Specifically, the four outputs of the four switches correspond to the JTAG signal pins of each processor, including the TDI pin, TDO pin, TMS pin, and TCK pin, which are connected respectively. The inputs are connected to different targets according to the signal type.

[0031] Specifically, for the TMS and TCK pins, one input is connected to the corresponding signal line of the processor's independent JTAG interface, and the other input is connected to the TMS and TCK common signal lines in the cascaded JTAG interface shared by all processors. Similarly, for the TDI and TDO pins, one input is also connected to the independent JTAG interface, and the other input is connected to the TDO and TDI pins of the adjacent processors in the daisy chain, respectively.

[0032] Therefore, this embodiment can achieve mode switching by switching the level signal of the electronic switch control pin. In independent mode, the JTAG signal (TDI / TDO / TMS / TCK) of each processor is connected to the jumper of the independent debugging interface. The JTAG signals of each processor are physically isolated and can be debugged individually. In cascade mode, the multi-channel electronic switch can connect the TDI pin and TDO pin of each processor to the corresponding pin of the adjacent processor in series to form a daisy chain, and connect the TMS pin and TCK pin in parallel for sharing, thereby realizing unified access of multiple devices.

[0033] In this embodiment, mode switching requires manual adjustment of the electronic switch control pin level via external circuitry, such as through a DIP switch or jumper cap. This manual intervention simplifies the traditionally complex operations of flying wires or resistor replacements to simple level settings, and ensures precise synchronization of all signal path switching, thus avoiding the risk of misoperation. The specific logic state relationship after switching can be found in [reference needed]. Figure 3 truth table and Figure 4 The design principle of FPGA daisy chain.

[0034] Figure 3 When both EN# and IN are 0, all channels are connected to one set of inputs of the multiplexer for standalone mode; when EN# is 0 and IN is 1, all channels are connected to the other set of inputs of the multiplexer for cascade mode; when EN# is 1 and IN is X, all switches are disconnected.

[0035] Figure 4The signal connection principle in cascaded mode is illustrated using three FPGAs as an example. In this mode, by controlling an electronic switch, the TMS and TCK pins of all processors are selected to a common signal line, allowing all processors to respond synchronously to the same test mode instructions and test clock. Simultaneously, the TDO and TDI pins of each processor are configured in series: the TDI pin of the first processor receives data from an external debugger, its TDO pin is connected to the TDI pin of the second processor, the TDO pin of the second processor is connected to the TDI pin of the third processor, and so on, forming a complete daisy chain. The final output of this daisy chain (the TDO pin of the last processor) is sent back to the debugger.

[0036] Example 2 See Figure 5 This embodiment, based on the hardware structure in Embodiment 1, introduces a microcontroller unit (MCU) as the control core, thereby achieving fully automatic switching. In this embodiment, Figure 1 The level control signals that require manual setting are all provided by the GPIO pins of the MCU. The MCU is preferably a domestic GD32 series microcontroller. This microcontroller has a pre-stored switch configuration table. The switch configuration table defines under what conditions any combination of levels should be output to switch to the corresponding cascade mode or independent mode. When the system receives a command from an external debugging tool, the microcontroller MCU will query the configuration table and output the corresponding control signal to the input terminal of the CH445P electronic switch through the GPIO pin. The CH445P electronic switch responds and quickly and synchronously switches all its internal channels to the specified throw position, thereby completing the switching of the JTAG topology of the entire device between cascade module and independent mode.

[0037] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the scope of the invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0038] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can be appropriately combined to form other embodiments that can be understood by those skilled in the art. The above content is only for illustrating the technical concept of the present invention and should not be construed as limiting the scope of protection of the present invention. Any modifications made based on the technical concept proposed in this invention shall fall within the scope of protection of the claims of this invention.

Claims

1. An apparatus for automatic switching of multi-processor JTAG debug modes, comprising: The application relates to a JTAG signal dynamic reconfiguration method and device. The application comprises the following: a micro control unit (MCU) for defining a switch configuration table of a JTAG signal path and outputting a level control signal through a GPIO pin according to the switch configuration table or an external instruction; at least one multi-path electronic switch comprising a plurality of control input ends and a plurality of signal channels, wherein the plurality of control input ends are electrically connected with the GPIO pin of the micro control unit (MCU) and used for receiving the level control signal; a plurality of processors, each of which is provided with JTAG signal pins including a TDI pin, a TDO pin, a TMS pin and a TCK pin; wherein the JTAG signal pins of the plurality of processors are electrically connected with the plurality of signal channels of the multi-path electronic switch; 2. The apparatus of claim 1, wherein the JTAG debug mode is one of a run test / evaluation (RTE) mode, a boundary scan (BSC) mode, and a boundary scan test (BST) mode. wherein the multi-path electronic switch can dynamically reconfigure the JTAG signal pins of the plurality of processors into a cascade mode and an independent mode by switching the connection state of the internal signal channels in response to the level control signal. The cascade mode comprises the following: the TMS pin and the TCK pin of the processor are respectively connected in parallel to a common TMS signal line and a common TCK signal line; 3. The apparatus of claim 2, wherein the processor is further configured to: the multi-path electronic switch connects the TDO pin of the first processor to the TDI pin of the second processor, connects the TDO pin of the second processor to the TDI pin of the third processor, and repeatedly connects the TDO pin of the last processor to the TDI pin of the first processor, so as to form a daisy chain by connecting the JTAG signals of all the processors in series.

4. The automatic switching device of JTAG debug mode of multiple processors according to claim 1, characterized in that, The starting end and the ending end of the daisy chain are connected to an external JTAG interface. The independent mode comprises the following:

5. The apparatus of claim 4, wherein the processor is further configured to: the TMS pin, the TCK pin, the TDI pin and the TDO pin of each processor are respectively routed to an independent JTAG signal channel through the multi-path electronic switch. In the independent mode, the TMS pins of all the processors are commonly connected to a group of independent TMS common signal lines, and the TCK pins of all the processors are commonly connected to a group of independent TCK common signal lines; 6. The apparatus of claim 1, wherein the JTAG debug mode is one of a run test / evaluation mode (RTE) and a boundary scan test mode (BIST). the TDI pin and the TDO pin of each processor are independently routed.

7. The apparatus of claim 6, wherein the processor is further configured to: The multi-path electronic switch is a four-path double-throw analog electronic switch.

8. The apparatus of claim 6, wherein the processor is further configured to: The four signal channels in the four-path double-throw analog switch are respectively used for switching the TDI signal, the TDO signal, the TMS signal and the TCK signal of the processor.

9. A method for switching a multi-processor JTAG debug mode, using the automatic switching device of any one of claims 1 to 9, wherein The model of the four-path double-throw analog electronic switch is CH445P. The method comprises the following steps: the micro control unit (MCU) generates a corresponding level control signal according to a pre-stored switch configuration table or an external instruction; the micro control unit (MCU) outputs the level control signal to the control input end of the multi-path electronic switch through a GPIO pin; 10. The method of claim 9, wherein the method further comprises: the multi-path electronic switch switches the connection state of the internal plurality of signal channels in response to the level control signal; and dynamically reconfigures the JTAG signal pins of the plurality of processors between the cascade mode and the independent mode by switching the signal channels. In the cascade mode, all the processors form a JTAG daisy chain; and in the independent mode, each processor has an independent JTAG signal channel.

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