Hardware defense method, chip and system based on satellite navigation frequency adjustment

Abstract

The invention discloses a hardware defense method, chip and system based on satellite navigation frequency adjustment, and relates to the navigation and signal processing technology, and the method comprises the steps: setting a hardware defense module in a satellite navigation positioning chip; when the hardware defense module does not receive the trigger signal, the hardware defense module is controlled to be in a standby state, so that the satellite navigation positioning chip works normally; and under the condition that the hardware defense module is controlled to receive an external trigger signal, the internal logic function of the hardware defense module is triggered and enters a trigger state, so that the power supply period of a PLL phase-locked loop end is modified, power supply of the PLL is interfered, and interference on the data analysis module is realized. According to the application, the hardware defense module is designed for the PLL module, so that certain interference is generated on the PLL module under a specific signal to cause frequency fluctuation of a system clock, a certain error is finally generated by positioning data output by a satellite navigation chip, and the problem that the navigation positioning chip is maliciously used by an unauthorized party is solved.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of navigation and signal processing, in particular to a hardware defense method based on satellite navigation frequency adjustment, a chip and a system. BACKGROUND

[0002] Navigation positioning chips are usually applied in satellite navigation systems, can help devices obtain positioning information by receiving satellite signals, and are widely used in unmanned aerial vehicles or military equipment. However, when the navigation positioning chip is maliciously used by an unauthorized party, it does not have the function of suspending work or self-destruction. Therefore, the navigation positioning device is easy to be obtained and used by others, which is not conducive to the controllability of the navigation positioning system of our side.

[0003] In the prior art, CN119989341A discloses a hardware defense method against speculative cache side-channel attacks. The patent provides a hardware defense method against speculative cache side-channel attacks. The framework is based on the speculative windows generated by different speculation sources inside the processor, and a low-overhead insecure speculation memory instruction hardware tracking scheme is designed; and based on the changes of the speculation memory instruction in the speculation window to the different states of the cache system, different hardware delay schemes are designed to delay the insecure speculation memory instruction at different stages of the memory pipeline.

[0004] CN120407507A discloses a security debugging method of an embedded microprocessor and the embedded microprocessor. The patent implants a random module in the microprocessor, constructs a resistance network array by the random distribution of silicon substrate lattice defects, and generates a chaotic sequence. If the microprocessor data is accessed, a debugging session is established, three types of physical features are generated synchronously to construct a composite key, a triple dynamic confusion layer is constructed inside the microprocessor, the dynamic confusion layer and the composite key construct physical logic linkage protection, and the probe access instruction logical address is called. If physical intrusion is detected, the probe triggers a hidden checkpoint, and verifies the integrity of the execution environment. If abnormal debugging is detected, the hardware defense mechanism is triggered, an access attack model is established, the confusion parameters are optimized and trained, and the module interconnection mode is changed, breaking the learning cycle of the attacker and reducing the risk of machine learning method attacking the processor.

[0005] Most of the existing hardware defense methods are designed for processors, which achieve the function of hindering illegal access through hardware design. However, such hardware defense methods can be detected through laboratory tests, and the avoidance means can be found after multiple runs.

[0006] Furthermore, existing patents do not include hardware defense designs for satellite navigation system chips. The hardware defense functions designed for processing these chips are not applicable to satellite navigation systems and cannot achieve defense control based on changes in the chip's application environment, thus failing to meet the need to prevent the illegal use of satellite navigation chips.

[0007] The patent describes a secure debugging method for embedded microprocessors and an embedded microprocessor. The hardware defense mechanism mentioned in the patent is trained and optimized through an attack model. This process increases the overall power consumption of the chip and is not suitable for satellite navigation chip systems. Summary of the Invention

[0008] This application provides a hardware defense method, chip, and system based on satellite navigation frequency adjustment, which aims to generate a certain error in the positioning data output by the satellite navigation chip and solve the problem of unauthorized malicious use of navigation and positioning chips.

[0009] This application provides a hardware defense method based on satellite navigation frequency modulation, including: Inside the satellite navigation and positioning chip, a hardware defense module is set up as an independent IP core. The satellite navigation and positioning chip includes a signal receiving module, a data parsing module, and a PLL phase-locked loop. The signal receiving module is used to receive satellite navigation data and input it to the data parsing module for parsing. The data parsing module is used to output the parsed data. The PLL provides a system clock for the signal receiving module and the data parsing module. The hardware defense module is configured to receive data information from the signal receiving module. The hardware defense module is kept in standby mode when no trigger signal is received, so that the satellite navigation and positioning chip can work normally. When the hardware defense module receives an external trigger signal, its internal logic function is triggered, and it enters a trigger state to modify the power supply cycle of the PLL phase-locked loop terminal, thereby interfering with the PLL power supply and thus interfering with the data parsing module.

[0010] This application provides a hardware-based defense satellite navigation and positioning chip based on satellite navigation frequency modulation, including a signal receiving module, a hardware defense module, a data parsing module, and a PLL phase-locked loop. The signal receiving module is used to receive satellite navigation data and input it into the data parsing module for parsing. The data parsing module is used to parse and output the data. The PLL phase-locked loop is used to provide a system clock for the signal receiving module and the data parsing module; The hardware defense module is configured to receive data information from the signal receiving module; The hardware defense module is in standby mode when no trigger signal is received, allowing the satellite navigation and positioning chip to work normally. When the hardware defense module receives an external trigger signal, its internal logic function is triggered, and it enters a triggered state to modify the power supply cycle of the PLL phase-locked loop terminal, thereby interfering with the power supply of the PLL and thus interfering with the data parsing module.

[0011] This application also proposes a hardware defense system based on satellite navigation frequency adjustment, characterized in that it includes a satellite navigation positioning chip as described above.

[0012] This application embodiment designs a hardware defense module for the PLL module, which can cause certain interference to the PLL module under specific signals, resulting in frequency fluctuations in the system clock. Ultimately, this causes a certain error in the positioning data output by the satellite navigation chip, thus solving the problem of unauthorized malicious use of navigation and positioning chips.

[0013] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0014] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings: Figure 1 This is a schematic diagram of the architecture of a satellite navigation and positioning chip in the hardware defense method based on satellite navigation frequency adjustment according to an embodiment of this application. Figure 2 This is a schematic diagram of the triggering process of the hardware defense method based on satellite navigation frequency adjustment in an embodiment of this application. Detailed Implementation

[0015] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0016] This application provides a hardware defense method based on satellite navigation frequency modulation, such as... Figure 1 As shown, it includes: Within the satellite navigation and positioning chip, a hardware defense module is set up as an independent IP core. The satellite navigation and positioning chip includes a signal receiving module, a data parsing module, and a PLL (phase-locked loop). The signal receiving module receives satellite navigation data and inputs it to the data parsing module for analysis. The data parsing module outputs the parsed data. The PLL provides a system clock for the signal receiving module and the data parsing module. The hardware defense module is configured to receive data from the signal receiving module. In some embodiments, the satellite navigation and positioning chip also includes a power supply module. The hardware defense module is positioned between the signal receiving module and the power supply module, and upon triggering, the hardware defense module interferes with the power supply module.

[0017] The hardware defense module is kept in standby mode when no trigger signal is received, so that the satellite navigation and positioning chip can work normally. When the hardware defense module receives an external trigger signal, its internal logic function is triggered, and it enters a trigger state to modify the power supply cycle of the PLL phase-locked loop terminal, thereby interfering with the PLL power supply and thus interfering with the data parsing module.

[0018] This application embodiment designs a hardware defense module for the PLL module, which can cause certain interference to the PLL module under specific signals, resulting in frequency fluctuations in the system clock. Ultimately, this causes a certain error in the positioning data output by the satellite navigation chip, thus solving the problem of unauthorized malicious use of navigation and positioning chips.

[0019] In some embodiments of this application, once the hardware defense module is triggered, it will not exit the triggered state unless the module is restarted.

[0020] In some embodiments of this application, the trigger signal is configured as a signal of a specified frequency, which can be mixed into the satellite navigation signal and received by the signal receiving module. The hardware defense module is used to detect the signal of the specified frequency. The specified frequency has a signal frequency that meets the receiving frequency range of the navigation and positioning chip, and its signal power is similar to the signal power of the satellite navigation and positioning chip when it is working normally.

[0021] In a specific example, the trigger signal is designed with a trigger signal frequency. The trigger signal power is -100dBm. The frequency of the trigger signal meets the receiving frequency range of the navigation and positioning chip and can be received normally by the chip. The signal power of the trigger signal is similar to the normal operating signal power of the chip, and does not affect the analysis of satellite signals by the signal receiving module. It can be processed into a digital signal by the signal receiving module and transmitted to the hardware defense module.

[0022] In some embodiments of this application, such as Figure 2 As shown, the triggering process of the hardware defense module includes: The hardware defense module uses signal processing to calculate the signal frequency and amplitude in order to identify the trigger signal; Upon receiving a trigger signal, the control hardware defense module initiates its internal logic and uses a counter to count the number of times the trigger signal is sampled. If a specified number of trigger signals are sampled consecutively, the control hardware defense module enters the trigger state.

[0023] In some specific examples, after receiving a trigger signal, the hardware defense module can activate its internal logic to count the number of trigger signal samples using a counter. If 10 sets of trigger signals are sampled consecutively, the hardware defense module enters the trigger state. If the hardware defense module does not receive a trigger signal or the number of trigger signals does not reach 10 consecutive sets, the hardware defense module remains in the detection state and does not trigger. This application is only an example, and the specific number of sets is not limited.

[0024] In some embodiments of this application, the hardware defense module executes the following process after being triggered: The hardware defense module controls the power supply module of the satellite navigation and positioning chip to periodically and briefly reduce the power supply periodically, causing the PLL (phase-locked loop) to experience a system clock offset. Specifically, upon triggering, the hardware defense module modifies the power supply section of the navigation and positioning chip's PL (phase-locked loop) terminal, periodically and briefly reducing the PLL's power supply to cause some interference.

[0025] In some embodiments of this application, the hardware defense module is controlled such that the minimum frequency of the system clock offset generated by the PLL phase-locked loop is greater than the maximum deviation of the normal operating frequency of the data parsing module.

[0026] In the navigation baseband chip, the PLL module is used to convert the external input clock into its internal system clock after frequency conversion or amplitude modification. The main control signals for the PLL module are the reference clock and the supply voltage. When the power supply to the phase-locked loop fluctuates, it directly affects the operation of the voltage-controlled oscillator (VCO), ultimately causing frequency drift or noise in the output system clock. In some embodiments of this application, the normal operating frequency requirement for the data parsing module is... In this case, the hardware defense module is controlled to make the system clock offset generated by the PLL phase-locked loop 20MHz~100MHz.

[0027] Based on the method of this application, when the satellite navigation signal enters the satellite navigation positioning chip, it is collected by the signal receiving module and converted into satellite navigation data. Subsequently, the satellite navigation data is transmitted to the data parsing module for data decoding, ultimately forming navigation and positioning information.

[0028] The normal operation of both the signal receiving module and the data parsing module depends on the stability of the system clock. If the system clock experiences frequency drift or excessive noise, it will cause errors in the sampled data of the signal receiving section. Furthermore, during the data parsing module's processing, an unstable system clock will introduce errors into the operation of the internal processor and the calculation of the satellite navigation signal frequency, ultimately resulting in incorrect time and location information in the output data.

[0029] This application presents a conditional trigger hardware defense module designed for satellite navigation chips. The trigger signal exhibits a high degree of similarity to satellite signals, making it difficult to detect through operational testing unless the frequency of the trigger signal is known in advance. Furthermore, this hardware defense module is implemented by modifying the PLL power supply to offset the internal system clock frequency. The power consumption of the PLL is significantly lower than the overall power consumption of the satellite navigation chip, typically only affecting it by about 5%. The implementation effect will not significantly impact the overall power consumption of the chip, making it difficult to detect through power consumption detection methods in the laboratory. This low risk of breach makes it difficult to detect through power consumption detection methods while the hardware defense module is operating. Therefore, this hardware defense module is highly feasible for use in satellite navigation chips. Compared to methods that directly and excessively modify the chip clock or increase internal chip computation, this application has a smaller impact on chip power consumption, reducing the risk of the hardware defense module being compromised.

[0030] This application also proposes a hardware-based defense satellite navigation and positioning chip based on satellite navigation frequency modulation, including a signal receiving module, a hardware defense module, a data parsing module, and a PLL phase-locked loop. The signal receiving module is used to receive satellite navigation data and input it into the data parsing module for parsing. The data parsing module is used to parse and output the data. The PLL phase-locked loop is used to provide a system clock for the signal receiving module and the data parsing module; The hardware defense module is configured to receive data information from the signal receiving module; The hardware defense module is in standby mode when no trigger signal is received, allowing the satellite navigation and positioning chip to work normally. When the hardware defense module receives an external trigger signal, its internal logic function is triggered, and it enters a triggered state to modify the power supply cycle of the PLL phase-locked loop terminal, thereby interfering with the power supply of the PLL and thus interfering with the data parsing module.

[0031] This application also proposes a hardware defense system based on satellite navigation frequency adjustment, characterized in that it includes a satellite navigation positioning chip as described above.

[0032] It should be noted that, in the embodiments of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0033] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0034] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0035] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims. All of these forms are within the protection scope of this application.

Claims

1. A hardware defense method based on satellite navigation frequency adjustment, characterized in that, The application relates to a satellite navigation positioning chip, which comprises a hardware defense module arranged in the satellite navigation positioning chip in the form of an independent IP core, a signal receiving module, a data analysis module and a PLL phase-locked loop, wherein the signal receiving module is used for receiving satellite navigation data and inputting the satellite navigation data to the data analysis module for analysis, the data analysis module is used for data output after analysis, the PLL phase-locked loop is used for providing system clock for the signal receiving module and the data analysis module, and the hardware defense module is configured to receive data information of the signal receiving module. The hardware defense module is controlled to be in a standby state when no trigger signal is received, so that the satellite navigation positioning chip normally works. When the hardware defense module receives an external trigger signal, the internal logic function of the hardware defense module is triggered to enter a trigger state, so as to modify the power supply cycle of the PLL phase-locked loop end, interfere with the power supply of the PLL, and realize interference on the data analysis module. After the hardware defense module is triggered, the module is restarted, and the trigger state will not be exited.

2. The hardware defense method based on satellite navigation frequency adjustment as claimed in claim 1, wherein, The trigger signal is a signal of a specified frequency, the signal of the specified frequency can be mixed into satellite navigation signals, is received by the signal receiving module, and the hardware defense module is used for detecting the signal of the specified frequency.

3. The hardware defense method based on satellite navigation frequency adjustment as claimed in claim 1, wherein, The signal frequency of the specified frequency meets the receiving frequency range of the navigation positioning chip, and the signal power is close to the signal power of the normal working satellite navigation positioning chip. The trigger process of the hardware defense module comprises the following steps:

4. The hardware defense method based on satellite navigation frequency adjustment as claimed in claim 3, wherein, The hardware defense module calculates the signal frequency and amplitude through signal processing to identify the trigger signal. After the trigger signal is received, the internal logic of the hardware defense module is controlled to start, and the number of trigger signal samples is counted by a counter. If a specified number of trigger signals are continuously sampled, the hardware defense module is controlled to enter the trigger state. After the hardware defense module is triggered, the following processes are executed:

5. The hardware defense method based on satellite navigation frequency adjustment as claimed in claim 1, wherein, The hardware defense module controls the power supply module of the satellite navigation positioning chip to be temporarily reduced in cycles, so that the PLL phase-locked loop generates system clock offset. The hardware defense module controls the frequency minimum value of the system clock offset generated by the PLL phase-locked loop to be greater than the maximum deviation of the normal working frequency of the data analysis module.

6. The hardware defense method based on satellite navigation frequency adjustment as claimed in claim 5, wherein, The hardware defense module controls the system clock offset generated by the PLL phase-locked loop to be 20MHz-100MHz.

7. The hardware defense method based on satellite navigation frequency adjustment as claimed in claim 6, wherein, The application relates to a satellite navigation positioning chip, which comprises a hardware defense module arranged in the satellite navigation positioning chip in the form of an independent IP core, a signal receiving module, a data analysis module and a PLL phase-locked loop, wherein the signal receiving module is used for receiving satellite navigation data and inputting the satellite navigation data to the data analysis module for analysis, the data analysis module is used for data output after analysis, the PLL phase-locked loop is used for providing system clock for the signal receiving module and the data analysis module, and the hardware defense module is configured to receive data information of the signal receiving module.

8. A satellite navigation positioning chip based on hardware defense of satellite navigation frequency adjustment, characterized in that, The hardware defense module is controlled to be in a standby state when no trigger signal is received, so that the satellite navigation positioning chip normally works. ​ ​ ​ ​ ​ The hardware defense module, in the case of receiving an external trigger signal, its internal logic function is triggered, enters the trigger state, to modify the power supply cycle of the PLL phase-locked loop end, the power supply of the PLL is disturbed, and interference to the data analysis module is generated.

9. A hardware defense system based on satellite navigation frequency adjustment, characterized in that, The satellite navigation positioning chip comprises the satellite navigation positioning chip as claimed in claim 8.

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