Global navigation satellite system receiver and global navigation satellite system receiving method

Abstract

A global navigation satellite system receiver includes a multiplexer circuit, a fast Fourier transform circuit, a pre-sampler circuit, a code generator circuit, and a hypothesis scheduler. The multiplexer circuit is provided with a first input port, a second input port and an output port. The fast Fourier transform circuit is coupled to the output port. The pre-sampler circuit generates and outputs a data sequence to the first input port of the multiplexer circuit. The code generator circuit generates and outputs a local replica output to the second input port of the multiplexer circuit. The hypothesis scheduler is coupled to the multiplexer circuit, the pre-sampler circuit, and the code generator circuit. Under the coordination of the hypothesis scheduler, the fast Fourier transform circuit is shared between the pre-sampler circuit and the code generator circuit through the multiplexer circuit.

Description

TECHNICAL FIELD

[0001] The present application relates to a global navigation satellite system (GNSS) receiver design, and in particular, to a GNSS receiver with hardware sharing by a hypothesis scheduling machine and a correlation method. BACKGROUND

[0002] GNSS is often described as a "stealthy tool" that provides two powerful basic services, time and position, with accuracy, reliability and affordability. Many aspects of the modern world have come to rely on them. Each GNSS satellite is equipped with a high-precision atomic clock, and when four or more satellites are in view, a GNSS receiver can measure the range to each satellite by estimating the signal propagation time delay from the satellite to the receiver. From these measurements, GNSS-enabled devices can compute their own position and synchronize to the precise GNSS system time.

[0003] GNSS satellite signals are modulated by a pseudo random noise (PRN) code. A PRN code is a code sequence of randomly distributed 0s and 1s. Each satellite transmits a unique PRN code, so a GNSS receiver can identify any satellite by its unique PRN code. The unique PRN code is continuously repeated, and a GNSS receiver can use a local replica of the unique PRN code to perform a correlation operation on the received satellite signal for acquisition. More specifically, since GNSS is a spread spectrum communication system, the de-spreading process of a GNSS receiver is to perform a correlation operation between the received satellite signal and the local replica. The correlation operation can be a time-domain correlation operation or a frequency-domain correlation operation. Nowadays, there is an increasing interest in processing high-complexity GNSS signals with a frequency-domain correlation operation. Therefore, there is a need for a GNSS receiver that can directly acquire high-complexity GNSS signals. SUMMARY

[0004] One of the objectives of the present application is to provide a GNSS receiver with hardware sharing by a hypothesis scheduling machine and a correlation method.

[0005] In one embodiment of the present application, a GNSS receiver is disclosed, comprising a multiplexer circuit, a fast Fourier transform circuit, a pre-sampler circuit, a code generator circuit, and a hypothesis scheduler. The multiplexer circuit has a first input port, a second input port, and an output port. The fast Fourier transform circuit is coupled to the output port. The pre-sampler circuit is configured to generate and output a data sequence output to the first input port of the multiplexer circuit. The code generator circuit is configured to generate and output a local replica output to the second input port of the multiplexer circuit. The hypothesis scheduler is coupled to the multiplexer circuit, the pre-sampler circuit, and the code generator circuit, wherein the fast Fourier transform circuit is shared between the pre-sampler circuit and the code generator circuit through the multiplexer circuit under the coordination of the hypothesis scheduler.

[0006] In one embodiment of the present application, a GNSS receiving method is disclosed, comprising: performing a multi-task operation for a data sequence output of a pre-sampling operation and a local replica output of a code generation operation to generate a multi-task output; and performing a fast Fourier transform on the multi-task output.

[0007] The hypothesis scheduler disclosed in the present application has the characteristics of low power consumption, low area cost, and real-time adjustment, so that a pair of low complexity fast Fourier transform circuit and low complexity inverse fast Fourier transform circuit in a GNSS receiver can have maximum hardware component sharing to complete millisecond-level real-time signal processing. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 is a schematic diagram of a GNSS receiver system-on-chip according to one embodiment of the present application.

[0009] Figure 2 is a schematic diagram of a pre-processor circuit according to one embodiment of the present application.

[0010] Figure 3 is a schematic diagram of a pre-sampler circuit according to one embodiment of the present application.

[0011] Figure 4 is a schematic diagram of four data interleaving modes according to one embodiment of the present application.

[0012] Figure 5 is a schematic diagram of data streams based on four data interleaving modes according to one embodiment of the present application.

[0013] Figure 6 is a schematic diagram of a hypothesis scheduler according to one embodiment of the present application. Figure 1 is a schematic diagram of a GNSS receiver system-on-chip performing real-time signal processing according to one embodiment of the present application. DETAILED DESCRIPTION

[0014] Certain terms are used throughout the present description and claims. Those of ordinary skill in the art will understand that a hardware manufacturer can refer to a component by different names — the descriptions and claims should not be limited as a result. Where a component is referred to as being "coupled" or "coupled to" another component, it should be understood that the component can be directly coupled to the other component or be indirectly coupled through one or more other components. Where a component is referred to as being "coupled to" another component, it should be understood that the component can be directly coupled to the other component or be indirectly coupled through one or more other components.

[0015] The present disclosure proposes a GNSS receiver capable of directly acquiring high-complexity GNSS signals, such as Global Positioning System (GPS) L5, BeiDou B2a / b, Galileo E5a / b, E6, and Quasi-Zenith Satellite System (QZSS) L6. Figure 1is a schematic diagram of a GNSS receiver system-on-chip (SoC) of an embodiment of the present application. The GNSS receiver system-on-chip 100 includes a radio frequency front-end (labeled "RFFE") 102, an analog-to-digital converter (labeled "ADC") 104, a baseband processor 106, and a microcontroller unit (labeled "MCU") 108. In this embodiment, the baseband processor 106 includes a pre-processor circuit (labeled "pre-processor") 110, a pre-sampler circuit (labeled "pre-sampler") 112, a code generator circuit 114, a hypothesis scheduling machine (labeled "HSM") 115, a multiplexer circuit (labeled "MUX") 116, a low-complexity fast Fourier transform (labeled "LC-FFT") 118, a low-complexity inverse fast Fourier transform (labeled "LC-IFFT") 120, a correlation circuit 122, a spectrum memory (labeled "SMEM") 124, and a non-coherent integration memory 126.

[0016] The radio frequency front-end 102 includes all components necessary to down-convert satellite signals (i.e., raw radio frequency signals received from an antenna) to low-intermediate frequency (low-IF) signals SIF, e.g., radio frequency filters, radio frequency amplifiers, mixers, and local oscillators. The analog-to-digital converter 104 is used to perform analog-to-digital conversion on the analog low-IF signals SIF to produce and output an analog-to-digital converter output signal SD.

[0017] The pre-processor circuit 110 is configured to receive an analog-to-digital converter output signal SD (which is in a low intermediate frequency band) and perform a resampling operation on the analog-to-digital converter output signal SD to generate and output a data sequence input DS IN (which is in a baseband frequency band), e.g., the sampling rate (i.e., the number of samples per second) of the data sequence input DS IN is lower than the sampling rate (i.e., the number of samples per second) of the analog-to-digital converter output signal SD. Figure 2 FIG. 1 is a schematic diagram of a pre-processor circuit according to an embodiment of the present application. Figure 1 The pre-processor circuit 110 shown can be implemented using Figure 2 The pre-processor circuit 200 shown can be implemented. The pre-processor circuit 200 includes a filter 202, an intermediate frequency wipe off (IWO) circuit 204, and a linear interpolator / decimator circuit 206. The filter 202 and the intermediate frequency wipe off circuit 204 are configured to perform signal processing on the analog-to-digital converter output signal SD to generate a digital intermediate frequency signal SDBB. The linear interpolator / decimator circuit 206 includes a linear interpolator and / or a linear decimator, which is configured to perform a rate conversion on the digital intermediate frequency signal SDBB having a higher sampling rate to generate the data sequence input DS IN having a lower sampling rate to meet the requirements of a subsequent digital signal processing stage (e.g., the pre-sampler circuit 112). For example, the sampling rate of the analog-to-digital converter output signal SD is 85 MHz (megahertz), and the sampling rate of the data sequence input DS IN is 20 MHz, however, this is only illustrative and not limiting of the present application.

[0018] The pre-fetcher circuit 112 includes a sample memory 128. The pre-fetcher circuit 112 is configured to receive the data sequence input DS IN and store a plurality of data samples of the data sequence input DS IN in the sample memory 128 on a sample-by-sample basis. In addition, the pre-fetcher circuit 112 is further configured to generate and output the data sequence output DS OUT based on the plurality of data samples stored in the sample memory 128. In the present embodiment, the maximum number of data samples stored in the sample memory 128 is greater than the number of samples of a local copy generated by the code generator circuit 114 in a unit correlation time (e.g., 1 millisecond (ms)). For example, in a unit correlation time, a correlation operation is performed on a 1 ms long local copy and a 1 ms long data sequence to generate a correlation result. The sample memory 128 is sized to hold 2 ms of data samples, such that 2 ms of data samples stored in the sample memory 128 can support multiple (4) data interleaving correlation operations with the same local copy, achieving maximum utilization of input data, higher input efficiency, and lower power consumption.

[0019] Figure 3 FIG. 1 shows a pre-fetcher circuit according to an embodiment of the present application. Figure 1 The pre-fetcher circuit 112 shown in FIG. 1 can be implemented using Figure 3 The pre-fetcher circuit 300 shown in FIG. 3 can be implemented. The pre- fetcher circuit 300 includes a write pointer controller 302, a read pointer controller 304, an input buffer 306, a sample memory 308, and a selector 310. In the present embodiment, the sample memory 308 can be a first-in first-out (FIFO) buffer capable of storing 2 ms of data samples (i.e., data samples in a 2 ms period) and includes a plurality of memory blocks (labeled "Memory 0," "Memory 1," "Memory 2," "Memory 3," "Memory 4," "Memory 5," "Memory 6," and "Memory 7"), each of which is configured to temporarily store 0.25 ms of data samples. The input buffer 306 is configured to receive a plurality of data samples of the data sequence input DS IN on a sample-by-sample basis. The write pointer controller 302 controls the sequential writing of 0.25 ms of data samples in each memory block. The read pointer controller 304 controls the reading of 1 ms of data samples from the four memory blocks in the sample memory 308. In the present embodiment, as shown in FIG. 3, the write pointer controller 302 and the read pointer controller 304 are configured to control the writing and reading of data samples in the sample memory 308 in a round-robin manner.Figure 4 As shown, the sample memory 308 allows for four data interleaving modes with offsets of 0 ms, 0.25 ms, 0.5 ms, and 0.75 ms. The extra 0.25 ms of data samples is reserved to prevent data corruption due to racing between reading and writing. For example, different offsets can be selected one at a time, and when the offset of 0 ms is selected, a 1 ms data sequence DS_1 is read from the first-in-first-out buffer (i.e., the sample memory 308) as part of the data sequence output DS_OUT; when the offset of 0.25 ms is selected, the next 1 ms data sequence DS_2 is read from the first-in-first-out buffer (i.e., the sample memory 308) as part of the data sequence output DS_OUT; when the offset of 0.5 ms is selected, the next 1 ms data sequence DS_3 is read from the first-in-first-out buffer (i.e., the sample memory 308) as part of the data sequence output DS_OUT; and when the offset of 0.75 ms is selected, the next 1 ms data sequence DS_4 is read from the first-in-first-out buffer (i.e., the sample memory 308) as part of the data sequence output DS_OUT. As shown, the consecutive data sequences DS_1 and DS_2 have overlapping data samples read from the same memory location (e.g., the same memory block) in the first-in-first-out buffer (i.e., the sample memory 308), the consecutive data sequences DS_2 and DS_3 have overlapping data samples read from the same memory location (e.g., the same memory block) in the first-in-first-out buffer (i.e., the sample memory 308), and the consecutive data sequences DS_3 and DS_4 have overlapping data samples read from the same memory location (e.g., the same memory block) in the first-in-first-out buffer (i.e., the sample memory 308). Figure 4 As shown, the consecutive data sequences DS_1 and DS_2 have overlapping data samples read from the same memory location (e.g., the same memory block) in the first-in-first-out buffer (i.e., the sample memory 308), the consecutive data sequences DS_2 and DS_3 have overlapping data samples read from the same memory location (e.g., the same memory block) in the first-in-first-out buffer (i.e., the sample memory 308), and the consecutive data sequences DS_3 and DS_4 have overlapping data samples read from the same memory location (e.g., the same memory block) in the first-in-first-out buffer (i.e., the sample memory 308).

[0020] Figure 5 is a diagram of data flow based on four data interleaving modes according to an embodiment of the present application. Each region marked with a bold line indicates that a baseband signal is being written to a certain memory block of the plurality of memory blocks configured in the sample memory 308. After 1 ms of data samples are available in the sample memory 308 for use, 1 ms of data samples can be read from the sample memory 308 as part of the data sequence output DS_OUT for subsequent signal processing (e.g., a fast Fourier transform).

[0021] The code generator circuit 114 is configured to generate and output a local replica output Code_OUT, which can include samples of a plurality of PRN codes. The Doppler shift of a satellite signal is caused by the relative motion between the GNSS receiver and the GNSS satellite, thus, the GNSS baseband received signal is subject to Doppler effects, including Code Doppler and Carrier Doppler. The GNSS receiver system-on-chip 100 is capable of handling Doppler effects to improve the acquisition performance, for example, the code generator circuit 114 can be implemented by a code generator circuit with Code Doppler compensation and Carrier Doppler compensation, thus, the Code Doppler compensation and the Carrier Doppler compensation can be jointly implemented by the local replica output Code_OUT generated by the code generator circuit 114, in other words, the code generator circuit 114 is capable of performing Code Doppler compensation and Carrier Doppler compensation simultaneously when generating the local replica output Code_OUT, thus, the Code Doppler compensation and the Carrier Doppler compensation are jointly considered to set the final local replica output Code_OUT.

[0022] As Figure 1As shown, the GNSS receiver system SoC 100 has only one pair of LC-FFT circuit 118 and LC-IFFT circuit 120. The LC-FFT circuit 118 and LC-IFFT circuit 120 are implemented using individual independent circuits to achieve better signal processing performance. There are many fast Fourier transform algorithms and inverse fast Fourier transform algorithms available for real-time applications, for example, the LC-FFT circuit 118 and LC-IFFT circuit 120 can employ variable input length, radix 24, and pipelined single-delay-feedback for frequency domain signal processing. For example, the LC-FFT circuit 118 can include a plurality of N2-point decimation in frequency (DIF) FFT circuits followed by an N1-point DIF FFT circuit; and the LC-IFFT circuit 120 can include an N1-point decimation in time (DIT) IFFT circuit followed by a plurality of N2-point DIT IFFT circuits. In addition, data stream and twiddle factor optimization can further reduce / eliminate extra data memory. In some embodiments of the present application, the LC-FFT circuit 118 does not have index mapping logic and input memory, and the LC-IFFT circuit 120 does not have index mapping logic and output memory, in addition, coefficient data memory can be minimized, and non-trivial computation complexity can be minimized.

[0023] Since the GNSS receiver system SoC 100 has only one pair of LC-FFT circuit 118 and LC-IFFT circuit 120, the GNSS receiver system SoC 100 employs a hardware sharing technique. Figure 6 is a schematic diagram of the GNSS receiver system SoC 100 performing real-time signal processing according to an embodiment of the present application. The scheduler 115 is assumed to have low power consumption, low area cost, and real-time adjustment characteristics. The pair of LC-FFT circuit 118 and LC-IFFT circuit 120 can have maximum hardware component sharing to complete millisecond-level real-time signal processing. Further details of the hardware sharing technique are as follows.

[0024] Multiplexer circuit 116 has a first input port (labeled "0"), a second input port (labeled "1"), and an output port. LC-FFT circuit 118 is coupled to the output port of multiplexer circuit 116 and is used to receive the multitasking output M_OUT. Presampler circuit 112 generates and outputs a data sequence output DS_OUT to the first input port of multiplexer circuit 116. Code generator circuit 114 generates and outputs a local copy output Code_OUT to the second input port of multiplexer circuit 116. Assume that scheduler 115 is coupled to multiplexer circuit 116, presampler circuit 112, and code generator circuit 114. Under the coordination of the assumed scheduler 115, the LC-FFT circuit 118 is shared between the presampler circuit 112 and the code generator circuit 114 via the multiplexer circuit 116. Specifically, the scheduler 115 generates and outputs control signal C1 to the multiplexer circuit 116, control signal C2 to the code generator circuit 114, and control signal C3 to the presampler circuit 112. Control signal C2 indicates when the code generator circuit 114 should output a local copy output Code_OUT. Control signal C3 indicates when the code generator circuit 114 should output a data sequence output DS_OUT. Control signal C1 can serve as a selection control signal; for example, the multiplexer circuit 116 may couple its output port to a first input port when C1=0, and couple its output port to a second input port when C1=1. When the multiplexer circuit 116 is controlled by C1=0, it may couple its output port to a second input port for a period of time (e.g., Figure 6 After outputting a baseband input (provided by the presampler circuit 112) to the LC-FFT circuit 118 within T0~T1, it is assumed that the scheduler 115 can then output a baseband input (provided by the presampler circuit 112) to the LC-FFT circuit 118 within subsequent time periods (e.g., Figure 6 Within T1~T2, T2~T3, T3~T4, and T4~T5, C1=1 is set, thereby allowing the same baseband input to perform correlation operations with multiple code sequences used for acquisition. After performing correlation operations with the same baseband input and multiple code sequences, the incoherent integration memory 126 can store multiple hypothesis results, where each hypothesis result is obtained from a correlation operation within one unit correlation operation time.

[0025] exist Figure 6 During the time period T0 to T1, it is assumed that the scheduler 115 is used to set C1=0, and the LC-FFT circuit 118 is used to receive a data sequence output M_OUT=DS_OUT (labeled as "baseband signal") from the sample memory 128 of the presampler circuit 112.

[0026] exist Figure 6During the next time period T1 to T2, it is assumed that the scheduler 115 is used to set C1=1; and the LC-FFT circuit 118 is used to generate a baseband spectrum output BSFFT (labeled as "baseband spectrum") based on the data sequence output DS_OUT (labeled as "baseband signal") received during the previous time period T0 to T1, write the baseband spectrum output BSFFT (labeled as "baseband spectrum") into the spectrum memory 124 for subsequent use, and receive a local copy output M_OUT=Code_OUT (labeled as "local copy #0") from the code generator circuit 114.

[0027] exist Figure 6 During the next time period T2-T3, it is assumed that the scheduler 115 is used to set C1=1; the LC-FFT circuit 118 is used to generate a code spectrum output CSFFT (labeled "code spectrum #0") based on the local copy output Code_OUT (labeled "local copy #0") received during the previous time period T1-T2, and receives the next local copy output M_OUT=Code_OUT (labeled "local copy #1") from the code generator circuit 114; and the correlation circuit 122 is used to read the baseband spectrum output BSFFT (labeled "baseband spectrum") from the spectrum memory 124, and perform correlation operation on the baseband spectrum output BSFFT (labeled "baseband spectrum") and the code spectrum output CSFFT (labeled "code spectrum #0") to generate a correlation spectrum output CORFFT (labeled "correlation spectrum #0").

[0028] exist Figure 6During the next time period T3-T4, it is assumed that the scheduler 115 is used to set C1=1; the LC-FFT circuit 118 is used to generate a code spectrum output CSFFT (labeled "code spectrum #1") based on the local copy output Code_OUT (labeled "local copy #1") received during the previous time period T2-T3, and receives the next local copy output M_OUT=Code_OUT (labeled "local copy #2") from the code generator circuit 114; the correlation circuit 122 is used to read the same baseband spectrum output BSFFT (labeled "baseband spectrum") from the spectrum memory 124, and to process the baseband spectrum output B... The SFFT (labeled "fundamental frequency spectrum") and code spectrum output CSFFT (labeled "code spectrum #1") perform correlation operations to produce a correlation spectrum output CORFFT (labeled "correlation spectrum #1"); while the LC-IFFT circuit 120 is used to convert the correlation spectrum output CORFFT (labeled "correlation spectrum #0") output by the correlation circuit 122 into a correlation result CORIFFT (labeled "correlation result #0"), and store the correlation result CORIFFT (labeled "correlation result #0") in the incoherent integration memory 126 as a first hypothesis result for further processing.

[0029] exist Figure 6 During the next time period T4-T5, assuming scheduler 115 is used to set C1=1; LC-FFT circuit 118 is used to generate a code spectrum output CSFFT (labeled "code spectrum #2") based on the local copy output Code_OUT (labeled "local copy #2") received during the previous time period T3-T4, and receives the next local copy output M_OUT=Code_OUT (labeled "local copy #3") from code generator circuit 114; correlation circuit 122 is used to read the same baseband spectrum output BSFFT (labeled "baseband spectrum") from spectrum memory 124, and perform BSFFT on the baseband spectrum output BSFFT. The FFT (labeled "fundamental frequency spectrum") and the code spectrum output CSFFT (labeled "code spectrum #2") perform correlation operations to generate a correlation spectrum output CORFFT (labeled "correlation spectrum #2"); and the LC-IFFT circuit 120 is used to convert the correlation spectrum output CORFFT (labeled "correlation spectrum #1") output by the correlation circuit 122 into a correlation result CORIFFT (labeled "correlation result #1"), and store the correlation result CORIFFT (labeled "correlation result #1") in the incoherent integration memory 126 as a second hypothesis result for further processing.

[0030] The microcontroller unit 108 provides fundamental frequency signal processing. For example, depending on the sensitivity requirements, the microcontroller unit 108 can perform incoherent summation / integration on the correlation result CORIFFT. Specifically, the correlation result CORIFFT may contain multiple correlation values, each of which is generated within a unit correlation operation time (e.g., 1 millisecond), and the microcontroller unit 108 can perform incoherent summation / integration to accumulate the multiple correlation values. However, this is only an example and is not intended to limit the invention. For example, the post-correlation integration performed by the microcontroller unit 108 may be coherent integration.

[0031] In this embodiment, the microcontroller unit 108 is used to control the receiver acquisition and tracking via its firmware (FW). Specifically, the operation configuration of the hardware function blocks of the baseband processor 106 can be adaptively adjusted in real time by the FW running on the microcontroller unit 108. In this way, the GNSS receiver system single chip 100 can provide flexibility between performance scalability and power efficiency when acquiring / tracking highly complex GNSS signals. For example, with the assistance of hardware and firmware co-design, the FW executed on the microcontroller unit 108 can adaptively adjust the hypothetical scheduling configuration of the hypothetical scheduler 115 in real time. Therefore, the number of satellite vehicles (SVs) to be acquired / tracked and / or the number of channels to be acquired / tracked (e.g., lower-band data channels, lower-band pilot channels, upper-band data channels, and upper-band pilot channels) can be adaptively adjusted according to different operating scenarios. In some embodiments of the invention, the operating frequency of the correlation circuit 122 can also be adaptively adjusted according to different operating scenarios.

[0032] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

[0033] Symbol Explanation

[0034] 100: Global Navigation Satellite System Receiver System Single Chip

[0035] 102: Radio Frequency Front End

[0036] 104: Analog-to-digital converter

[0037] 106: Baseband Processor

[0038] 108: Microcontroller Unit

[0039] 110, 200: Preprocessor circuitry

[0040] 112, 300: Presampler circuit

[0041] 114: Code Generator Circuit

[0042] 115: Assume a scheduler

[0043] 116: Multiplexer circuit

[0044] 118: Low-complexity Fast Fourier Transform Circuit

[0045] 120: Low-complexity inverse fast Fourier transform circuit

[0046] 122: Correlation Circuit

[0047] 124: Spectrum Memory

[0048] 126: Incoherent Integral Memory

[0049] 128, 308: Sample memory

[0050] 202: Filter

[0051] 204: Intermediate Frequency Eraser Circuit

[0052] 206: Linear interpolator / decimator circuit

[0053] 302: Write to pointer controller

[0054] 304: Read pointer controller

[0055] 306: Input buffer

[0056] 310: Selector

[0057] SIF: Low-to-medium frequency signal

[0058] SD: Analog-to-digital converter output signal

[0059] DS_IN: Data sequence input

[0060] DS_OUT: Data sequence output

[0061] Code_OUT: Local copy output

[0062] M_OUT: Multitasking output

[0063] BSFFT: Baseband Spectrum Output

[0064] CSFFT: Code Spectrum Output

[0065] CORFFT: Correlation Spectrum Output

[0066] CORIFFT: Correlation Results

[0067] C1, C2, C3: Control signals

[0068] FW: Firmware

[0069] SDBB: Digital Baseband Signal

Claims

1. A global navigation satellite system receiver, comprising: a multiplexer circuit having a first input port, a second input port, and an output port; a fast Fourier transform circuit coupled to the output port; a pre-sampler circuit to generate and output a data sequence output to the first input port of the multiplexer circuit; a code generator circuit to generate and output a local replica output to the second input port of the multiplexer circuit; and a hypothesis scheduler coupled to the multiplexer circuit, the pre-sampler circuit, and the code generator circuit, wherein the fast Fourier transform circuit is shared between the pre-sampler circuit and the code generator circuit through the multiplexer circuit under coordination of the hypothesis scheduler.

2. The global navigation satellite system receiver of claim 1, wherein the fast Fourier transform circuit is to generate a baseband spectrum output from the data sequence output and a code spectrum output from the local replica output; and the global navigation satellite system receiver further comprises: a spectrum memory to store the baseband spectrum output outputted by the fast Fourier transform circuit; and a correlation circuit to receive the code spectrum output outputted by the fast Fourier transform circuit and the baseband spectrum output outputted by the spectrum memory, and to perform a correlation operation on the baseband spectrum output and the code spectrum output to generate a correlation spectrum output.

3. The global navigation satellite system receiver of claim 2, further comprising: an inverse fast Fourier transform circuit to convert the correlation spectrum output to a correlation result, wherein the inverse fast Fourier transform circuit and the fast Fourier transform circuit are individual independent circuits.

4. The global navigation satellite system receiver of claim 3, wherein the fast Fourier transform circuit does not have index mapping logic circuit and input memory, and the inverse fast Fourier transform circuit does not have index mapping logic circuit and output memory.

5. The global navigation satellite system receiver of claim 1, further comprising: a pre-processing circuit to receive an analog-to-digital converter output signal, and to perform a resampling operation on the analog-to-digital converter output signal to generate and output a data sequence input to the pre-sampler circuit, wherein the data sequence input is at a baseband.

6. The global navigation satellite system receiver of claim 5, wherein a sampling rate of the data sequence input is lower than a sampling rate of the analog-to-digital converter output signal.

7. The global navigation satellite system receiver of claim 5, wherein the pre-sampler circuit comprises a sample memory; the pre-sampler circuit is to receive a data sequence input, and to store data samples of the data sequence input to the sample memory on a sample-by-sample basis; and a maximum number of data samples stored in the sample memory is greater than a number of samples of a local replica generated by the code generator circuit in a unit correlation operation time. ​ 8. The GNSS receiver of claim 7, wherein the data sequence output comprises a first data sequence and a second data sequence following the first data sequence, and the first data sequence and the second data sequence comprise overlapping data samples read from the same memory location in the sample memory.

9. The GNSS receiver of claim 1, wherein the code generator circuit is a code generator circuit with code Doppler compensation and carrier Doppler compensation, and the code Doppler compensation and the carrier Doppler compensation are implemented jointly through the local replica output generated by the code generator circuit.

10. The GNSS receiver of claim 1, further comprising: a microcontroller unit to control receiver acquisition and tracking through a firmware running on the microcontroller unit; wherein the firmware running on the microcontroller unit adaptively adjusts the hypothesis scheduling configuration of the hypothesis scheduler in real time.

11. A GNSS receiving method, comprising: performing a multitasking operation on a data sequence output for a pre- sampling operation and a local replica output for a code generation operation to generate a multitasking output; and performing a fast Fourier transform on the multitasking output.

12. The GNSS receiving method of claim 11, wherein the fast Fourier transform generates a baseband spectrum output from the data sequence output and a code spectrum output from the local replica output; and the GNSS receiving method further comprises: storing the baseband spectrum output to a spectrum memory; and performing a correlation operation on the code spectrum output outputted by the fast Fourier transform and the baseband spectrum output read from the spectrum memory to generate a correlation spectrum output.

13. The GNSS receiving method of claim 12, further comprising: performing an inverse fast Fourier transform to convert the correlation spectrum output to a correlation result, wherein the inverse fast Fourier transform and the fast Fourier transform are performed by separate independent circuits.

14. The GNSS receiving method of claim 13, wherein the fast Fourier transform does not require index mapping logic circuit and input memory, and the inverse fast Fourier transform does not require index mapping logic circuit and output memory.

15. The GNSS receiving method of claim 11, further comprising: receiving an analog-to-digital converter output signal; and performing a resampling operation on the analog-to-digital converter output signal to generate and output a data sequence input to the pre-sampling operation, wherein the data sequence input is at a baseband.

16. The GNSS receiving method of claim 15, wherein a sampling rate of the data sequence input is lower than a sampling rate of the analog-to-digital converter output signal.

17. The GNSS receiving method of claim 15, wherein the pre-sampling operation comprises: receiving a data sequence input; and The plurality of data samples inputted by the data sequence are stored into a sample memory in a sample-by-sample manner, wherein a maximum number of data samples stored in the sample memory is greater than a number of samples of a local replica generated by the code generation operation in a unit correlation operation time.

18. The GNSS receiving method of claim 17, wherein the data sequence output comprises a first data sequence and a second data sequence following the first data sequence, and the first data sequence and the second data sequence comprise overlapping data samples read from the same memory location in the sample memory.

19. The GNSS receiving method of claim 11, wherein code Doppler compensation and carrier Doppler compensation are implemented jointly by the local replica output generated by the code generation operation.

20. The GNSS receiving method of claim 11, further comprising: controlling receiver acquisition and tracking by a firmware running on a microcontroller unit; wherein the multitasking operation, the prefetching operation, and the code generation operation are controlled by a hypothesis scheduler, and the firmware running on the microcontroller unit adaptively adjusts a hypothesis scheduling configuration of the hypothesis scheduler in real time.

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