Mask layout correction method, system and equipment and storage medium
By adding auxiliary patterns between and within the patterns on the photomask and performing optical proximity correction, the problem of pattern edge distortion during photolithography was solved, achieving more efficient and flexible photolithography processing and meeting the requirements of complex pattern design rules.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-05
- Publication Date
- 2026-03-10
AI Technical Summary
Existing technologies struggle to effectively correct distortion at the edges of patterns during photolithography, and optical proximity correction methods lack flexibility, failing to meet the requirements of complex pattern design rules.
Auxiliary graphics are created between and within the original graphics, and the target graphics are formed by merging them. Optical proximity correction is then performed to ensure mask regularity checks while improving the flexibility and customization of graphic design.
It improves the quality and efficiency of photolithography, meets the requirements of complex pattern design rules, and optimizes the precision and reliability of the photolithography process.
Smart Images
Figure CN121634677A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a mask layout correction method, system, apparatus and storage medium. Background Technology
[0002] A photomask is a pattern master used in photolithography processes. It consists of an opaque thin film forming a mask pattern structure on a transparent substrate, which is then transferred to the product substrate through an exposure process. Optical Proximity Correction (OPC) is a photolithography enhancement technique used in semiconductor device manufacturing to ensure that the edges of patterns involved in the manufacturing process are completely etched. OPC corrects image distortion during photolithography by moving the edges of the pattern on the photomask or adding additional polygons. Summary of the Invention
[0003] Therefore, it is necessary to provide a mask pattern correction method, system, device, and storage medium that can improve photolithography performance and offer flexible design to address the aforementioned technical problems.
[0004] In a first aspect, this disclosure provides a mask layout correction method, the method comprising:
[0005] Obtain the original layout to be photolithographically processed, and determine the original graphic corresponding to the original layout. The original graphic includes several main graphics.
[0006] A first auxiliary graphic is formed between the main graphics of the original graphic. The first auxiliary graphic is used to connect adjacent main graphics in a preset direction.
[0007] The original graphic is merged with the first auxiliary graphic to obtain the target graphic; the target map is determined based on the target graphic.
[0008] In some embodiments of this disclosure, the method further includes:
[0009] A second auxiliary graphic is formed within each main graphic of the original graphic. The second auxiliary graphic is used to connect the first auxiliary graphic corresponding to each main graphic.
[0010] The original graphic is merged with the first auxiliary graphic to obtain the target graphic, including:
[0011] The original graphic, the first auxiliary graphic, and the second auxiliary graphic are merged to obtain the target graphic.
[0012] In some embodiments of this disclosure, the preset direction includes a first direction and a second direction that are vertically set, forming a first auxiliary shape between the main shapes of the original shape, including:
[0013] Adjacent main graphics in a first direction and adjacent main graphics in a second direction are connected to form a first auxiliary graphic. In some embodiments of this disclosure, forming the first auxiliary graphic between the main graphics of the original graphic includes:
[0014] Determine the first symmetrical point of the edge of each main graphic;
[0015] Connect the first symmetrical points corresponding to adjacent main graphics to form the first auxiliary graphic.
[0016] In some embodiments of this disclosure, a first auxiliary graphic is formed between the main graphics of the original graphic, including:
[0017] Determine the endpoints of each main graphic element;
[0018] Connect the endpoints of adjacent main graphics to form the first auxiliary graphic.
[0019] In some embodiments of this disclosure, the method further includes:
[0020] Optical proximity correction is performed on the target image to obtain the corrected image;
[0021] Determining the target map based on the target graphic includes: determining the target map based on the correction graphic.
[0022] In some embodiments of this disclosure, the method further includes:
[0023] Simulation experiments were conducted on the target layout to obtain the corresponding performance parameters.
[0024] If the performance parameters do not meet the preset performance parameters, the calibration graph is updated, and the updated target layout is obtained based on the updated calibration graph; this continues until the updated target layout meets the preset performance parameters.
[0025] Secondly, this disclosure also provides a mask layout correction system, the system comprising:
[0026] The acquisition device is configured to: acquire the original layout to be photolithographically processed, and determine the original pattern corresponding to the original layout, wherein the original pattern includes several main patterns;
[0027] An auxiliary graphic adding device is configured to form a first auxiliary graphic between the main graphics of the original graphic, the first auxiliary graphic being used to connect adjacent main graphics in a preset direction;
[0028] The merging output device is configured to: merge the original graphic with the first auxiliary graphic to obtain the target graphic; and determine the target layout based on the target graphic.
[0029] Thirdly, this disclosure also provides an electronic device, including a memory and a processor, the memory storing a computer program, the processor executing the computer program to implement the steps of the method provided in any of the first aspects above.
[0030] Fourthly, this disclosure also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method provided in any of the first aspects above.
[0031] The embodiments disclosed herein may have, or at least have, the following advantages:
[0032] In this embodiment, after obtaining the original layout to be photolithographically processed, the original pattern corresponding to the original layout is first determined, wherein the original pattern includes several main patterns. Then, a first auxiliary pattern is formed between the main patterns of the original pattern, which connects adjacent main patterns in a preset direction. Finally, the original pattern and the first auxiliary pattern are merged to obtain the target pattern; the target layout is determined based on the target pattern. The mask layout correction method of this disclosure forms a first auxiliary pattern between main patterns in the original pattern that may violate photomask rule checks, in order to meet the photomask rule check requirements. This disclosure determines the position of the auxiliary pattern based on the photomask check rules, which has stronger targeting and customization, and can better adapt to complex pattern design rules. This disclosure merges the original pattern and the first auxiliary pattern to obtain the target pattern; ensures the collaborative work of the original pattern and the first auxiliary pattern during photolithography, improves the quality of the target layout during photolithography, can improve the layout flexibility of the auxiliary pattern, and optimize the photolithography process.
[0033] Details of one or more embodiments of this disclosure are set forth in the following drawings and description. Other features, objects, and advantages of this disclosure will become apparent from the specification, drawings, and claims. Attached Figure Description
[0034] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0035] Figure 1 This is a flowchart illustrating the mask layout correction method in some embodiments;
[0036] Figure 2 This is a schematic diagram of the target layout generation in some embodiments;
[0037] Figure 3This is a schematic diagram of the target layout generation in some other embodiments;
[0038] Figure 4 This is a schematic diagram showing the connection between the auxiliary graphic and the main graphic in some embodiments;
[0039] Figure 5 This is a schematic diagram showing the connection between the auxiliary graphic and the main graphic in other embodiments;
[0040] Figure 6 for Figure 4 or Figure 5 Corresponding target map diagram;
[0041] Figure 7 This is a schematic diagram showing the connection between the auxiliary graphic and the main graphic in other embodiments;
[0042] Figure 8 This is a schematic diagram showing the connection between the auxiliary graphic and the main graphic in other embodiments;
[0043] Figure 9 for Figure 7 or Figure 8 Corresponding target map diagram;
[0044] Figure 10 This is a flowchart illustrating the mask layout correction method in some other embodiments;
[0045] Figure 11 This is a schematic diagram of the structure of a mask layout correction system in one embodiment;
[0046] Figure 12 This is a diagram of the internal structure of an electronic device in one embodiment.
[0047] Explanation of reference numerals in the attached figures:
[0048] 10. Main graphic; 20. First auxiliary graphic; 30. Second auxiliary graphic; 40. Pore layer simulation profile; 50. Main correction graphic. Detailed Implementation
[0049] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.
[0051] It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.
[0052] It should be understood that when one element is considered to be "connected" to another element, it can be directly connected to the other element or connected to the other element through an intermediary element. Furthermore, in the following embodiments, "connection" should be understood as "electrical connection," "communication connection," etc., if there is a transmission of electrical signals or data between the connected objects.
[0053] It should be understood that the singular forms of “a,” “an,” and “the” can also include the plural forms unless the context clearly indicates otherwise. It should also be understood that terms such as “comprising,” “including,” or “having” specify the presence of the stated feature, whole, step, operation, component, part, or combination thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof.
[0054] This disclosure provides a mask layout correction method and system, electronic device, and storage medium, which can improve the flexibility and accuracy of auxiliary graphic design and improve the efficiency and reliability of photolithography processing.
[0055] It is understandable that during optical proximity correction of patterns in a mask layout, auxiliary patterns influence the mask patterns within the mask layout to enhance the printability of the generated patterns and reduce edge errors. The mask patterns in the mask layout are used to transfer onto the wafer during photolithography to form etched patterns; the auxiliary patterns formed in the mask layout are independent of the mask patterns and are not etched onto the wafer.
[0056] Please see Figure 1 The mask layout correction method provided in some embodiments of this disclosure may include the following steps 102 to 106.
[0057] Step 102: Obtain the original layout to be photolithographically processed and determine the original graphic corresponding to the original layout. The original graphic includes several main graphics.
[0058] Step 104: A first auxiliary graphic is formed between the main graphics of the original graphic. The first auxiliary graphic is used to connect adjacent main graphics in a preset direction.
[0059] Step 106: Merge the original graphic with the first auxiliary graphic to obtain the target graphic; determine the target layout based on the target graphic.
[0060] In this embodiment of the disclosure, after obtaining the original layout to be photolithographically processed, a mask pattern is determined on the original layout; this mask pattern is the original pattern of this disclosure. Please refer to [link to relevant documentation]. Figure 2 The original graphic was analyzed and processed to determine that it included several main graphics 10.
[0061] like Figure 2 As shown, the original layout includes multiple main graphics 10 distributed in a regular pattern. This disclosure forms a first auxiliary graphic 20 between each of the main graphics 10 in the original layout to meet the photomask rule check requirements. This first auxiliary graphic 20 is used to connect adjacent main graphics 10 in a preset direction. Finally, the original layout and the first auxiliary graphic 20 are merged and output to obtain the target layout, and the optimized target layout is determined based on the target layout.
[0062] Compared to photolithography based on the original layout, photolithography in this embodiment performs photolithography on the target layout. This embodiment forms a first auxiliary pattern 20 between main patterns 10 that might violate photomask rule checks, thus satisfying the photomask rule check requirements. This embodiment determines the position of the first auxiliary pattern 20 between the main patterns 10 according to the photomask rule checks, making it more targeted and customizable, and better adaptable to complex graphic design rules. With the target layout corrected by this embodiment, the distance between adjacent main patterns 10 after photolithography meets the photomask rule check requirements, improving the reliability of the photolithography process. The auxiliary pattern in this embodiment has high flexibility and good applicability.
[0063] Please see Figure 3 In other embodiments of this disclosure, the method further includes: forming a second auxiliary graphic 30 within each main graphic 10 of the original graphic, the second auxiliary graphic 30 being used to connect the first auxiliary graphic 20 corresponding to each main graphic 10; merging the original graphic, the first auxiliary graphic 20 and the second auxiliary graphic 30 to obtain the target graphic.
[0064] To facilitate the placement of auxiliary graphics and improve the efficiency of photolithography, when connecting the main graphics 10 in the original graphic through the first auxiliary graphics 20, a second auxiliary graphics 30 can also be set inside the main graphics 10 to connect the first auxiliary graphics 20, so that the first auxiliary graphics 20 and the second auxiliary graphics 30 form an integrated auxiliary graphics. Correspondingly, the target graphic in the target layout of this embodiment is generated by merging the original graphic, the first auxiliary graphics 20, and the second auxiliary graphics 30.
[0065] In this embodiment, for the main pattern 10 that may violate photomask rule checks, not only is a first auxiliary pattern 20 set between adjacent main patterns 10, but a second auxiliary pattern 30 is also set inside the main pattern 10, so that the first auxiliary pattern 20 and the second auxiliary pattern 30 form an integrated auxiliary pattern, satisfying the photomask rule check requirements. The correction method of this embodiment determines the auxiliary pattern according to the photomask rule check requirements, possessing stronger targeting and customization capabilities, and can better adapt to complex pattern design rules. The correction method of this embodiment greatly improves the flexibility of auxiliary pattern placement and optimizes the photolithography process.
[0066] In some specific embodiments of this disclosure, the preset direction includes a first direction and a second direction that are vertically set. Forming a first auxiliary graphic 20 between the main graphics 10 of the original graphic includes connecting adjacent main graphics 10 in the first direction and adjacent main graphics 10 in the second direction to form the first auxiliary graphic 20.
[0067] Please refer to [the original text]. Figure 2 and Figure 3 Taking into account both the efficiency of photolithography and the accuracy of the processed pattern, for a regular main pattern 10, the first and second perpendicular directions can be used as preset directions. Auxiliary patterns connecting adjacent main patterns 10 are set in the first direction and in the second direction, respectively, and the set auxiliary patterns together constitute the first auxiliary pattern 20.
[0068] like Figure 2 and Figure 3 As shown, the original layout is a square. Using the two diagonals of the original layout as a reference, a first direction and a second direction are set that are perpendicular to each other. Adjacent main graphics 10 along the first and second directions are connected. The first auxiliary graphics 20 and the original graphics are merged to form the target graphics, thus obtaining the target layout.
[0069] Furthermore, to facilitate the arrangement of the first auxiliary graphic 20, a second auxiliary graphic 30 can be set inside the main graphic 10 to connect with the first auxiliary graphic 20. During design, the first auxiliary graphic 20 and the second auxiliary graphic 30 can be arranged together to improve the generation efficiency of the auxiliary graphics of this disclosure and optimize the photolithography process.
[0070] Please see Figure 4 and Figure 5 In some exemplary embodiments of this disclosure, forming a first auxiliary graphic 20 between each main graphic 10 of the original graphic includes: determining the endpoints of each main graphic 10; and connecting the corresponding endpoints of adjacent main graphics 10 to form the first auxiliary graphic 20.
[0071] by Figure 4Taking the above example, the endpoints of the main graphic 10 are determined, and the endpoints of adjacent main graphics 10 are connected to obtain the first auxiliary graphic 20. Figure 4 The first auxiliary graphic 20, which is set in the middle structure, is located on the extension line of the diagonal of the main graphic 10. This can improve the processing efficiency of the target layout and reduce errors.
[0072] In other implementations, to improve the efficiency of laying out auxiliary graphics, such as Figure 5 As shown, a second auxiliary graphic 30 is set inside the main graphic 10, so that the first auxiliary graphic 20 and the second auxiliary graphic 30 form a whole.
[0073] Please see Figure 7 and Figure 8 In some exemplary embodiments of this disclosure, forming a first auxiliary graphic 20 between each main graphic 10 of the original graphic includes: determining a first symmetric point of the graphic edge of the main graphic 10; and connecting the first symmetric points corresponding to adjacent main graphics 10 to form the first auxiliary graphic 20.
[0074] by Figure 7 Taking the above example, a first symmetrical point is determined at the edge of the main graphic 10. The graphics on both sides of the first symmetrical point are symmetrically distributed. Connecting the first symmetrical points of adjacent main graphics 10 yields a first auxiliary graphic 20. In this embodiment, the first auxiliary graphic 20 is set on the symmetrical center line of each main graphic 10 to improve the processing efficiency of the target layout and reduce errors.
[0075] In other implementations, to improve the efficiency of laying out auxiliary graphics, such as Figure 8 As shown, a second auxiliary graphic 30 is set inside the main graphic 10, so that the first auxiliary graphic 20 and the second auxiliary graphic 30 form a whole.
[0076] Please see Figure 4 or Figure 5 or Figure 7 or Figure 8 In other embodiments of this disclosure, the method further includes: performing optical proximity correction on the target pattern to obtain a corrected pattern; and determining a target layout based on the target pattern, including: determining the target layout based on the corrected pattern.
[0077] Figure 4 and Figure 5 The original layout shown includes several regularly distributed main patterns 10. Through simulation, the pattern expected to be generated after illumination by the main patterns 10 on the original layout is represented as a simulated pore layer profile 40. That is, for... Figure 4 or Figure 5The main pattern 10 in the image, after photolithography, forms a simulated hole layer contour 40 on the wafer. To reduce errors in pattern processing, optical proximity correction is performed on the main pattern 10. This is done by moving the edges of the main pattern 10 or adding additional polygons to correct it, resulting in a corrected pattern. It can be understood that optical proximity correction of the target pattern primarily involves correcting the main pattern 10 within the target pattern to obtain a corrected main pattern 50, ensuring that the main corrected pattern 50 meets the performance requirements of photolithography.
[0078] Please continue to refer to Figures 4 to 9 , Figure 4 and Figure 7 This diagram illustrates the optical proximity correction performed after the first auxiliary pattern 20 is formed between the main patterns 10. Figure 5 and Figure 8 This diagram illustrates the optical proximity correction performed after forming a first auxiliary graphic 20 between the main graphic 10 and a second auxiliary graphic 30 inside the main graphic 10. Figure 5 and Figure 8 Combining the second auxiliary pattern 30 with the first auxiliary pattern 20 can improve the generation efficiency of auxiliary patterns and optimize the photolithography process.
[0079] Figure 6 for Figure 4 or Figure 5 A schematic diagram of the target layout corresponding to the structure. Figure 9 for Figure 7 or Figure 8 A schematic diagram of the target layout corresponding to the structure. (Refer to...) Figure 6 and Figure 9 It can be seen that in the merged target layout, the main correction graphic 50 overlaps with the second auxiliary graphic 30. It can be assumed that the setting of the second auxiliary graphic 30, while improving the efficiency of auxiliary graphic placement, has no impact on the graphics generated from the target layout.
[0080] In some further embodiments of this disclosure, the method further includes: performing a simulation experiment on the target layout to obtain the performance parameters corresponding to the target layout; if the performance parameters do not meet the preset performance parameters, updating the correction pattern and obtaining the updated target layout based on the updated correction pattern; until the updated target layout meets the preset performance parameters.
[0081] Simulation experiments are conducted on the illumination performance of the correction pattern obtained through optical proximity correction to evaluate the layout and performance of the target pattern after photolithography. The performance parameters of the simulation experiments include error verification between the photolithographically processed pattern and the preset simulated aperture layer contour 40. If the performance parameters obtained from the simulation do not meet the preset performance parameters, such as a large error between the generated pattern and the simulated aperture layer contour 40, the correction pattern is updated, and an updated target pattern is obtained based on the new correction pattern. This process continues until the performance data obtained from the simulation experiments for the updated target pattern meets the requirements. Updating the correction pattern includes optimizing the target pattern, such as adjusting auxiliary patterns, and performing optical proximity correction on the adjusted pattern to update the correction pattern and obtain the updated target pattern. This embodiment further optimizes the layout of auxiliary patterns in the target pattern through simulation experiments, improving the accuracy of the photolithography process.
[0082] Please see Figure 10 In some embodiments, a mask layout correction method is provided, including steps 1002 to 1008.
[0083] Step 1002: Obtain the original layout to be photolithographically processed, determine the original pattern on the original layout, and add auxiliary patterns inside and between the main patterns of the original pattern to obtain the target pattern.
[0084] First, obtain the original map and determine the original graphics on the original map. Figure 4 , Figure 5 or Figure 7 , Figure 8 Taking the structure as an example, the original graphic includes several main graphics 10 that are regularly distributed and have the same shape.
[0085] In this embodiment, auxiliary graphics are added between and inside the main graphic 10 that may violate the mask rule check. This is intended to improve the overall quality of the mask layout while ensuring that the MR (Mask Rule) is not violated. Violation of the mask rule will cause the generated simulated contour to not converge or the edge error to be too large, resulting in a serious deterioration of the lithography performance.
[0086] According to predetermined rules and optimization algorithms, auxiliary graphics are precisely added within the main graphic 10 and between adjacent main graphics 10 in a preset direction. (See reference...) Figure 4 or Figure 5 The method involves setting auxiliary graphics along the diagonal of the main graphic and its extension, or you can refer to... Figure 7 or Figure 8 Auxiliary graphics are set along the symmetrical centerline of the main graphic 10. Typically, for each main graphic 10, two mutually perpendicular auxiliary graphics are arranged so that the target layout can meet the mask rule inspection requirements after photolithography.
[0087] Step 1004: Perform optical proximity correction on the target image after adding auxiliary graphics to obtain the corrected image.
[0088] The target image, after the addition of auxiliary images, is corrected using an optical proximity correction method to obtain a corrected image. The corrected image includes a main corrected image 50 after correcting the main image 10, and also a corrected auxiliary image after correcting the auxiliary images. The optical proximity correction method is used to correct image distortion of the target image during the photolithography process.
[0089] Step 1006: Simulate and correct the initial layout after optical proximity correction.
[0090] The corrected initial layout is obtained based on the corrected pattern after optical proximity correction. Simulation experiments are then conducted on the initial layout to evaluate the layout and performance of the patterns within it. Based on the simulation results, the initial layout is adjusted, and the layout of auxiliary patterns is optimized to improve the layout design and performance, thereby enhancing the precision of the photolithography process.
[0091] If the simulation results do not meet the preset performance parameters, the auxiliary pattern is reset and optical proximity correction is performed to obtain a new corrected pattern. This process continues until the target layout corresponding to the updated corrected pattern meets the preset performance parameter standards after simulation. By simulating and updating the corrected pattern, the layout of the auxiliary pattern can be further optimized, improving the accuracy of the photolithography process.
[0092] Step 1008: Output the updated correction graphic to obtain the target layout.
[0093] The corrected and updated calibration pattern is output, which includes the simulated modified main calibration pattern 50 and the corrected auxiliary pattern. In this embodiment, the main pattern and the auxiliary pattern are output together to ensure that they work together to improve the quality of the target layout during photolithography.
[0094] This embodiment proposes a mask layout correction method. Auxiliary patterns are added inside and between the main pattern 10, which may violate mask rule checks, to improve pattern accuracy during photolithography and resolve mask rule violation issues. This embodiment determines the location of the auxiliary patterns based on mask check rules, offering greater targeting and customization, and better adapting to complex pattern design rules. The auxiliary pattern design method of this embodiment can better handle complex design rules, improve the layout flexibility of auxiliary patterns, better adapt to complex design rules, and optimize the photolithography process.
[0095] Please see Figure 11In some embodiments, the mask layout correction system includes: an acquisition device 1102, an auxiliary pattern adding device 1104, and a merging output device 1106. The acquisition device 1102 is configured to: acquire the original layout to be photolithographically processed; determine the original pattern corresponding to the original layout; wherein the original pattern includes a plurality of main patterns 10. The auxiliary pattern adding device 1104 is configured to: form a first auxiliary pattern 20 between each of the main patterns 10 of the original pattern; the first auxiliary pattern 20 is used to connect adjacent main patterns 10 in a preset direction. The merging output device 1106 is configured to: merge the original pattern with the first auxiliary pattern 20 to obtain a target pattern; and determine the target layout based on the target pattern.
[0096] For example, the auxiliary graphic adding device 1104 is further configured to form a second auxiliary graphic 30 within each main graphic 10 of the original graphic, the second auxiliary graphic 30 being used to connect the first auxiliary graphic 20 corresponding to each main graphic 10. The original graphic, the first auxiliary graphic 20, and the second auxiliary graphic 30 are merged to obtain the target graphic.
[0097] For example, the preset directions include a first direction and a second direction that are set vertically, and the auxiliary graphic adding device 1104 is also configured to connect adjacent main graphics in the first direction and adjacent main graphics in the second direction to form a first auxiliary graphic 20.
[0098] For example, the auxiliary graphic adding device 1104 is further configured to: determine the first symmetry point of the graphic edge of each main graphic 10; and connect the first symmetry points corresponding to adjacent main graphics 10 to form a first auxiliary graphic 20.
[0099] For example, the auxiliary graphic adding device 1104 is further configured to: determine the first symmetry point of the graphic edge of each main graphic 10; and connect the first symmetry points corresponding to adjacent main graphics 10 to form a first auxiliary graphic 20.
[0100] For example, the mask layout correction system is further configured to: perform optical proximity correction on the target pattern to obtain a corrected pattern; and determine the target layout based on the target pattern, including: determining the target layout based on the corrected pattern.
[0101] For example, the mask layout correction system is also configured to: perform a simulation experiment on the target layout to obtain the performance parameters corresponding to the target layout; if the performance parameters do not meet the preset performance parameters, update the correction pattern and obtain the updated target layout based on the updated correction pattern; until the updated target layout meets the preset performance parameters.
[0102] In the mask layout correction system provided in some of the above embodiments, the term "device" and the like used in this specification can be used to refer to computer-related entities, hardware, firmware, combinations of hardware and software, software, or software in execution. For example, "device" can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. For example, "device" can be executed from various computer-readable media on which various data structures are stored. Furthermore, in the above embodiments provided in this disclosure, it should be understood that the disclosed "device" can be implemented in other ways. For example, the devices described above are merely illustrative. For example, the division of devices is merely a logical functional division, and in actual implementation, there may be other division methods, such as multiple devices can be combined or integrated into another device, or some features can be ignored or not executed. The described interconnections can be through some interfaces, indirect coupling or communication connections between devices, and can be electrical, mechanical, or other forms. The devices described separately may or may not be physically separate. Some or all of the devices can be selected to achieve the purpose of the embodiments of this disclosure according to actual needs.
[0103] In some embodiments, this disclosure also provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the mask layout correction method involved in the above embodiments.
[0104] For example, the electronic device can be a terminal, and its internal structure diagram can be as follows: Figure 12 As shown.
[0105] This electronic device includes a processor, memory, input / output interfaces, a communication interface, a display unit, and an input device. The processor, memory, and input / output interfaces are connected via a system bus, and the communication interface, display unit, and input device are also connected to the system bus via the input / output interfaces. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The input / output interfaces are used for exchanging information between the processor and external devices. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, NFC (Near Field Communication), or other technologies. When the computer program is executed by the processor, it implements the mask layout correction method described above. The display unit is used to form a visually visible image and can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be an LCD screen or an e-ink screen. The input device of the electronic device can be a touch layer covering the display screen, or buttons, trackballs, or touchpads set on the casing of the electronic device, or external keyboards, touchpads, or mice, etc.
[0106] Those skilled in the art will understand that Figure 12 The structure shown is merely a block diagram of a portion of the structure related to the present disclosure and does not constitute a limitation on the electronic device to which the present disclosure is applied. A specific electronic device may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.
[0107] In some embodiments, this disclosure also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the mask layout correction method involved in the above embodiments.
[0108] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this disclosure can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this disclosure may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this disclosure may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.
[0109] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0110] The embodiments described above are merely illustrative of several implementations of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the scope of protection of this disclosure. Therefore, the scope of protection of this patent should be determined by the appended claims.
Claims
1. A method of mask layout modification, characterized by, The method comprises: obtaining an original layout to be processed by photolithography, and determining an original pattern corresponding to the original layout, wherein the original pattern comprises a plurality of main patterns; forming a first auxiliary pattern between each of the main patterns of the original pattern, the first auxiliary pattern being used to connect adjacent main patterns in a preset direction; merging the original pattern and the first auxiliary pattern to obtain a target pattern; and determining a target layout according to the target pattern.
2. The method of claim 1, wherein, The method further comprises: forming a second auxiliary pattern in each of the main patterns of the original pattern, the second auxiliary pattern being used to connect the first auxiliary patterns corresponding to each of the main patterns; the step of merging the original pattern and the first auxiliary pattern to obtain a target pattern comprises: merging the original pattern, the first auxiliary pattern and the second auxiliary pattern to obtain a target pattern.
3. The method according to claim 1 or 2, characterized in that, The preset direction comprises a first direction and a second direction arranged vertically, and the step of forming a first auxiliary pattern between each of the main patterns of the original pattern comprises: connecting the main patterns adjacent in the first direction and the main patterns adjacent in the second direction respectively to form the first auxiliary pattern.
4. The method of claim 1, wherein, The step of forming a first auxiliary pattern between each of the main patterns of the original pattern comprises: determining a first symmetry point of a pattern edge of each of the main patterns; connecting the first symmetry points corresponding to adjacent main patterns to form the first auxiliary pattern.
5. The method of claim 1, wherein, The step of forming a first auxiliary pattern between each of the main patterns of the original pattern comprises: determining an end point of each of the main patterns; connecting the end points corresponding to adjacent main patterns to form the first auxiliary pattern.
6. The method of claim 1, wherein, The method further comprises: performing optical proximity correction on the target pattern to obtain a corrected pattern; the step of determining a target layout according to the target pattern comprises determining the target layout according to the corrected pattern.
7. The method of claim 6, wherein, The method further comprises: performing simulation experiments on the target layout to obtain a performance parameter corresponding to the target layout; if the performance parameter does not meet a preset performance parameter, updating the corrected pattern, and obtaining an updated target layout according to the updated corrected pattern; and repeating the above steps until the updated target layout meets the preset performance parameter.
8. A mask layout modification system, characterized by, The system comprises: an obtaining device configured to obtain an original layout to be processed by photolithography, and determine an original pattern corresponding to the original layout, wherein the original pattern comprises a plurality of main patterns; an auxiliary pattern adding device configured to form a first auxiliary pattern between each of the main patterns of the original pattern, the first auxiliary pattern being used to connect adjacent main patterns in a preset direction; a merging and outputting device configured to merge the original pattern and the first auxiliary pattern to obtain a target pattern; and determine a target layout according to the target pattern. 9.An electronic device comprising a memory and a processor, the memory storing a computer program, wherein, The processor implements the steps of the method of any one of claims 1 to 7 when executing the computer program.
10. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program, when executed by the processor, implements the steps of the method of any one of claims 1 to 7.