Controller backboard system based on PCIE bus and control method thereof

Abstract

The invention discloses a controller backboard system based on a PCIE (Peripheral Component Interface Express) bus. The controller backboard system comprises a main control module, a backboard connector, an expansion IO (Input / Output) module and a PCIE switching module, the main control module outputs a plurality of PCIE interfaces and communicates with the expansion IO module through the backboard connector; the expansion IO module adopts a PCIE (Peripheral Component Interface Express) interface chip to convert a serial signal into a parallel bus signal for the MCU processor to access; and when the number of the interfaces is insufficient, more interfaces are expanded through the PCIE switching module. The PCIE bus is adopted as a backplane communication basis, and the high-speed serial point-to-point characteristic of the PCIE bus is utilized, so that bandwidth scrambling and arbitration delay of a traditional serial bus are avoided, and the data transmission rate and the system response speed are remarkably improved; meanwhile, the interface expansion capability is enhanced by introducing the PCIE switching module, multi-stage connection is supported, and the problem that the expansibility of an existing backboard system is limited is solved. The system is suitable for the field of industrial control, and meets the core requirements of a high-performance intelligent controller on high speed, low delay and strong expansibility.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of industrial control, in particular to a high-performance intelligent controller backplane system based on a PCIE bus and a control method thereof, which is used to improve the data transmission speed, response speed and module expansion capability of a control system. BACKGROUND

[0002] In an industrial control system, a controller backplane bus is a key interface for connecting a master module and an expansion module, and its performance directly affects the response speed, reliability and expandability of the entire system. Existing backplane buses mostly use serial communication interfaces such as IIC, SPI, CAN, UART or Ethernet. These interfaces have low hardware costs and simple protocols, but have problems such as slow communication rate, short communication distance, susceptibility to interference, low data transmission efficiency and poor real-time performance. For example, although Ethernet communication has a high rate, the overall communication speed cannot meet the real-time requirements of high-performance control systems due to the need for single-chip microcomputer intervention for protocol processing. SUMMARY

[0003] The present application aims to solve the technical problems of slow communication speed, high response delay, limited expansion capability and insufficient reliability of existing controller backplane systems, and proposes a controller backplane system based on a PCIE bus and a control method thereof. To achieve the above-mentioned purpose, the technical solution adopted by the present application includes:

[0004] In a first aspect, the present application provides a controller backplane system based on a PCIE bus, comprising:

[0005] a master module configured to output multiple PCIE bus interfaces;

[0006] a backplane connector for connecting an expansion IO module and the master module;

[0007] at least one expansion IO module in communication with the master module through the backplane connector; each expansion IO module includes a PCIE interface chip and an MCU processor, the PCIE interface chip converts a PCIE bus interface into a parallel data address bus interface for use by the MCU processor when accessing the PCIE interface chip;

[0008] a PCIE switching module for expanding PCIE interfaces by being connected to the backplane connector when the number of PCIE channels of the master module is insufficient to support more expansion IO modules;

[0009] wherein the master module, expansion IO module and PCIE switching module communicate data through a PCIE bus to achieve data transmission and module expansion.

[0010] Further, the PCIE switching module comprises a PCIE switching chip and an ARM processor.

[0011] The PCIE switching chip is used for expanding a PCIE interface and realizing data switching.

[0012] The ARM processor is used for at least one of module configuration management, channel dynamic data management and hot plug management.

[0013] Further, the expansion IO module further comprises an input and output interface circuit, which is used for realizing input or output functions of digital or analog signals.

[0014] The PCIE interface chip of the expansion IO module is a PCIE bus general interface chip.

[0015] The PCIE bus general interface chip decodes PCIE bus signals.

[0016] The MCU processor communicates and interacts data with the PCIE bus interface chip through the PCIE bus general interface chip, so as to control the input and output interface circuit.

[0017] Further, the host control module is configured with a real-time operating system and a lightweight communication protocol, which is used for realizing real-time transmission and control of data, and synchronizing operations of each module through a distributed clock mechanism.

[0018] Further, the controller backplane system supports a hot plug function.

[0019] The expansion IO module and the PCIE switching module can be inserted or removed when the controller backplane system is running, and report module states and slot information to the host control module through a PCIE bus.

[0020] Further, communication between the host control module and the expansion IO module adopts a point-to-point mode, each expansion IO module exclusively occupies a PCIE interface, so as to avoid bandwidth contention and arbitration delay.

[0021] Further, the host control module dynamically generates a system topology according to slot information and function information reported by the expansion IO module and the PCIE switching module, and issues configuration parameters to optimize a communication path.

[0022] Further, a rear stage of the PCIE switching module can continue to connect the expansion IO module or other PCIE switching modules to form a multi-stage expansion structure.

[0023] Further, the PCIE bus adopts a PCIE 2.0 protocol, and a communication rate of each X1 interface is 500 MB / s.

[0024] Secondly, embodiments of this application provide a control method for the controller backplane system described in any of the foregoing claims, comprising:

[0025] The main control module detects the downstream connected extended I / O modules and PCIe switching modules to obtain module information;

[0026] The extended I / O module and the PCIe switching module report module information to the main control module through the PCIe bus, and the main control module performs module verification.

[0027] After the verification is successful, the main control module sends configuration and control information to the extended I / O module and the PCIe switching module based on the module information;

[0028] The main control module communicates with the extended I / O module in real time to control the extended I / O module to perform input and output functions.

[0029] When the input / output function, communication, or bus of the extended I / O module malfunctions, the extended I / O module reports the fault information to the main control module through the PCIe bus, and the main control module handles the fault.

[0030] This application provides a controller backplane system based on a PCIe bus, including a main control module, a backplane connector, an expansion I / O module, and a PCIe switching module. The main control module outputs multiple PCIe interfaces, communicating with the expansion I / O modules through the backplane connector. The expansion I / O modules use PCIe interface chips to convert serial signals into parallel bus signals for access by the MCU processor. When the number of interfaces is insufficient, more interfaces are added through the PCIe switching module. By using the PCIe bus as the basis for backplane communication, leveraging its high-speed serial point-to-point characteristics, the bandwidth contention and arbitration delays of traditional serial buses are avoided, thus significantly improving data transmission rate and system response speed. Simultaneously, the introduction of the PCIe switching module enhances interface expansion capabilities, supports multi-level connections, and solves the problem of limited scalability in existing backplane systems. This system is suitable for industrial control fields, meeting the core requirements of high-performance intelligent controllers for high speed, low latency, and strong scalability. Attached Figure Description

[0031] Figure 1 A schematic diagram of a controller backplane system based on a PCIe bus provided for an embodiment of this application;

[0032] Figure 2 A schematic diagram illustrating the connection between the main control module and the extended I / O module provided in an embodiment of this application;

[0033] Figure 3 A schematic diagram illustrating the connection between the main control module and the expansion I / O module with a PCIe switching module provided in an embodiment of this application;

[0034] Figure 4 This is a flowchart illustrating a control method for the aforementioned controller backplane system provided in an embodiment of this application. Detailed Implementation

[0035] To enable those skilled in the art to better understand the technical solutions of this application, exemplary embodiments of this application are described below with reference to the accompanying drawings, including various details of the embodiments of this application to aid understanding. These should be considered merely exemplary. Therefore, those skilled in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this application. Similarly, for clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description. Unless otherwise specified, the various embodiments of this application and the features within those embodiments can be combined with each other.

[0036] As used herein, the term “and / or” includes any and all combinations of one or more of the associated enumerated entries. The terminology used herein is for describing particular embodiments only and is not intended to limit the application. As used herein, the singular forms “a” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprising” and / or “made of” are used in this specification, the presence of the stated features, integrals, steps, operations, elements, and / or components is specified, but the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof is not excluded. Terms such as “connected” or “linked” are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect.

[0037] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It should also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having the meaning consistent with their meaning in the context of the relevant art and this application, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined herein.

[0038] The controller backplane is the data communication interface between the controller and the expansion module. The controller backplane system determines the response speed and expansion capability of the controller system, and affects the functionality, performance and reliability of the entire control system. It is a core key technology in the field of industrial control.

[0039] Currently, most controller backplane buses use serial communication interfaces. Serial buses have fewer signal lines, lower hardware costs, simpler communication protocols, and are easier to implement. Commonly used serial communication interfaces for industrial backplane buses include IIC, SPI, CAN, UART, and Ethernet.

[0040] Conventional general-purpose processing chips integrate the aforementioned peripheral interfaces. However, IIC, SPI, CAN, and UART interfaces have slow communication rates and short communication distances. They are also susceptible to interference when used for local bus expansion and cannot meet the communication and response speed requirements of a local bus. While Ethernet offers fast communication speeds, the need for microcontroller intervention during protocol processing results in slow data processing speeds and low data transmission efficiency, ultimately leading to slow overall communication speeds that fail to meet real-time requirements.

[0041] PCIe (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard with advantages such as high bandwidth, low latency, point-to-point full-duplex communication, and flexible expansion. As industrial control systems increasingly demand high-performance intelligent controllers and their expansion modules, there is an urgent need for a new backplane system based on the PCIe bus to address the shortcomings of existing technologies. PCIe is a high-speed serial computer expansion bus standard that uses serial differential signals, providing high-speed transmission performance. The single-channel rate has increased from 2.5 GT / s in PCIe 1.0 to 32 GT / s in PCIe 5.0. It employs a point-to-point access mode, avoiding bandwidth contention and arbitration latency, enabling full-duplex communication and concurrent access by multiple devices, while also possessing flexible scalability and reliability.

[0042] As industrial control systems place increasingly higher demands on high-performance intelligent controllers and their expansion modules for high bandwidth, low latency, and strong scalability, higher standards are being set for the communication speed, response time, and reliability of the backplane bus. Based on the advantages of PCIe as a bus for transmission, this application designs a high-performance intelligent controller backplane system based on the PCIe bus.

[0043] refer to Figures 1-3 One embodiment of this application proposes a controller backplane system based on the PCIe bus. The controller backplane system may specifically include a main control module, a backplane connector, at least one expansion I / O module, and a PCIe switching module.

[0044] The main control module is configured to output multiple PCIe bus interfaces. Specifically, the main control module uses a processor with a PCIe 2.0 interface, responsible for communicating with subsequent expansion I / O modules via the backplane bus. Through a real-time operating system, integrated lightweight communication protocols, and a distributed clock mechanism, it ensures real-time data transmission and control, meeting the core requirements of the controller backplane system for high performance, low latency, high reliability, and flexible expansion. More specifically, the main control module runs the FreeRTOS real-time operating system, integrating a custom lightweight protocol stack to handle PCIe communication and data distribution. The distributed clock mechanism distributes synchronization signals through the PCIe bus, ensuring that the time deviation of all expansion I / O modules is less than 1 microsecond. This ensures real-time data communication and precise synchronization, meeting the requirements of industrial control for low latency and high-precision timing, such as motion control and high-speed data acquisition. The PCIe bus uses the PCIe 2.0 protocol, with a communication rate of 500 MB / s for each X1 interface. Specifically, the main control module's PCIe interface conforms to the PCIe 2.0 standard, with each X1 lane providing 500 MB / s bandwidth for transmitting control data and I / O status information. This provides a high-speed communication rate, ensuring the system's high bandwidth performance, making it suitable for industrial applications involving large data volume transmissions, such as image processing or high-speed data acquisition.

[0045] Backplane connectors are used to connect expansion I / O modules and the main control module.

[0046] At least one expansion I / O module communicates with the main control module via a backplane connector. Each expansion I / O module includes a PCIe interface chip and an MCU processor. The PCIe interface chip converts the PCIe bus interface into a parallel data and address bus interface for the MCU processor to access. Specifically, the expansion I / O module uses an MCU processor, a PCIe bus universal interface chip (a standard type of PCIe interface chip), and input / output interface circuitry. The PCIe bus universal interface chip decodes the high-speed PCIe bus signals, converting them into simplified data, address, and control signals. The MCU processor communicates and interacts with the PCIe bus interface chip through this universal interface chip, thereby controlling the input / output interface circuitry of the expansion I / O module to achieve digital or analog signal input or output functions. More specifically, the expansion I / O module uses Nanjing Qinheng's CH368 PCIe bus interface chip, which converts PCIe 2.0 X1 signals into a parallel data bus (16-bit data, 8-bit address) and control signals (such as chip select and read / write enable). The MCU processor (such as an ARM Cortex-M4) reads sensor data or controls actuators through this bus, enabling digital input / output functions. This simplifies the design of the extended I / O module, enabling the MCU to efficiently access the PCIe bus, thereby reducing development complexity while maintaining high-speed data exchange capabilities, making it suitable for a variety of industrial I / O applications.

[0047] Communication between the main control module and the expansion I / O modules adopts a point-to-point method, with each expansion I / O module having its own dedicated PCIe interface to avoid bandwidth contention and arbitration delays. Specifically, each PCIe x1 interface of the main control module is directly connected to one expansion I / O module, forming an independent communication link. Data is encapsulated and transmitted using the PCIe protocol, eliminating the need for arbitration and enabling full-duplex communication. This embodiment utilizes the point-to-point characteristics of PCIe to ensure dedicated bandwidth and low-latency communication for each module, thereby improving system response speed and concurrent processing capabilities.

[0048] When the number of PCIe lanes in the main control module is insufficient, the PCIe switching module expands the PCIe interface by connecting to the backplane connector to support more expansion I / O modules. Specifically, the PCIe switching module is mainly used to expand the PCIe interfaces of the controller backplane system. When the system needs to expand with more expansion I / O modules, the number N of PCIe 2.0 x1 bus interfaces output by the main control module is limited. Therefore, an M-lane PCIe switching module needs to be added at the last-stage PCIe backplane connector to achieve the expansion of the M-lane PCIe bus. The subsequent stages of the PCIe switching module can continue to expand with M more expansion I / O modules, thus significantly improving the system's scalability. The PCIe switching module can be composed of a PCIe switching chip and an MCU processor. The PCIe switching chip is mainly used to expand the number of PCIe interfaces and perform high-speed real-time data exchange. Multiple subsequent expansion I / O modules can be connected to the same PCIe switching chip and controlled hierarchically, enabling data communication between the main control module and the expansion I / O modules. The MCU processor can be an ARM processor, which is used for module configuration management, channel dynamic data management, and hot-swapping management of the expansion I / O modules, achieving real-time and reliable control of the expansion I / O modules. More specifically, a PCIe switch chip (such as Broadcom's PEX8608) expands one PCIe x1 interface of the main control module into seven PCIe x1 interfaces, each connecting to an expansion I / O module. An ARM processor (such as a Cortex-A5) runs embedded Linux, monitoring the insertion and removal events of the expansion I / O modules, dynamically allocating bandwidth and processing configuration data. This expands the number of PCIe interfaces through the PCIe switch chip, supporting the connection of more modules; the ARM processor also provides intelligent management functions, enabling automatic module identification, configuration, and hot-swapping support, improving system flexibility and maintainability.

[0049] The main control module, expansion I / O module, and PCIe switching module all communicate via the PCIe bus to achieve high-speed data transmission and module expansion.

[0050] Preferably, the controller backplane system supports hot-swapping. Expansion I / O modules and PCIe switching modules can be inserted or removed while the controller backplane system is running, and report module status and slot information to the main control module via the PCIe bus. Specifically, when an expansion I / O module is inserted into the backplane connector, the PCIe interface chip detects the connection, the MCU initializes the module, and reports the module ID, type, and slot information to the main control module. After verifying the information, the main control module dynamically updates the system topology and allocates resources. This improves system availability and maintainability, allows for online module expansion and replacement, reduces system downtime, and is suitable for industrial environments requiring high reliability.

[0051] Preferably, the main control module dynamically generates the system topology based on the slot and function information reported by the extended I / O modules and PCIe switching modules, and issues configuration parameters to optimize communication paths. Specifically, at system startup, the main control module scans all connected modules, collects slot, type, and function data, and generates a topology diagram. It allocates PCIe addresses and interrupt resources according to the topology and sets data priorities. This achieves automatic system identification and optimized configuration, simplifies the installation and debugging process, and improves the system's adaptability and performance.

[0052] refer to Figure 3 The PCIe switching module can be further connected to expansion I / O modules or other PCIe switching modules to form a multi-level expansion structure. Specifically, the main control module connects to a PCIe switching module that expands to seven PCIe interfaces. Six of these interfaces connect to expansion I / O modules, and the remaining interface can connect to a secondary PCIe switching module, further expanding to seven expansion I / O modules. This multi-level expansion significantly increases the number of modules that can be connected to the system, meeting the needs of large-scale I / O expansion while maintaining high-speed communication, making it suitable for complex industrial control systems.

[0053] This application utilizes the PCIe bus as the backplane communication foundation, leveraging its high-speed serial point-to-point characteristics to avoid bandwidth contention and arbitration delays inherent in traditional serial buses, thereby significantly improving data transmission rates and system response speed. Simultaneously, the introduction of the PCIe switching module enhances interface expansion capabilities, supporting multi-level connections and resolving the limited scalability issue of existing backplane systems. This system is suitable for industrial control applications, meeting the core requirements of high-performance intelligent controllers for high speed, low latency, and strong scalability.

[0054] refer to Figure 4 Another embodiment of this application proposes a control method for the aforementioned controller backplane system, which may specifically include the following steps.

[0055] Step 1: The main control module detects the extended I / O modules and PCIe switching modules connected to the downstream level and obtains the module information.

[0056] Step 2: The extended I / O module and PCIe switching module report module information to the main control module through the PCIe bus, and the main control module performs module verification.

[0057] Step 3: After successful verification, the main control module sends configuration and control information to the extended I / O module and PCIe switching module based on the module information.

[0058] Step 4: The main control module communicates with the extended I / O module in real time to control the extended I / O module to realize input and output functions.

[0059] Step 5: When the input / output function, communication, or bus of the extended I / O module is abnormal, the extended I / O module reports the fault information to the main control module through the PCIe bus, and the main control module handles the fault.

[0060] Specifically, after the system powers on, the main control module scans all modules on the backplane via the PCIe bus to obtain the functions, quantities, and slot information of the expansion I / O modules and PCIe switching modules. Each module reports its own information through the PCIe configuration space. After verifying information compatibility, the main control module issues configuration commands (such as setting I / O mode and sampling rate). During normal operation, the main control module periodically exchanges data with the expansion I / O modules to control input / output functions. If a module detects a fault (such as communication timeout or hardware abnormality), it reports the error via PCIe interrupt, and the main control module logs the error and takes isolation or restart measures.

[0061] The aforementioned embodiments of the controller backplane system based on the PCIE bus and the embodiments of the control method for the controller backplane system are technically related and can be referred to each other in terms of technical details and technical effectiveness, which will not be repeated here.

[0062] The flowcharts or block diagrams in the accompanying drawings illustrate the architecture, functionality, and / or operation of possible implementations of systems, methods, and / or computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0063] Exemplary embodiments have been disclosed herein, and while specific terminology has been used, it is used and should be interpreted only in a general illustrative sense and is not intended to be limiting. In some embodiments, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in conjunction with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of this application as set forth by the appended claims.

Claims

1. A PCIE bus based controller backplane system, characterized in that, The application relates to a controller backplane system, which comprises a main control module, a backplane connector, at least one extension IO module and a PCIE switching module. The main control module is configured to output a plurality of PCIE bus interfaces. The backplane connector is used for connecting the extension IO module and the main control module. Each of the extension IO modules comprises a PCIE interface chip and an MCU processor. The PCIE switching module is connected to the backplane connector to expand the PCIE interface and support more extension IO modules when the number of PCIE channels of the main control module is insufficient. The main control module, the extension IO module and the PCIE switching module are in data communication through a PCIE bus to realize data transmission and module expansion.

2. The controller backplane system of claim 1, wherein, The PCIE switching module comprises a PCIE switching chip and an ARM processor. The PCIE switching chip is used for expanding the PCIE interface and realizing data switching. The ARM processor is used for at least one of module configuration management, channel dynamic data management and hot plug management.

3. The controller backplane system of claim 1, wherein, The extension IO module further comprises an input and output interface circuit used for realizing the input or output function of digital or analog signals. The PCIE interface chip of the extension IO module is a PCIE bus general interface chip. The PCIE bus general interface chip decodes PCIE bus signals. The MCU processor communicates and interacts with the PCIE bus interface chip through the PCIE bus general interface chip, thereby controlling the input and output interface circuit.

4. The controller backplane system of claim 1, wherein, The main control module is configured with a real-time operating system and a lightweight communication protocol to realize real-time transmission and control of data and synchronize the operation of each module through a distributed clock mechanism.

5. The controller backplane system of claim 1, wherein, The controller backplane system supports the hot plug function. The extension IO module and the PCIE switching module can be inserted or removed when the controller backplane system is running, and report the module state and slot information to the main control module through the PCIE bus.

6. The controller backplane system of claim 1, wherein, The communication between the main control module and the extension IO module adopts a point-to-point mode, and each extension IO module exclusively occupies a PCIE interface to avoid bandwidth contention and arbitration delay.

7. The controller backplane system of claim 1, wherein, The main control module dynamically generates a system topology according to the slot information and function information reported by the extension IO module and the PCIE switching module, and issues configuration parameters to optimize the communication path.

8. The controller backplane system of claim 1, wherein, The rear stage of the PCIE switching module can continue to connect the extension IO module or other PCIE switching modules to form a multi-stage expansion structure.

9. The controller backplane system of claim 1, wherein, The PCIE bus adopts the PCIE 2.0 protocol, and the communication rate of each X1 interface is 500 MB / s.

10. A control method for the controller backplane system of any of claims 1-9, characterized by, The main control module detects the extension IO module and the PCIE switching module connected in the rear stage, and obtains module information. The extension IO module and the PCIE switching module report the module information to the main control module through the PCIE bus, and the main control module performs module checking. After the checking is passed, the main control module issues configuration and control information to the extension IO module and the PCIE switching module based on the module information. ​ The main control module communicates with the extension IO module in real time to control the extension IO module to realize input and output functions. When the input and output functions of the extension IO module are abnormal, communication is abnormal or the bus is abnormal, the extension IO module reports fault information to the main control module through the PCIE bus, and the main control module processes the fault.

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