Memory controller, method of operating the same, memory device, and nonvolatile

Abstract

A memory controller, a method of operating the same, a memory device, and a non-volatile memory device are provided. The memory controller includes: processing circuitry configured to control a memory device including a plurality of data blocks, where the processing circuitry is further configured to: classify a first portion of the plurality of data blocks into a first group; classifying a second portion of the plurality of data blocks into a second group, the second portion being different from the first portion; determining first setting data based on the environmental information, the first setting data to be used for sensing data blocks included in a first group; determining second setting data based on the environmental information, the first setting data to sense data blocks included in a second group; and storing initialization information on the determined first setting data and second setting data in a memory device.

Description

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2024-0119140, filed on September 3, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0002] One or more example embodiments disclosed relate to a memory controller, a storage device including the same, and a non-volatile memory device. BACKGROUND

[0003] A storage device including a solid state drive (SSD) or the like includes a memory device storing data and a memory controller controlling overall operations of the memory device.

[0004] Setup data is information required for initialization processing before initial driving of the memory device. During initial driving (booting) of the storage device, a setup operation of loading setup data to set the memory device can be performed so that the non-volatile memory device can operate normally.

[0005] As technology develops, users' demands for storage devices are becoming more diverse, and research is being conducted on how to quickly boot the storage device while accepting various demands of users. SUMMARY

[0006] One or more example embodiments disclosed provide a memory controller that can allow a memory device to adaptively apply several pieces of setup data according to characteristics of groups.

[0007] One or more example embodiments disclosed provide a storage device for adaptively applying several pieces of setup data according to characteristics of groups.

[0008] It is another object to provide a non-volatile memory device for adaptively applying several pieces of setup data according to characteristics of groups.

[0009] According to an aspect of example embodiments disclosed, there is provided a memory controller including a processing circuit configured to control a memory device including a plurality of data blocks, wherein the processing circuit is further configured to classify a first portion of the plurality of data blocks into a first group, classify a second portion of the plurality of data blocks into a second group, the second portion being different from the first portion, determine first setup data to be used for sensing data blocks included in the first group based on environment information, determine second setup data to be used for sensing data blocks included in the second group based on the environment information, and store initialization information about the determined first setup data and the second setup data in the memory device.

[0010] According to an aspect of the disclosed example embodiments, there is provided a storage device including: a memory device including data blocks belonging to a first group and data blocks belonging to a second group; and a memory controller configured to control the memory device, wherein the memory controller is further configured to: determine first setting data based on environment information, the first setting data including a first sensing condition to be used for sensing the data blocks belonging to the first group; determine second setting data based on the environment information, the second setting data including a second sensing condition to be used for sensing the data blocks belonging to the second group; and provide initialization information about the determined first setting data and second setting data to the memory device, and wherein the memory device is configured to: perform a setting operation in response to an initialization command of the memory controller, sense the data blocks belonging to the first group in the first sensing condition based on the initialization information, and sense the data blocks belonging to the second group in the second sensing condition based on the initialization information.

[0011] According to an aspect of the disclosed example embodiments, there is provided a method of operating a memory controller, the method including: classifying, by the memory controller, a plurality of data blocks included in a memory device into a first group and a second group; determining, by the memory controller, first setting data to be used for sensing the data blocks belonging to the first group based on environment information; determining, by the memory controller, second setting data to be used for sensing the data blocks belonging to the second group based on the environment information; and providing, by the memory controller, initialization information about the determined first setting data and second setting data for each group to the memory device.

[0012] According to an aspect of the disclosed example embodiments, there is provided a non-volatile memory device including: a memory cell array including a first memory plane having first data blocks and a second memory plane having second data blocks; and a control logic circuit configured to write in or read from the first memory plane in the memory cell array, wherein the memory cell array stores first initialization information, first setting data, and second setting data, the first initialization information being used to determine setting data including a sensing condition to be used for sensing each data block, the first setting data including a first sensing condition, and the second setting data including a second sensing condition, and wherein the control logic circuit is further configured to: perform a metadata opening operation in response to an initialization command; store the first setting data and the second setting data in an initialization register; and sense the first memory plane in the first sensing condition and the second memory plane in the second sensing condition according to the first initialization information.

[0013] The disclosed purposes are not limited to those mentioned above, and additional purposes of the disclosure that are not mentioned herein will be clearly understood by those skilled in the art from the following disclosed description. BRIEF DESCRIPTION OF DRAWINGS

[0014] The above and other aspects, features, and advantages of the disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0015] Figure 1 is a block diagram illustrating a memory device according to one or more example embodiments.

[0016] Figure 2 is a block diagram illustrating a memory device according to one or more example embodiments.

[0017] Figure 3 is a block diagram illustrating a non-volatile memory device according to one or more example embodiments.

[0018] Figure 4 is a diagram illustrating a memory block included in a memory cell array of Figure 3 .

[0019] Figure 5 is a flowchart illustrating an operation of a memory controller according to one or more example embodiments.

[0020] Figure 6 is a block diagram illustrating an operation of a memory controller according to one or more example embodiments.

[0021] Figure 7 is a diagram illustrating a data block according to one or more example embodiments.

[0022] Figure 8 is a diagram illustrating a method of classifying a plurality of data blocks into a first group and a second group by a memory controller according to one or more example embodiments.

[0023] Figure 9 is a diagram illustrating a method of classifying a plurality of data blocks into a first group and a second group by a memory controller according to one or more example embodiments.

[0024] Figure 10 is a diagram illustrating a method of classifying a plurality of data blocks into a first group and a second group by a memory controller according to one or more example embodiments.

[0025] Figure 11 is a flowchart illustrating an operation of a memory controller according to one or more example embodiments.

[0026] Figure 12is a table illustrating a method of determining, by a memory controller, setting data needed for sensing data blocks included in each group according to one or more example embodiments.

[0027] Figure 13 is a table illustrating a method of determining, by a memory controller, setting data needed for sensing data blocks included in each group according to one or more example embodiments.

[0028] Figure 14 is a flowchart illustrating an operation of a non-volatile memory device according to one or more example embodiments.

[0029] Figure 15 is a block diagram illustrating a memory cell array according to one or more example embodiments.

[0030] Figure 16 is a diagram illustrating setting data according to one or more example embodiments.

[0031] Figure 17 and Figure 18 is a diagram illustrating a method of sensing memory blocks by a non-volatile memory device according to one or more example embodiments.

[0032] Figure 19 is a diagram illustrating setting data according to one or more example embodiments.

[0033] Figure 20 is a diagram illustrating a method of sensing memory blocks by a non-volatile memory device according to one or more example embodiments.

[0034] Figure 21 is a block diagram illustrating a host storage system including a storage device according to one or more example embodiments.

[0035] Figure 22 is a block diagram illustrating a system applying a storage device according to one or more example embodiments. DETAILED DESCRIPTION

[0036] Hereinafter, one or more example embodiments according to the spirit of the disclosed technology will be described with reference to the accompanying drawings.

[0037] As used herein, the recitation "at least one of a list of elements is meant to mean at least one element from the list of elements, and not each individual element individually. For example, the recitation "at least one of a, b, and c" should be understood as including only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.

[0038] In the disclosure, "write" can be used interchangeably with "program".

[0039] In the memory device, "sensing" can be a term generally used to indicate determining whether a memory cell is an on cell ("1") or an off cell ("0") based on a charge amount of a bit line of a memory cell array in various cases, or as a general term for an operation of writing data, reading data, or erasing data in a memory cell. In the disclosure, "sensing" can be used as a general term for an operation of writing data, reading data, and erasing data in a memory cell.

[0040] Figure 1 is a block diagram illustrating a memory device according to one or more example embodiments.

[0041] Referring to Figure 1 The memory system 1 can include a host 10 and a memory device 20. The memory system 1 can be implemented as, for example, but not limited to, a personal computer (PC), a data server, a laptop computer, or a portable device. The portable device can be implemented as, for example, but not limited to, a mobile phone, a smart phone, a tablet PC, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a digital video camera, a portable multimedia player (PMP), a personal navigation device (PND), a handheld game console, or an electronic book. In addition, the memory system 1 can be implemented as a system on chip (SoC).

[0042] The host 10 can request the memory device 20 to perform a data processing operation (e.g., a data read operation, a data write (program) operation, and / or a data erase operation). For example, the host 10 can include, for example, but not limited to, a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor, or an application processor (AP).

[0043] The memory device 20 can include a memory controller 200 and a non-volatile memory device 100. The memory device 20 can be implemented as various types of memory devices such as, for example, but not limited to, a solid state drive (SSD), an embedded multimedia card (eMMC), a universal flash storage (UFS), a compact flash (CF), a secure digital (SD) card, a micro secure digital (Micro-SD) card, a mini secure digital (mini-SD) card, an extreme digital (xD) card, or a memory stick.

[0044] The memory controller 200 can be integrated with the host 10 and the storage device 20. In response to a request from the host 10, the memory controller 200 can be configured to access the non-volatile memory device 100. For example, the memory controller 200 can be configured to control the overall operation of the storage device 20. The memory controller 200 can perform various management operations, such as, but not limited to, cache / buffer management, firmware management, garbage collection management, wear leveling management, data deduplication management, read refresh / reclaim management, bad block management, multi-stream management, host data and non-volatile memory mapping management, Quality of Service (QoS) management, system resource allocation management, non-volatile memory queue management, read level management, erase / programming management, hot / cold data management, power-down protection management, dynamic thermal management, and initialization management.

[0045] Although not clearly shown in the accompanying drawings, the memory controller 200 may be configured to provide an interface between the storage device 20 and the host 10. Furthermore, the memory controller 200 may be configured to drive firmware configured to control the storage device 20, either upon request from the host 10 or by itself.

[0046] For example, the memory controller 200 may also include known components such as host controller (HCORE) 211, memory controller (FCORE) 212, memory 220, host interface (not shown) and memory interface (not shown) .

[0047] The host controller (HCORE) 211 can execute the host interface layer (HIL) of the firmware to transmit read or write commands from the host 10 to the flash translation layer (FTL) of the firmware.

[0048] The storage controller (FCORE) 212 executes the firmware's FTL and flash memory interface layer (FIL). The FIL performs input / output to the non-volatile memory device 100 and the memory controller 200. For example, data can be written to mapped physical page addresses and / or read from mapped physical page addresses via the FTL.

[0049] The host interface of the memory controller 200 may include protocols for performing data exchange between the host 10 and the memory controller 200. For example, the memory controller 200 may be configured to communicate with the host 10 via at least one of a variety of interface protocols, such as, but not limited to, Universal Serial Bus (USB) protocol, Multimedia Card (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, PCI-Fast (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial-ATA protocol, Parallel-ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, and Electronic Integrated Drive (IDE) protocol.

[0050] The memory interface of the memory controller 200 can send signals to and receive signals from the non-volatile memory device 100 via multiple pins. For example, the multiple pins can respectively send DQ signal, DBI signal, DQS signal, RE signal, CE signal, ALE signal, CLE signal, and WE signal.

[0051] The DQ signal can be a data signal and may include the transmitted command CMD, address ADDR, and data DATA. The DQ signal can be transmitted via multiple data signal lines. The DBI signal can be a data bus inversion signal, and the memory controller 200 and non-volatile memory device 100 can send and receive data that has undergone data bus conversion calculations or data masking calculations. For example, the data may be encrypted for security or privacy. The DQS signal can be a data strobe signal, and the RE signal can be a read enable signal; these signals can be input as data output control signals when reading data from the non-volatile memory chip. The RE signal can be used to generate the DQS signal. The CE signal can be a chip enable signal and can be a signal that allows the memory controller 200 to selectively activate and access at least one of the non-volatile memory devices 100. The CLE signal can be a command latch enable signal, and the ALE signal can be an address latch enable signal. The CLE signal is enabled when the command CMD is included in the DQ signal, the ALE signal is enabled when the address ADDR is included in the DQ signal, and the CLE or ALE signal is disabled when general data is sent to the DQ signal. The WE signal is a write enable signal, and the memory controller 200 can send the data signal DQ, including the command CMD or address ADDR, and the switched write enable signal WE to the non-volatile memory device 100.

[0052] For example, the non-volatile memory device 100 can perform write, read, and / or erase operations based on the CLE and ALE signals by latching the command CMD or address ADD on the edge of the WE signal. For instance, during a read operation, the CE signal can be activated, the CLE signal can be activated during the command transmission cycle, the ALE signal can be activated during the address transmission cycle, and the RE signal can be toggled during the period when data is transmitted through the DQ line. The DQS signal can be toggled at a frequency corresponding to the data input / output speed. Read data can be sequentially transmitted synchronously with the data strobe signal DQS.

[0053] The non-volatile memory device 100 may include a memory cell array 400 and peripheral circuitry units 300 connected to the memory cell array 400, and the memory cell array 400 may include multiple memory planes. The non-volatile memory device 100 may support plane-independent commands (PICs). A PIC can mean that in a non-volatile memory device 100 including multiple memory planes, read operations, programming operations, and erase operations can be performed on another memory plane even when one memory plane is busy. The memory 220 may be used as at least one of the following: operational memory of the host controller 211 or memory controller 212; cache memory between the memory device 20 and the host 10; and buffer memory between the memory device 20 and the host 10. For example, the memory 220 may be implemented as random access memory (RAM). The memory controller 212 controls the overall operation of the memory controller 200.

[0054] Figure 2 This is a block diagram illustrating a storage device according to one or more example embodiments.

[0055] Reference Figure 2 The storage device 20 may include a memory device 50 and a memory controller 200.

[0056] The storage device 20 can support multiple channels CH1 to CHm, and the memory device 50 and the memory controller 200 can be connected to each other through multiple channels CH1 to CHm.

[0057] The memory device 50 may include non-volatile memory devices NVM11 to NVMmn. Figure 1The non-volatile memory device 100 can be any one of the non-volatile memory devices NVM11 to NVMmn, but the disclosure is not limited thereto. Each of the non-volatile memory devices NVM11 to NVMmn can be connected to one of a plurality of channels CH1 to CHm via a corresponding way (e.g., one of the corresponding ways W11 to W1n, W21 to W2n, and Wm1 to Wmn). For example, the non-volatile memory devices NVM11 to NVM1n can be connected to the first channel CH1 via way W11 to W1n, and the non-volatile memory devices NVM21 to NVM2n can be connected to the second channel CH2 via way W21 to W2n. Each of the non-volatile memory devices NVM11 to NVMmn can be implemented as a random access memory cell operable according to individual commands from the memory controller 200. For example, each of the non-volatile memory devices NVM11 to NVMmn can be implemented as a memory chip or a memory die, but the disclosure is not limited thereto.

[0058] The memory controller 200 can send signals to and receive signals from the memory device 50 through multiple channels CH1 to CHm. For example, the memory controller 200 can send commands CMDa to CMDm, addresses ADDRa to ADDRm, and data DATAa to DATAm to the memory device 50 through channels CH1 to CHm, respectively, or it can receive data DATAa to DATAm from the memory device 50 through channels CH1 to CHm, respectively.

[0059] The memory controller 200 can select one of the non-volatile memory devices NVM11 to NVM1n connected to the corresponding channel via each channel, and can send signals to and receive signals from the selected non-volatile memory device. For example, the memory controller 200 can select non-volatile memory device NVM11 from the non-volatile memory devices NVM11 to NVM1n connected to the first channel CH1. The memory controller 200 can send command CMDa, address ADDRa, and data DATAa to the selected non-volatile memory device NVM11 via the first channel CH1, or receive data DATAa from the selected non-volatile memory device NVM11 via the first channel CH1.

[0060] The memory controller 200 can send signals to and receive signals from the memory device 50 in parallel through different channels. For example, while sending command CMDa to the memory device 50 through the first channel CH1, the memory controller 200 can send command CMDb to the memory device 50 through the second channel CH2. For example, while receiving data DATAa from the memory device 50 through the first channel CH1, the memory controller 200 can receive data DATAb from the memory device 50 through the second channel CH2.

[0061] The memory controller 200 controls the overall operation of the memory device 50. The memory controller 200 can control each of the non-volatile memory devices NVM11 to NVM1n connected to channels CH1 to CHm by sending signals to channels CH1 to CHm. For example, the memory controller 200 can control the selection of one of the non-volatile memory devices NVM11 to NVM1n by sending command CMDa and address ADDRa to the first channel CH1.

[0062] Each of the non-volatile memory devices NVM11 to NVMmn can operate under the control of the memory controller 200. For example, non-volatile memory device NVM11 can program data DATAa according to the command CMDa and address ADDRa provided to the first channel CH1. For example, non-volatile memory device NVM21 can read data DATAb according to the command CMDb and address ADDRb provided to the second channel CH2, and can send the read data DATAb to the memory controller 200.

[0063] although Figure 2 The memory device 50 is shown communicating with the memory controller 200 via a number of channels CH1 to CHm, and the memory device 50 includes a number of non-volatile memory devices corresponding to each channel, but various modifications can be made to the number of channels and the number of non-volatile memory devices connected to a channel.

[0064] Figure 3 This is a block diagram illustrating a non-volatile memory device according to one or more example embodiments.

[0065] Reference Figure 3 The non-volatile memory device 100 may include a memory cell array 400 and peripheral circuitry units 300 connected to the memory cell array 400. The non-volatile memory device 100 may be compared with a reference... Figure 2The described non-volatile memory devices correspond to one of NVM11 to NVMmn. Peripheral circuitry unit 300 may include a voltage generator 350, a row decoder 360, a page buffer 340, an input / output (I / O) buffer 320, and control logic circuitry 310. Memory cell array 400 may include multiple memory blocks BLK1 to BLKz. Each of the multiple memory blocks BLK1 to BLKz is connected to the row decoder 360 via word line WL, serial select line SSL, and ground select line GSL, and is connected to the page buffer 340 via bit line BL.

[0066] The memory cell array 400 may include multiple memory cells disposed in regions where multiple word lines WL and multiple bit lines BL intersect each other. Each of the memory cells may be formed in various cell types, including, but not limited to, single-level cell (SLC), multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), etc.

[0067] The control logic circuit 310 can receive the command CMD and the address ADDR to generate control signals CTRL_vol for controlling the voltage generator 350 and control signals for controlling the page buffer 340, and can generate row address X_ADDR and column address Y_ADDR based on address ADDR. The control logic circuit 310 can output row address X_ADDR to row decoder 360 and column address Y_ADDR to input / output buffer 320.

[0068] The voltage generator 350 can receive power PWR, adjust the word line base voltage VWL for memory operation according to the control signal CTRL_vol from the control logic circuit 310, and provide the word line base voltage VWL to the memory cell array 400 through the row decoder 360.

[0069] The row decoder 360 can be connected to the memory cell array 400 via the word line WL, the serial select line SSL, and the ground select line GSL. The row decoder 360 can decode the row address X_ADDR input from the control logic circuit 310 to select at least one of a plurality of memory blocks BLK1 to BLKz. That is, the row decoder 360 can select the word line WL, the serial select line SSL, and the ground select line GSL using the row address X_ADDR. The row decoder 360 can supply the word line basic voltage VWL supplied from the voltage generator 350 to the word line WL.

[0070] Page buffer 340 can be connected to memory cell array 400 via bit line BL, and can also be connected to input / output buffer 320 via bit line BL. During programming operations, input / output buffer 320 can receive signals from memory controller (e.g., ...). Figure 1The input / output buffer 320 provides programming data DATA from the control logic circuit 310 (Y_ADDR), and can provide programming data DATA to the page buffer 340 based on the column address Y_ADDR provided from the control logic circuit 310. During a read operation, the input / output buffer 320 can provide read data DATA stored in the page buffer 340 to the memory controller (e.g., based on the column address Y_ADDR provided from the control logic circuit 310). Figure 1 (of 200).

[0071] The control logic circuit 310 can control the overall operation of the non-volatile memory device 100 and output each control signal related to memory operation. For example, the control logic circuit 310 can control the non-volatile memory device 100 by using internal control signals based on at least one of the address ADDR, command CMD, and control signal CTRL received from the memory controller 200.

[0072] The control logic circuit 310 may include an initialization register 311, which includes a latch. The latch may be a fuse-type latch. The control logic circuit 310 can read setting data, store the read setting data in the initialization register 311, and generate internal control signals based on at least one of the address ADDR, command CMD, and control signal CTRL, and the stored setting data. The setting data will be described in more detail later.

[0073] Figure 4 It is shown that it includes Figure 3 A diagram of memory blocks in a memory cell array.

[0074] Reference Figure 4 Each of the multiple memory blocks BLK1 to BLKz can be formed on the substrate in a three-dimensional structure. For example, the (i)th memory block BLKi may include multiple memory NAND strings NS11 to NS33 connected between multiple bit lines BL1 to BL3 and a common source line CSL. Each of the multiple memory NAND strings NS11 to NS33 may include a string select transistor SST, multiple memory cells MC, and a ground select transistor GST. Although Figure 3 It is shown that there are three bit lines BL1 to BL3 and nine memory NAND strings NS11 to NS33, and each of the multiple memory NAND strings NS11 to NS33 includes eight memory cells MC, but the disclosure is not limited thereto and may be implemented in different numbers according to embodiments.

[0075] The gate of the serial select transistor SST can be connected to the corresponding serial select line among serial select lines SSL1 to SSL3. Multiple memory cells MC can be connected to their respective word lines WL1 to WL8. Word lines WL1 to WL8 correspond to gate lines GTL1 to GTL8. The gate of the ground select transistor GST can be connected to the corresponding ground select line among ground select lines GSL1 to GSL3. The serial select transistor SST can be connected to the corresponding bit lines among multiple bit lines BL1 to BL3, and the ground select transistor GST can be connected to the common source line CSL.

[0076] Word lines (e.g., WL1) at the same height in memory block (i) BLKi can be connected together, and ground select lines GSL1 to GSL3 and string select lines SSL1 to SSL3 at the same height in memory block (i) BLKi can be set separately.

[0077] Figure 5 This is a flowchart illustrating the operation of a memory controller according to one or more example embodiments. Figure 6 This is a block diagram illustrating the operation of a memory controller according to one or more example embodiments. Figure 7 This is a diagram illustrating a data block according to one or more example embodiments.

[0078] Reference Figure 5 to Figure 7 Describe the operation of the memory controller.

[0079] As described above, the memory controller 200 may include processing circuitry 210 and memory 220. Memory 220 may include firmware, which may be a set of multiple command languages ​​for specifying the operation of processing circuitry 210. Processing circuitry 210 can control the memory device (e.g., ...) by executing the firmware stored in memory 220. Figure 2 The processing circuit 210 can execute firmware stored in the memory 220 to implement the group management unit 230 and the initialization determination unit 240, but the disclosure is not limited thereto. The group management unit 230 and the initialization determination unit 240 can be configured as hardware including separate circuits and can exist in the memory controller 200 or can be integrally formed with the processing circuit 210. The memory device can include multiple data blocks DB. The data blocks DB can correspond to a set of data or a zone in which the storage space in the memory device is logically or physically divided.

[0080] For example, the concept of zone namespaces (ZNS) has been introduced, which allows multiple users or applications to use storage devices without interfering with each other. Since the concept of zone namespaces is known, its detailed description will be omitted. In this case, the data block DB can correspond to multiple partitions allocated to each user or application.

[0081] For another example, to effectively manage the storage space of a storage device, the concept of Flexible Data Placement (FDP) is introduced, and in this case, the data block database (DB) can correspond to a Reclaimable Unit (RU), which is a spatial unit in which data can be placed. Since FDP is known to those skilled in the art, its detailed description will be omitted. As another example, the data block database can correspond to the Physical Function (PF) in the concept of Single Root I / O Virtualization (SR-IOV), a known virtualization technology. However, the data block database is not limited to the above concepts.

[0082] The memory controller 200 can classify multiple data blocks into a first group and a second group (S110). For example, the group management unit 230 of the memory controller 200 can classify multiple data blocks DB into a first group GR1 and a second group GR2. Various criteria for classifying multiple data blocks DB into a first group GR1 and a second group GR2 by the group management unit 230 will be described later. In the disclosure, the group management unit 230 is described as classifying multiple data blocks DB into two groups, but the embodiments are not limited to this, and the data blocks DB can be classified into three or more groups.

[0083] The memory controller 200 may determine first setup data required for sensing data blocks included in the first group based on environmental information (S120). For example, the initialization determination unit 240 of the memory controller 200 may determine first setup data required for sensing multiple data blocks DB included in the first group GR1 based on environmental information. Details of the environmental information will be described later.

[0084] The memory controller 200 may determine, based on environmental information, the second setup data required for sensing the data blocks included in the second group (S130). For example, the initialization determination unit 240 of the memory controller 200 may determine, based on environmental information, the second setup data required for sensing the multiple data blocks DB included in the second group GR2. Details of the environmental information will be described later.

[0085] The memory controller 200 can provide initialization information (S140). For example, the processing circuit 210 of the memory controller 200 can provide the initialization information generated by the operation of the initialization determination unit 240 to the memory device (e.g., Figure 1(100 of the original text). Initialization information may include information about determined setup data. Initialization information may be stored in a specific area of ​​the memory device.

[0086] According to some embodiments, the memory controller 200 can classify multiple data blocks into several groups according to various criteria, determine setting data suitable for the sensing conditions of each group based on environmental information reflecting the characteristics of the data blocks, and provide the setting data to the memory device. The memory device can write or read data by applying the setting data suitable for each group based on the provided information. For example, the memory device can load first setting data for sensing memory blocks belonging to a first group based on initialization information provided from the memory controller. The memory device can sense memory blocks belonging to the first group under a first sensing condition based on the first setting data. Furthermore, the memory device can load second setting data for sensing memory blocks belonging to a second group based on initialization information provided from the memory controller. The memory device can sense memory blocks belonging to the second group under a second sensing condition based on the second setting data. In other words, it is feasible to provide a memory controller that can be used by adaptively applying various setting data according to the characteristics of data blocks belonging to each group, and a memory device and non-volatile memory device that can be used by adaptively applying various setting data according to the characteristics of data blocks belonging to each group.

[0087] Figure 8 This is a diagram illustrating a method of classifying multiple data blocks into a first group and a second group by a memory controller according to one or more example embodiments.

[0088] Reference Figure 8 The memory controller 200 can be accessed by itself or by the host (e.g., Figure 1Under the control of (10), multiple data blocks DB are classified into a first group and a second group. As described above, the memory cell array 400 of the memory device may include multiple memory cells. Each memory cell may be formed in various cell types, including single-level cell (SLC), multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), etc. The memory cell array 400 may include, for example, a first-level space 400S and a second-level space 400T. The first-level space 400S may include first-level memory cells. The first-level memory cells may be, for example, any one of SLC, MLC, and TLC. The second-level space 400T may include second-level memory cells. The second-level memory cells may be memory cells that store a larger number of data bits per cell than the first-level memory cells. That is, when the first-level memory cell is, for example, SLC, the second-level memory cell may correspond to one or more of MLC, TLC, and QLC. When the first-level memory cell is, for example, MLC, the second-level memory cell may correspond to one or more of TLC and QLC. When the first-level memory cell is, for example, TLC, the second-level memory cell may correspond to QLC.

[0089] The memory controller 200 can classify multiple data blocks DB belonging to the first-level space 400S into a first group GR1, and can classify multiple data blocks DB belonging to the second-level space 400T into a second group GR2. In other words, the memory controller 200 can classify data blocks that include first-level memory cells into the first group GR1, and can classify data blocks that include second-level memory cells into the second group GR2.

[0090] The memory controller 200 can determine, based on environmental information, first setup data required for sensing data blocks included in the first group GR1, and second setup data required for sensing data blocks included in the second group GR2. The memory controller 200 can provide initialization information, including information about the determined setup data, to the memory device.

[0091] The memory device can load first configuration data for sensing memory blocks belonging to the first group GR1 based on initialization information. Furthermore, the memory device can load second configuration data for sensing memory blocks belonging to the second group GR2 based on initialization information provided from the memory controller.

[0092] The memory device can sense memory blocks belonging to a first group GR1 under a first sensing condition based on first setting data. The memory device can sense memory blocks belonging to a second group GR2 under a second sensing condition based on second setting data. In other words, the memory device can sense multiple data blocks DB including first-level memory cells under a first sensing condition based on first setting data, and can sense multiple data blocks DB including second-level memory cells under a second sensing condition based on second setting data.

[0093] Figure 9 This is a diagram illustrating a method of classifying multiple data blocks into a first group and a second group by a memory controller according to one or more example embodiments.

[0094] Reference Figure 9 The memory controller 200 can classify multiple data blocks DB into a first group GR1 and a second group GR2, either on its own or under the control of the host 10. In this case, a portion of the data blocks DB may be data blocks DB allocated to the first application APP1 (or the first user) of the host 10. Another portion of the data blocks DB may be data blocks DB allocated to the second application APP2 (or the second user) of the host 10. The memory controller 200 can classify the data blocks DB in which data is written to and read from the first application APP1 (or the first user) into the first group GR1, and can classify the data blocks DB in which data is written to and read from the second application APP2 (or the second user) into the second group GR2.

[0095] The memory controller 200 can determine, based on environmental information, first setup data required for sensing data blocks included in the first group GR1, and second setup data required for sensing data blocks included in the second group GR2. The memory controller 200 can provide initialization information, including information about the determined setup data, to the memory device.

[0096] The memory device can load first configuration data for sensing memory blocks belonging to the first group GR1 based on initialization information. Furthermore, the memory device can load second configuration data for sensing memory blocks belonging to the second group GR2 based on initialization information provided from the memory controller.

[0097] The memory device can sense memory blocks belonging to a first group GR1 under a first sensing condition based on first setting data. The memory device can sense memory blocks belonging to a second group GR2 under a second sensing condition based on second setting data. In other words, the memory device can sense multiple data blocks DB allocated to a first application under a first sensing condition based on the first setting data, and can sense multiple data blocks DB allocated to a second application, which is different from the first application, under a second sensing condition based on the second setting data.

[0098] Figure 10 This is a diagram illustrating a method of classifying multiple data blocks into a first group and a second group by a memory controller according to one or more example embodiments.

[0099] Reference Figure 10 The memory controller 200 can classify multiple data blocks DB into a first group GR1 and a second group GR2, either on its own or under the control of the host 10. Memory devices (e.g., Figure 2 The memory controller 200 (50) may include a plurality of non-volatile memory devices NVM11 to NVMmn as described above. Each of the plurality of non-volatile memory devices NVM11 to NVMmn may be implemented as a random access memory cell (e.g., a memory chip or memory die) operable according to individual commands from the memory controller 200. The memory controller 200 may include, for example, first to fourth memory dies Die0, Die1, Die2, and Die3 operable according to individual commands. Although in Figure 10 Four memory dies are shown, but the disclosure is not limited to this; fewer or more memory dies may exist in a memory device that can be operated according to individual commands. The memory controller 200 can classify the memory dies into groups. For example, the first memory die Die0 and the second memory die Die1 can be classified into a first group GR1, and the third memory die Die2 and the fourth memory die Die3 can be classified into a second group GR2. That is, the data block DB included in the first memory die Die0 and the second memory die Die1 can be classified into the first group GR1, and the data block DB included in the third memory die Die2 and the fourth memory die Die3 can be classified into the second group GR2. The classification method is not limited to the above example, and in one embodiment, each memory die can be classified into one of a different group. For example, the first memory die0 can be classified into the first group GR1, and the second memory die Die1 can be classified into the second group GR2.

[0100] The memory controller 200 can determine, based on environmental information, first setup data required for sensing data blocks included in the first group GR1, and second setup data required for sensing data blocks included in the second group GR2. The memory controller 200 can provide initialization information, including information about the determined setup data, to the memory device.

[0101] The memory device can load first configuration data for sensing memory blocks belonging to the first group GR1 based on initialization information. Furthermore, the memory device can load second configuration data for sensing memory blocks belonging to the second group GR2 based on initialization information provided from the memory controller.

[0102] The memory device can sense memory blocks belonging to the first group GR1 under the first sensing condition based on first setting data. The memory device can sense memory blocks belonging to the second group GR2 under the second sensing condition based on second setting data. In other words, the memory device can sense memory blocks included in the first memory die (e.g., ...) under the first sensing condition based on the first setting data. Figure 10 Multiple data blocks DB in Die0 and Die1) and can be sensed under second sensing conditions according to second setting data, including those in the second memory die (e.g., Figure 10 Multiple data blocks DB in Die2 and Die3.

[0103] Although already Figure 8 to Figure 10 The method for classifying multiple data blocks into a first group and a second group by means of a memory controller is described in detail, but the method for classifying multiple data blocks into a first group and a second group by means of a memory controller is not limited to this. Figure 8 to Figure 10 The method described herein, and multiple data blocks can be classified into a first group and a second group in various ways, and multiple data blocks can be classified into three or more groups instead of two groups.

[0104] Figure 11 This is a flowchart illustrating the operation of a memory controller according to one or more example embodiments.

[0105] Except for reference Figure 5 to Figure 7 In addition to those described, reference will be made to Figure 11 Describe the operation of the memory controller.

[0106] The memory controller can classify multiple data blocks into a first group and a second group (S210). Because S210 and... Figure 5 S110 corresponds to and has already been described in detail above, so its detailed description will be omitted.

[0107] The memory controller can receive workload information and update environmental information (S220). For example, the processing circuitry 210 of the memory controller 200 can receive workload information from the memory device. The workload information may be information used by the memory controller 200 to classify multiple data blocks into a first group and a second group and determine the setup data required for sensing data blocks included in the first and second groups. The processing circuitry 210 of the memory controller 200 can update the environmental information based on the received workload information.

[0108] The memory controller can reclassify multiple data blocks into a first group and a second group based on workload information (S230). For example, the group management unit 230 of the memory controller 200 can reclassify multiple data blocks into a first group and a second group based on workload information received from the memory device.

[0109] The memory controller may determine first setup data required for sensing data blocks included in the first group based on environmental information (S240). For example, the initialization determination unit 240 of the memory controller 200 may update the environmental information based on workload information received from the memory device, and may determine the first setup data required for sensing data blocks included in the first group based on the updated environmental information.

[0110] The memory controller can determine second setup data required for sensing data blocks included in the second group based on environmental information (S250). For example, the initialization determination unit 240 of the memory controller 200 can update the environmental information based on workload information received from the memory device, and can determine the second setup data required for sensing data blocks included in the second group based on the updated environmental information.

[0111] The memory controller can provide initialization information (S260). Because S260 and... Figure 5 S140 corresponds to and has already been described in detail above, so its detailed description will be omitted.

[0112] Figure 12 This is a table illustrating a method by which a memory controller determines the setup data required for sensing data blocks included in each group, according to one or more example embodiments.

[0113] Reference Figure 6 and Figure 12 The method described in detail is for determining the setup data required for sensing the data blocks included in each group via the memory controller.

[0114] Environmental information may include a first hold parameter for data blocks included in the first group GR1 and a second hold parameter for data blocks included in the second group GR2. Assume that among multiple data blocks DB in the memory device, the first data blocks DB1 to the fourth data blocks DB4 belong to the first group GR1, and the fifth data blocks DB5 to the eighth data blocks DB8 belong to the second group GR2. The initialization determination unit 240 of the memory controller 200 may determine first setup data required for sensing data blocks DB1 to DB4 included in the first group GR1 based on the first hold parameter of the first data blocks DB1 to the fourth data blocks DB4 included in the first group GR1. The first hold parameter may include, for example, information regarding the hold request value of each of the data blocks DB1 to DB4 included in the first group GR1.

[0115] Undesirable distortions of data can occur in memory devices due to various factors, such as degradation of memory cells caused by prolonged use. For example, when a non-volatile memory device (such as NAND flash memory) is left idle for an extended period after data has been programmed, distortions can occur in the distribution of the threshold voltage due to charge outflow or hole movement. The number of bits that result in errors when reading data can increase due to these distortions in the distribution of the threshold voltage.

[0116] Therefore, there may be a need for users of storage devices to ensure that data stored in the storage device is maintained in its original state for a specific period of time. For example, there may be a need for users of storage devices to ensure that data stored in the storage device is maintained in its original state for at least one week. The data retention period requested by the users of the storage device may be referred to as the retention request value. Various retention request values ​​may exist (e.g., one week, two weeks, three weeks, one month, and three months).

[0117] The initialization determination unit 240 of the memory controller 200 may determine the setup data required for sensing the data blocks DB1 to DB4 included in the first group as first setup data based on a first hold parameter (e.g., information about each of the hold request values ​​t1, t2, t3, and t4 for the first data blocks DB1 to the fourth data blocks DB4 included in the first group). Similarly, the initialization determination unit 240 of the memory controller 200 may determine the second setup data required for sensing the data blocks DB5 to DB8 included in the second group GR2 based on a second hold parameter (e.g., information about each of the hold request values ​​t5, t6, t7, and t8 for the fifth data blocks DB5 to the eighth data blocks DB8 included in the second group GR2), but the embodiment is not limited thereto. In addition to the hold request values ​​for each data block DB, the hold parameters may also include various other information, and setup data (e.g., first setup data and second setup data) may be determined based on such information.

[0118] Figure 13 This is a table illustrating a method by which a memory controller determines the setup data required for sensing data blocks included in each group, according to one or more example embodiments.

[0119] Reference Figure 6 and Figure 13 The method described in detail is for determining the setup data required for sensing the data blocks included in each group via the memory controller.

[0120] Assume that among multiple data blocks DB in a non-volatile memory device, for example, first data blocks DB1 to fourth data blocks DB4 belong to a first group GR1, and fifth data blocks DB5 to eighth data blocks DB8 belong to a second group GR2. According to some embodiments, environmental information may include a first persistence parameter of the data blocks included in the first group GR1 and a second persistence parameter of the data blocks included in the second group GR2. The initialization determination unit 240 of the memory controller 200 may determine first setup data needed for sensing the data blocks DB1 to DB4 included in the first group GR1 based on the first persistence parameter of the first data blocks DB1 to fourth data blocks DB4 included in the first group GR1. The first persistence parameter may include, for example, information regarding the program / erase (P / E) cycle or erase count for each of the data blocks DB in the first group GR1. Figure 13 The text describes determining setup data based on information about the programming / erasing cycle, but the embodiments are not limited to this.

[0121] The initialization determination unit 240 of the memory controller 200 may determine the setup data required for sensing data blocks DB1 to DB4 included in the first group GR1 as first setup data based on a first persistence parameter (e.g., information about each of the P / E cycles c1, c2, c3, and c4 for the first data blocks DB1 to the fourth data blocks DB4 included in the first group). Similarly, the initialization determination unit 240 of the memory controller 200 may determine the second setup data required for sensing data blocks DB5 to DB8 included in the second group GR2 based on a second persistence parameter (e.g., information about each of the P / E cycles c5, c6, c7, and c8 for the fifth data blocks DB5 to the eighth data blocks DB8 included in the second group GR2), but the embodiments are not limited thereto. In addition to the P / E cycles or erase counts for each data block DB, the persistence parameter may include various other information, and setup data (e.g., first setup data and second setup data) may be determined based on such information.

[0122] Figure 14 This is a flowchart illustrating the operation of a non-volatile memory device according to one or more example embodiments.Figure 15 This is a block diagram illustrating a memory cell array according to one or more example embodiments. Figure 16 This is a diagram illustrating setup data according to one or more example embodiments. (Refer to...) Figure 14 to Figure 16 Describe the operation of a non-volatile memory device.

[0123] First, refer to Figure 15 The memory cell array 400 of the non-volatile memory device may include a first region R1, a second region R2, and a third region R3. The partitioning of the first region R1, the second region R2, and the third region R3 may be variable and logical (not physical). The first region R1 and the second region R2 may be collectively referred to as the meta-region. Metadata may be stored in the meta-region. The third region R3 may be represented as the user region. User data may be stored in the third region R3. The memory controller may control multiple memory blocks included in the memory cell array 400 (e.g., ...). Figure 3 At least a portion of BLK1 to BLKz is designated as the first region R1, another portion is designated as the second region R2, and the remainder is designated as the third region R3.

[0124] Reference Figure 16 The memory cell array 400 of the non-volatile memory device may include a memory plane 401 and a replica memory plane 402.

[0125] Setup data can also be referred to as Information Data Read (IDR) data. Setup data represents the data required for the operation of the non-volatile memory device, and more specifically may include option information, column repair information, and bad block information for each memory die. Setup data may include setup conditions for operating peripheral circuitry units 300, pump circuits, etc., of the non-volatile memory device. During the testing phase of the non-volatile memory device, setup data may be stored in a specific area of ​​the memory cell array 400 (e.g., a specific word line WL). To prepare for distortion caused by degradation of the memory cell array 400, the non-volatile memory device may also store copied setup data to replace the setup data. The copied setup data may be stored in a different memory plane than the memory plane 401 in which the setup data is stored, or it may be stored in the same memory plane as the memory plane 401 in which the setup data is stored. Multiple copies of setup data may exist corresponding to one set of setup data.

[0126] Reference Figure 16In the memory plane 401 of the non-volatile memory device, the previously set data IDR_P can be stored in a region 411 belonging to the first region R1. In the memory plane 401 of the non-volatile memory device, the subsequent two set data IDR_H and IDR_C can be stored in another region 421 belonging to the second region R2. The previously set data IDR_P can be set data that was set before the subsequent set data, and this will be described in detail later. Although in Figure 16 The following two setup data, IDR_H and IDR_C, are shown, but the embodiment is not limited to this, and three or more subsequent setup data may be stored therein. In the memory plane 401 of the non-volatile memory device, user data may be stored in another region 431 belonging to the third region R3. In the copy memory plane 402 of the non-volatile memory device, the copy setup data of the previous setup data IDR_P may be stored in a region 412 belonging to the first region R1. In the copy memory plane 402 of the non-volatile memory device, the copy setup data of the subsequent two setup data, IDR_H and IDR_C, may be stored in another region 422 belonging to the second region R2. In the copy memory plane 402 of the non-volatile memory device, user data may be stored in another region 432 belonging to the third region R3.

[0127] Reference Figure 14 The non-volatile memory device can receive an initialization command (S1010). When the memory device is powered on, the memory controller can provide the initialization command to the non-volatile memory device. The non-volatile memory device can begin an initialization operation in response to the initialization command.

[0128] A non-volatile memory device can perform a first setup operation (S1020). The first setup operation can be performed for operations that are preferentially required by the non-volatile memory device. The first setup operation may include sensing previous setup data IDR_P, verifying the validity of the sensed previous setup data IDR_P, and storing the verified previous setup data IDR_P in a specific space (e.g., an initialization register). The previous setup data IDR_P may be setup data that includes only the preferentially required setup data from all setup data. The non-volatile memory device can reduce its boot time by performing the first setup operation by first using only the preferentially required previous setup data IDR_P.

[0129] The non-volatile memory device can perform a metadata opening operation (S1030). The metadata opening operation can instruct the loading of metadata recorded before the power loss of the memory device and the reconfiguration of the loaded metadata to the latest information. The memory controller can use the metadata to process various requests from the host. The metadata can be setting information about each element in the non-volatile memory device. The metadata may include initialization information. Initialization information can be information used to group multiple memory blocks in the memory device and determine setting data including sensing conditions suitable for each group. Since the initialization information has already been described in detail above along with the memory controller, its detailed description will be omitted here.

[0130] The non-volatile memory device can perform a second setup operation (S1040). The second setup operation can be performed for general operation of the non-volatile memory device. The second setup operation may include sensing subsequent setup data IDR_H and IDR_C, verifying the validity of the sensed subsequent setup data IDR_H and IDR_C, and storing the validated subsequent setup data IDR_H and IDR_C in a specific space (e.g., an initialization register). In this case, the non-volatile memory device may store at least one of the two subsequent setup data IDR_H and IDR_C in a specific space (e.g., an initialization register) based on initialization information.

[0131] When performing a second setup operation, the first setup data and the second setup data can be stored in a specific space (e.g., an initialization register) of the non-volatile memory device. When setting operation variables for operating the non-volatile memory device, the non-volatile memory device may use only one setup data, or it may use two or more setup data together. The first setup data can be either of the subsequent two setup data, IDR_H and IDR_C. The second setup data can be either of the subsequent two setup data, IDR_H and IDR_C. The first setup data may include a first sensing condition. The first sensing condition may include various operation variables used in the non-volatile memory device. For example, the first sensing condition may include at least one of the programming time tPROG, the read time tR, and the erase time tERS when writing data to the non-volatile memory device. For example, as the programming time tPROG increases, data retention characteristics may be improved, but sequential write performance and random write performance may be reduced. The second setup data may include a second sensing condition. The second sensing condition may include various operation variables used in the non-volatile memory device. In this case, the operation variables of the second sensing condition may have different values ​​than the operation variables of the first sensing condition.

[0132] The non-volatile memory device can sense a first data block under a first sensing condition (S1050), and the non-volatile memory device can sense a second data block under a second sensing condition (S1060). S1050 and S1060 will be described in more detail later.

[0133] Figure 17 and Figure 18 This is a diagram illustrating a method of sensing a memory block via a non-volatile memory device according to one or more example embodiments.

[0134] Reference Figure 17 and Figure 18 The non-volatile memory device 100 can sense memory planes by applying the same or different setting data to different memory planes. For example, based on the initialization information and setting data stored in the initialization register 311, the control logic circuit 310 of the non-volatile memory device 100 can sense the first memory plane MP1 and the second memory plane MP2 under the first sensing condition SC1, or it can sense the first memory plane MP1 under the first sensing condition SC1 and sense the second memory plane MP2 under the second sensing condition SC2.

[0135] Based on the initialization information of the non-volatile memory device 100, the first memory plane MP1 and the second memory plane MP2 may belong to the same group, or they may belong to different groups. For example, the first memory plane MP1 may include a first data block, and the second memory plane MP2 may include a second data block. When the first data block and the second data block belong to the same group, the first memory plane MP1 and the second memory plane MP2 may belong to the same group; and when the first data block and the second data block belong to different groups, the first memory plane MP1 and the second memory plane MP2 may belong to different groups.

[0136] When the first data block and the second data block belong to the first group, the control logic circuit 310 of the non-volatile memory device 100 can sense the first memory plane MP1 and the second memory plane MP2 under the first sensing condition SC1 by using the first setting data stored in the initialization register 311. When the first data block belongs to the first group and the second data block belongs to the second group, the control logic circuit 310 of the non-volatile memory device 100 can sense the first memory plane MP1 under the first sensing condition SC1 by using the first setting data, and can sense the second memory plane MP2 under the second sensing condition SC2 by using the second setting data, but the embodiment is not limited to this. Various other methods for sensing each memory plane may exist.

[0137] Figure 19This is a diagram illustrating setup data according to one or more example embodiments.

[0138] Reference Figure 19 In the first memory plane 401 of the non-volatile memory device, the previous setup data IDR_P can be stored in a region 411 belonging to the first region R1. In the memory plane 401 of the non-volatile memory device, the subsequent three setup data IDR_H, IDR_W, and IDR_C can be stored in another region 421 belonging to the second region R2. In the memory plane 401 of the non-volatile memory device, user data can be stored in another region 431 belonging to the third region R3. In the copy memory plane 402 of the non-volatile memory device, the copy setup data of the previous setup data IDR_P can be stored in a region 412 belonging to the first region R1. In the copy memory plane 402 of the non-volatile memory device, the copy setup data of the subsequent three setup data IDR_H, IDR_W, and IDR_C can be stored in another region 422 belonging to the second region R2. In the copy memory plane 402 of the non-volatile memory device, user data can be stored in another region 432 belonging to the third region R3.

[0139] In this scenario, in S1040, the first setting data can be any one of the subsequent three setting data sets: IDR_H, IDR_W, and IDR_C. The second setting data can also be any one of the subsequent three setting data sets: IDR_H, IDR_W, and IDR_C.

[0140] Figure 20 This is a diagram illustrating a method of sensing a memory block via a non-volatile memory device according to one or more example embodiments.

[0141] Reference Figure 20 The non-volatile memory device 100 can sense memory planes by applying the same or different setting data to different memory planes. For example, the control logic circuit 310 of the non-volatile memory device 100 can sense the first memory plane MP1, the second memory plane MP2, and the third memory plane MP3 under the first sensing condition SC1 based on the initialization information and setting data stored in the initialization register 311, or it can sense the first memory plane MP1 under the first sensing condition SC1, sense the second memory plane MP2 under the second sensing condition SC2, and sense the third memory plane MP3 under the third sensing condition SC3.

[0142] For example, a non-volatile memory device may store at least one of three subsequent setup data IDR_H, IDR_W, and IDR_C in an initialization register based on initialization information. The first setup data can be any one of the subsequent three setup data IDR_H, IDR_W, and IDR_C. The second setup data can be any one of the subsequent three setup data IDR_H, IDR_W, and IDR_C. The third setup data can be any one of the subsequent three setup data IDR_H, IDR_W, and IDR_C.

[0143] The first setting data may include a first sensing condition SC1. The second setting data may include a second sensing condition SC2. The third setting data may include a third sensing condition SC3. Each sensing condition may include various operational variables used in a non-volatile memory device. In this case, the operational variable of the second sensing condition SC2 may have a value different from the value of the first sensing condition SC1, and the operational variable of the third sensing condition SC3 may have a value different from the values ​​of the first sensing condition SC1 and the second sensing condition SC2.

[0144] The first memory plane MP1 may include a first data block. The second memory plane MP2 may include a second data block. The third memory plane MP3 may include a third data block. When the first, second, and third data blocks belong to a first group, the control logic circuit 310 of the non-volatile memory device 100 can sense the first memory plane MP1 to the third memory plane MP3 under a first sensing condition SC1 by using first setting data stored in the initialization register 311. When the first data block belongs to the first group, the second data block belongs to the second group, and the third data block belongs to the third group, the control logic circuit 310 of the non-volatile memory device 100 can sense the first memory plane MP1 under a first sensing condition SC1 by using first setting data, sense the second memory plane MP2 under a second sensing condition SC2 by using second setting data, and sense the third memory plane MP3 under a third sensing condition SC3 by using third setting data. However, the embodiments are not limited to this. Many other methods for sensing each memory plane may exist.

[0145] Figure 21 This is a block diagram illustrating a host storage system including a storage device according to one or more example embodiments.

[0146] Reference Figure 21The host-storage system may include a host 1000 and a storage device 2000. Furthermore, the storage device 2000 may include a storage controller 2100 and non-volatile memory (NVM) 2200. Additionally, according to the disclosed exemplary embodiments, the host 1000 may include a host controller 1100 and host memory 1200. The host memory 1200 may be used as a buffer memory configured to temporarily store data to be sent to or from the storage device 2000.

[0147] Storage device 2000 may include a storage medium configured to store data in response to a request from host 1000. As an example, storage device 2000 may include at least one of a solid-state drive (SSD), embedded memory, and removable external memory. When storage device 2000 is an SSD, it may be a device conforming to the Non-Volatile Memory Faster (NVMe) standard. When storage device 2000 is embedded memory or external memory, it may be a device conforming to the Universal Flash Storage (UFS) or Embedded Multimedia Card (eMMC) standard. Each of host 1000 and storage device 2000 may generate and send packets according to a standard protocol employed.

[0148] When the non-volatile memory (or non-volatile memory device) 2200 of the storage device 2000 includes flash memory, the flash memory may include a two-dimensional (2D) NAND memory array or a three-dimensional (3D) (or vertical) NAND (VNAND) memory array. As another example, the storage device 2000 may include various other types of non-volatile memory. For example, magnetic random access memory (MRAM), spin-torque MRAM, conductive bridged RAM (CBRAM), ferroelectric RAM (FeRAM), phase RAM (PRAM), resistive RAM, and various other types of memory may be used in the storage device 2000.

[0149] Each of the host controller 1100 and the host memory 1200 can be implemented as a separate semiconductor chip. Alternatively, the host controller 1100 and the host memory 1200 can be integrated into the same semiconductor chip. As an example, the host controller 1100 can be any of a plurality of modules disposed in the application processor, and the application processor can be implemented as a system-on-a-chip (SoC). Furthermore, the host memory 1200 can be embedded memory disposed in the application processor, or it can be non-volatile memory or a memory module disposed outside the application processor.

[0150] The host controller 1100 can store data in the buffer area (e.g., write data) in the non-volatile memory 2200, or can manage operations that store data in the non-volatile memory 2200 (e.g., read data) in the buffer area.

[0151] Storage controller 2100 may include a host interface (I / F) 2110, a storage-memory interface 2120, and a central processing unit (CPU) 2130. Storage controller 2100 may also include a flash translation layer (FTL) 2140, a packet (PCK) manager 2150, a buffer (BUF) memory 2160, an error correction code (ECC) engine 2170, and an Advanced Encryption Standard (AES) engine 2180. Storage controller 2100 may also include working memory (not shown) in which the flash translation layer (FTL) 2140 is loaded, and CPU 2130 can control data write and read operations for non-volatile memory device 2200 by executing the flash translation layer 2140.

[0152] In detail, storage device 2000 can receive storage device drive signals from host 1000 via host interface 2110. CPU 2130 can send an initialization command in response to the storage device drive signals. The initialization command can be sent to non-volatile memory device 2200 via storage device-memory interface 2120.

[0153] Host interface 2110 can send packets to and receive packets from host 1000. Packets sent from host 1000 to host interface 2110 may include commands or data to be written to non-volatile memory device 2200, and packets sent from host interface 2110 to host 1000 may include responses to commands or data read from non-volatile memory device 2200. Storage device-to-memory interface 2120 can send data to be written to non-volatile memory device 2200, or receive data read from non-volatile memory device 2200. Such storage device-to-memory interface 2120 may be implemented in accordance with standard protocols such as Toggle or Open NAND Flash Interface (ONFI).

[0154] The flash translation layer 2140 performs various functions, such as address mapping, wear leveling, and garbage collection. Address mapping is the process of changing a logical address received from host 1000 to a physical address used to actually store data in the non-volatile memory device 2200. Wear leveling is a technique used to prevent excessive degradation of specific blocks by allowing for uniform use of blocks in the non-volatile memory device 2200, and can be exemplarily implemented through firmware techniques for balancing erase counts of physical blocks. Garbage collection is a technique used to ensure available capacity in the non-volatile memory device 2200 by copying valid data from a block to a new block and then erasing the existing block.

[0155] Packet manager 2150 can generate packets according to the protocol of the interface negotiated with host 1000, or analyze various types of information from packets received from host 1000. Furthermore, buffer memory 2160 can temporarily store data to be written to or read from non-volatile memory device 2200.

[0156] The buffer memory 2160 may be located in the storage controller 2100 or external to the storage controller 2100.

[0157] ECC engine 2170 performs error detection and correction functions on read data read from non-volatile memory device 2200. More specifically, ECC engine 2170 generates parity bits for the data to be written to non-volatile memory device 2200, and the generated parity bits are stored in non-volatile memory device 2200 along with the written data. When reading data from non-volatile memory device 2200, ECC engine 2170 can correct errors in the read data by using the parity bits read from non-volatile memory device 2200 along with the read data, and then output the error-corrected read data.

[0158] The AES engine 218 can perform at least one of encryption and decryption operations on the data input to the storage controller 2100 using a symmetric key algorithm.

[0159] According to some embodiments, host 1000 can be connected to Figure 1 The host 10 corresponds to the storage device 2000. Figure 1 The storage device 20 corresponds to the storage controller 2100. Figure 1 The memory controller 200 corresponds to the non-volatile memory device 2200. Figure 1 The non-volatile memory device 100 corresponds to this.

[0160] According to some embodiments, the storage controller 2100 may classify a portion of a plurality of data blocks of the non-volatile memory device 2200 into a first group. The storage controller 2100 may also classify another portion of the plurality of data blocks of the non-volatile memory device 2200, different from the portion classified into the first group, into a second group. The storage controller 2100 may determine, based on environmental information, first setup data required for sensing data blocks included in the first group. The storage controller 2100 may determine, based on environmental information, second setup data required for sensing data blocks included in the second group. The storage controller 2100 may store initialization information regarding the determined setup data in the memory device.

[0161] According to some embodiments, the non-volatile memory device 2200 may include a memory cell array and control logic circuitry. The memory cell array includes a first data block and a second memory plane containing a second data block. The control logic circuitry is configured to write data to or read data from the memory cell array. The memory cell array may store first initialization information, first setting data, and second setting data. The first initialization information is used to determine setting data including sensing conditions for sensing each data block. The first setting data includes a first sensing condition, and the second setting data includes a second sensing condition. The control logic circuitry may perform a metadata open operation in response to an initialization command. The control logic circuitry may store the first setting data and the second setting data in an initialization register. The control logic circuitry may sense the first memory plane under a first sensing condition and sense the second memory plane under a second sensing condition based on the first initialization information. The control logic circuitry may receive second initialization information from a memory controller and update the first initialization information based on the second initialization information. The second initialization information is used to determine setting data including sensing conditions for sensing each data block.

[0162] Figure 22 This is a block diagram illustrating a system of application storage devices according to one or more example embodiments.

[0163] Figure 22 The system (or electronic system) 10000 can be a mobile system (such as a mobile communication terminal (e.g., a mobile phone), a smartphone, a tablet PC, a wearable device, a healthcare device, or an Internet of Things (IoT) device). However, Figure 22 The system 10000 is not limited to mobile systems and can be a personal computer, laptop computer, server, media player, or automotive device (e.g., a navigation system).

[0164] Reference Figure 22System 10000 may include a main processor 11000, memory (e.g., 12000a and 12000b), and storage devices (e.g., 13000a and 13000b). System 10000 may also include at least one of an image capturing device 14100, a user input device 14200, a sensor 14300, a communication device 14400, a display 14500, a speaker 14600, a power supply device 14700, and a connection interface 14800.

[0165] The main processor 11000 controls the overall operation of the electronic system 10000 (more specifically, the operation of other components constituting the electronic system 10000). The main processor 11000 can be implemented as a general-purpose processor, a special-purpose processor, or an application processor.

[0166] The main processor 11000 may include one or more CPU cores 11100, and may also include a controller 11200 configured to control memories 12000a and 12000b, and / or storage devices 13000a and 13000b. In some embodiments, the main processor 11000 may also include an accelerator 11300 as dedicated circuitry for high-speed data computation, such as artificial intelligence (AI) data computation. The accelerator 11300 may include a graphics processing unit (GPU), a neural network processor (NPU), and / or a data processor (DPU), and may be implemented as a separate chip physically separate from other components of the main processor 11000.

[0167] Memory 12000a and 12000b may be used as the main memory device of system 10000 and may include volatile memory (such as static random access memory (SRAM) and / or dynamic random access memory (DRAM)), but may also include non-volatile memory (such as flash memory, phase-change RAM (PRAM) and / or resistive PRAM). Memory 12000a and 12000b may be implemented in the same package as main processor 11000.

[0168] Storage devices 13000a and 13000b may be non-volatile storage devices for storing data regardless of whether power is supplied, and may have a larger storage capacity than memories 12000a and 12000b. Storage devices 13000a and 13000b may include storage controllers (STRG CTRL) 13100a and 13100b and non-volatile memory (NVM) 13200a and 13200b, which are configured to store data under the control of storage controllers 1310a and 1310b. Non-volatile memory 13200a and 13200b may include flash memory with a two-dimensional (2D) structure or a three-dimensional (3D) vertical NAND (V-NAND) structure, but may also include other types of non-volatile memory (such as PRAM and / or RRAM).

[0169] Storage devices 13000a and 13000b can be included in system 10000 in a physically separate state from the main processor 11000, and can be implemented in the same package as the main processor 11000. Furthermore, storage devices 13000a and 13000b can be of the type of solid-state drive (SSD) or memory card, and can be detachably coupled to other components of system 10000 via an interface (such as connection interface 1480, described later). Such storage devices 13000a and 13000b can be, but are not limited to, devices applying standard protocols such as Universal Flash Storage (UFS), embedded multimedia card (eMMC), or Non-Volatile Memory Fast (NVMe).

[0170] Image capturing device 14100 can capture still images or videos. Image capturing device 14100 may include a camera, video camera, and / or webcam.

[0171] User input device 14200 can receive various types of data input from users of system 10000 and may include a touchpad, keypad, keyboard, mouse and / or microphone.

[0172] Sensor 14300 can sense various types of physical quantities that can be obtained from outside the system 10000, and can convert the sensed physical quantities into electrical signals. Sensor 14300 may include temperature sensors, pressure sensors, illuminance sensors, position sensors, acceleration sensors, biosensors, and / or gyroscope sensors.

[0173] The communication device 14400 can perform signal transmission and reception between other devices outside the system 10000 according to various communication protocols. The communication device 14400 may include an antenna, a transceiver, and / or a modem.

[0174] The display 14500 and speaker 14600 can be used as output devices for a user configured to output visual and auditory information to the system 10000, respectively.

[0175] The power supply device 14700 can appropriately convert the power supplied from an external power source and / or a battery (not shown) embedded in the system 10000 to provide the converted power to each element of the system 10000.

[0176] The connection interface 14800 provides connectivity between the system 10000 and external devices connected to the system 10000 for sending and receiving data to and from the system 10000. The connection interface 14800 can be implemented in various interface modes, such as Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer Small Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI), PCI Fast (PCIe), NVM Fast (NVMe), IEEE 1394, Universal Serial Bus (USB) interface, Secure Digital (SD) card interface, Multimedia Card (MMC) interface, Embedded Multimedia Card (eMMC) interface, Universal Flash Storage (UFS) interface, Embedded Universal Flash Storage (eUFS) interface, and Compact Flash (CF) card interface.

[0177] According to some embodiments, the main processor 11000 can be coupled with... Figure 1 Corresponding to host 10. Each of storage devices 13000a and 13000b can be connected to... Figure 1 The storage device 20 corresponds to this.

[0178] Although some embodiments have been described above with reference to the accompanying drawings, the disclosure is not limited to these embodiments and can be implemented in various different forms. Those skilled in the art will understand that the disclosure can be implemented in other specific forms without altering the technical concept or essential characteristics. Therefore, it should be understood that the embodiments described above are not limiting in any way, but rather exemplary.

Claims

1. A memory controller, comprising: processing circuitry configured to control a memory device including a plurality of data blocks, wherein the processing circuitry is further configured to: classify a first portion of the plurality of data blocks into a first group; classify a second portion of the plurality of data blocks into a second group, the second portion being different from the first portion; determine first setting data based on the environmental information, the first setting data to be used for sensing data blocks included in the first group; determine second setting data based on the environmental information, the second setting data to be used for sensing data blocks included in the second group; and store initialization information about the determined first and second setting data in the memory device.

2. The memory controller of claim 1, wherein, the plurality of data blocks include first-level memory cells and second-level memory cells, the second-level memory cells storing a greater number of data bits per cell than the first-level memory cells, and wherein the processing circuitry is configured to classify data blocks including the first-level memory cells into the first group and to classify data blocks including the second-level memory cells into the second group.

3. The memory controller of claim 1, wherein, the processing circuitry is further configured to classify data blocks among the plurality of data blocks assigned to a first application into the first group and to classify data blocks among the plurality of data blocks assigned to a second application into the second group, the second application being different from the first application.

4. The memory controller of claim 1, wherein, the processing circuitry is further configured to classify data blocks among the plurality of data blocks included in a first memory die of the memory device into the first group and to classify data blocks among the plurality of data blocks included in a second memory die of the memory device into the second group, the first memory die being different from the second memory die.

5. The memory controller of claim 1, wherein, the processing circuitry is further configured to receive workload information about the plurality of data blocks from the memory device and to reclassify the plurality of data blocks into the first and second groups based on the workload information.

6. The memory controller of claim 5, wherein, the processing circuitry is further configured to update the environmental information based on the workload information.

7. The memory controller of claim 1, wherein, the environmental information includes a first retention parameter of data blocks included in the first group and a second retention parameter of data blocks included in the second group.

8. The memory controller of claim 7, wherein, the first retention parameter includes information about a retention request value of each of the data blocks included in the first group, and wherein the second retention parameter includes information about a retention request value of each of the data blocks included in the second group.

9. The memory controller of claim 1, wherein, the environmental information includes a first endurance parameter of data blocks included in the first group and a second endurance parameter of data blocks included in the second group.

10. The memory controller of claim 9, wherein, the first endurance parameter includes at least one of erase count information and program-erase cycle information of each of the data blocks included in the first group, and wherein the second endurance parameter includes at least one of erase count information and program-erase cycle information of each of the data blocks included in the second group.

11. The memory controller of claim 1, wherein, the processing circuitry is further configured to: classify a third portion of the plurality of data blocks into a third group, the third portion being different from the first and second portions; and determine third setting data based on the environmental information, the third setting data to be used for sensing data blocks included in the third group.

12. A memory device, comprising: a memory device including data blocks belonging to a first group and data blocks belonging to a second group; and a memory controller configured to control the memory device, wherein the memory controller is further configured to: determine first setting data based on the environment information, the first setting data including a first sensing condition to be used for sensing data blocks belonging to the first group; determine second setting data based on the environment information, the second setting data including a second sensing condition to be used for sensing data blocks belonging to the second group; and provide initialization information about the determined first setting data and second setting data to the memory device, and wherein the memory device is configured to: perform a setting operation in response to an initialization command of the memory controller; sense data blocks belonging to the first group under the first sensing condition based on the initialization information; and sense data blocks belonging to the second group under the second sensing condition based on the initialization information.

13. The memory device of claim 12, wherein, the memory device includes first-level memory cells and second-level memory cells that store a larger number of data bits per cell than the first-level memory cells, and wherein the data blocks belonging to the first group include data blocks including the first-level memory cells, and wherein the data blocks belonging to the second group include data blocks including the second-level memory cells.

14. The memory device of claim 12, wherein, the data blocks belonging to the first group include data blocks allocated to a first application, and wherein the data blocks belonging to the second group include data blocks allocated to a second application different from the first application.

15. The memory device of claim 12, wherein, the memory device includes a first memory die and a second memory die different from the first memory die, wherein the data blocks belonging to the first group include data blocks included in the first memory die, and wherein the data blocks belonging to the second group include data blocks included in the second memory die.

16. The memory device of claim 12, wherein, the memory controller is further configured to receive workload information about the data blocks belonging to the first group and the data blocks belonging to the second group from the memory device, and update the environment information based on the workload information.

17. The memory device of claim 12, wherein, the environment information includes a first retention parameter of the data blocks belonging to the first group and a second retention parameter of the data blocks belonging to the second group.

18. The memory device of claim 17, wherein, the first retention parameter includes information about a retention request value for each of the data blocks belonging to the first group, and wherein the second retention parameter includes information about a retention request value for each of the data blocks belonging to the second group.

19. The memory device of claim 12, wherein, the environment information includes a first durability parameter of the data blocks belonging to the first group and a second durability parameter of the data blocks belonging to the second group. 20.A method of operating a memory controller, the method comprising: classifying, by the memory controller, a plurality of data blocks included in a memory device into a first group and a second group; determining, by the memory controller, first setting data to be used for sensing data blocks belonging to the first group based on environment information; determining, by the memory controller, second setting data to be used for sensing data blocks belonging to the second group based on the environment information; and providing, by the memory controller, initialization information about the determined first setting data and second setting data for each group to the memory device.

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