Storage driving device, information processing device, and control method

Abstract

The invention relates to a storage driving apparatus, an information processing apparatus, and a control method. The storage drive device includes a data storage region, a test storage region, and a control unit. The data storage region is configured from a rewritable non-volatile memory and is capable of storing data used for information processing. The test storage region is configured from the non-volatile memory and stores predetermined test data. The control unit determines that a predetermined data retention period has been reached when date and time information acquired from a higher-level device is correct and when a power-off period based on the date and time information exceeds a threshold period, and determines that the predetermined data retention period has been reached when the date and time information is not correct. When the predetermined data storage period has been reached, it is determined on the basis of an index value relating to a storage failure for a test storage region in which predetermined test data has been stored in advance, and when the predetermined data storage period has been reached, the stored data is re-written to the data storage region.

Description

Technical Field

[0001] This invention relates to a storage drive device, an information processing device, and a control method. Background Technology

[0002] In recent years, storage drive devices such as SSDs (Solid State Drives) have been known (see, for example, Patent Document 1). In such storage drive devices, non-volatile memory such as NAND flash memory is used, for example.

[0003] Patent document 1: Japanese Patent Application Publication No. 2020-17262.

[0004] Furthermore, in rewritable non-volatile memories such as NAND flash memory, written data sometimes becomes corrupted over time. This characteristic of data corruption due to time is called retention characteristic, and the period during which the data is retained is called retention period. In the aforementioned conventional memory drive devices, it is difficult to determine the exact amount of time elapsed since the data was written, so data corruption may occur, for example, if the retention period has exceeded. Summary of the Invention

[0005] The present invention was made to solve the above-mentioned problems, and its purpose is to provide a storage drive device, an information processing device, and a control method that can reduce data garbled characters based on retention characteristics and improve reliability.

[0006] To address the aforementioned problems, one aspect of the present invention is a storage drive device having rewritable non-volatile memory. The storage drive device includes: a data storage area, composed of the non-volatile memory, capable of storing data used for information processing; a test storage area, also composed of the non-volatile memory, storing predetermined test data; and a control unit that, upon reaching a predetermined data retention period, rewrites the stored data in the data storage area. The control unit calculates the power-off period of the host device based on date and time information obtained from a host device connected to the storage drive device. If the obtained date and time information is correct and the power-off period exceeds a threshold period, the predetermined data retention period is determined to have been reached. If the date and time information is incorrect, the predetermined data retention period is determined to have been reached based on an indicator value related to poor storage of the test storage area containing the predetermined test data.

[0007] Alternatively, in the above-mentioned storage drive device, based on the first date and time information obtained from the BIOS (Basic Input Output System) of the host device as the date and time information obtained when the host device is started, and the second date and time information as the date and time information when the power of the storage drive device is stopped, the period during which the power is stopped is calculated, and based on the time relationship between the first date and time information and the second date and time information, it is determined whether the obtained date and time information is correct.

[0008] Alternatively, in the above-described storage drive device, the index value includes the bit error rate when reading the test data from the test storage area. If the date and time information is incorrect, the control unit determines, based on the bit error rate, that the specified data retention period has been reached, using the index value as the index value.

[0009] Alternatively, in the storage drive device described above, the control unit, when the date and time information is correct, uses the longer of a first power-off period calculated based on the first date and time information and the second date and time information, and a second power-off period inferred based on the bit error rate, as the power-off period; when the date and time information is incorrect, it uses the second power-off period as the power-off period; and when the power-off period exceeds the threshold period, it determines that the predetermined data retention period has been reached, and performs a rewrite of the stored data in the data storage area.

[0010] Alternatively, in another aspect of the present invention, the storage drive device may include a warning processing unit. If the date and time information obtained is correct, the warning processing unit may infer the average ambient temperature of the host device based on the difference between the first power-off period and the second power-off period. If the average ambient temperature is above a threshold temperature, the warning processing unit may output a warning message to the host device.

[0011] Alternatively, in the above-described storage drive device, the control unit uses an inference model to infer the power outage period based on the bit error rate to infer the second power outage period. The storage drive device includes an inference correction unit that corrects the inference model when the difference between the first power outage period and the second power outage period is greater than a certain period, so that the first power outage period and the second power outage period are consistent.

[0012] Alternatively, in the storage drive device described above, the control unit may rewrite the stored data in the data storage area when the date and time information is incorrect and the bit error rate reaches a predetermined threshold indicating that the specified data retention period has been reached.

[0013] Alternatively, in the storage drive device described above, if the date and time information is incorrect and the change in the bit error rate reaches a predetermined threshold indicating that the specified data retention period has been reached, the control unit performs a rewrite of the stored data in the data storage area.

[0014] In addition, one aspect of the present invention is an information processing apparatus that is a host device equipped with the aforementioned storage drive device and performs information processing using data stored in the aforementioned storage drive device.

[0015] Another aspect of the present invention is a control method for a storage drive device. The storage drive device has a rewritable non-volatile memory and includes: a data storage area, composed of the non-volatile memory, capable of storing data used for information processing; and a test storage area, composed of the non-volatile memory, storing predetermined test data. In the control method, a control unit calculates the power-off period of the host device based on date and time information obtained from a host device connected to the storage drive device. If the obtained date and time information is correct and the power-off period exceeds a threshold period, it determines that a predetermined data retention period has been reached. If the date and time information is incorrect, it determines that the predetermined data retention period has been reached based on an indicator value related to poor storage of the test storage area containing the predetermined test data. When the predetermined data retention period has been reached, the stored data is rewritten to the data storage area.

[0016] According to the above-described method of the present invention, data garbled characters based on retention characteristics can be reduced, thereby improving reliability. Attached Figure Description

[0017] Figure 1 This is a diagram illustrating an example of the main hardware structure of the information processing apparatus and SSD according to the first embodiment.

[0018] Figure 2 This is a block diagram illustrating an example of the functional structure of an SSD according to the first embodiment.

[0019] Figure 3 This is a flowchart illustrating an example of the operation of the SSD in the first embodiment.

[0020] Figure 4 This is a flowchart illustrating an example of the correction processing of the inference model of the SSD in the first embodiment.

[0021] Figure 5 This is a flowchart illustrating an example of warning handling for an SSD in the first embodiment.

[0022] Figure 6 This is a block diagram illustrating an example of the functional structure of the SSD in the second embodiment.

[0023] Figure 7 This is a flowchart illustrating an example of the operation of the SSD in the second embodiment.

[0024] Figure 8 This is a block diagram illustrating an example of the functional structure of the SSD in the third embodiment.

[0025] Figure 9 This is a flowchart illustrating an example of the operation of the SSD in the third embodiment.

[0026] Explanation of reference numerals in the attached figures

[0027] 10…Main control unit; 11…CPU; 12…Main memory; 13…Video subsystem; 14…Display unit; 21…Chipset; 22…BIOS memory; 31…Embedded controller (EC); 32…Input unit; 33…Power supply circuit; 40, 40a, 40b…SSD; 41…Flash memory; 42…Memory controller; 50, 50a, 50b…Data storage unit; 51…Data storage area; 52…ECC storage area; 53…Test storage area; 54…Timestamp storage area; 55…Inference model storage unit; 56…BER storage area; 60, 60a, 60b…Control unit; 61…Main I / F processing unit; 62…Memory I / F processing unit; 63…Data management unit; 64…ECC processing unit; 65, 65a, 65b…Test processing unit; 67…Correction processing unit; 68…Warning processing unit; 100…Information processing device. Detailed Implementation

[0028] Hereinafter, a storage drive device, an information processing device, and a control method according to one embodiment of the present invention will be described with reference to the accompanying drawings.

[0029] [First Implementation Method]

[0030] Figure 1 This is a diagram illustrating an example of the main hardware structure of the information processing device 100 and SSD 40 in the first embodiment.

[0031] like Figure 1As shown, the information processing device 100 is, for example, a notebook computer, which includes a CPU 11, a main memory 12, a video subsystem 13, a display unit 14, a chipset 21, a BIOS memory 22, an embedded controller 31, an input unit 32, a power supply circuit 33, and an SSD 40.

[0032] The CPU (Central Processing Unit) 11 performs various arithmetic operations through program control, and controls the entire information processing device 100.

[0033] Main memory 12 is a writable memory used as a read-in area for the CPU 11's executable program or as a work area for writing processing data to the executable program. Main memory 12 is, for example, composed of multiple DRAM (Dynamic Random Access Memory) chips. The executable program includes an OS (operating system), various drivers for hardware operations on peripheral devices, various services / utilities, applications, etc.

[0034] The video subsystem 13 is a subsystem for implementing functions related to image display and includes a video controller. The video controller processes drawing commands from the CPU 11, writes the processed drawing information into the video memory, and reads the drawing information from the video memory and outputs it as drawing data (display data) to the display unit 14.

[0035] The display unit 14 is, for example, a liquid crystal display, which displays a screen based on the drawing data (display data) output from the video subsystem 13.

[0036] Chipset 21 features controllers for USB (Universal Serial Bus), Serial ATA (AT Attachment), SPI (Serial Peripheral Interface), PCI (Peripheral Component Interconnect), PCI-Express, and LPC (Low Pin Count) buses, enabling the connection of multiple devices. Figure 1 In the example of the device, BIOS memory 22 and SSD 40 are connected to chipset 21.

[0037] Among them, CPU11 and chipset 21 correspond to main control unit 10.

[0038] The BIOS (Basic Input Output System) memory 22 is composed of electrically rewritable non-volatile memory such as EEPROM (Electrically Erasable Programmable Read Only Memory) or flash ROM. The BIOS memory 22 stores system firmware used to control the BIOS and embedded controller 31, etc.

[0039] The SSD (Solid State Drive) 40 (an example of a storage drive) is a storage drive with rewritable non-volatile memory that stores the operating system, various drivers, various services / utilities, applications, and various data. The information processing device 100 utilizes the data stored in the SSD 40 to perform various information processing tasks. The SSD 40 is connected to the chipset 21, for example, via a serial ATA or PCI-Express bus. The SSD 40 can also be connected to the CPU 11. In this embodiment, the SSD 40 is connected to the chipset 21 via an NVMe connection using a PCI-Express bus.

[0040] In addition, the SSD40 has multiple flash memory 41 and a memory controller 42.

[0041] Flash memory 41, for example, is NAND flash memory, an example of rewritable non-volatile memory. Flash memory 41 writes data ("0") or erases data ("1") to the memory cell by injecting or extracting electrons into the floating gate of the memory cell. In flash memory 41, the data stored in the memory cell sometimes becomes corrupted over time due to the movement of electrons in the floating gate. In flash memory 41, this characteristic of data corruption over time is called retention characteristic, and the period during which the data is retained is called retention period. Furthermore, there is a tendency for the retention period to shorten as the temperature increases.

[0042] The memory controller 42 is, for example, a processor including a CPU, ROM, RAM, etc. (not shown), which uniformly controls the SSD 40. The memory controller 42 performs, for example, control processing of the main interface (main I / F) with the chipset 21, control processing of the memory interface (memory I / F) with the flash memory 41, and data management processing of the flash memory 41.

[0043] The embedded controller 31 is a one-chip microcomputer that monitors and controls various devices (peripheral devices, sensors, etc.) independently of the system state of the information processing device 100. Furthermore, the embedded controller 31 has power management functions for controlling the power supply circuit 33. In addition, the embedded controller 31 is composed of a CPU, ROM, RAM, etc. (not shown), and has multiple channels of A / D input terminals, D / A output terminals, timers, and digital input / output terminals. The embedded controller 31 controls the operation of input units 32 and power supply circuits 33, for example, connected to these input / output terminals.

[0044] The input unit 32 is, for example, an input device such as a keyboard, a pointing device, or a touchpad.

[0045] The power supply circuit 33 includes, for example, a DC / DC converter, a charging / discharging unit, and an AC / DC adapter, which converts the DC voltage supplied from an external power source or battery into multiple voltages required to operate the information processing device 100. Furthermore, the power supply circuit 33 supplies power to various parts of the information processing device 100 based on control from the embedded controller 31.

[0046] Next, refer to Figure 2 The functional structure of the SSD40 in this embodiment will be explained.

[0047] Figure 2 This is a block diagram illustrating an example of the functional structure of the SSD40 in this embodiment.

[0048] like Figure 2 As shown, the SSD40 includes a data storage unit 50 and a control unit 60.

[0049] The SSD40 is connected to the main control unit 10 of the host device (information processing device 100) via an NVMe connection.

[0050] The main control unit 10 is a functional unit implemented by executing programs stored in the main memory 12 through the CPU 11 and chipset 21, and performs various OS-based processing. For example, the main control unit 10 performs information processing using data stored in the SSD 40. Furthermore, the main control unit 10 boots the OS (e.g., Windows) by executing a BIOS program. The main control unit 10 includes, for example, a BIOS processing unit 101.

[0051] The BIOS processing unit 101 is a functional unit implemented by causing the CPU 11 to execute the BIOS program, and performs various BIOS processes. For example, the BIOS processing unit 101 performs the process of booting the OS. In addition, when the boot information processing device 100 is started, the BIOS processing unit 101 sends a timestamp (date and time information) to the SSD 40 through the NVMe Timestamp function.

[0052] The data storage unit 50 is, for example, a storage unit composed of a plurality of flash memory 41 as described above, and includes, for example, a data storage area 51, an ECC (Error Correction Code) storage area 52, a test storage area 53, a timestamp storage area 54, and an inference model storage unit 55.

[0053] Data storage area 51 is composed of flash memory 41 and is a storage area capable of storing data used for information processing. Data storage area 51 may store, for example, the operating system, various drivers, various services / utilities, applications, and various data.

[0054] ECC storage area 52 is composed of flash memory 41 and is a storage area for storing error correction codes (ECCs) for the data stored in data storage area 51 and test storage area 53. For example, ECC storage area 52 stores the error correction code (ECC) corresponding to the data when data is stored in (written to) data storage area 51 or test storage area 53.

[0055] The test storage area 53 is composed of flash memory 41 and stores specified test data. The test storage area 53 stores test data used to determine whether a specified data retention period, representing a predetermined period, has been reached since the data was written. For example, test data is stored in the test storage area 53 when the information processing device 100 is manufactured. Alternatively, for example, the test data may be stored (rewritten) in the test storage area 53 again after the information processing device 100 is manufactured and the OS is reinstalled.

[0056] The timestamp storage area 54 is composed of flash memory 41 and stores BIOS timestamps obtained from the BIOS (timestamp at startup), power-off timestamps (power-off timestamp), etc. The timestamp storage area 54 can also store the history of past BIOS timestamps and power-off timestamps.

[0057] The inference model storage unit 55 is composed of flash memory 41, which stores an inference model that infers the power-off time based on the bit error rate (hereinafter referred to as BER) when reading test data from the test storage area 53. The power-off time refers to the period during which the power is cut off in the information processing device 100.

[0058] The inference model, for example, uses the following equation (1) which represents the data retention period (AF) that can be inferred, past BER and actual values ​​of power outage time to infer the power outage time from the BER.

[0059] [Formula 1]

[0060]

[0061] In equation (1), k represents the Boltzmann constant, and H represents the activation energy. Additionally, T1 represents the test temperature (43℃ = 316.15K), and T2 represents the actual temperature.

[0062] The control unit 60 is a functional unit implemented by the memory controller 42 described above, and performs various processes of the SSD 40. The control unit 60 includes a main I / F processing unit 61, a memory I / F processing unit 62, a data management unit 63, an ECC processing unit 64, a test processing unit 65, a counting processing unit 66, a correction processing unit 67, and a warning processing unit 68.

[0063] The main I / F processing unit 61 controls the interface between the chipset 21 and the SSD 40. For example, the main I / F processing unit 61 controls the PCI-Express bus (NVMe) interface, receiving commands for writing and reading data from the chipset 21. Additionally, the main I / F processing unit 61 outputs data, such as data read from the data storage unit 50, to the chipset 21 via the PCI-Express bus (NVMe) interface. The main I / F processing unit 61 can also control the interface between the CPU 11 and the SSD 40.

[0064] The memory I / F processing unit 62 controls the interface between the control unit 60 (memory controller 42) and the data storage unit 50 (multiple flash memory flashes 41). The memory I / F processing unit 62 outputs erase, write, and read commands to the flash memory flashes 41, for example, and controls the flash memory flashes 41.

[0065] The data management unit 63 manages the correspondence between the logical addresses of the SSD 40 used for control and the physical addresses of the data storage unit 50 (flash memory 41) from the information processing device 100, and manages the data stored in the data storage unit 50. The data management unit 63 performs various processes based on various instructions received from the chipset 21 by the main I / F processing unit 61.

[0066] The ECC processing unit 64 (an example of a correction processing unit) corrects errors in the data read from the data storage unit 50 based on ECC (Error Correction Code). For example, the ECC processing unit 64 determines whether data garbled characters (bit garbled characters) have occurred based on the read data and the ECC corresponding to the read data. If data garbled characters (bit garbled characters) have occurred, it uses ECC to perform error correction processing to correct the data garbled characters.

[0067] If the SSD 40 reaches the specified data retention period, the test processing unit 65 performs at least a rewrite of the already stored data in the data storage area 51. For example, the test processing unit 65 switches between and utilizes the power-off time A (first power-off period) based on the timestamp (BIOS timestamp) obtained from the main control unit 10 (host device) and the power-off time B (second power-off period) based on the BER of the test storage area 53 to determine whether the specified data retention period has been reached.

[0068] The test processing unit 65 calculates the power-off time (power-off period) of the host device based on the BIOS timestamp (date and time information) obtained from the host device (main control unit 10 of information processing device 100) connected to the SSD 40. For example, the test processing unit 65 calculates the power-off time A by the difference between the obtained BIOS timestamp (first date and time information) and the timestamp stored in the timestamp storage area 54 (past timestamps such as power-off timestamp (second power-off period)).

[0069] Furthermore, the test processing unit 65 infers the power-off time B based on indicator values ​​related to storage defects in the test storage area 53, which contains pre-stored specified test data. Indicator values ​​related to storage defects include, for example, the bit error rate (BER) when reading test data from the test storage area 53. The test processing unit 65 calculates the BER from the test storage area 53, for example, using an inference model stored in the inference model storage unit 55, and infers the power-off time B based on the calculated BER.

[0070] Furthermore, the test processing unit 65 determines whether the acquired BIOS timestamp is correct. For example, the test processing unit 65 determines the correctness of the acquired BIOS timestamp by checking for any discrepancies between the acquired BIOS timestamp and the timestamp stored in the timestamp storage area 54. That is, the test processing unit 65 determines the correctness of the acquired BIOS timestamp based on the time relationship between the BIOS timestamp and the power-off timestamp.

[0071] In cases where the BIOS timestamp is incorrect, for example, consider resetting the RTC (Real Time Clock) of the chipset 21 of the information processing device 100, or cutting off the battery (backup power) power supply for the RTC.

[0072] If the obtained BIOS timestamp is correct, the test processing unit 65 uses the longer of power-off time A and power-off time B for the power-off time. Conversely, if the obtained BIOS timestamp is incorrect, the test processing unit 65 uses power-off time B for the power-off time.

[0073] Furthermore, if the power-off time exceeds a threshold period, the test processing unit 65 determines that the specified data retention period has been reached and performs a rewrite of the already stored data in the data storage area 51. That is, if the obtained BIOS timestamp is correct and the power-off time exceeds the threshold period, the test processing unit 65 determines that the specified data retention period has been reached and performs a rewrite of the already stored data in the data storage area 51.

[0074] The test processing unit 65, via the memory I / F processing unit 62, saves the data already stored in the data storage area 51 in the buffer storage unit composed of RAM (not shown), and then writes (restores) the data.

[0075] In addition, if the obtained BIOS timestamp is incorrect, the test processing unit 65 uses power-off time B for the power-off time. Therefore, in the case of an incorrect timestamp, it determines that the specified data retention period has been reached based on the index value (e.g., BER) related to the storage failure of the test storage area 53.

[0076] Furthermore, when the test processing unit 65 rewrites the already stored data to the data storage area 51, other areas (test storage area 53, timestamp storage area 54, inference model storage unit 55, etc.) can also rewrite data at the same time.

[0077] The counting processing unit 66 stores the acquired BIOS timestamp in the timestamp storage area 54 and uses the internal clock of the SSD 40 to count the date and time based on the BIOS timestamp.

[0078] When the difference between power-off time A and power-off time B is greater than a certain period, the correction processing unit 67 corrects the inference model to make power-off time A and power-off time B consistent. For example, the correction processing unit 67 adjusts the activation energy H in the above formula (1) to correct the inference model to make power-off time A and power-off time B consistent. The correction processing unit 67 stores the corrected inference model in the inference model storage unit 55.

[0079] If the obtained BIOS timestamp is correct, the warning processing unit 68 infers the average ambient temperature of the information processing device 100 (host device) based on the difference between power-off time A and power-off time B. The warning processing unit 68 infers the average ambient temperature of the information processing device 100 (host device) using, for example, the above-described formula (1). If the average ambient temperature is above a threshold temperature, the warning processing unit 68 outputs a warning message (e.g., a warning message) to the host device (the main control unit 10 of the information processing device 100). Here, the threshold temperature is, for example, a temperature exceeding the upper limit of the guaranteed storage temperature of the SSD 40. The warning processing unit 68 sends a warning message indicating that the guaranteed storage temperature exceeds the upper limit and saves it as a warning message to the main control unit 10 and outputs it to the information processing device 100.

[0080] Next, the operation of the SSD40 in this embodiment will be described with reference to the accompanying drawings.

[0081] Figure 3 This is a flowchart illustrating an example of the operation of the SSD40 in this embodiment. Here, the SSD40's handling of preventing data corruption based on data retention will be explained.

[0082] like Figure 3 As shown, the control unit 60 of the SSD40 first obtains a timestamp from the BIOS of the information processing device 100 (step S101). The test processing unit 65 of the control unit 60 obtains the timestamp sent by the BIOS processing unit 101 of the main control unit 10 through the NVMe Timestamp function, and uses it as the BIOS timestamp (first date and time information). In addition, the counting processing unit 66 of the control unit 60 stores the obtained BIOS timestamp in the timestamp storage area 54, and uses the internal clock of the SSD40 to count the date and time from the BIOS timestamp.

[0083] Next, the test processing unit 65 calculates the power-off time A based on the acquired timestamp and the timestamp of the last power-off (step S102). For example, the test processing unit 65 calculates the power-off time A by the difference between the acquired BIOS timestamp and the power-off timestamp stored in the timestamp storage area 54.

[0084] Next, the test processing unit 65 calculates the BER of the test storage area 53 (step S103). The test processing unit 65 reads the test data of the test storage area 53 via the memory I / F processing unit 62 and calculates the BER.

[0085] Next, the test processing unit 65 infers the power disconnection time B based on the BER (step S104). The test processing unit 65 uses the inference model stored in the inference model storage unit 55 to infer the power disconnection time B based on the BER.

[0086] Next, the test processing unit 65 determines whether the timestamp obtained from the BIOS is correct (step S105). For example, the test processing unit 65 determines whether the obtained BIOS timestamp is correct based on whether there is a contradiction between the obtained BIOS timestamp and the timestamp stored in the timestamp storage area 54. That is, the test processing unit 65 determines whether the obtained BIOS timestamp is correct based on the time relationship between the BIOS timestamp and the power-off timestamp. If the BIOS timestamp is correct (step S105: Yes), the test processing unit 65 proceeds to step S106. Conversely, if the BIOS timestamp is incorrect (step S105: No), the test processing unit 65 proceeds to step S107.

[0087] In step S106, the test processing unit 65 uses the longer of power-off time A and power-off time B for the power-off time. After processing in step S106, the test processing unit 65 proceeds to step S108.

[0088] Additionally, in step S107, the test processing unit 65 uses power-off time B for the power-off time. After processing in step S107, the test processing unit 65 proceeds to step S108.

[0089] Next, in step S108, the test processing unit 65 determines whether the power-off time exceeds a threshold period. If the power-off time exceeds the threshold period (step S108: Yes), the test processing unit 65 determines that the predetermined data retention period has been reached, and proceeds to step S109. Conversely, if the power-off time does not exceed the threshold period (below the threshold period) (step S108: No), the test processing unit 65 determines that the predetermined data retention period has not been reached, and proceeds to step S110.

[0090] In step S109, the test processing unit 65 performs a data refresh process. For example, the test processing unit 65 saves the data already stored in the data storage area 51 in a buffer storage unit composed of RAM (not shown) via the memory I / F processing unit 62, and then writes (restores) the data.

[0091] Next, in step S110, the test processing unit 65 determines whether a shutdown request has been received from the BIOS. The test processing unit 65 determines, via the main I / F processing unit 61, whether a shutdown request instruction has been received from the BIOS. If a shutdown request has been received from the BIOS (step S110: Yes), the test processing unit 65 proceeds to step S111. Conversely, if no shutdown request has been received from the BIOS (step S110: No), the test processing unit 65 returns to step S110.

[0092] In step S111, the test processing unit 65 stores a timestamp in the timestamp storage area 54 before powering off. The test processing unit 65 also stores the power-off timestamp (second date and time information) after the counting processing unit 66 uses the internal clock of the SSD 40 to count in the timestamp storage area 54. After the processing in step S111, the test processing unit 65 performs the power-off process for the SSD 40 and ends the process.

[0093] Next, refer to Figure 4 The correction process for the inference model of SSD40 is explained.

[0094] Figure 4 This is a flowchart illustrating an example of the correction processing of the inference model of the SSD40 in this embodiment.

[0095] like Figure 4 As shown, the correction processing unit 67 of the control unit 60 determines whether the timestamp obtained from the BIOS is correct (step S201). If the timestamp obtained from the BIOS (BIOS timestamp) is correct (step S201: Yes), the correction processing unit 67 causes the process to proceed to step S202. Otherwise, if the timestamp obtained from the BIOS (BIOS timestamp) is incorrect (step S201: No), the correction processing unit 67 causes the process to return to step S201.

[0096] In step S202, the correction processing unit 67 determines whether the difference between power-off time A and power-off time B is greater than or equal to a certain period. If the difference between power-off time A and power-off time B is greater than or equal to a certain period (step S202: Yes), the correction processing unit 67 proceeds to step S203. Otherwise, if the difference between power-off time A and power-off time B is less than a certain period (step S202: No), the correction processing unit 67 returns to step S201.

[0097] In step S203, the correction processing unit 67 performs a recalibration of the test storage area 53 to correct the inference model. The correction processing unit 67 corrects the inference model to make the power-off time A and the power-off time B consistent. For example, the correction processing unit 67 adjusts the activation energy H of the above formula (1) to correct the inference model to make the power-off time A and the power-off time B consistent. The correction processing unit 67 stores the corrected inference model in the inference model storage unit 55. After the processing in step S203, the correction processing unit 67 returns the processing to step S201.

[0098] Next, refer to Figure 5 This section explains how to handle warnings from SSD40.

[0099] Figure 5 This is a flowchart illustrating an example of warning handling in the SSD40 of this embodiment.

[0100] like Figure 5 As shown, the warning processing unit 68 of the control unit 60 determines whether the timestamp obtained from the BIOS is correct (step S301). If the timestamp obtained from the BIOS (BIOS timestamp) is correct (step S301: Yes), the warning processing unit 68 causes the process to proceed to step S302. Otherwise, if the timestamp obtained from the BIOS (BIOS timestamp) is incorrect (step S301: No), the warning processing unit 68 causes the process to return to step S301.

[0101] In step S302, the warning processing unit 68 infers the average ambient temperature based on the difference between the power-off time A and the power-off time B. For example, the warning processing unit 68 uses the above-described formula (1) to infer the average ambient temperature of the information processing device 100 (host device).

[0102] Next, the warning processing unit 68 determines whether the average ambient temperature is above the threshold temperature (step S303). If the average ambient temperature is above the threshold temperature (step S303: Yes), the warning processing unit 68 proceeds to step S303. Otherwise, if the average ambient temperature is below the threshold temperature (step S303: No), the warning processing unit 68 returns the process to step S301.

[0103] In step S304, the warning processing unit 68 sends a warning message to the information processing device 100. For example, the warning processing unit 68 sends a message warning that the upper limit of the guaranteed storage temperature has been exceeded and that this situation has been saved as a warning message to the main control unit 10, and outputs it to the information processing device 100. After processing in step S304, the warning processing unit 68 returns the processing to step S301.

[0104] As explained above, the SSD 40 (storage drive device) of this embodiment is a storage drive device having rewritable flash memory 41 (non-volatile memory), and includes a data storage area 51, a test storage area 53, and a control unit 60. The data storage area 51 is composed of flash memory 41 and is an area capable of storing data used for information processing. The test storage area 53 is composed of flash memory 41 and stores predetermined test data. When a predetermined data retention period is reached, the control unit 60 rewrites the already stored data in the data storage area 51. Based on the BIOS timestamp (date and time information) obtained from the host device (information processing device 100) connected to the SSD 40, the control unit 60 calculates the power-off time (power-off period) of the host device. If the obtained BIOS timestamp is correct and the power-off time exceeds a threshold period, the control unit 60 determines that the predetermined data retention period has been reached. If the timestamp is incorrect, the control unit 60 determines that the predetermined data retention period has been reached based on an indicator value (e.g., BER) related to poor storage of the test storage area 53, which pre-stores predetermined test data.

[0105] Therefore, the SSD 40 (storage drive device) of this embodiment switches between determining whether a predetermined data retention period has been reached based on the power-off time (power-off period) of the BIOS timestamp (date and time information) obtained from the host device (information processing device 100) and determining whether a predetermined data retention period has been reached based on an indicator value (e.g., BER). Thus, the SSD 40 (storage drive device) of this embodiment can appropriately and reliably determine whether the predetermined data retention period has been reached, and therefore can appropriately rewrite the data storage area 51 before data corruption occurs, reducing data corruption based on retention characteristics and improving reliability.

[0106] Furthermore, in this embodiment, the control unit 60 calculates the power disconnection time based on the timestamp obtained when the host device is started (i.e., the BIOS timestamp, or first date and time information) and the timestamp when the SSD 40's power is cut off (i.e., the power cut-off timestamp, or second date and time information) obtained from the host device's BIOS, and the power disconnection timestamp. Additionally, the control unit 60 determines whether the obtained BIOS timestamp is correct based on the time relationship between the BIOS timestamp and the power cut-off timestamp.

[0107] Therefore, the SSD40 of this embodiment can easily calculate the power-off time using the BIOS timestamp (first date and time information) and the power-off timestamp (second date and time information). Furthermore, the SSD40 of this embodiment can appropriately determine whether the BIOS timestamp is correct by using the time relationship between the BIOS timestamp and the power-off timestamp. Thus, by appropriately utilizing the power-off time calculated based on the BIOS timestamp, the SSD40 of this embodiment can reduce data corruption based on retention characteristics and improve reliability.

[0108] Furthermore, in this embodiment, the indicator value includes the bit error rate (BER) when reading test data from the test storage area 53. When the BIOS timestamp is incorrect, the control unit 60 determines, based on the bit error rate (BER), that the predetermined data retention period has been reached, using this as an indicator value.

[0109] Therefore, even when temperature changes occur during periods when the information processing device 100 is not powered on, the SSD 40 of this embodiment can accurately determine the possibility of data corruption based on retention by utilizing the bit error rate (BER). Thus, the SSD 40 of this embodiment can more appropriately reduce data corruption based on the retention characteristics of the flash memory 41.

[0110] Furthermore, in this embodiment, when the BIOS timestamp is correct, the control unit 60 uses the longer of either the power-off time A (first power-off period) calculated based on the BIOS timestamp and the power-off timestamp, or the power-off time B (second power-off period) inferred based on the bit error rate (BER), as the power-off time. Conversely, when the BIOS timestamp is incorrect, the control unit 60 uses power-off time B as the power-off time. If the power-off time exceeds a threshold period, the control unit 60 determines that a predetermined data retention period has been reached and performs a rewrite of the already stored data in the data storage area 51.

[0111] Therefore, the SSD 40 of this embodiment uses a more appropriate power-off time between power-off time A (first power-off period) and power-off time B (second power-off period) to properly and accurately determine that the specified data retention period has been reached, and can more appropriately reduce data garbled characters based on the retention characteristics of flash memory 41.

[0112] Furthermore, the SSD 40 in this embodiment includes a warning processing unit 68. When the obtained BIOS timestamp is correct, the warning processing unit 68 infers the average ambient temperature of the host device based on the difference between power-off time A and power-off time B. If the average ambient temperature is above a threshold temperature, it outputs a warning message to the host device. Here, the threshold temperature is, for example, a specified temperature exceeding the upper limit of the guaranteed storage temperature of the SSD 40.

[0113] Therefore, the SSD40 of this embodiment can output a warning to the user, for example, when storing the SSD40 in a condition that exceeds the upper limit of the guaranteed storage temperature or in a high-temperature environment.

[0114] Furthermore, in this embodiment, the control unit 60 uses an inference model that infers the power-off time based on the bit error rate to infer the power-off time B. The SSD 40 in this embodiment includes a correction processing unit 67. The correction processing unit 67 corrects the inference model when the difference between the power-off time A and the power-off time B is greater than a certain period, so that the power-off time A and the power-off time B are consistent.

[0115] Therefore, when the difference between the power-off time A based on the BIOS timestamp and the power-off time B based on BER increases, the SSD40 of this embodiment can appropriately correct the inference model and improve the inference accuracy of the power-off time.

[0116] Furthermore, the information processing device 100 of this embodiment is a host device that includes the SSD 40 described above and uses the data stored in the SSD 40 to perform information processing.

[0117] Therefore, the information processing device 100 of this embodiment achieves the same effect as the SSD 40 of this embodiment described above, which can reduce data garbled characters based on retention characteristics and improve reliability.

[0118] Furthermore, the control method of this embodiment is a control method for an SSD 40. The SSD 40 has a rewritable flash memory 41 and includes: a data storage area 51 composed of the flash memory 41, capable of storing data used for information processing; and a test storage area 53 composed of the flash memory 41, storing predetermined test data. The control method includes a first processing step, a second processing step, and a third processing step. In the first processing step, the control unit 60 calculates the power-off time of the host device based on the BIOS timestamp obtained from the host device (information processing device 100) connected to the SSD 40. If the obtained BIOS timestamp is correct and the power-off time exceeds a threshold period, it determines that the predetermined data retention period has been reached. In the second processing step, if the BIOS timestamp is incorrect, the control unit 60 determines that the predetermined data retention period has been reached based on an indicator value (e.g., BER) related to poor storage of the test storage area 53, which pre-stores predetermined test data. In the third processing step, if the predetermined data retention period has been reached, the control unit 60 rewrites the already stored data to the data storage area 51.

[0119] Therefore, the control method of this embodiment achieves the same effect as the SSD40 of this embodiment described above, which can reduce data garbled characters based on retention characteristics and improve reliability.

[0120] [Second Implementation]

[0121] Next, the SSD40a of the second embodiment will be described with reference to the accompanying drawings.

[0122] In the second embodiment, a variation of the determination of whether the data retention period based on BER has been reached will be described without using the power disconnection time.

[0123] Figure 6 This is a block diagram illustrating an example of the functional structure of the SSD40a in this embodiment.

[0124] like Figure 6 As shown, the SSD40a (an example of a storage drive device) includes a data storage unit 50a and a control unit 60a.

[0125] Furthermore, in this figure, for... Figure 2 The same structures are given the same reference numerals, and their descriptions are omitted. Furthermore, the hardware structure of the SSD40a and the information processing device 100 in this embodiment is similar to... Figure 1 The first embodiment shown is the same, so its description is omitted here.

[0126] The data storage unit 50a is a storage unit composed of the aforementioned multiple flash memory 41, and for example, includes a data storage area 51, an ECC storage area 52, a test storage area 53, and a timestamp storage area 54.

[0127] In this embodiment, the data storage unit 50a differs from the data storage unit 50 in the first embodiment in that it does not have an inference model storage unit 55.

[0128] The control unit 60a is a functional unit implemented by the memory controller 42 described above, and performs various processes of the SSD 40a. The control unit 60a includes a main I / F processing unit 61, a memory I / F processing unit 62, a data management unit 63, an ECC processing unit 64, a test processing unit 65a, and a counting processing unit 66.

[0129] In this embodiment, the control unit 60a differs from the control unit 60 in the following ways: it does not have a correction processing unit 67 and a warning processing unit 68; and the processing of the test processing unit 65a is different.

[0130] If the BIOS timestamp is correct, the test processing unit 65a calculates the power-off time based on the BIOS timestamp. If the BIOS timestamp is correct and the power-off time exceeds a threshold period, the test processing unit 65a determines that the specified data retention period has been reached and performs a rewrite of the already stored data to the data storage area 51.

[0131] In addition, the test processing unit 65a calculates the BER for the test storage area 53. If the BIOS timestamp is incorrect and the BER reaches the specified threshold indicating that the specified data retention period has been reached, it determines that the specified data retention period has been reached and performs a rewrite of the stored data in the data storage area 51.

[0132] The details of the power-off time calculation and the BER calculation of the test processing unit 65a are the same as those of the test processing unit 65 in the first embodiment described above, so their description is omitted here.

[0133] Next, refer to Figure 7 The operation of the SSD40a in this embodiment will be explained.

[0134] Figure 7 This is a flowchart illustrating an example of the operation of the SSD40a in this embodiment. Here, the SSD40a's handling of preventing data corruption based on retention will be explained.

[0135] exist Figure 7 In this process, the steps from S401 to S403 are the same as described above. Figure 3The processes from step S101 to step S103 shown are the same, so their description is omitted here. Furthermore, in this embodiment, in step S402, the test processing unit 65a calculates the power-off time A as the power-off time.

[0136] Next, in step S404, the test processing unit 65a determines whether the timestamp obtained from the BIOS is correct. For example, the test processing unit 65a determines whether the obtained BIOS timestamp is correct based on whether there is a contradiction between the obtained BIOS timestamp and the timestamp stored in the timestamp storage area 54. That is, the test processing unit 65a determines whether the obtained BIOS timestamp is correct based on the time relationship between the BIOS timestamp and the power-off timestamp. If the BIOS timestamp is correct (step S404: Yes), the test processing unit 65a proceeds to step S405. Conversely, if the BIOS timestamp is incorrect (step S404: No), the test processing unit 65a proceeds to step S406.

[0137] In step S405, the test processing unit 65a determines whether the power-off time exceeds a threshold period. If the power-off time exceeds the threshold period (step S405: Yes), the test processing unit 65a determines that the predetermined data retention period has been reached, and proceeds to step S407. Conversely, if the power-off time does not exceed the threshold period (below the threshold period) (step S405: No), the test processing unit 65a determines that the predetermined data retention period has not been reached, and proceeds to step S408.

[0138] Additionally, in step S406, the test processing unit 65a determines whether the BER is above a predetermined threshold. Here, the predetermined threshold is a value indicating that a predetermined data retention period has been reached. That is, the test processing unit 65a determines whether the predetermined data retention period has been reached based on the BER. If the BER is above the predetermined threshold (step S406: Yes), the test processing unit 65a proceeds to step S407. If the BER is below the predetermined threshold (step S406: No), the test processing unit 65a proceeds to step S408.

[0139] In step S407, the test processing unit 65a performs a data refresh process. For example, the test processing unit 65a saves the data already stored in the data storage area 51 in a buffer storage unit composed of RAM (not shown) via the memory I / F processing unit 62, and then writes (restores) the data.

[0140] Next, the processing in steps S408 and S409 is the same as described above. Figure 3 The processes of steps S110 and S111 shown are the same, so their descriptions are omitted here.

[0141] As described above, the SSD 40a of this embodiment includes a data storage area 51, a test storage area 53, and a control unit 60a. The control unit 60a calculates the power-off time (power-off period) of the host device based on the BIOS timestamp (date and time information) obtained from the host device to which the SSD 40 is connected. If the obtained BIOS timestamp is correct and the power-off time exceeds a threshold period, it determines that the predetermined data retention period has been reached. Conversely, if the timestamp is incorrect, the control unit 60a determines that the predetermined data retention period has been reached based on an indicator value (e.g., BER) related to poor storage of the test storage area 53, which pre-stores predetermined test data. When the predetermined data retention period has been reached, the control unit 60a rewrites the already stored data to the data storage area 51.

[0142] Therefore, the SSD40a of this embodiment, like the SSD40 of the first embodiment described above, can appropriately rewrite the data storage area 51 before data corruption occurs, thereby reducing data corruption based on retention characteristics and improving reliability.

[0143] In addition, in this embodiment, if the BIOS timestamp is incorrect and the bit error rate (BER) reaches a predetermined threshold indicating that the predetermined data retention period has been reached, the control unit 60a performs a rewrite of the already stored data in the data storage area 51.

[0144] Therefore, the SSD40a of this embodiment achieves the same effect as the SSD40 of the first embodiment described above, which can reduce data garbled characters based on retention characteristics and improve reliability.

[0145] [Third Implementation Method]

[0146] Next, the SSD40b of the third embodiment will be described with reference to the accompanying drawings.

[0147] In the third embodiment, a variation of the second embodiment, which determines the duration of a predetermined data retention period by the change in the index value (BER), will be described.

[0148] Figure 8 This is a block diagram illustrating an example of the functional structure of the SSD40b in this embodiment.

[0149] like Figure 8 As shown, the SSD40b (an example of a storage drive device) includes a data storage unit 50b and a control unit 60b.

[0150] Furthermore, in this figure, for... Figure 6 The same structures are given the same reference numerals, and their descriptions are omitted. Furthermore, the hardware structure of the SSD40b and the information processing device 100 in this embodiment is similar to... Figure 1 The first embodiment shown is the same, so its description is omitted here.

[0151] The data storage unit 50b is a storage unit composed of the aforementioned multiple flash memory 41, and for example, it includes a data storage area 51, an ECC storage area 52, a test storage area 53, a timestamp storage area 54, and a BER storage area 56.

[0152] The BER storage area 56 is composed of flash memory 41 and stores the initial value of the BER of the test storage area 53. Furthermore, the initial value of the BER is updated when data is rewritten to the data storage area 51 via the test processing unit 65b.

[0153] The control unit 60b is a functional unit implemented by the memory controller 42 described above, and performs various processes of the SSD 40b. The control unit 60b includes a main I / F processing unit 61, a memory I / F processing unit 62, a data management unit 63, an ECC processing unit 64, a test processing unit 65b, and a counting processing unit 66.

[0154] If the BIOS timestamp is correct, the test processing unit 65b calculates the power-off time based on the BIOS timestamp. If the BIOS timestamp is correct and the power-off time exceeds a threshold period, the test processing unit 65b determines that the specified data retention period has been reached and performs a rewrite of the already stored data to the data storage area 51.

[0155] In addition, the test processing unit 65b calculates the BER for the test storage area 53. If the BIOS timestamp is incorrect and the change in BER reaches the specified threshold indicating that the specified data retention period has been reached, it determines that the specified data retention period has been reached and performs a rewrite of the stored data in the data storage area 51.

[0156] For example, the test processing unit 65b calculates the BER of the test storage area 53 and obtains the initial value of the BER stored in the BER storage area 56. If the change in the calculated BER from the initial value of the BER exceeds a predetermined threshold ΔR1, the test processing unit 65b determines that a predetermined data retention period has been reached. Here, the predetermined threshold ΔR1 is, for example, based on the retention characteristics of the flash memory 41 (the relationship between the elapsed time and data corruption), and in the error correction processing based on the ECC processing unit 64, it is set to the amount of BER change corresponding to the period within which the data in the test storage area 53 can be corrected.

[0157] In addition, when the change in BER reaches or exceeds a predetermined threshold ΔR1, the test processing unit 65b rewrites the already stored data to the data storage area 51 and updates the initial value of BER stored in the BER storage area 56 to the calculated current BER value.

[0158] Furthermore, the processing of the test processing unit 65b in this embodiment differs from the processing point where it determines that the data retention period has reached the specified amount of change based on the aforementioned index value (BER). Other processing is the same as that of the test processing unit 65a in the second embodiment.

[0159] Next, refer to Figure 9 The operation of the SSD40b in this embodiment will be explained.

[0160] Figure 9 This is a flowchart illustrating an example of the operation of the SSD40b in this embodiment. Here, the SSD40b's handling of preventing data corruption based on data retention will be explained.

[0161] exist Figure 9 In this process, the steps from S501 to S505 are the same as described above. Figure 7 The processes shown from step S401 to step S405 are the same, so their description is omitted here.

[0162] In step S506, the test processing unit 65b obtains the initial value of BER (the past value of BER) from the BER storage area 56. The test processing unit 65b obtains the initial value of BER stored in the BER storage area 56 via the memory I / F processing unit 62.

[0163] Next, the test processing unit 65b determines whether the change in BER is greater than or equal to a predetermined threshold ΔR1 (step S507). Here, the predetermined threshold ΔR1 is a value representing the condition that a predetermined data retention period has been reached. The test processing unit 65b calculates the change in BER by the difference between the calculated BER and the initial value of BER, and determines whether the change in BER is greater than or equal to the predetermined threshold ΔR1. If the change in BER is greater than or equal to the predetermined threshold ΔR1 (step S507: Yes), the test processing unit 65b proceeds to step S508. Alternatively, if the change in BER is less than the predetermined threshold ΔR1 (step S507: No), the test processing unit 65b proceeds to step S510.

[0164] In step S508, the test processing unit 65b rewrites the data in the data storage area 51. The test processing unit 65b performs the same steps as described above. Figure 3 The same process as step S109.

[0165] Next, the test processing unit 65b stores the BER in the BER storage area 56 (step S509). That is, the test processing unit 65b updates the initial value of the BER stored in the BER storage area 56 to the calculated current value of the BER. After the processing in step S509, the test processing unit 65b causes the processing to proceed to step S510.

[0166] Next, the processing in steps S510 and S511 is the same as described above. Figure 7 The processes in steps S408 and S409 shown are the same, so their descriptions are omitted here.

[0167] Furthermore, the test processing unit 65b can also rewrite the stored data in the data storage area 51 and the test storage area 53 after the specified data retention period has been reached.

[0168] As explained above, in this embodiment, if the BIOS timestamp is incorrect and the change in bit error rate (BER) reaches a predetermined threshold ΔR1 indicating that the predetermined data retention period has been reached, the control unit 60b performs a rewrite of the already stored data in the data storage area 51.

[0169] Therefore, the SSD40b (storage drive device) and the information processing device 100 of this embodiment achieve the same effect as the first and second embodiments described above, which can reduce data corruption based on the retention characteristics of flash memory 41 and improve reliability.

[0170] Furthermore, the present invention is not limited to the embodiments described above, and can be modified within the scope of the present invention without departing from its spirit.

[0171] For example, in the embodiments described above, the information processing device 100 is described as a notebook computer, but it is not limited to this. For example, it may also be a desktop computer, a tablet computer, or other information processing device.

[0172] Furthermore, in the embodiments described above, examples of using BER as an indicator value representing the proportion of storage defects in the test storage region 53 have been given, but this is not a limitation. For example, other indicator values ​​such as the applied voltage value corresponding to the change in cell VT voltage, i.e., the cell applied voltage, may also be used. Additionally, in the embodiments described above, BER and cell applied voltage may be used in combination as indicator values, for example.

[0173] Furthermore, in the above embodiments, examples of the processing based on the control unit 60 (60a, 60b) (test processing unit 65 (65a, 65b)) being performed as internal processing of the SSD 40 (40a, 40b) have been described, but this is not a limitation. The information processing device 100 may also perform part of the processing of the test processing unit 65 (65a, 65b).

[0174] Furthermore, in the embodiments described above, examples have been given of the test processing unit 65 (65a, 65b) continuously executing the determination process of reaching the specified data retention period and the rewrite process of rewriting to the data storage area 51. However, this is not a limitation, and the determination process and the rewrite process may be executed separately. For example, the test processing unit 65 (65a, 65b) may also execute the rewrite process triggered by the background media scan of the SSD 40 (40a, 40b).

[0175] Additionally, the test processing units 65 (65a, 65b) can also perform rewrite processing on blocks (or pages) of the flash memory 41 in the data storage area 51 where data has been written. Furthermore, the test processing units 65 (65a, 65b) can also, for example, detect blocks (or pages) in the data storage area 51 with high BER (BER) values ​​that are compensated by the ECC function, and perform rewrite processing on the detected blocks (or pages) with high BER values.

[0176] Furthermore, in the above embodiments, the SSD 40 (40a, 40b) is provided with an ECC processing unit 64 as an example of a functional unit implemented by the memory controller 42, but it is not limited to this. For example, the flash memory 41 may also be provided with an ECC processing unit 64.

[0177] Furthermore, each of the aforementioned SSD 40 (40a, 40b) and the structures included in the information processing device 100 has an internal computer system. Moreover, programs for implementing the functions of the aforementioned SSD 40 (40a, 40b) and the structures included in the information processing device 100 can be recorded on a computer-readable recording medium, and processing in the aforementioned SSD 40 (40a, 40b) and the structures included in the information processing device 100 can be performed by having the computer system read and execute the program recorded on the recording medium. Here, "having the computer system read and execute the program recorded on the recording medium" includes installing programs into the computer system. The term "computer system" here includes hardware such as an operating system and peripheral devices.

[0178] Furthermore, a "computer system" can also include multiple computer devices connected via networks including the Internet, WAN, LAN, and dedicated lines. Additionally, "computer-readable recording media" refers to portable media such as floppy disks, optical disks, ROMs, and CD-ROMs, as well as recording devices built into computer systems such as hard drives. Thus, recording media storing programs can be non-transitory recording media such as CD-ROMs.

[0179] Furthermore, the recording medium also includes internal or external recording media that can be accessed from a distribution server for distributing the program. Additionally, the program can be divided into multiple parts and downloaded at different times, forming a structure comprised of the various components of the SSD 40 (40a, 40b) and the information processing device 100, with each part distributed via a different distribution server. Moreover, the term "computer-readable recording medium" also includes structures that retain the program for a certain period, such as a server in the case of sending the program over a network or volatile memory (RAM) within a computer system acting as a client. Furthermore, the program described above can also be a structure used to implement the aforementioned functions. Further, it can also be a so-called differential file (differential program) that can be implemented by combining the aforementioned functions with a program already recorded in the computer system.

[0180] Alternatively, some or all of the above functions can be implemented as integrated circuits such as LSI (Large Scale Integration). The functions described above can be processed independently or partially or completely integrated. Furthermore, the method of integrated circuit implementation is not limited to LSI; it can also be implemented using dedicated circuits or general-purpose processors. Additionally, if advancements in semiconductor technology lead to integrated circuit technologies that replace LSI, integrated circuits based on these technologies can also be used.

Claims

1. A storage drive having a rewritable nonvolatile memory, comprising: a data storage area constituted by the nonvolatile memory, capable of storing data used for information processing; a test storage area constituted by the nonvolatile memory, storing prescribed test data; and a control section performing re-writing of already-stored data to the data storage area in a case where a prescribed data retention period is reached, the control section calculating a power stop period of a host device connected to the storage drive based on date-time information acquired from the host device, determining that the prescribed data retention period is reached in a case where the acquired date-time information is correct and the power stop period exceeds a threshold period, determining that the prescribed data retention period is reached based on an index value related to a storage failure of the test storage area in which the prescribed test data is stored in advance in a case where the date-time information is not correct.

2. The storage drive according to claim 1, wherein the control section calculates the power stop period based on first date-time information acquired from a BIOS (Basic Input Output System) of the host device as the date-time information acquired at the time of starting the host device and second date-time information as date-time information at the time of power stop of the storage drive, and determines whether the acquired date-time information is correct based on a time relationship of the first date-time information and the second date-time information.

3. The storage drive according to claim 2, wherein the index value includes a bit error rate at the time of reading the test data of the test storage area, and the control section determines that the prescribed data retention period is reached based on the bit error rate as the index value in a case where the date-time information is not correct.

4. The storage drive according to claim 3, wherein the control section adopts a longer one of a first power stop period calculated based on the first date-time information and the second date-time information and a second power stop period inferred based on the bit error rate as the power stop period in a case where the date-time information is correct, adopts the second power stop period as the power stop period in a case where the date-time information is not correct, and determines that the prescribed data retention period is reached in a case where the power stop period exceeds the threshold period, and performs re-writing of already-stored data to the data storage area.

5. The storage drive according to claim 4, wherein ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ The warning processing section infers the average ambient temperature of the host device based on the difference between the first power stop period and the second power stop period when the acquired date and time information is correct, and outputs information indicating a warning to the host device when the average ambient temperature is equal to or higher than a threshold temperature.

6. The storage drive device according to claim 4, wherein the control section infers the second power stop period using an inference model that infers the power stop period from the error bit rate, the storage drive device has a correction processing section that corrects the inference model to make the first power stop period and the second power stop period coincide when the difference between the first power stop period and the second power stop period is equal to or longer than a certain period.

7. The storage drive device according to claim 3, wherein the control section performs re-writing of already stored data to the data storage area when the date and time information is not correct and the error bit rate reaches a prescribed threshold value indicating that the prescribed data retention period has been reached.

8. The storage drive device according to claim 3, wherein the control section performs re-writing of already stored data to the data storage area when the date and time information is not correct and the amount of change in the error bit rate reaches a prescribed threshold value indicating that the prescribed data retention period has been reached.

9. An information processing device, has the storage drive device described in any one of claims 1 to 8, is the host device that performs information processing using data stored by the storage drive device.

10. A control method that is a control method of a storage drive device that has a rewritable nonvolatile memory and has: a data storage area composed of the nonvolatile memory and capable of storing data used for information processing; and a test storage area composed of the nonvolatile memory and storing prescribed test data, in the control method, a control section calculates a power stop period of a host device connected to the storage drive device based on date and time information acquired from the host device, and determines that a prescribed data retention period has been reached when the acquired date and time information is correct and the power stop period exceeds a threshold period, determines that the prescribed data retention period has been reached based on an index value related to storage failure with respect to the test storage area in which the prescribed test data is stored in advance when the date and time information is not correct, performs re-writing of already stored data to the data storage area when the prescribed data retention period has been reached.

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