Model language architecture optimization method, system, equipment and medium
By tracing back the topology analysis and coupling quantification of the input interface through the output interface, the architecture design of the automotive software model was optimized, solving the problems of overly complex models and low code quality, and achieving accurate architecture partitioning and code generation.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-05
- Publication Date
- 2026-03-10
AI Technical Summary
Existing technologies in automotive software model design suffer from problems such as excessively large and complex models, low quality of static analysis, complex unit testing, poor code readability, and unclear model architecture. In particular, it is difficult to control model complexity and reverse architecture partitioning in top-down design methods.
A topology analysis method that traces back from the output interface to the input interface is adopted. Combined with coupling quantification, the model architecture is optimized by virtualizing operation nodes, merging or separating subsystems, constructing an accurate topology architecture diagram, and setting coupling thresholds for architecture adjustment.
Improvements were made to model analysis and testing, enhancing the quality and readability of code generation. This ensured the uniqueness of the functional objectives of the unit topology architecture and the simplicity of the architecture, avoiding the problem of unreasonable subsystems caused by experience-based judgments in traditional methods.
Smart Images
Figure CN121635862A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The application belongs to the technical field of software development, and particularly relates to a model language architecture optimization method, system, device and medium. BACKGROUND
[0002] With the development of new energy electric vehicles and the improvement of the intelligent level of vehicles, vehicles need to develop large-scale software function components, and the complexity of software is higher and higher. With the use of various formal model languages, the development of vehicle electronic software is greatly facilitated, but at the same time, the design of the model is too large and complex, which requires the design and optimization of the model architecture, so as to facilitate the static model analysis of the model and the dynamic test of the unit subsystem. For a large and complex model, the following disadvantages generally exist: 1. The quality of general static analysis is not high; 2. For unit testing of a complex model, due to the complexity of the model, when designing a unit test case, the test case is too complex due to too many interfaces; 3. Due to unclear model architecture, the readability of the generated code is not high, and the code quality is not high; therefore, a high-quality model architecture is crucial. At present, the model architecture design is mostly a top-down design method, which cannot control the complexity of the model in the implementation process, and may also lead to a too large and complex implementation model. At the same time, this method is not suitable for reverse architecture division of the existing model. SUMMARY
[0003] To solve the above problems, the application provides a model language architecture optimization method, system, device and medium, which uses a topology analysis method of output interface reverse tracking input interface, combines coupling quantization judgment, can realize accurate architecture division of a complex model, and improves the model analysis, test and code generation effect.
[0004] The following is the technical content of the present disclosure: A model language architecture optimization method, comprising: Virtualizing all operation nodes in a model under a model language architecture, and extracting a node topology architecture diagram of the model according to the number of C instructions generated by each module in the model; In the node topology architecture diagram of the model, tracing from each output interface to all input interfaces to obtain a unit topology architecture of each output interface; Calculating the coupling degree of the unit topology architecture of each output interface; Setting a coupling degree threshold T, if the coupling degree of the unit topology architecture is < T, merging it with other unit topology architectures with a coupling degree lower than T to obtain a subsystem with a coupling degree > T, if the coupling degree of the unit topology architecture is > T, directly setting it as an independent subsystem, and obtaining an optimized model architecture.
[0005] Furthermore, The virtualization of all operation nodes in the model under the model language architecture includes: Set a threshold T1 for merging C code execution instructions, and count the number of C code execution instructions generated by each module in the model; Each control operation module in the model signal flow is taken as an initial operation node. If the number of C code execution instructions generated by a certain module is less than the threshold T1, the module is merged with the adjacent module in the link to form a virtual operation node. The initial operation node and the virtual operation node together form a set of virtual operation nodes.
[0006] Furthermore, The node topology diagram of the model is extracted based on the number of C instructions generated by each module in the model; including: Based on the set of virtual operation nodes, the signal flow relationships and control dependencies among the virtual operation nodes are analyzed. Each virtual operation node is treated as a node in the topology graph, and the signal flow and control relationship between nodes are treated as connecting edges in the topology graph. The importance weight of each node is marked according to the number of C instructions generated by the module, and finally a complete model node topology architecture diagram is constructed and output.
[0007] Furthermore, The coupling degree of the unit topology architecture for each output interface is calculated using the following formula:
[0008] in, , , ... The number of nodes associated with each node. This represents the number of nodes in the unit's topology.
[0009] Furthermore, In the node topology diagram of the model, tracing back from each output interface to all input interfaces yields the unit topology of each output interface; including: Starting from each output interface, traverse all virtual operation nodes involved in the generation of the output signal along the reverse path of the model signal flow, and record the signal input source and output destination of each node; during the tracing process, exclude virtual operation nodes that have no signal association or control dependency with the current output interface, and only retain nodes that directly or indirectly affect the signal of the output interface. The final selected nodes and their connections are integrated to form the unit topology architecture corresponding to the output interface, where each unit topology architecture only contains nodes related to the corresponding output.
[0010] Furthermore, After virtualizing all operation nodes in the model under the model language architecture, it further includes: Assign a unique identifier to each virtual operation node and establish a mapping relationship between the identifier and the original module information; The original module information includes: the total number of execution instructions for the original module to generate C code, the functional type of the original module, and the initial position of the original module in the model.
[0011] An optimization system for a model language architecture includes: An architecture diagram extraction module, which is used to virtualize all operation nodes in the model under the model language architecture and extract the node topology architecture diagram of the model according to the number of C instructions generated by each module in the model; A unit topology architecture division module, which is used to trace from each output interface to all input interfaces in the node topology architecture diagram of the model to obtain the unit topology architecture of each output interface; A coupling degree calculation module, which is used to calculate the coupling degree of the unit topology architecture of each output interface; An architecture adjustment module, which is used to set a coupling degree threshold T. If the coupling degree of the unit topology architecture < T, then merge it with other unit topology architectures with a coupling degree lower than T to obtain a subsystem with a coupling degree > T; if the coupling degree of the unit topology architecture > T, then directly set it as an independent subsystem; to obtain an optimized model architecture.
[0012] Furthermore, The architecture diagram extraction module is configured as: Set a C code execution instruction merging threshold T1, and count the number of execution instructions for each module in the model to generate C code; Regard each control operation module in the model signal flow as an initial operation node. If the number of execution instructions for a certain module to generate C code is less than the threshold T1, then merge this module with the adjacent module in the link to form a virtual operation node; the initial operation nodes and virtual operation nodes together form a set of virtual operation nodes; Based on the set of virtual operation nodes, sort out the signal transfer relationship and control dependency relationship between each virtual operation node; Regard each virtual operation node as a node in the topology diagram, and the signal flow and control relationship between nodes as the connection edges in the topology diagram; Mark the importance weight of each node according to the amount of C instructions generated by the module, and finally construct and output a complete model node topology architecture diagram.
[0013] An optimization device for a model language architecture includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the optimization method for the model language architecture.
[0014] A computer storage medium having executable instructions stored thereon, which, when executed by a processor, cause the processor to implement the method described thereon.
[0015] Compared with the prior art, this application has the following advantages: Traditional models often contain numerous small, simple modules, leading to a complex topology with fragmented signal flow and increased analysis costs. This technique addresses this by setting a C code execution instruction merging threshold T1. Small modules generating fewer than T1 instructions are merged with adjacent modules into virtual operation nodes, while only core modules meeting the instruction threshold are retained as independent nodes. Essentially, this technique uses the actual complexity of the generated code as a benchmark to streamline ineffective nodes and prevent the topology from becoming chaotic due to the dispersion of small modules. Simultaneously, it assigns importance weights to nodes based on the number of C instructions generated by each module, allowing the topology to not only reflect connectivity but also differentiate the levels of influence of nodes on functional implementation and code generation. This solves the problems of traditional topology diagrams lacking priority and wasting analytical effort, laying a concise and clearly defined foundation for subsequent architecture partitioning. Traditional architecture partitioning is prone to blurring of unit boundaries due to the cross-influence of multiple inputs. For example, when an input simultaneously affects multiple outputs, it is difficult to define its affiliation. This technology starts from each output interface and traverses all virtual nodes involved in the generation of that output in reverse along the signal flow, while excluding nodes without signal association or control dependency, ultimately forming a unit topology architecture that serves only a single output. This reverse tracing with "output function" as the core can accurately identify the core associated nodes corresponding to each output, ensuring that the functional goal of each unit topology is unique, avoiding the mixing of irrelevant nodes across outputs, and solving the problems of unclear unit boundaries and chaotic associations in traditional architectures.
[0016] Other features and advantages of this application will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the application. The objectives and other advantages of this application may be realized and obtained by means of the structures pointed out in the description, claims and drawings. Attached Figure Description
[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0018] Figure 1 A schematic diagram of the method of this disclosure is shown; Figure 2 A model node topology diagram according to this disclosure is shown; Figure 3 A topology partitioning diagram according to this disclosure is shown. Detailed Implementation
[0019] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0020] like Figure 1 The optimization method for the model language architecture disclosed herein includes: This disclosure proposes to trace the topology of the model's input interface back through the model's output interface, count all operation nodes in the topology of the output and input, calculate the aggregation degree of the topology, adjust the topology of the software architecture based on the aggregation degree value, calculate the aggregation degree of the adjusted architecture, until the aggregation degree of the architecture reaches the optimal value. The specific steps include: Step 1: Virtualize all operation nodes in the model. Based on the number of C instructions generated by the module (nodes include each control operation node in the signal flow), extract the node topology diagram of the model. Figure 2 This is a virtual architecture diagram of the topological nodes of a certain model; Specifically, all operational nodes in the model are virtualized; including: Set a threshold T1 for merging C code execution instructions, and count the number of C code execution instructions generated by each module in the model; Each control operation module in the model signal flow is taken as an initial operation node. If the number of C code execution instructions generated by a certain module is less than the threshold T1, the module is merged with the adjacent module in the link to form a virtual operation node. The initial operation node and the virtual operation node together form a set of virtual operation nodes.
[0021] Specifically, the step of extracting the node topology diagram of the model based on the number of C instructions generated by each module in the model includes: Based on the set of virtual operation nodes, the signal flow relationships and control dependencies among the virtual operation nodes are analyzed. Each virtual operation node is treated as a node in the topology graph, and the signal flow and control relationship between nodes are treated as connecting edges in the topology graph. The importance weight of each node is marked according to the number of C instructions generated by the module, and finally a complete model node topology architecture diagram is constructed and output.
[0022] The virtualization of all operation nodes in the model under the model language architecture also includes: Assign a unique identifier to each virtual operation node and establish a mapping relationship between the identifier and the original module information; The original module information includes: the total number of C code execution instructions generated by the original module, the function type of the original module, and the initial position of the original module in the model.
[0023] Step 2: Trace the model's topology back to all input interfaces for each output interface, and divide the unit topology corresponding to each output interface; Specifically, including: Starting from each output interface, traverse all virtual operation nodes involved in the generation of the output signal along the reverse path of the model signal flow, and record the signal input source and output destination of each node; during the tracing process, exclude virtual operation nodes that have no signal association or control dependency with the current output interface, and only retain nodes that directly or indirectly affect the signal of the output interface. The final selected nodes and their connections are integrated to form the unit topology architecture corresponding to the output interface, where each unit topology architecture only contains nodes related to the corresponding output.
[0024] Step 3: Count the nodes in the topology. For each output node b, calculate the number of nodes that are affected by node b or affect node b (including node b itself). Step 4: Based on the unit topology of each output node b, calculate the coupling degree of each unit topology: ; in, , , ... The number of nodes associated with each node. This represents the number of all nodes in the unit's topology. Calculate based on the above formula: A1 = (6 + 6 + 3 + 5 + 5 + 5) / 62 = 0.83 A2 = (5 + 5 + 5 + 5 + 4 + 7 + 4) / 72 = 0.75 A3 = (4 + 4 + 4 + 3 + 3 + 6) / 62 = 0.67 A4 = (3 + 3 + 4 + 4 + 5 + 5 + 7) / 72 = 0.63 Set a reasonable threshold for coupling degree T = 0.7. Divide each unit topology according to the values of the coupling degrees A1, A2, A3,... of the unit topology. For the unit topology with AX < T, combine multiple units into a unit subsystem until the coupling degree At of the combined subsystem > 0.7; for the unit topology with unit AX > T, it indicates that the coupling of this unit is very high, and set it as a subsystem; According to the thresholds set above, divide the model topologies A1 and A2 into one subsystem respectively, and combine A3 and A4 into one subsystem (as Figure 3 shown).
[0025] Technical effect: The division of the traditional architecture depends on the experience of engineers. There is no objective standard for judging whether to combine or separate units, and problems such as loose or excessive coupling within the subsystem are likely to occur. This technology calculates the coupling degree through a quantitative formula, divides the sum of the associated nodes of each node in the unit by the square of the total number of nodes, and converts the degree of association within the unit into a numerically comparable value. In essence, it uses "node association density" as an objective criterion to replace subjective experience judgment, providing a clear quantitative basis for subsequent subsystem division and avoiding unreasonable architectures caused by empirical errors; After setting the coupling degree threshold T in this technology, directly set the unit topology with a coupling degree higher than T as an independent subsystem, because high coupling means strong association between nodes within the unit, and it can be tested and modified separately without affecting other parts after independence; for units with a coupling degree lower than T, merge them with other low-coupling units until the coupling degree meets the standard after merging, avoiding the "over-dispersed subsystems" caused by low-coupling units forming subsystems alone, and at the same time preventing the "bloated subsystems" caused by forcibly merging unrelated functions. This differential treatment solves the extreme problems of either over-dispersed or bloated subsystems in the traditional architecture, ensuring that the final architecture is both concise and functionally complete.
[0026] Based on the method of the present invention, the embodiments of the present disclosure also provide a system corresponding to the above method, which includes: An architecture diagram extraction module, used to virtualize all operation nodes in the model under the model language architecture, and extract the node topology architecture diagram of the model according to the number of C instructions generated by each module in the model; A unit topology architecture division module, used to trace from each output interface to all input interfaces in the node topology architecture diagram of the model to obtain the unit topology architecture of each output interface; A coupling degree calculation module for calculating the coupling degree of the unit topological architectures of each output interface; An architecture adjustment module for setting a coupling degree threshold T. If the coupling degree of a unit topological architecture < T, it is merged with other unit topological architectures with a coupling degree lower than T to obtain a subsystem with a coupling degree > T; if the coupling degree of a unit topological architecture > T, it is directly set as an independent subsystem; thus obtaining an optimized model architecture.
[0027] Based on the same inventive concept of the above-disclosed content, an embodiment of the present disclosure further provides a device corresponding to the above method, which includes at least one processor; and a memory communicatively connected to the at least one processor; wherein, the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the above method.
[0028] It should be noted that the electrical connections between the above-mentioned various units do not necessarily represent direct connections between the circuits. Indirect connection methods, as long as they can achieve the purpose of the present disclosure, are applicable to the embodiments of the present disclosure.
[0029] Based on the same inventive concept, the present disclosure also provides a computer storage medium, on which executable instructions are stored, and the instructions are executed by a processor to implement the above method.
[0030] Although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.
Claims
1. A method of optimizing a model language architecture, the method comprising: The method comprises the following steps: all operation nodes in the model under the model language architecture are virtualized, and a node topology architecture diagram of the model is extracted according to the number of C instructions generated by each module in the model; in the node topology architecture diagram of the model, each output interface is traced back to all input interfaces to obtain a unit topology architecture of each output interface; the coupling degree of the unit topology architecture of each output interface is calculated; a coupling degree threshold T is set, if the coupling degree of the unit topology architecture is less than T, the unit topology architecture is merged with other unit topology architectures whose coupling degrees are less than T to obtain a subsystem whose coupling degree is greater than T, if the coupling degree of the unit topology architecture is greater than T, the unit topology architecture is directly set as an independent subsystem, and an optimized model architecture is obtained.
2. The method of optimizing a model language architecture of claim 1, wherein, After the virtualization of all operation nodes in the model under the model language architecture, the method further comprises the following steps: a C code execution instruction merging threshold T1 is set, and the number of C code execution instructions generated by each module in the model is counted; each control operation module in the model signal flow is taken as an initial operation node, if the number of C code execution instructions generated by a module is less than the threshold T1, the module is merged with adjacent modules in the chain to form a virtual operation node, and the initial operation nodes and the virtual operation nodes jointly form a virtual operation node set.
3. The method of claim 1, wherein, The extraction of the node topology architecture diagram of the model according to the number of C instructions generated by each module in the model comprises the following steps: the signal flow conversion relationship and the control dependency relationship between each virtual operation node are sorted based on the virtual operation node set; each virtual operation node is taken as a node in a topology diagram, and the signal flow and the control relationship between the nodes are taken as connection edges in the topology diagram; the importance weight of each node is marked according to the number of C instructions generated by the module, and finally a complete model node topology architecture diagram is constructed and output.
4. The method of claim 1, wherein, The coupling degree of the unit topology architecture of each output interface is calculated according to the following formula: wherein , , , is the number of nodes associated with each node, is the number of all nodes in the unit topology architecture.
5. The method of claim 1, wherein, In the node topology architecture diagram of the model, each output interface is traced back to all input interfaces to obtain a unit topology architecture of each output interface, which comprises the following steps: starting from each output interface, all virtual operation nodes participating in the generation process of the output signal are traversed along the reverse path of the model signal flow, and the signal input source and the output destination of each node are recorded; in the tracing process, the virtual operation nodes that have no signal association and no control dependency with the current output interface are excluded, and only the nodes that directly or indirectly affect the signal of the output interface are retained; the finally screened nodes and the connection relationship between the nodes are integrated to form a unit topology architecture corresponding to the output interface, wherein each unit topology architecture only contains nodes related to the corresponding output.
6. The method of claim 1, wherein, After the virtualization of all operation nodes in the model under the model language architecture, the method further comprises the following steps: a unique identifier is allocated to each virtual operation node, and a mapping relationship between the identifier and original module information is established; the original module information comprises the total number of C code execution instructions generated by the original module, the functional type of the original module and the initial position of the original module in the model.
7. An optimization system for a model language architecture, characterized by The method comprises the following steps: an architecture diagram extraction module is configured to virtualize all operation nodes in the model under the model language architecture, and extract a node topology architecture diagram of the model according to the number of C instructions generated by each module in the model; The unit topology architecture division module is configured to trace back from each output interface to all input interfaces in the node topology architecture diagram of the model to obtain unit topology architectures of the output interfaces; The coupling degree calculation module is configured to calculate coupling degrees of the unit topology architectures of the output interfaces; The architecture adjustment module is configured to set a coupling degree threshold T, and if the coupling degree of a unit topology architecture is less than T, the unit topology architecture is merged with other unit topology architectures having coupling degrees less than T to obtain a subsystem having a coupling degree greater than T, and if the coupling degree of a unit topology architecture is greater than T, the unit topology architecture is directly set as an independent subsystem to obtain an optimized model architecture.
8. The model language architecture optimization system of claim 7, wherein, The architecture diagram extraction module is configured to: set a C code execution instruction merging threshold T1, and count the number of execution instructions of C code generated by each module in the model; take each control operation module in the model signal flow as an initial operation node, merge a module with adjacent modules in a link to form a virtual operation node if the number of execution instructions of C code generated by the module is less than the threshold T1, and combine the initial operation nodes and the virtual operation nodes to form a virtual operation node set; based on the virtual operation node set, sort the signal flow conversion relationship and control dependency relationship between the virtual operation nodes; take each virtual operation node as a node in a topology diagram, and take the signal flow and control relationship between the nodes as a connection edge in the topology diagram; according to the number of C instructions generated by the modules, mark the importance weight of each node, and finally construct and output a complete model node topology architecture diagram.
9. An optimization device of a model language architecture, characterized by, comprise: at least one processor; and a memory connected in communication with the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the optimization method of the model language architecture in any one of claims 1 to 6.
10. A computer storage medium, characterized in that executable instructions are stored thereon, and the instructions are executed by a processor to enable the processor to implement the method in any one of claims 1 to 6.