Processor and branch predictor
By introducing a hierarchical branch predictor into the processor and utilizing a layered storage design with low-order and high-order tags, the problems of high BTB hardware overhead and alias conflicts are solved, achieving higher prediction accuracy and lower hardware cost.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-09
- Publication Date
- 2026-03-10
AI Technical Summary
The branch target buffer (BTB) of the branch predictor in existing processors has a large hardware overhead, and address space overlap leads to frequent alias conflicts, affecting prediction accuracy and processor performance.
The branch predictor employs a hierarchical structure, including a cache module and a register module. The cache module stores the low-order TAG of the historical branch instruction address, while the register module stores the high-order TAG. The hierarchical matching process improves prediction accuracy and reduces hardware resource requirements.
It effectively balances resource utilization and prediction accuracy, significantly saves area and power consumption, and improves processor performance.
Smart Images
Figure CN121635973A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present disclosure relates to a processor and a branch predictor. BACKGROUND
[0002] In modern processors, branch prediction is one of the key techniques to improve the efficiency of instruction pipeline, and a Branch Target Buffer (BTB) is used to store the target addresses of historical branch instructions to speed up the prediction and acquisition of branch targets. SUMMARY
[0003] At least one embodiment of the present disclosure provides a processor comprising a branch predictor, wherein the branch predictor comprises a cache module and a register module, the cache module comprises at least one entry, and a TAG field in the at least one entry is configured to store a low-bit TAG of a historical branch instruction address; the register module comprises a high-bit TAG table configured to store a high-bit TAG of the historical branch instruction address; and the branch predictor is configured to perform the following process of branch prediction: matching a low-bit TAG of a current branch instruction address with a TAG field in a target entry of the cache module, wherein the target entry corresponds to an index field of the current branch instruction address; in response to the low-bit TAG of the current branch instruction address matching the TAG field in the target entry of the cache module, obtaining a high-bit index, wherein the high-bit index points to a high-bit TAG entry of the high-bit TAG table corresponding to the low-bit TAG recorded in the TAG field in the target entry; matching a high-bit TAG of the current branch instruction address with a high-bit TAG in the high-bit TAG entry; and in response to the high-bit TAG of the current branch instruction address matching the high-bit TAG in the high-bit TAG entry, determining a branch prediction hit.
[0004] For example, in the processor provided by at least one embodiment of the present disclosure, the target entry comprises a high-bit index.
[0005] For example, in the processor provided by at least one embodiment of the present disclosure, the number of entries of the cache module is associated with the number of valid bits of the index field.
[0006] For example, in the processor provided by at least one embodiment of the present disclosure, the current branch instruction address is 32 bits, the number of valid bits of the index field is equal to 6, and the number of entries in the cache module is equal to 64.
[0007] For example, in the processor provided by at least one embodiment of the present disclosure, the number of valid bits of the high-bit index is equal to 2, and the number of entries in the high-bit TAG table is equal to 4.
[0008] For example, in the processor provided in at least one embodiment of this disclosure, the cache module adopts a group-associative mode to match the low-order TAG of the current branch instruction address with the TAG field in the target entry of the cache module, including: matching the low-order TAG of the current branch instruction address with the TAG field in the target entry of the cache module corresponding to m paths, where m is an integer greater than 1.
[0009] For example, in the processor provided in at least one embodiment of this disclosure, the high-order TAG table adopts a fully associative mode.
[0010] For example, in the processor provided in at least one embodiment of this disclosure, the branch predictor is further configured to perform the following branch prediction process: in response to a mismatch between the low-order TAG of the current branch instruction address and the TAG field in the target entry corresponding to the m-way of the cache module, a first entry is inserted into the cache module, the first entry being used to record the low-order TAG of the current branch instruction address; or, in response to a mismatch between the high-order TAG of the current branch instruction address and the high-order TAG in the high-order TAG table, a second entry is inserted into the high-order TAG table, the second entry being used to record the high-order TAG of the current branch instruction address.
[0011] For example, in the processor provided in at least one embodiment of this disclosure, m equals 2. Inserting a first entry into the cache module includes: when the two corresponding target entries of the cache module are full when inserting the first entry, replacing the two corresponding target entries of the cache module using a pseudo-random replacement method; or, inserting a second entry into the high-order TAG table includes: when the high-order TAG table is full when inserting the second entry, replacing the least used entry in the high-order TAG table using an LRU algorithm.
[0012] For example, in a processor provided in at least one embodiment of this disclosure, the cache module includes a branch target buffer.
[0013] At least one embodiment of this disclosure also provides a branch predictor, including a cache module and a register module. The cache module includes at least one entry, where the TAG field of the at least one entry is configured to store the low-order TAG of a historical branch instruction address. The register module includes a high-order TAG table, which is configured to store the high-order TAG of a historical branch instruction address. The branch predictor further includes a first matching unit configured to match the low-order TAG of the current branch instruction address with the TAG field of a target entry in the cache module, wherein the index field of the target entry matches the current branch instruction address. Correspondingly, the following configurations are configured: a retrieval unit, configured to retrieve a high-order index in response to matching the low-order TAG of the current branch instruction address with the TAG field in the target entry of the cache module, wherein the high-order index points to the high-order TAG entry in the high-order TAG table corresponding to the low-order TAG recorded in the TAG field of the target entry; a second matching unit, configured to match the high-order TAG of the current branch instruction address with the high-order TAG in the high-order TAG entry; and a determination unit, configured to determine a branch prediction hit in response to matching the high-order TAG of the current branch instruction address with the high-order TAG in the high-order TAG entry.
[0014] For example, in the branch predictor provided in at least one embodiment of this disclosure, the cache module adopts a group-associative mode, and the first matching unit is further configured to match the low-order TAG of the current branch instruction address with the TAG field in the target table entry corresponding to the m paths of the cache module, where m is an integer greater than 1.
[0015] For example, at least one embodiment of the branch predictor provided in this disclosure further includes: an insertion unit configured to insert a first entry in the cache module in response to a mismatch between the low-order TAG of the current branch instruction address and the TAG field in the target entry corresponding to the m-way of the cache module, the first entry being used to record the low-order TAG of the current branch instruction address; or, in response to a mismatch between the high-order TAG of the current branch instruction address and the high-order TAG in the high-order TAG table, insert a second entry in the high-order TAG table, the second entry being used to record the high-order TAG of the current branch instruction address.
[0016] For example, in the branch predictor provided in at least one embodiment of this disclosure, m equals 2, and the branch predictor further includes: a replacement unit configured to replace the target entries corresponding to the m paths of the cache module in a pseudo-random replacement manner when the target entries corresponding to the m paths of the cache module are full when the first entry is inserted; or, when the entries of the high-order TAG table are full when the second entry is inserted, to replace the least used entry in the high-order TAG table in an LRU algorithm.
[0017] For example, in a branch predictor provided in at least one embodiment of this disclosure, the caching module includes a branch target buffer. Attached Figure Description
[0018] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.
[0019] Figure 1 This is a schematic diagram of an exemplary data structure for the address of a branch instruction;
[0020] Figure 2 This is a schematic diagram of the structure of a processor provided in at least one embodiment of the present disclosure;
[0021] Figure 3 This is a schematic diagram illustrating the process of a branch predictor performing branch prediction according to at least one embodiment of this disclosure;
[0022] Figure 4 This is a schematic diagram of the structure of a branch target buffer with two interconnected paths provided in at least one embodiment of this disclosure;
[0023] Figure 5 This is an example of branch prediction hit provided in at least one embodiment of this disclosure; and
[0024] Figure 6 This is a schematic diagram of a branch predictor provided in at least one embodiment of the present disclosure. Detailed Implementation
[0025] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.
[0026] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.
[0027] In the branch prediction hardware of the central processing unit (CPU), such as the branch target buffer (BTB), the branch instruction address itself is "deconstructed" and assigned to different fields to enable fast lookup and comparison.
[0028] Figure 1 This is a schematic diagram of an exemplary data structure for the address of a branch instruction. For example... Figure 1 As shown, the address of this branch instruction is usually divided into three parts: the high-order TAG, the index, and the offset (intra-block offset).
[0029] The offset is typically the lowest few bits of the branch instruction address (e.g., [1:0] or [2:0]). For a BTB, each entry corresponds to the prediction information of an entire branch instruction, not a data block. Therefore, the offset bits are usually ignored when querying the BTB. Because the CPU fetches instructions aligned to the instruction word length (e.g., 4 bytes), the lower 2 bits of the address are always 0.
[0030] The index is typically a few bits from the middle of the branch instruction address, used for quick location of entries in the BTB (Branch Targeting Block). The number of index bits, n, determines the number of slots in the BTB, with a total of 2^n slots. n For example, if the index is [10:2] (9 bits), then this BTB has 2. 9 =512 entries. When a branch instruction address arrives, the CPU directly extracts the index bit and uses it as the address to read the corresponding entry (or group of entries) from the BTB's SRAM.
[0031] The TAG (Tag) represents all the high-order bits of the branch instruction address, excluding the index and offset bits, used for uniqueness verification. Specifically, when the CPU finds an entry in the BTB (Branch-Based Targeting) using the index, it compares the TAG stored in that entry with the TAG of the current branch instruction address. If they match, it's a BTB hit, and the CPU can use the prediction state and target address from that entry. If they don't match, it's a BTB miss, the predictor cannot make a prediction, or a default operation is required.
[0032] However, the inventors of this application have discovered through research that the BTB structure typically adopts a flat (single-level) TAG table design: that is, all TAG fields cover the full address high bits of the branch instruction address, storing TAGs for all branch instruction addresses, which has a large hardware overhead; and using only low-bit TAGs (part of the low bits in the TAG) can reduce hardware resources, but due to address space overlap, BTB alias conflicts occur frequently, affecting prediction accuracy and reducing processor performance.
[0033] To address the BTB alias conflict issue, exemplary solutions rely on complex structures such as increased associativity or multiplexed entries, or utilize larger-capacity fully associative caches. However, such designs are difficult to implement in embedded systems due to the significant increase in silicon area and power consumption caused by the additional storage and comparison logic.
[0034] In view of the above, at least one embodiment of this disclosure provides a processor including a branch predictor, wherein the branch predictor includes a cache module and a register module, the cache module includes at least one entry, the TAG field of which is configured to store the low-order TAG of the historical branch instruction address; the register module includes a high-order TAG table, which is configured to store the high-order TAG of the historical branch instruction address; the branch predictor is configured to perform the following branch prediction process: matching the low-order TAG of the current branch instruction address with the TAG field in the target entry of the cache module. The process involves several steps: First, the target entry corresponds to the index field of the current branch instruction address. Second, in response to the low-order TAG of the current branch instruction address matching the TAG field in the target entry of the cache module, a high-order index is obtained. This high-order index points to the high-order TAG entry in the high-order TAG table corresponding to the low-order TAG recorded in the TAG field of the target entry. Third, the high-order TAG of the current branch instruction address is matched with the high-order TAG in the high-order TAG entry. Finally, in response to the high-order TAG of the current branch instruction address matching the high-order TAG in the high-order TAG entry, a branch prediction hit is determined.
[0035] At least one embodiment of this disclosure also provides a branch predictor.
[0036] The branch predictor in the processor provided in at least one embodiment of this disclosure adopts a hierarchical storage design scheme, which effectively balances resource utilization and prediction accuracy by using a layered storage method with a small number of high-order TAG entries and a large number of low-order TAG entries; at the same time, the dual-level entry structure significantly saves area and power consumption compared to the flatter TAG full-store BTB or expanding the number of BTB entries.
[0037] The processor of this disclosure will be described below through specific embodiments.
[0038] Figure 2 , Figure 3 This is a schematic diagram of the structure of a processor provided in at least one embodiment of the present disclosure, and a flowchart of the branch predictor in the processor performing branch prediction. For example... Figure 2 , Figure 3 As shown, the processor 100 includes a branch predictor 110, wherein the branch predictor 110 includes a cache module 120 and a register module 130, and the branch predictor 110 performs branch prediction in steps S200 to S230.
[0039] Step S200: Match the low-order TAG of the current branch instruction address with the TAG field in the target entry of the cache module. The target entry corresponds to the index field of the current branch instruction address, and the TAG field in the target entry stores the low-order TAG of historical branch instruction addresses. For example, the "cache module" here includes the branch target buffer BTB. Unless otherwise specified, the following description will refer to the branch target buffer BTB.
[0040] For example, refer to Figure 1 The low-order TAG of the branch instruction address is a portion of the low-order region of the TAG. For example, when the branch instruction address is 32 bits (i.e., [31:0]), the TAG is [31:8], a total of 24 bits, and the low-order TAG can be [14:8], a total of 7 bits. The TAG field in each entry of the branch destination buffer (BTB) is used to store the low-order TAG of the historical branch instruction address.
[0041] The "target entry" here can correspond to the index field of the current branch instruction address. As mentioned above, the index is usually a few bits in the middle of the branch instruction address, used for quickly locating the entry in the BTB.
[0042] For example, the number of entries in the branch target buffer is related to the number of significant bits in the index field. Specifically, the number of significant bits n in the index field determines how many entries (or "slots") the BTB has, with a total of 2^n entries. n For example, if the index field is 6 bits ([7:2]) of a 32-bit branch instruction address, then the number of valid bits in the index field is 6. Therefore, BTB has a total of 2...6 =64 entries (i.e., entries 0 through 63). For example, with the index field "001100", the corresponding target entry is the 12th entry; with the index field "011100", the corresponding target entry is the 28th entry.
[0043] Step S210: In response to the low-order TAG of the current branch instruction address matching the TAG field in the target entry of the cache module, obtain the high-order index, wherein the high-order index points to the high-order TAG entry in the high-order TAG table corresponding to the low-order TAG recorded in the TAG field of the target entry.
[0044] For example, if the index field is "001100", the corresponding target entry is the 12th entry. The low-order TAG of the current branch instruction address (e.g., [14:8] in 32-bit) is matched with the low-order TAG of the historical branch instruction address recorded in the TAG field of the 12th entry (e.g., [14:8] in 32-bit). If the match is successful, it means that the first match is hit, that is, the low-order TAG match is hit. At this time, the high-order index is obtained. The high-order index points to the high-order TAG table corresponding to the high-order TAG of the historical branch instruction address recorded in the 12th entry.
[0045] For example, in one possible implementation, the high-order index can be recorded in a register, wherein the low-order TAG recorded in the TAG field of the target entry has a mapping relationship with the corresponding high-order index, and the corresponding high-order index value is obtained in the register according to the mapping relationship.
[0046] For example, in another possible implementation, the target entry may also allocate a portion of its data space to record the high-order index corresponding to the low-order TAG in its TAG field.
[0047] For example, the processing method for this high-order index is similar to that of the index fields mentioned above. The number of entries in the high-order TAG table is related to the number of valid bits in the high-order index. Specifically, the number of valid bits *m* in the high-order index determines how many entries (i.e., "slots") are in the high-order TAG table, and the total number of high-order TAG entries is 2. m For example, if the number of valid bits in a high-order index is 2, then the high-order TAG table has a total of 2. 2 =4 high-order TAG entries (i.e., the 0th high-order TAG entry to the 3rd high-order TAG entry). For example, when the high-order index is "11", the corresponding high-order TAG entry is the 3rd entry; when the index field is "10", the corresponding target entry is the 2nd entry.
[0048] Step S220: Match the high-order TAG of the current branch instruction address with the high-order TAG in the high-order TAG table entry.
[0049] It should be noted here that the reference Figure 1 The high-order TAG of the current branch instruction address is the remaining part of the TAG excluding the low-order TAG. For example, if the current branch instruction address is 32 bits, the corresponding TAG is the high 24 bits (i.e., [31:8]), the low-order TAG is the low 7 bits of the TAG (i.e., [14:8]), and the high-order TAG is the remaining part of the TAG, i.e., the high 17 bits ([31:15]). The entries in the high-order TAG table record the high-order TAGs corresponding to the historical branch instruction addresses.
[0050] Step S230: In response to the high-order TAG of the current branch instruction address matching with the high-order TAG in the high-order TAG table entry, it is determined that the branch prediction has been hit.
[0051] For example, with the index field "001100", the corresponding target entry is the 12th entry. The low-order TAG of the current branch instruction address (e.g., [14:8] in 32-bit) is matched with the low-order TAG of the historical branch instruction address recorded in the TAG field of the 12th entry (e.g., [14:8] in 32-bit). If a match is successful, it means the first match is successful, i.e., the low-order TAG match is successful. At this time, the high-order index is "11", corresponding to the 3rd entry in the high-order TAG table. The high-order TAG of the current branch instruction address (e.g., [31:15] in 32-bit) is matched with the high-order TAG recorded in the 3rd entry of the high-order TAG table (e.g., [31:15] in 32-bit). If a match is successful, it means the high-order TAG match is successful, i.e., the branch prediction is successful.
[0052] For example, in one possible implementation, when the branch instruction address is 32 bits, the TAG is the high 24 bits of the branch instruction address ([31:8]), the high-order TAG is the high 17 bits of the TAG ([31:15]), the low-order TAG is the low 7 bits of the TAG ([14:8]), the offset is the low 2 bits of the branch instruction address ([1:0]), and the remaining bits ([7:2]) are the index field. Specifically, the number of valid bits used for the index field is equal to 6, corresponding to 64 entries in the branch target buffer; the number of valid bits used for the high-order index is equal to 2, corresponding to 4 entries in the high-order TAG table.
[0053] It should be noted that, based on the principle of locality of reference, high-order address changes are infrequent. Therefore, using only the aforementioned four high-order TAG entries is sufficient to maintain the high 17 bits of the full 32-bit address. Compared to the traditional BTB directly storing all TAG data, this reduces storage by approximately 90%. Furthermore, by refining the index through low-order entries (i.e., the entries in the branch target buffer), 64 entries can cover the low 15 bits of the address, significantly reducing the probability of alias conflicts. Of course, the number of entries in the branch target buffer and the number of entries in the high-order TAG table are merely illustrative examples. Those skilled in the art can set the specific number of entries according to actual power consumption and performance requirements; the embodiments disclosed herein do not impose limitations on this. Unless otherwise specified, the following description assumes the branch target buffer includes 64 entries and the high-order TAG table includes 4 entries.
[0054] For example, in one possible implementation, the branch target buffer adopts a set-associative mode, matching the low-order TAG of the current branch instruction address with the TAG field in the target entry of the branch target buffer, including: matching the low-order TAG of the current branch instruction address with the TAG field in the target entry corresponding to m paths of the cache module, where m is an integer greater than 1.
[0055] In branch target buffers, set-associative mode offers an ideal compromise between direct mapping and fully associative mode: by mapping an address to a specific set but allowing it to be stored in multiple locations within the set, it effectively avoids the high collisions and missing values caused by multiple critical branches competing for the same entry in direct mapping, thus significantly improving the hit rate; at the same time, its lookup operation only requires a limited number of parallel comparisons within a single set, which is lower in hardware cost and faster in access compared to fully associative mode, which requires comparing all entries. This ensures that the branch target buffer can achieve efficient single-cycle access on the processor's critical path, ultimately achieving the best performance balance with controllable hardware overhead.
[0056] Figure 4 This is a schematic diagram of the structure of a branch target buffer using two interconnected groups provided in at least one embodiment of this disclosure.
[0057] like Figure 4As shown, the branch target buffer adopts a two-way group associative mode (m=2). The 64 entries in the branch target buffer are divided into 32 groups (Way0 and Way1), with each group containing 2 entries. For example, if the index field of the current branch instruction address is "001100", the corresponding target entry is the 12th entry (i.e., the 12th group, which includes two target entries). The low-order TAG of the current branch instruction address (e.g., [14:8] in 32 bits) is matched with the low-order TAG of the historical branch instruction address recorded in the TAG fields of the two target entries in the 12th group (e.g., [14:8] in 32 bits). If the low-order TAG of any target entry in the group matches the low-order TAG of the current branch instruction address, the high-order index corresponding to the matching target entry is obtained for secondary matching of the subsequent high-order TAG table.
[0058] For example, in one possible implementation, in response to a mismatch between the low-order TAG of the current branch instruction address and the TAG field in the target entry corresponding to the m-way of the cache module, a first entry is inserted into the cache module. The first entry is used to record the low-order TAG of the current branch instruction address.
[0059] For example, still Figure 4 Taking the example of two-way group association, when the index field of the current branch instruction address is "000110", the corresponding target entry is the 6th entry (i.e., the 6th group, which includes two target entries, where the target entry of Way0 has data and the target entry of Way1 is empty). The low-order TAG of the current branch instruction address (e.g., [14:8] in 32-bit) is matched with the low-order TAG of the historical branch instruction address recorded in the TAG field of the two target entries in the 6th group (e.g., [14:8] in 32-bit). Since the target entry of Way1 is empty, it only needs to be matched with the target entry of Way0. If the low-order TAG in the target entry of Way0 in this group does not match the low-order TAG of the current branch instruction address, the low-order TAG of the current branch instruction address can be directly stored in the target entry of Way1 for subsequent branch prediction.
[0060] For example, in another possible implementation, inserting a first entry into the cache module includes: when the target entries corresponding to the m paths of the cache module are full at the time of inserting the first entry, replacing the target entries corresponding to the m paths of the cache module using a pseudo-random replacement method, where m equals 2.
[0061] For example, refer to Figure 4When the index field of the current branch instruction address is "011111", the corresponding target entry is the 31st entry (i.e., the 31st group, which includes two target entries). The lower-order TAGs of the current branch instruction address (e.g., [14:8] in 32-bit) are matched against the lower-order TAGs (e.g., [14:8] in 32-bit) of the historical branch instruction addresses recorded in the TAG fields of the two target entries in the 31st group. If neither of these two target entries (both containing valid data, i.e., both target entries are full) matches, a pseudo-random replacement method is used to replace the two target entries corresponding to the 31st group. For example, a linear feedback shift register can be used to generate a pseudo-random sequence to replace the target entry corresponding to Way1 in the 31st group. Other replacement methods can also be used depending on the actual situation, and the embodiments of this disclosure do not limit this.
[0062] It should be noted that the above-mentioned branch target buffer using a two-way group interconnection is only one example. Four-way and eight-way group interconnection modes can also be used. The embodiments disclosed herein do not limit this.
[0063] For example, in one possible implementation, the high-order TAG table adopts a fully associative mode. This allows any branch instruction entry to be stored in any empty space within the table, thus completely eliminating capacity failures caused by address mapping conflicts of multiple branch instructions. When the BTB capacity is sufficient, it can achieve the theoretically highest hit rate, providing the most complete historical information support for branch prediction.
[0064] For example, in one possible implementation, if the high-order TAG of the current branch instruction address does not match the high-order TAG in the high-order TAG table entry, a second entry is inserted into the high-order TAG table to record the high-order TAG of the current branch instruction address.
[0065] For example, in one possible implementation, if the high-order TAG table is full when inserting the second entry, the LRU algorithm is used to replace the least used entry in the high-order TAG table. Here, since the high-order TAGs are highly unique, the LRU algorithm can retain those long-used entries while replacing the least used entries.
[0066] The branch prediction method provided in at least one embodiment of this disclosure combines the LRU algorithm and pseudo-random replacement to achieve adaptive replacement of high-order TAG table and BTB table entries, balancing hit rate and implementation complexity.
[0067] Figure 5 This is an example of branch prediction hit provided in at least one embodiment of this disclosure.
[0068] like Figure 5As shown, the branch prediction involves two levels of matching: low-order TAG matching in the BTB and high-order TAG matching in the register module's high-order TAG table. Low-order TAG matching is the first level, and high-order TAG matching is the second level. For low-order TAG matching, the target entry in the BTB with the two-way group is located based on the index field "000100" of the current branch instruction address. This target entry is group 4, which includes two target entries in Way0 and Way1. The low-order TAG "0010010" of the current branch instruction address is matched with the low-order TAGs of the historical branch instruction addresses recorded in the two target entries in Way0 and Way1. Here, the target entry corresponding to Way1 is matched. Then, the high-order index "01" in the target entry corresponding to Way1 is obtained. Based on this high-order index "01", the second entry in the high-order TAG table is obtained and matched with the high-order TAGs of the historical branch instruction addresses recorded in the second entry. If the match is successful, the branch prediction is confirmed to have hit.
[0069] The branch predictor in the processor provided in at least one embodiment of this disclosure adopts a hierarchical BTB storage design scheme, which effectively balances resource utilization and prediction accuracy by using a layered storage method with a small number of high-order TAG entries and a large number of low-order TAG entries. At the same time, the dual-level entry structure has significant savings in area and power consumption compared with the traditional flat TAG full storage BTB or increasing the number of BTB entries.
[0070] At least one embodiment of this disclosure also provides a branch predictor. Figure 6 This is a schematic diagram of a branch predictor provided in at least one embodiment of the present disclosure.
[0071] like Figure 6 As shown, the branch predictor 300 includes a cache module and a register module (not shown in the figure). The cache module includes at least one entry, in which the TAG field is configured to store the low-order TAG of the historical branch instruction address. The register module includes a high-order TAG table, which is configured to store the high-order TAG of the historical branch instruction address. The branch predictor 300 also includes a first matching unit 310, an acquisition unit 320, a second matching unit 330, and a determination unit 340.
[0072] The first matching unit 310 is configured to match the low-order TAG of the current branch instruction address with the TAG field in the target entry of the cache module, wherein the target entry corresponds to the index field of the current branch instruction address. The specific operation process is described in step S200 above and will not be repeated here.
[0073] The acquisition unit 320 is configured to acquire the high-order index in response to a match between the low-order TAG of the current branch instruction address and the TAG field in the target entry of the cache module. The high-order index points to the high-order TAG entry in the high-order TAG table that corresponds to the low-order TAG recorded in the TAG field of the target entry. The specific operation process is described in step S210 above and will not be repeated here.
[0074] The second matching unit 330 is configured to match the high-order TAG of the current branch instruction address with the high-order TAG in the high-order TAG table entry. The specific operation process is described in step S220 above and will not be repeated here.
[0075] The determining unit 340 is configured to determine if the branch prediction hit is achieved when the high-order TAG of the current branch instruction address matches the high-order TAG in the high-order TAG table entry. The specific operation process is described in step S230 above and will not be repeated here.
[0076] For example, in one possible implementation, the cache module in the branch predictor 300 adopts a set-associative mode, and the first matching unit 210 is further configured to match the low-order TAG of the current branch instruction address with the TAG fields in the target entries corresponding to m paths of the cache module, where m is an integer greater than 1. The specific operation process will not be described in detail here.
[0077] For example, in one possible implementation, the branch predictor 200 further includes an insertion unit (not shown in the figure), which is configured to insert a first entry in the cache module in response to a mismatch between the low-order TAG of the current branch instruction address and the TAG field in the target entry corresponding to the m-way of the cache module. The first entry is used to record the low-order TAG of the current branch instruction address; or, in response to a mismatch between the high-order TAG of the current branch instruction address and the high-order TAG in the high-order TAG table, a second entry is inserted in the high-order TAG table in response to a mismatch between the high-order TAG of the current branch instruction address and the high-order TAG in the high-order TAG table. The second entry is used to record the high-order TAG of the current branch instruction address.
[0078] For example, in one possible implementation, the branch predictor 200 further includes a replacement unit (not shown in the figure), configured to replace the target entries corresponding to the m paths of the branch target buffer using a pseudo-random replacement method when the m-path target entries of the branch target buffer are full when inserting the first entry, where m equals 2; or, when the high-order TAG table is full when inserting the second entry, to replace the least used entry in the high-order TAG table using the LRU algorithm. The specific replacement method is described above and will not be repeated here.
[0079] For example, in one possible implementation, the above-described cache module includes a branch target buffer.
[0080] It should be noted that, for clarity and brevity, the embodiments of this disclosure do not provide all the constituent units of the processor 100 and the branch predictor 300 described above. To implement the necessary functions of the processor 100 and the branch predictor 300, those skilled in the art can provide and set other constituent units (not shown) according to specific needs, and the embodiments of this disclosure do not impose any limitations on this.
[0081] Although the present disclosure has been described in detail above with general descriptions and specific embodiments, modifications or improvements can be made to the embodiments of the present disclosure, which will be obvious to those skilled in the art. Therefore, all such modifications or improvements made without departing from the spirit of the present disclosure are within the scope of protection claimed by the present disclosure.
[0082] The following points should be noted regarding this disclosure:
[0083] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.
[0084] (2) For clarity, the thickness of layers or regions in the drawings used to describe embodiments of the present disclosure is enlarged or reduced, i.e., these drawings are not drawn to actual scale.
[0085] (3) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.
[0086] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure should be determined by the scope of protection of the claims.
Claims
1. A processor comprising a branch predictor, wherein, The branch predictor comprises a cache module and a register module, The cache module comprises at least one table entry, and a TAG field in the at least one table entry is configured to store a low-bit TAG of a history branch instruction address; The register module comprises a high-bit TAG table, and the high-bit TAG table is configured to store a high-bit TAG of the history branch instruction address; The branch predictor is configured to perform the following branch prediction process: matching a low-bit TAG of a current branch instruction address with a TAG field in a target table entry of the cache module, wherein the target table entry corresponds to an index field of the current branch instruction address; in response to the low-bit TAG of the current branch instruction address matching the TAG field in the target table entry of the cache module, obtaining a high-bit index, wherein the high-bit index points to a high-bit TAG table entry in the high-bit TAG table corresponding to the low-bit TAG recorded in the TAG field in the target table entry; matching a high-bit TAG of the current branch instruction address with a high-bit TAG in the high-bit TAG table entry; and in response to the high-bit TAG of the current branch instruction address matching the high-bit TAG in the high-bit TAG table entry, determining a branch prediction hit.
2. The processor of claim 1, wherein, The target table entry comprises the high-bit index.
3. The processor of claim 1, wherein, The number of table entries of the cache module is associated with the number of valid bits of the index field.
4. The processor of claim 3, wherein, The current branch instruction address is 32 bits, the number of valid bits of the index field is equal to 6, and the number of table entries in the cache module is equal to 64.
5. The processor of claim 4, wherein, The number of valid bits of the high-bit index is equal to 2, and the number of table entries in the high-bit TAG table is equal to 4.
6. The processor of any one of claims 1-5, wherein, The cache module adopts a set-associative mode, The matching of the low-bit TAG of the current branch instruction address with the TAG field in the target table entry of the cache module comprises: matching the low-bit TAG of the current branch instruction address with TAG fields in target table entries corresponding to m ways of the cache module respectively, wherein m is an integer greater than 1.
7. The processor of any one of claims 1-5, wherein, The high-bit TAG table adopts a full-associative mode.
8. The processor of claim 6, wherein, The branch predictor is further configured to perform the following branch prediction process: in response to the low-bit TAG of the current branch instruction address not matching the TAG fields in the target table entries corresponding to m ways of the cache module, inserting a first table entry in the cache module, wherein the first table entry is used to record the low-bit TAG of the current branch instruction address; or, in response to the high-bit TAG of the current branch instruction address not matching the high-bit TAG in the high-bit TAG table entry, inserting a second table entry in the high-bit TAG table, wherein the second table entry is used to record the high-bit TAG of the current branch instruction address.
9. The processor of claim 8, wherein, m is equal to 2, The inserting of the first table entry in the cache module comprises: in a case where target table entries corresponding to two ways of the cache module are full when the first table entry is inserted, replacing the target table entries corresponding to the two ways of the cache module in a pseudo-random replacement manner; or The inserting of the second table entry in the high-bit TAG table comprises: In a case that entries of the high-bit TAG table are full when the second entry is inserted, the least recently used (LRU) algorithm is used to replace the least used entry in the high-bit TAG table.
10. The processor of any one of claims 1-5, wherein, The cache module includes a branch target buffer.
11. A branch predictor comprising a cache module and a register module, wherein, The cache module includes at least one entry, a TAG field in the at least one entry is configured to store a low-bit TAG of a history branch instruction address; the register module includes a high-bit TAG table, the high-bit TAG table is configured to store a high-bit TAG of the history branch instruction address, and the branch predictor further includes: A first matching unit, configured to match a low-bit TAG of a current branch instruction address with a TAG field in a target entry of the cache module, wherein the target entry corresponds to an index field of the current branch instruction address; A obtaining unit, configured to obtain a high-bit index in response to the low-bit TAG of the current branch instruction address matching the TAG field in the target entry of the cache module, wherein the high-bit index points to a high-bit TAG entry of the high-bit TAG table corresponding to the low-bit TAG recorded in the TAG field in the target entry; A second matching unit, configured to match a high-bit TAG of the current branch instruction address with a high-bit TAG in the high-bit TAG entry; and A determining unit, configured to determine a branch prediction hit in response to the high-bit TAG of the current branch instruction address matching the high-bit TAG in the high-bit TAG entry.
12. The branch predictor of claim 11, wherein, The cache module uses a set-associative mode, The first matching unit is further configured to match the low-bit TAG of the current branch instruction address with TAG fields in m-way corresponding target entries of the cache module respectively, wherein m is an integer greater than 1.
13. The branch predictor of claim 11, further comprising: An inserting unit, configured to insert a first entry in the cache module in response to the low-bit TAG of the current branch instruction address not matching the TAG fields in the m-way corresponding target entries of the cache module, the first entry being configured to record the low-bit TAG of the current branch instruction address; Or, insert a second entry in the high-bit TAG table in response to the high-bit TAG of the current branch instruction address not matching the high-bit TAG in the high-bit TAG entry, the second entry being used to record the high-bit TAG of the current branch instruction address.
14. The branch predictor of claim 13, wherein, m is equal to 2, and the branch predictor further includes: A replacing unit, configured to replace the two-way corresponding target entries of the cache module in a pseudo-random replacement manner in a case that the two-way corresponding target entries of the cache module are full when the first entry is inserted; or In a case that entries of the high-bit TAG table are full when the second entry is inserted, the least recently used (LRU) algorithm is used to replace the least used entry in the high-bit TAG table.
15. The branch predictor of any of claims 11-14, wherein, The cache module includes a branch target buffer. The cache module includes at least one entry, a TAG field in the at least one entry is configured to store a low-bit TAG of a history branch instruction address; the register module includes a high-bit TAG table, the high-bit TAG table is configured to store a high-bit TAG of the history branch instruction address, and the branch predictor further includes: A first matching unit, configured to match a low-bit TAG of a current branch instruction address with a TAG field in a target entry of the cache module, wherein the target entry corresponds to an index field of the current branch instruction address; A obtaining unit, configured to obtain a high-bit index in response to the low-bit TAG of the current branch instruction address matching the TAG field in the target entry of the cache module, wherein the high-bit index points to a high-bit TAG entry of the high-bit TAG table corresponding to the low-bit TAG recorded in the TAG field in the target entry; A second matching unit, configured to match a high-bit TAG of the current branch instruction address with a high-bit TAG in the high-bit TAG entry; and A determining unit, configured to determine a branch prediction hit in response to the high-bit TAG of the current branch instruction address matching the high-bit TAG in the high-bit TAG entry. The cache module uses a set-associative mode, The first matching unit is further configured to match the low-bit TAG of the current branch instruction address with TAG fields in m-way corresponding target entries of the cache module respectively, wherein m is an integer greater than 1.