Interrupt scheduling processing method and hardware interrupt controller
By setting an interrupt dispatcher in the hardware interrupt controller, the problem of interrupts not being processed for a long time due to virtual machine monitor scheduling in the virtual machine system is solved, ensuring the normal operation of the system.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-11
- Publication Date
- 2026-03-10
AI Technical Summary
In a virtual machine system, when the virtual machine monitor schedules VLPI interrupts, the interrupts cannot be processed for a long time when the second virtual machine is in a suspended state, affecting the normal operation of the system.
An interrupt controller dispatcher is set up inside the hardware interrupt controller. By finding the target interrupt and determining the virtual machine status, it sends an interrupt signal to the virtual machine monitor to notify it of the existence of an interrupt to be processed, thus ensuring resource allocation and processing.
This avoids the VLPI interrupts scheduled to the second virtual machine from going unprocessed for extended periods, ensuring normal system operation.
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Figure CN121636058A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of computers, and more particularly to an interrupt scheduling method and a hardware interrupt controller. Background Technology
[0002] In a virtual machine system, the hardware interrupt controller can directly inject Virtual Locality-Specific Peripheral Interrupts (VLPIs) into the virtual machine through the virtual CPU interface of the virtual machine system. For example, when it is necessary to send a VLPI interrupt to a virtual machine, the hardware interrupt controller can directly send a VLPI interrupt to the corresponding virtual machine.
[0003] The virtual machine monitor in the virtual machine system may schedule VLPI interrupts sent to the virtual machine at any time for some reason. For example, it may temporarily schedule the VLPI interrupt sent to the first virtual machine to the second virtual machine. In this case, the virtual machine monitor only needs to send an interrupt scheduling instruction to the hardware interrupt controller to instruct the hardware interrupt controller to perform the corresponding interrupt scheduling operation.
[0004] However, in the above scenario, if the second virtual machine is in a suspended state, the hardware interrupt controller will send the interrupt destined for the second virtual machine to an off-chip storage location instead of reaching the second virtual machine. However, the virtual machine monitor is unaware that the interrupt has not been processed by the second virtual machine, nor is it aware that there is an interrupt that needs to be processed by the second virtual machine stored off-chip. This may result in the VLPI interrupt scheduled to the second virtual machine not being processed for a long time, which may affect the normal operation of the system. Summary of the Invention
[0005] Based on the above-mentioned technical problems, this application provides an interrupt scheduling method and a hardware interrupt controller, which can avoid the situation where VLPI interrupts are not processed for a long time during the VLPI interrupt scheduling process, thereby affecting the normal operation of the system.
[0006] The first aspect of this application provides an interrupt scheduling method applied to the hardware interrupt controller of a virtual machine system, wherein an interrupt controller dispatcher is provided inside the hardware interrupt controller. The method includes: When the interrupt controller dispatcher receives an interrupt scheduling instruction sent by the virtual machine monitor, it searches for the target interrupt in the hardware interrupt controller; the interrupt scheduling instruction is used to instruct the target interrupt destined for the first virtual machine to be scheduled to the second virtual machine, and the target interrupt is a virtual local specific peripheral interrupt; Upon locating the target interrupt and determining that the second virtual machine is in a suspended state, the interrupt controller dispatcher sends an interrupt signal to the virtual machine monitor, so that the virtual machine monitor can determine that there is an interrupt that the second virtual machine needs to handle.
[0007] In some implementations, the hardware interrupt controller also includes an interrupt translation service module, and the method further includes: When the interrupt translation service module receives the interrupt scheduling instruction sent by the virtual machine monitor, it determines the state of the second virtual machine and sends the interrupt scheduling instruction and the state information of the second virtual machine to the interrupt controller distributor.
[0008] In some implementations, the interrupt controller dispatcher includes an off-chip interrupt management controller, a virtual local specific peripheral interrupt controller, and an interrupt management controller; the off-chip interrupt management controller is used to manage interrupts stored outside the hardware interrupt controller, the virtual local specific peripheral interrupt controller is used to manage virtual local specific peripheral interrupts inside the hardware interrupt controller, and the interrupt management controller is used to manage interrupts sent to each processor core. When the interrupt controller dispatcher receives an interrupt scheduling instruction sent by the virtual machine monitor, it searches for the target interrupt from the hardware interrupt controller, including: The off-chip interrupt management controller, the virtual local specific peripheral interrupt controller, and the interrupt management controller respectively receive the interrupt scheduling instruction sent by the interrupt translation service module and the status information of the second virtual machine, and respectively search for the target interrupt from the interrupts they manage.
[0009] In some implementations, upon locating the target interrupt and determining that the second virtual machine is in a suspended state, the interrupt controller dispatcher sends an interrupt signal to the virtual machine monitor, including: When any one of the off-chip interrupt management controller, the virtual local specific peripheral interrupt controller, and the interrupt management controller finds the target interrupt and determines that the second virtual machine is in a suspended state based on the state information of the second virtual machine, it sends an interrupt signal to the virtual machine monitor.
[0010] In some implementations, the interrupt controller dispatcher further includes a local specific peripheral interrupt controller for managing local specific peripheral interrupts within the hardware interrupt controller; Any one of the off-chip interrupt management controller, the virtual local specific peripheral interrupt controller, and the interrupt management controller sends an interrupt signal to the virtual machine monitor, including: Any one of the off-chip interrupt management controller, the virtual local specific peripheral interrupt controller, and the interrupt management controller sends an interrupt signal to the local specific peripheral interrupt controller; When the local specific peripheral interrupt controller receives an interrupt signal from any one of the off-chip interrupt management controller, the virtual local specific peripheral interrupt controller, and the interrupt management controller, it sends an interrupt to the virtual machine monitor.
[0011] In some implementations, when any one of the off-chip interrupt management controller, the virtual local specific peripheral interrupt controller, and the interrupt management controller sends an interrupt signal to the local specific peripheral interrupt controller, it also sends the interrupt scheduling instruction information to the local specific peripheral interrupt controller so that the local specific peripheral interrupt controller can determine interrupt scheduling information based on the interrupt scheduling instruction information. The interrupt sent by the local specific peripheral interrupt controller to the virtual machine monitor carries the interrupt scheduling information.
[0012] A second aspect of this application provides a hardware interrupt controller, wherein the hardware interrupt controller internally includes an interrupt controller dispatcher; When the interrupt controller dispatcher receives an interrupt scheduling instruction sent by the virtual machine monitor, it searches for the target interrupt in the hardware interrupt controller; the interrupt scheduling instruction is used to instruct the target interrupt destined for the first virtual machine to be scheduled to the second virtual machine. Upon locating the target interrupt and determining that the second virtual machine is in a suspended state, the interrupt controller dispatcher sends an interrupt signal to the virtual machine monitor, so that the virtual machine monitor can determine that there is an interrupt that the second virtual machine needs to handle.
[0013] In some implementations, the hardware interrupt controller also includes an interrupt translation service module. When the interrupt translation service module receives the interrupt scheduling instruction sent by the virtual machine monitor, it determines the state of the second virtual machine and sends the interrupt scheduling instruction and the state information of the second virtual machine to the interrupt controller distributor.
[0014] In some implementations, the interrupt controller dispatcher includes an off-chip interrupt management controller, a virtual local specific peripheral interrupt controller, and an interrupt management controller; the off-chip interrupt management controller is used to manage interrupts stored outside the hardware interrupt controller, the virtual local specific peripheral interrupt controller is used to manage virtual local specific peripheral interrupts inside the hardware interrupt controller, and the interrupt management controller is used to manage interrupts sent to each processor core. When the interrupt controller dispatcher receives an interrupt scheduling instruction sent by the virtual machine monitor, it searches for the target interrupt from the hardware interrupt controller, including: The off-chip interrupt management controller, the virtual local specific peripheral interrupt controller, and the interrupt management controller respectively receive the interrupt scheduling instruction sent by the interrupt translation service module and the status information of the second virtual machine, and respectively search for the target interrupt from the interrupts they manage; Upon locating the target interrupt and determining that the second virtual machine is in a suspended state, the interrupt controller dispatcher sends an interrupt signal to the virtual machine monitor, including: When any one of the off-chip interrupt management controller, the virtual local specific peripheral interrupt controller, and the interrupt management controller finds the target interrupt and determines that the second virtual machine is in a suspended state based on the state information of the second virtual machine, it sends an interrupt signal to the virtual machine monitor.
[0015] In some implementations, the interrupt controller dispatcher also includes a local specific peripheral interrupt controller for managing virtual local specific peripheral interrupts within the hardware interrupt controller; Any one of the off-chip interrupt management controller, the virtual local specific peripheral interrupt controller, and the interrupt management controller sends an interrupt signal to the virtual machine monitor, including: Any one of the off-chip interrupt management controller, the virtual local specific peripheral interrupt controller, and the interrupt management controller sends an interrupt signal to the local specific peripheral interrupt controller; When the local specific peripheral interrupt controller receives an interrupt signal from any one of the off-chip interrupt management controller, the virtual local specific peripheral interrupt controller, and the interrupt management controller, it sends an interrupt to the virtual machine monitor.
[0016] In the interrupt scheduling method provided in this application, when the interrupt dispatcher in the hardware interrupt controller receives an interrupt scheduling instruction from the virtual machine monitor to schedule a target interrupt destined for the first virtual machine to the second virtual machine, it searches for the target interrupt in the hardware interrupt controller. If the target interrupt is found and it is determined that the second virtual machine is in a suspended state, it can be determined that the target interrupt has not yet been sent. However, since the second virtual machine has already resolved the suspended state, the interrupt dispatcher sends an interrupt signal to the virtual machine monitor, so that the virtual machine monitor can determine that there is an interrupt that needs to be handled by the second virtual machine. In this way, the virtual machine monitor can allocate resources to the second virtual machine again if resources permit, so that the second virtual machine can run and handle the interrupt that needs to be handled by the second virtual machine. The above scheme can avoid the situation where the VLPI interrupt scheduled to the second virtual machine cannot be handled for a long time, thereby affecting the normal operation of the system. Attached Figure Description
[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.
[0018] Figure 1 This is a schematic diagram of a hardware interrupt controller provided in an embodiment of this application.
[0019] Figure 2 This is a schematic diagram illustrating the process by which the interrupt translation service module provided in this application translates VLPI interrupts.
[0020] Figure 3 This is a schematic diagram illustrating the processing procedure of the vPE context switch provided in an embodiment of this application.
[0021] Figure 4 This is a flowchart illustrating an interrupt scheduling method provided in an embodiment of this application.
[0022] Figure 5 This is a schematic diagram illustrating a process for locating a target interrupt and sending an interrupt signal, provided in an embodiment of this application. Detailed Implementation
[0023] In virtual machine systems, the traditional method of injecting Virtual Locality-specific Peripheral Interrupt (VLPI) into a vPE (Virtual Processing Element) requires the following five steps: (1) The hardware interrupt controller sends a physical interrupt to the physical CPU interface.
[0024] (2) A physical interrupt is received.
[0025] (3) The Hypervisor sends interrupts to the running vPE.
[0026] (4) Hypervisor writes to registers to send a VLPI interrupt.
[0027] (5) The VLPI interrupt is received and reaches vPE.
[0028] In the above process, the involvement of the hypervisor is called a trap, requiring the software to perform a significant amount of work to save the current state, which greatly consumes system time. VLPI interrupt direct injection avoids trapping the hypervisor, directly injecting virtual interrupts into the virtual CPU interface, thus greatly improving system efficiency. VLPI interrupt direct injection only requires the following two steps: (1) The interrupt controller sends a VLPI interrupt to the virtual CPU interface.
[0029] (2) The VLPI interrupt is received by the vPE.
[0030] Figure 1 The internal structure of the hardware interrupt controller is shown.
[0031] See Figure 1 As shown, the hardware interrupt controller includes an Interrupt Translation Service (ITS) module, an Interrupt Controller Distributor (PICD), and a Redistributor (RD).
[0032] The main function of ITS is to receive the device ID and event ID sent by the device, and translate the device ID and event ID into LPI interrupt (Locality-specific Peripheral Interrupt) or VLPI interrupt by looking up three interrupt translation tables.
[0033] like Figure 2 As shown, there are three interrupt translation tables: Device table, InterruptTranslation Table (ITT table, or instruction translation table), and vPE table (virtual processing unit table). DeviceTable uses deviceID for addressing and stores the entry address of the ITT table; the ITT table stores vPEID (virtual processing unit ID) and INTID (interrupt number); vPE table uses vPEID as the address and stores the entry address (vpt_addr) of the VLPI pending table and the interrupt target core number (RDbase).
[0034] The entry address of the Device table is stored in the GITS_BASER0 register, and the entry address of the vPE table is stored in the GITS_BASER2 register.
[0035] The following is a basic VLPI interrupt translation process: The interrupt source device sends its DeviceID and EventID to the ITS. The Device table uses GITS_BASER0 + DeviceID as the address to read the Device table and obtain the entry address of the ITT table. Then, it uses the ITT table entry address + EventID to obtain vPEID and INTID. Finally, it uses GITS_BASER2 + vPEID as the address to read the vPE table and obtain vpt_addr and RDbase.
[0036] Ultimately, the VLPI interrupt carries the following information: interrupt number INTID, the pending table entry address of the target vPE (vpt_addr), and the target core number (RDbase).
[0037] The PICD is the core component of the hardware interrupt controller, which controls and distributes LPI and VLPI interrupts. The RD receives interrupt information sent by the PICD and sends LPI interrupts to the physical CPU interface and VLPI interrupts to the virtual CPU interface.
[0038] During the operation of the virtual machine system, when the Hypervisor needs to switch the Guest OS (vPE) for some reason, such as switching the Guest OS from vPE1 to vPE3, the hardware interrupt controller needs to recall all pending interrupts of vPE1 to the hardware interrupt controller and then send them together to the corresponding off-chip pending table of vPE1. This process is called the deschedule process of vPE1.
[0039] When the Hypervisor switches the Guest OS to vPE3, the hardware interrupt controller needs to check if there are any pending interrupts in the off-chip pending table corresponding to vPE3. If so, the interrupts are sent to the hardware interrupt controller. This process is called the vPE3 scheduling (or resource allocation) process.
[0040] The entire process of scheduling vPE1 and then scheduling vPE3 is called vPE context switch.
[0041] Figure 3 A schematic diagram of the hardware interrupt controller implementing the vPE context switch described above is shown.
[0042] Figure 3 The black arrows indicate the vPE1 scheduling process, and the white arrows indicate the vPE3 scheduling process.
[0043] During the vPE1 Deschedule process, PICD needs to do the following three things: (1) Search for interrupts sent to vPE1 in VLPI RAM and transmit them to PICD; (2) If there is a pending interrupt of vPE1 in the VCPU Interface, the PICD sends a release command to the PPI (Point-to-Point Interconnect) module, which forwards it to the VCPU Interface to recall the pending interrupt of vPE1 to the PICD. (3) PICD sends all pending VLPI interrupts of vPE1 to the corresponding off-chip pendingtable of vPE1.
[0044] During the vPE3 scheduling process, PICD needs to do the following three things: (1) Read the VLPI interrupt in the external pending table corresponding to vPE3 into the hardware interrupt controller; (2) Write the read VLPI interrupt into VLPI RAM; (3) Send the VLPI interrupt read in to PPI, and PPI forwards it to VCPU Interface.
[0045] In addition, the Hypervisor can use the VMOVI command to transfer VLPI interrupts from one vPE to another, that is, to change the target (destination) of an already issued VLPI interrupt from one vPE to another. For example, changing a VLPI interrupt destined for vPE1 to be destined for vPE3.
[0046] The implementation logic of the VMOVI command is to modify the vPEID in the ITT table so that it points to another vPE, that is, to another entry in the vPE table, which in turn points to another Rdbase and VPT_addr.
[0047] When the hardware interrupt controller receives the VMOVI command from the Hypervisor, it transfers the corresponding VLPI interrupt from one vPE to another, for example, from vPE1 to vPE3. At this time, vPE3 may be in a scheduled state or a descheduled state.
[0048] If vPE3 is in a scheduled state, the hardware interrupt controller can send the VLPI interrupt to vPE3 so that vPE3 can handle the VLPI interrupt.
[0049] If vPE3 is in a scheduled state, the hardware interrupt controller will send the VLPI interrupt to the external pending table corresponding to vPE3 for storage. However, in this case, the hypervisor is unaware that the external pending table corresponding to vPE3 still stores unprocessed VLPI interrupts. This may cause the hypervisor to not allocate resources to vPE3 for a long time, meaning vPE3 will not be scheduled for an extended period. Consequently, the VLPI interrupts stored in the external pending table corresponding to vPE3 will not be processed for a long time, potentially affecting the normal operation of the system.
[0050] To address the aforementioned technical issues, this application provides an interrupt scheduling method. This method, in scenarios where the Hypervisor reschedules an interrupt destined for one virtual machine to another, can prevent scheduled interrupts from being unprocessed for extended periods due to virtual machine suspension, thereby affecting the normal operation of the system.
[0051] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0052] This application first provides an interrupt scheduling method, which can be executed by the hardware interrupt controller in the virtual machine system, specifically by the interrupt controller distributor (PICD) in the hardware interrupt controller.
[0053] See Figure 4 As shown, the interrupt scheduling method provided in this embodiment includes: S101, When the interrupt controller dispatcher (PICD) receives an interrupt scheduling instruction sent by the virtual machine monitor (Hypervisor), it searches for the target interrupt from the hardware interrupt controller.
[0054] The aforementioned interrupt scheduling instruction refers to the VMOVI instruction sent by the Hypervisor, which instructs the target interrupt destined for the first virtual machine to be scheduled to the second virtual machine. In this embodiment, the target interrupt is the Virtual Local Specific Peripheral Interrupt (VLPI).
[0055] The interrupt scheduling instruction described above carries the identifier (PID) of the target interrupt to be scheduled, as well as the original destination (tgt_old) and the new destination (tgt_new) of the target interrupt. tgt_old and tgt_new can be virtual machine IDs, such as vPE IDs, or the target core number of the processor core where the virtual machine resides. In this embodiment, tgt_old can be represented by the ID of the first virtual machine, and tgt_new can be represented by the ID of the second virtual machine.
[0056] In addition, the interrupt scheduling instruction can also include the entry address of the original interrupt vpending table and the entry address of the new interrupt vpending table, which is the interrupt vpt_addr.
[0057] When the PICD receives the interrupt scheduling instruction mentioned above, it can extract the identifier (PID) of the target interrupt to be scheduled, as well as the original destination (tgt_old) and the new destination (tgt_new) of the target interrupt from the interrupt scheduling instruction.
[0058] Based on this, the PICD begins searching for the target interrupt, limiting the search scope to the entire hardware interrupt controller. This means it not only searches within the PICD itself but also coordinates with other modules within the hardware interrupt controller that might store the target interrupt to perform the search. If no other hardware interrupt controller module besides the PICD stores the target interrupt, the search can be performed solely within the PICD.
[0059] When the hardware interrupt controller receives a VLPI interrupt, it may immediately send the VLPI interrupt to the virtual machine, or due to link congestion or virtual machine busyness, it may temporarily store and buffer the VLPI interrupt inside the PICD for a period of time before sending it to the virtual machine.
[0060] In this situation, when the Hypervisor reschedules a target interrupt that has already been sent to the hardware interrupt controller by sending the VMOVI instruction, the hardware interrupt controller may have already sent the target interrupt to the virtual machine. In this case, the target interrupt no longer exists in the hardware interrupt controller, and therefore cannot be scheduled again by the VMOVI instruction. Only when the hardware interrupt controller has not yet actually sent the target interrupt to the virtual machine can the target interrupt be rescheduled within the hardware interrupt controller.
[0061] Therefore, when the PICD receives an interrupt scheduling instruction, it first uses the identifier of the target interrupt carried in the interrupt scheduling instruction to find the target interrupt.
[0062] If the target interrupt is found in the hardware interrupt controller, the interrupt controller dispatcher (PICD) further determines the state of the second virtual machine, that is, whether the second virtual machine is in a scheduled state or a descheduled state.
[0063] In some embodiments, sending the target core number of the second virtual machine to another module can obtain the entry address vpt_addr_schedule of the current schedule vPE for that core. If the new vpt_addr carried in the interrupt scheduling instruction is the same as the aforementioned vpt_addr_schedule, it indicates that the second virtual machine is in a scheduled state; otherwise, it is in a descheduled state. Through this method, PICD can determine the state of the second virtual machine.
[0064] S102. If the target interrupt is found and it is determined that the second virtual machine is in a suspended state, the interrupt controller dispatcher sends an interrupt signal to the virtual machine monitor so that the virtual machine monitor determines that there is an interrupt that needs to be processed by the second virtual machine.
[0065] Specifically, when the interrupt dispatcher PICD locates the target interrupt from the hardware interrupt controller and determines that the second virtual machine is in a suspended state, refer to... Figure 3 The processing logic of the schedule shown is that the PICD will send the target interrupt to the off-chip pending table corresponding to the second virtual machine for storage.
[0066] In addition to sending the target interrupt to the off-chip pending table corresponding to the second virtual machine for storage, in this embodiment, the PICD also sends a doorbell interrupt signal to the Hypervisor to notify the Hypervisor that there is an interrupt in the off-chip pending table that needs to be processed by the second virtual machine.
[0067] In this embodiment, when the hypervisor receives a doorbell interrupt from the PICD, it can determine that the second virtual machine is in a suspended state. However, there are still VLPI interrupts in the off-chip pending table corresponding to the second virtual machine that need to be processed by the second virtual machine. In this case, when resources permit, the hypervisor can allocate physical resources to the second virtual machine, allowing the second virtual machine to resume its scheduled state. At this time, the PICD can then proceed according to the schedule. Figure 3 The processing logic of the schedule shown reads the VLPI interrupts stored in the off-chip pending table corresponding to the second virtual machine into the hardware interrupt controller and sends them to the second virtual machine for processing.
[0068] As described above, in the interrupt scheduling method provided in this application embodiment, when the interrupt dispatcher in the hardware interrupt controller receives an interrupt scheduling instruction sent by the virtual machine monitor to schedule a target interrupt destined for the first virtual machine to the second virtual machine, it searches for the target interrupt in the hardware interrupt controller. If the target interrupt is found and it is determined that the second virtual machine is in a suspended state, it can be determined that the target interrupt has not yet been sent. However, since the second virtual machine has already processed the suspended state, the interrupt dispatcher sends an interrupt signal to the virtual machine monitor, so that the virtual machine monitor can determine that there is an interrupt that needs to be processed by the second virtual machine. In this way, the virtual machine monitor can allocate resources to the second virtual machine again if resources permit, so that the second virtual machine can run and process the interrupt that needs to be processed by the second virtual machine. The above scheme can avoid the situation where the VLPI interrupt scheduled to the second virtual machine cannot be processed for a long time, thereby affecting the normal operation of the system.
[0069] A more specific implementation of the interrupt scheduling method is disclosed in another embodiment of this application.
[0070] In this embodiment, when the interrupt translation service module in the hardware interrupt controller receives the interrupt scheduling instruction sent by the virtual machine monitor, it determines the status of the second virtual machine and sends the interrupt scheduling instruction and the status information of the second virtual machine to the interrupt controller distributor.
[0071] See Figure 5 As shown, in this embodiment, when the Interrupt Translation Service (ITS) module receives the interrupt scheduling instruction sent by the Hypervisor, it parses the interrupt scheduling instruction through its_stream. During the parsing process, it determines the state of the second virtual machine and finally... Figure 5 Signals ③ and ② shown in the diagram send the parsed interrupt scheduling instruction vmovi_cmd and the second virtual machine's status information vpe_schedule_flag to the PICD. The second virtual machine's status information vpe_schedule_flag can represent different states with different values. For example, when vpe_schedule_flag has the first value, it indicates that the second virtual machine is in a scheduled state; when vpe_schedule_flag has the second value, it indicates that the second virtual machine is in a descheduled state.
[0072] In addition, see Figure 5As shown, after parsing the interrupt scheduling instruction, its_stream will also send the target interrupt identifier PID and the new destination tgt_new obtained from the interrupt scheduling instruction to the PICD through the vmovi_cmd_pid signal and the vmovi_cmd_tgt_new signal, respectively.
[0073] The interrupt controller dispatcher includes an off-chip interrupt management controller vpt_ctrl, a virtual local specific peripheral interrupt controller vlpi_ctrl, and an interrupt management controller dest_ctrl.
[0074] The external interrupt management controller vpt_ctrl is used to manage interrupts stored outside the hardware interrupt controller. For example, vpt_ctrl can search for VLPI interrupts in the external vPE pending table and read the searched VLPI interrupts back to the PICD.
[0075] The virtual local specific peripheral interrupt controller vlpi_ctrl is used to manage the virtual local specific peripheral interrupts inside the hardware interrupt controller. For example, vlpi_pipe can search for VLPI interrupts in VLPI_RAM.
[0076] The interrupt management controller dest_ctrl is used to manage interrupts sent to each processor core. Each processor core has its own corresponding storage space to store interrupts sent to the corresponding processor core.
[0077] When the Interrupt Translation Service (ITS) module receives an interrupt scheduling instruction and parses it via its_stream, it can send the parsed interrupt scheduling instruction vmovi_cmd and the second virtual machine's status information vpe_schedule_flag to the external interrupt management controller vpt_ctrl, the virtual local specific peripheral interrupt controller vlpi_ctrl, and the interrupt management controller dest_ctrl in the PICD, respectively. That is, the external interrupt management controller vpt_ctrl, the virtual local specific peripheral interrupt controller vlpi_ctrl, and the interrupt management controller dest_ctrl in the PICD can all receive the interrupt scheduling instruction vmovi_cmd and the second virtual machine's status information vpe_schedule_flag. In addition, it can also receive the vmovi_cmd_pid signal and the vmovi_cmd_tgt_new signal, thereby determining the target interrupt identifier PID and the new destination tgt_new of the target interrupt.
[0078] Based on the above processing, the off-chip interrupt management controller vpt_ctrl, the virtual local specific peripheral interrupt controller vlpi_ctrl, and the interrupt management controller dest_ctrl each search for the target interrupt from the interrupts they manage, according to the received interrupt scheduling instruction vmovi_cmd and the status information vpe_schedule_flag of the second virtual machine.
[0079] exist Figure 5 Taking the Virtual Local Specific Peripheral Interrupt Controller (vlpi_ctrl) as an example, this paper illustrates the process by which the vlpi_ctrl receives the interrupt scheduling instruction vmovi_cmd sent by its_stream and the status information vpe_schedule_flag of the second virtual machine, and performs the target interrupt lookup. The same process applies to other parts, such as the off-chip interrupt management controller vpt_ctrl and the interrupt management controller dest_ctrl, or other components, when they receive the interrupt scheduling instruction vmovi_cmd and the status information vpe_schedule_flag of the second virtual machine and perform the target interrupt lookup.
[0080] like Figure 5 As shown, after the virtual local specific peripheral interrupt controller vlpi_ctrl receives the interrupt scheduling instruction vmovi_cmd and the status information vpe_schedule_flag of the second virtual machine, it searches for the target interrupt in VLPI_RAM according to the identifier PID of the target interrupt. If the target interrupt is found, the vmovi_match signal is set to valid, which means that the target interrupt has been found.
[0081] Inside the virtual local specific peripheral interrupt controller vlpi_ctrl, when the vmovi_match signal is valid, vpe_schedule_flag indicates that the second virtual machine is in a suspended state, and the current instruction is an interrupt scheduling instruction, i.e., vmovi_cmd is valid, that is, when all three conditions are met, an interrupt signal vlpi_vmov_doorbell_valid is generated and output. This interrupt signal vlpi_vmov_doorbell_valid may be the interrupt signal that is eventually sent to the Hypervisor.
[0082] Similarly, other modules or components, such as the external interrupt management controller vpt_ctrl and the interrupt management controller dest_ctrl in the PICD, follow the same process as the virtual local specific peripheral interrupt controller vlpi_ctrl. Specifically, after receiving the interrupt scheduling instruction vmovi_cmd and the status information vpe_schedule_flag from the second virtual machine, the external interrupt management controller vpt_ctrl searches for the target interrupt in the pending table based on its PID identifier. If the target interrupt is found, the vmovi_match signal is set to active, indicating that the target interrupt has been found.
[0083] Inside the off-chip interrupt management controller vpt_ctrl, when the vmovi_match signal is valid, vpe_schedule_flag indicates that the second virtual machine is in a suspended state, and the current instruction is an interrupt scheduling instruction, i.e., vmovi_cmd is valid, that is, when all three conditions are met, an interrupt signal vpt_vlpi_vmov_doorbell_valid is generated and output. This interrupt signal vpt_vlpi_vmov_doorbell_valid may be the interrupt signal that is finally sent to the Hypervisor.
[0084] As described above, the external interrupt management controller vpt_ctrl, the virtual local specific peripheral interrupt controller vlpi_ctrl, and the interrupt management controller dest_ctrl each search for the target interrupt from the interrupts they manage. When any one of these three controllers finds the target interrupt and determines that the second virtual machine is in a suspended state, it generates and sends a doorbell interrupt signal, which is then sent to the virtual machine monitor (Hypervisor).
[0085] Since the target interrupt can only be stored once in the hardware interrupt controller after it is sent to the hardware interrupt controller, and it may be located in any location, when each module searches for the target interrupt in the hardware interrupt controller, only one module can find the target interrupt, that is, only one module will issue the doorbell interrupt signal.
[0086] See also Figure 5The interrupt controller dispatcher (PICD) also includes a local specific peripheral interrupt controller (lpi_ctrl), which manages and controls the sending, receiving, and storage of local specific peripheral interrupts (LPIs) within the hardware interrupt controller.
[0087] When any one of the external interrupt management controller vpt_ctrl, the virtual local specific peripheral interrupt controller vlpi_ctrl, and the interrupt management controller dest_ctrl sends a doorbell interrupt signal to the Hypervisor, the doorbell interrupt signal can be sent to the local specific peripheral interrupt controller lpi_ctrl.
[0088] Then, the local specific peripheral interrupt controller lpi_ctrl sends an interrupt signal vlpi_lpi_vmov_doorbell_valid to the Hypervisor based on the received doorbell interrupt signal.
[0089] To facilitate the local peripheral interrupt controller (lpi_ctrl) in obtaining information about the target interrupt, when any of the external interrupt management controller (vpt_ctrl), the virtual local peripheral interrupt controller (vlpi_ctrl), and the interrupt management controller (dest_ctrl) sends a doorbell interrupt signal to the Hypervisor, it also sends interrupt scheduling instruction information to the local peripheral interrupt controller (lpi_ctrl). Specifically, it sends the target interrupt identifier (PID) and the new destination (tgt_new) of the target interrupt, for example... Figure 5 As shown, the virtual local specific peripheral interrupt controller vlpi_ctrl sends the vlpi_lpi_vmov_doorbell_pid and vlpi_lpi_vmov_doorbell_tgt signals to the local specific peripheral interrupt controller lpi_ctrl, so that the local specific peripheral interrupt controller lpi_ctrl can determine the interrupt scheduling information. Specifically, it determines the identifier (PID) of the target interrupt to be scheduled based on the vlpi_lpi_vmov_doorbell_pid signal, and determines the new destination of the target interrupt based on the vlpi_lpi_vmov_doorbell_tgt signal.
[0090] The interrupt signal vlpi_lpi_vmov_doorbell_valid sent by the local peripheral interrupt controller lpi_ctrl to the hypervisor carries the aforementioned interrupt scheduling information, namely the identifier (PID) of the target interrupt and the new destination of the target interrupt.
[0091] According to the above embodiment, when a target interrupt is found, the PICD can send a doorbell interrupt signal to the virtual machine monitor so that the virtual machine monitor knows that there is a VLPI interrupt waiting for a second virtual machine to process in the off-chip pending table.
[0092] Another embodiment of this application also provides a hardware interrupt controller, wherein an interrupt controller dispatcher is provided inside the hardware interrupt controller; When the interrupt controller dispatcher receives an interrupt scheduling instruction sent by the virtual machine monitor, it searches for the target interrupt in the hardware interrupt controller; the interrupt scheduling instruction is used to instruct the target interrupt destined for the first virtual machine to be scheduled to the second virtual machine. Upon locating the target interrupt and determining that the second virtual machine is in a suspended state, the interrupt controller dispatcher sends an interrupt signal to the virtual machine monitor, so that the virtual machine monitor can determine that there is an interrupt that the second virtual machine needs to handle.
[0093] In some embodiments, the hardware interrupt controller is further provided with an interrupt translation service module; When the interrupt translation service module receives the interrupt scheduling instruction sent by the virtual machine monitor, it determines the state of the second virtual machine and sends the interrupt scheduling instruction and the state information of the second virtual machine to the interrupt controller distributor.
[0094] In some embodiments, the interrupt controller dispatcher includes an off-chip interrupt management controller, a virtual local specific peripheral interrupt controller, and an interrupt management controller; the off-chip interrupt management controller is used to manage interrupts stored outside the hardware interrupt controller, the virtual local specific peripheral interrupt controller is used to manage virtual local specific peripheral interrupts inside the hardware interrupt controller, and the interrupt management controller is used to manage interrupts sent to each processor core. When the interrupt controller dispatcher receives an interrupt scheduling instruction sent by the virtual machine monitor, it searches for the target interrupt from the hardware interrupt controller, including: The off-chip interrupt management controller, the virtual local specific peripheral interrupt controller, and the interrupt management controller respectively receive the interrupt scheduling instruction sent by the interrupt translation service module and the status information of the second virtual machine, and respectively search for the target interrupt from the interrupts they manage; In some embodiments, when the target interrupt is found and it is determined that the second virtual machine is in a suspended state, the interrupt controller dispatcher sends an interrupt signal to the virtual machine monitor, including: When any one of the off-chip interrupt management controller, the virtual local specific peripheral interrupt controller, and the interrupt management controller finds the target interrupt and determines that the second virtual machine is in a suspended state based on the state information of the second virtual machine, it sends an interrupt signal to the virtual machine monitor.
[0095] In some embodiments, the interrupt controller dispatcher further includes a local specific peripheral interrupt controller for managing virtual local specific peripheral interrupts within the hardware interrupt controller; Any one of the off-chip interrupt management controller, the virtual local specific peripheral interrupt controller, and the interrupt management controller sends an interrupt signal to the virtual machine monitor, including: Any one of the off-chip interrupt management controller, the virtual local specific peripheral interrupt controller, and the interrupt management controller sends an interrupt signal to the local specific peripheral interrupt controller; When the local specific peripheral interrupt controller receives an interrupt signal from any one of the off-chip interrupt management controller, the virtual local specific peripheral interrupt controller, and the interrupt management controller, it sends an interrupt to the virtual machine monitor.
[0096] In some embodiments, when any one of the off-chip interrupt management controller, the virtual local specific peripheral interrupt controller, and the interrupt management controller sends an interrupt signal to the local specific peripheral interrupt controller, it also sends the interrupt scheduling instruction information to the local specific peripheral interrupt controller so that the local specific peripheral interrupt controller determines interrupt scheduling information based on the interrupt scheduling instruction information. The interrupt sent by the local specific peripheral interrupt controller to the virtual machine monitor carries the interrupt scheduling information.
[0097] The hardware interrupt controller provided in this embodiment belongs to the same concept as the interrupt scheduling and processing method provided in the above embodiments of this application. It can execute the interrupt scheduling and processing method provided in any of the above embodiments of this application and has the corresponding functional modules and beneficial effects of the execution method. Technical details not described in detail in this embodiment can be found in the specific processing content of the interrupt scheduling and processing method provided in the above embodiments of this application, and will not be repeated here.
[0098] Another embodiment of this application provides a virtual machine system that includes the aforementioned hardware interrupt controller. In this virtual machine system, the interrupt scheduling processing method provided in any of the above embodiments can be executed through the aforementioned hardware interrupt controller, and the beneficial effects achieved by executing the interrupt scheduling processing method can be obtained.
[0099] For the foregoing method embodiments, in order to simplify the description, they are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, because according to this application, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily essential to this application.
[0100] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For apparatus embodiments, since they are basically similar to method embodiments, the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.
[0101] The steps in the methods of the various embodiments of this application can be adjusted, merged, or deleted in order according to actual needs, and the technical features described in each embodiment can be replaced or combined.
[0102] The modules and sub-modules in the various embodiments of the present application's devices and terminals can be merged, divided, and deleted according to actual needs.
[0103] It should be understood that the disclosed terminals, devices, and methods can be implemented in other ways, given the several embodiments provided in this application. For example, the terminal embodiments described above are merely illustrative. For instance, the division of modules or sub-modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple sub-modules or modules may be combined or integrated into another module, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or modules, and may be electrical, mechanical, or other forms.
[0104] The modules or submodules described as separate components may or may not be physically separate. The components that constitute a module or submodule may or may not be physical modules or submodules; that is, they may be located in one place or distributed across multiple network modules or submodules. Some or all of the modules or submodules can be selected to achieve the purpose of this embodiment's solution, depending on actual needs.
[0105] Furthermore, the functional modules or sub-modules in the various embodiments of this application can be integrated into one processing module, or each module or sub-module can exist physically separately, or two or more modules or sub-modules can be integrated into one module. The integrated modules or sub-modules described above can be implemented in hardware or in the form of software functional modules or sub-modules.
[0106] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.
[0107] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software unit executed by a processor, or a combination of both. The software unit can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.
[0108] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0109] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A method of interrupt scheduling processing, characterized by, The application relates to a hardware interrupt controller applied to a virtual machine system, wherein an interrupt controller distributor is arranged in the hardware interrupt controller. The method comprises: The interrupt controller distributor finds a target interrupt from the hardware interrupt controller when receiving an interrupt scheduling instruction sent by a virtual machine monitor; the interrupt scheduling instruction is used for scheduling the target interrupt sent to a first virtual machine to a second virtual machine, and the target interrupt is a virtual local specific peripheral interrupt; In the case that the target interrupt is found and it is determined that the second virtual machine is in a suspended state, the interrupt controller distributor sends an interrupt signal to the virtual machine monitor, so that the virtual machine monitor determines that there is an interrupt that needs to be processed by the second virtual machine.
2. The method of claim 1, wherein, The hardware interrupt controller is further provided with an interrupt translation service module inside, and the method further comprises: The interrupt translation service module determines the state of the second virtual machine when receiving the interrupt scheduling instruction sent by the virtual machine monitor, and sends the interrupt scheduling instruction and the state information of the second virtual machine to the interrupt controller distributor.
3. The method of claim 2, wherein, The interrupt controller distributor comprises an off-chip interrupt management controller, a virtual local specific peripheral interrupt controller and an interrupt management controller; the off-chip interrupt management controller is used for managing interrupts stored outside the hardware interrupt controller, the virtual local specific peripheral interrupt controller is used for managing virtual local specific peripheral interrupts inside the hardware interrupt controller, and the interrupt management controller is used for managing interrupts sent to each processor core; The interrupt controller distributor finds a target interrupt from the hardware interrupt controller when receiving an interrupt scheduling instruction sent by a virtual machine monitor, and comprises: The off-chip interrupt management controller, the virtual local specific peripheral interrupt controller and the interrupt management controller respectively receive the interrupt scheduling instruction and the state information of the second virtual machine sent by the interrupt translation service module, and find the target interrupt from the interrupts managed by the off-chip interrupt management controller, the virtual local specific peripheral interrupt controller and the interrupt management controller respectively.
4. The method of claim 3, wherein, The interrupt controller distributor sends an interrupt signal to the virtual machine monitor in the case that the target interrupt is found and it is determined that the second virtual machine is in a suspended state, and comprises: When any one of the off-chip interrupt management controller, the virtual local specific peripheral interrupt controller and the interrupt management controller finds the target interrupt and determines that the second virtual machine is in a suspended state based on the state information of the second virtual machine, an interrupt signal is sent to the virtual machine monitor.
5. The method of claim 3, wherein, The interrupt controller distributor further comprises a local specific peripheral interrupt controller used for managing local specific peripheral interrupts inside the hardware interrupt controller; Any one of the off-chip interrupt management controller, the virtual local specific peripheral interrupt controller and the interrupt management controller sends an interrupt signal to the virtual machine monitor, and comprises: Any one of the off-chip interrupt management controller, the virtual local specific peripheral interrupt controller and the interrupt management controller sends an interrupt signal to the local specific peripheral interrupt controller; The local specific peripheral interrupt controller sends an interrupt to the virtual machine monitor when receiving an interrupt signal sent by any one of the off-chip interrupt management controller, the virtual local specific peripheral interrupt controller and the interrupt management controller.
6. The method of claim 5, wherein, When any one of the off-chip interrupt management controller, the virtual local specific peripheral interrupt controller and the interrupt management controller sends an interrupt signal to the local specific peripheral interrupt controller, the local specific peripheral interrupt controller also sends information of the interrupt scheduling instruction to the local specific peripheral interrupt controller, so that the local specific peripheral interrupt controller determines interrupt scheduling information based on the information of the interrupt scheduling instruction. The interrupt sent by the local specific peripheral interrupt controller to the virtual machine monitor carries the interrupt scheduling information.
7. A hardware interrupt controller, characterized by The hardware interrupt controller is internally provided with an interrupt controller distributor. The interrupt controller distributor finds a target interrupt from the hardware interrupt controller when receiving an interrupt scheduling instruction sent by the virtual machine monitor; the interrupt scheduling instruction is used to indicate that the target interrupt sent to a first virtual machine is scheduled to a second virtual machine. In the case that the target interrupt is found and it is determined that the second virtual machine is in a suspended state, the interrupt controller distributor sends an interrupt signal to the virtual machine monitor, so that the virtual machine monitor determines that there is an interrupt that needs to be processed by the second virtual machine.
8. The hardware interrupt controller of claim 7, wherein, The hardware interrupt controller is internally further provided with an interrupt translation service module. The interrupt translation service module determines the state of the second virtual machine when receiving the interrupt scheduling instruction sent by the virtual machine monitor, and sends the interrupt scheduling instruction and the state information of the second virtual machine to the interrupt controller distributor.
9. The hardware interrupt controller of claim 8, wherein, The interrupt controller distributor comprises an off-chip interrupt management controller, a virtual local specific peripheral interrupt controller and an interrupt management controller; the off-chip interrupt management controller is used to manage interrupts stored outside the hardware interrupt controller, the virtual local specific peripheral interrupt controller is used to manage virtual local specific peripheral interrupts inside the hardware interrupt controller, and the interrupt management controller is used to manage interrupts sent to each processor core. The interrupt controller distributor finds a target interrupt from the hardware interrupt controller when receiving an interrupt scheduling instruction sent by the virtual machine monitor, and comprises the following steps: The off-chip interrupt management controller, the virtual local specific peripheral interrupt controller and the interrupt management controller respectively receive an interrupt scheduling instruction and state information of the second virtual machine sent by the interrupt translation service module, and respectively find the target interrupt from the interrupts managed by each of them. The interrupt controller distributor sends an interrupt signal to the virtual machine monitor in the case that the target interrupt is found and it is determined that the second virtual machine is in a suspended state, and comprises the following steps: When any one of the off-chip interrupt management controller, the virtual local specific peripheral interrupt controller and the interrupt management controller finds the target interrupt and determines that the second virtual machine is in a suspended state based on the state information of the second virtual machine, an interrupt signal is sent to the virtual machine monitor.
10. The hardware interrupt controller of claim 8, wherein, The interrupt controller distributor further comprises a local specific peripheral interrupt controller for managing a virtual local specific peripheral interrupt inside the hardware interrupt controller. Any one of the off-chip interrupt management controller, the virtual local specific peripheral interrupt controller and the interrupt management controller sends an interrupt signal to the virtual machine monitor, comprising: Any one of the off-chip interrupt management controller, the virtual local specific peripheral interrupt controller and the interrupt management controller sends an interrupt signal to the local specific peripheral interrupt controller; When the local specific peripheral interrupt controller receives the interrupt signal sent by any one of the off-chip interrupt management controller, the virtual local specific peripheral interrupt controller and the interrupt management controller, an interrupt is sent to the virtual machine monitor.