Modt motherboard on-board multi-core cpu performance prediction and scheduling system ai monitoring method

Abstract

The application relates to the technical field of computers and discloses an AI monitoring method for performance prediction and scheduling of a multi-core CPU on a MODT mainboard. The method comprises the following steps: collecting multi-core running states and mainboard physical topology data, and constructing a communication delay-dynamic power consumption joint feature map; performing space-time modeling through a graph neural network to generate a multi-core state embedding vector; fusing task features to calculate a task-core matching degree matrix; establishing a multi-objective optimization model with the minimum communication delay, balanced power consumption and controllable temperature as constraints, and solving the model by an reinforcement learning agent to output optimal scheduling instructions. The application reduces the standard deviation of communication delay and temperature rise and improves the energy efficiency ratio through physical perception and AI collaborative scheduling, and application code does not need to be modified.

Description

Technical Field

[0001] This invention belongs to the field of computer technology, specifically relating to an AI monitoring method for MODT motherboard onboard multi-core CPU performance prediction and scheduling system. Background Technology

[0002] With the widespread application of multi-core processors in high-performance computing, data centers, and edge intelligent devices, the demand for refined task scheduling and resource management is becoming increasingly urgent. Modern CPUs generally adopt heterogeneous multi-core architectures to balance energy efficiency and computing power, and their performance is highly dependent on the operating system scheduler's rational allocation of computing tasks. However, traditional scheduling strategies mainly make decisions based on static load indicators, ignoring the profound impact of the motherboard's physical layer on the efficiency of inter-core communication.

[0003] Specifically, in MODT (Multi-chip On-chip Die Topology) motherboards, different computing cores are interconnected through complex wiring networks. Significant differences exist in signal propagation path length, trace impedance, and power supply noise environment, resulting in non-uniform distribution of inter-core communication latency and dynamic power consumption. This hardware-level heterogeneity can easily induce local communication hotspots in high-concurrency task scenarios, causing some cores to idle while waiting for data, while other cores overheat and throttle due to frequent communication, severely weakening overall throughput and energy efficiency.

[0004] Optimizing heterogeneous inter-core communication based on dynamic topology awareness in edge computing has become a key direction for improving the performance of multi-core systems. This direction aims to overcome the limitations of traditional schedulers' "black box" processing of hardware topology by constructing a task mapping mechanism that matches the actual electrical characteristics of the motherboard through real-time awareness of physical connection status and communication load distribution. Its core objective is to minimize the usage frequency of high-latency or high-power communication links while ensuring balanced computing load, thereby suppressing the formation of communication hotspots and extending the stable operating window of the system.

[0005] In existing technologies, some studies have attempted to introduce hardware performance counters or on-chip network (NoC) monitoring units to obtain communication traffic information. However, these methods suffer from coarse monitoring granularity, slow response, and lack of predictive scheduling based on physical models of electrical signal propagation. More importantly, existing solutions generally lack the ability to collaboratively sense power management units and computing units, failing to capture dynamic communication performance degradation caused by voltage fluctuations and current transients.

[0006] While graph structures are used to abstract inter-core connections, traditional graph algorithms struggle to learn topological evolution patterns online and are not deeply integrated with AI models to achieve forward-looking task remapping. Therefore, in MODT motherboard environments, a novel scheduling mechanism that integrates edge monitoring, physical modeling, and intelligent prediction is urgently needed to address communication hotspots and performance bottlenecks caused by ignoring wiring delays and dynamic power consumption differences. Summary of the Invention

[0007] This invention provides an AI monitoring method for MODT motherboard onboard multi-core CPU performance prediction and scheduling system. It constructs a joint modeling mechanism for multi-core communication latency and dynamic power consumption that is aware of the motherboard's physical topology. Combining real-time task load characteristics and chip-level thermal distribution data, it uses graph neural networks to perform spatiotemporal coupling modeling of the communication path inside the multi-core processor, extracting the dynamic evolution law of inter-core communication hotspot formation. At the same time, it constructs a multi-objective optimization constraint space based on historical scheduling trajectories and current system state, introduces a reinforcement learning-driven scheduling policy generator, and dynamically outputs thread migration and task allocation instructions that meet the triple objectives of minimizing communication latency, maximizing power consumption balance, and controlling temperature gradient. Thus, while ensuring computing throughput, it eliminates the problems of local overheating and energy efficiency degradation caused by asymmetrical wiring and concentrated communication load.

[0008] This invention provides an AI monitoring method for an onboard multi-core CPU performance prediction and scheduling system on MODT motherboards, including:

[0009] The operating status data of each computing core of the multi-core central processing unit is collected in real time through an embedded sensor array on the motherboard.

[0010] Obtain the physical wiring topology data of the motherboard;

[0011] Based on the physical wiring topology data and the operating status data, a multi-core communication latency-dynamic power consumption joint feature graph is constructed, where graph nodes represent each computing core, and graph edge weights are determined by the product of the measured latency and instantaneous power consumption of the corresponding inter-core communication path.

[0012] Graph convolutional encoding is performed on the multi-core communication delay-dynamic power consumption joint feature map to generate a high-dimensional embedding vector of multi-core states that includes spatial adjacency relationships and temporal evolution trends;

[0013] Synchronously acquire task feature data of the current set of tasks to be scheduled, including task type identifier, memory access mode, computational intensity, communication dependency graph and expected execution time;

[0014] The multi-core state high-dimensional embedding vector and the task feature data are input into the multi-head cross-attention fusion module to generate a task-core matching degree matrix. Each element of the task-core matching degree matrix represents the comprehensive evaluation value of the communication overhead and heat accumulation effect caused by a specific task when it is executed on a specific core.

[0015] Based on the task-core matching degree matrix, a multi-objective integer programming model is constructed with the constraints of minimizing the total communication delay, minimizing the variance of dynamic power consumption of each core, and ensuring that the maximum core temperature is less than a preset threshold.

[0016] A deep reinforcement learning agent based on policy gradient is used to solve the multi-objective integer programming model, and the optimal task allocation scheme and thread migration instruction set are output.

[0017] Based on the optimal task allocation scheme and thread migration instruction set, the operating system scheduler is controlled to perform task remapping and thread migration operations, and the task queues of each core are updated.

[0018] Preferably, the real-time acquisition of operating status data of each computing core of the multi-core central processing unit via an embedded sensor array on the motherboard includes:

[0019] Distributed temperature sensors are deployed on the surface of the processor packaging substrate;

[0020] The on-chip current sensing unit is integrated into each core power supply branch and is used to sample instantaneous current waveforms;

[0021] The voltage monitoring circuit is equipped with a 12-bit analog-to-digital converter;

[0022] The performance counter interface reads the microarchitectural event counts of each core directly through the processor's internal performance monitoring unit.

[0023] Preferably, obtaining the motherboard physical wiring topology data includes:

[0024] During the motherboard design phase, a structured topology description file is exported using electronic design automation tools and stored in non-volatile memory.

[0025] During the system startup phase, the firmware module loads the structured topology description file and establishes a mapping table between core logic numbers and physical location coordinates.

[0026] During runtime, the scheduling and monitoring module calls the mapping table to resolve the communication path characteristics between any two cores.

[0027] Preferably, based on the physical wiring topology data and the operating status data, a multi-core communication latency-dynamic power consumption joint feature map is constructed, including:

[0028] Determine the theoretical signal transmission delay baseline value between any two cores based on the physical cabling topology data;

[0029] Calculate the dynamic power consumption value on this communication path by combining the actual communication traffic and voltage / current parameters in the operational status data. The calculation formula is: ,in For the switching activity factor, This is the equivalent load capacitance. Operating voltage For communication frequency;

[0030] The theoretical delay baseline value is multiplied by the dynamic power consumption value as the initial weight of the corresponding graph edge, and the weighted average of 5 consecutive sampling periods within the sliding time window is used as the final edge weight.

[0031] Preferably, graph convolutional encoding is performed on the multi-core communication delay-dynamic power consumption joint feature map to generate a high-dimensional embedding vector of multi-core states containing spatial adjacency relationships and temporal evolution trends, including:

[0032] A three-layer stacked graph attention network structure is adopted, with each layer containing two sub-operations: node feature update and edge weight adaptive adjustment.

[0033] In node feature update, the embedding vector of each core is aggregated with the embedding information of its first-order neighbor cores, and the aggregation weight is obtained by normalizing the edge weights.

[0034] In the adaptive adjustment of edge weights, a new similarity score is calculated based on the node embedding output by the current layer, and linearly interpolated with the original edge weights. The interpolation coefficient is controlled by a time decay factor, which decays exponentially with the system runtime.

[0035] Preferably, obtaining the task feature data of the current set of tasks to be scheduled includes:

[0036] The task type identifier uses an 8-bit integer code to distinguish between four types: computationally intensive, memory intensive, communication intensive, and hybrid.

[0037] Memory access patterns are quantized into a two-dimensional vector using page fault rate and TLB hit rate;

[0038] Computational density is defined as the ratio of the number of floating-point instructions to the total number of instructions.

[0039] The communication dependency graph represents the explicit data dependencies between tasks in the form of an adjacency matrix;

[0040] The expected execution time is estimated by the moving average of the execution times of similar historical tasks.

[0041] Preferably, the high-dimensional embedding vector of the multi-core state and the task feature data are input into the multi-head cross-attention fusion module to generate a task-core matching degree matrix, including:

[0042] The multi-head cross-attention fusion module contains four parallel attention heads, which focus on four dimensions: the matching degree between task computation intensity and core computing power, the matching degree between task memory bandwidth requirements and core cache level, the matching degree between task communication dependency and inter-core latency sensitivity, and the matching degree between task heat generation rate and core heat dissipation capability.

[0043] The outputs of each attention head are concatenated and compressed into a matching degree vector of uniform dimension through a fully connected layer, and then normalized by the Softmax function to generate the task-core matching degree matrix.

[0044] Preferably, based on the task-core matching degree matrix, a multi-objective integer programming model is constructed with constraints of minimizing the total communication delay, minimizing the variance of dynamic power consumption of each core, and ensuring that the maximum core temperature is less than a preset threshold, including:

[0045] The objective function is defined as follows: ,in For the task Assigned to core The resulting communication delay For binary decision variables, With core Dynamic power consumption, With core Real-time temperature, , , For preset weighting coefficients and ;

[0046] The constraints include that each task is assigned to only one core, the length of the task queue for each core is less than the preset upper limit, the temperature of all cores is less than the safety threshold at any time, and the total power consumption of the system is less than the power supply limit.

[0047] Preferably, a deep reinforcement learning agent based on policy gradients is used to solve the multi-objective integer programming model, outputting an optimal task allocation scheme and thread migration instruction set, including:

[0048] The state space of a deep reinforcement learning agent consists of a high-dimensional embedding vector of multi-core states, a task-core matching degree matrix, and the current task queue.

[0049] The action space represents all possible combinations of task assignments and thread migrations.

[0050] The reward function is defined as the negative objective function value of a multi-objective integer programming model;

[0051] The agent is trained using a near-end policy optimization algorithm. The training data comes from historical scheduling logs and sensor sampling sequences during system operation. An online fine-tuning is triggered every 100 scheduling cycles.

[0052] Preferably, based on the optimal task allocation scheme and thread migration instruction set, the operating system scheduler is controlled to perform task remapping and thread migration operations, and the task queues of each core are updated, including:

[0053] Before performing task remapping and thread migration operations, the cache consistency status of the target core is checked. If the cache lines of the target core and the source core have shared data, the migration path with the least cache consistency protocol overhead is selected first.

[0054] If the migration operation is expected to cause the target core temperature to exceed a threshold in the next sampling period, the migration instruction will be delayed until the thermal condition is alleviated.

[0055] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0056] 1. This invention is the first to use the physical wiring topology of the motherboard as the core input variable for multi-core scheduling, and establishes a joint quantization model of communication delay and dynamic power consumption, overcoming the fundamental defect of traditional schedulers that rely only on logical core numbers and ignore physical interconnection differences.

[0057] 2. By using graph neural networks to perform spatiotemporal modeling of multi-core states, it is possible to accurately capture the precursors to the formation of communication hotspots, thereby realizing a shift in scheduling paradigm from passive response to proactive prevention.

[0058] A reinforcement learning scheduling strategy under multi-objective constraints is introduced to ensure that load balancing is improved while suppressing local temperature rises and power consumption spikes.

[0059] 3. This method runs entirely in the operating system kernel space and firmware layer, without requiring modification of application code, and has good compatibility and ease of deployment. Attached Figure Description

[0060] Figure 1 This is a schematic diagram of the overall technical solution architecture of the present invention;

[0061] Figure 2 This is a schematic diagram of the core principle framework of the multi-core communication delay-dynamic power consumption joint modeling and graph neural network spatiotemporal coupling analysis based on motherboard physical topology awareness in this invention;

[0062] Figure 3 This is a flowchart illustrating the logical process of generating high-dimensional embedding vectors for multi-core states and constructing task-core matching degree matrices in this invention.

[0063] Figure 4This is a flowchart illustrating the logical process framework for constructing a multi-objective integer programming model and generating a reinforcement learning-driven scheduling strategy in this invention.

[0064] Figure 5 This is a schematic diagram of the multi-level interaction relationship and data flow between the motherboard embedded sensor array, physical wiring topology data and scheduling monitoring module in this invention;

[0065] Figure 6 This is a logical framework diagram of cache consistency verification and hot safety constraint control during the task remapping and thread migration execution phases in this invention. Detailed Implementation

[0066] Please refer to Figures 1 to 6 This invention provides an AI monitoring method for the MODT motherboard onboard multi-core CPU performance prediction and scheduling system. Its core lies in constructing a joint modeling mechanism for communication latency and dynamic power consumption by integrating motherboard physical wiring topology data and real-time operating status data of the multi-core processor. Based on this, graph neural networks and deep reinforcement learning techniques are introduced to achieve refined and proactive control of multi-core task scheduling. The specific implementation process of this method will be detailed item by item according to the S steps listed in the invention description.

[0067] The method first performs step S1: real-time acquisition of the operating status data of each computing core of the multi-core central processing unit through the embedded sensor array on the motherboard. The operating status data includes the clock frequency, instruction throughput, cache hit rate, voltage and current parameters, on-chip temperature value, and task queue depth of each core.

[0068] The motherboard's embedded sensor array consists of distributed temperature sensors, on-chip current sensing units, voltage monitoring circuitry, and a performance counter interface. Distributed temperature sensors are arranged at a density of at least one per square millimeter on the processor's package substrate surface, ensuring high-resolution sensing capabilities for localized hotspot areas. The on-chip current sensing units are integrated into each core's power supply branch, with a sampling frequency greater than 1000 Hz, used to capture transient current waveforms to reflect sudden changes in core load. The voltage monitoring circuitry is equipped with a 12-bit analog-to-digital converter, with a sampling accuracy better than ±5 millivolts, ensuring accurate capture of voltage fluctuations. The performance counter interface directly reads the microarchitectural event counts of each core through the processor's internal performance monitoring unit, including low-level metrics such as instructions per cycle, L1 and L2 cache misses, and branch prediction failure rate.

[0069] All sensor data is transmitted to the scheduling and monitoring module via a high-speed serial bus. The sampling period is set to two milliseconds to form a continuous time series stream for subsequent modeling and analysis.

[0070] Then, step S2 is executed: obtain the physical wiring topology data of the motherboard, which includes the physical length of the interconnection channel between each computing core, the number of signal trace layers, the dielectric constant of the medium, the impedance matching parameters, and the signal transmission delay reference value.

[0071] The physical wiring topology data is exported by electronic design automation tools during the motherboard design phase and stored in a structured topology description file in non-volatile memory. The file format adopts a hierarchical node-edge representation, with each node corresponding to a computing core and recording its physical coordinates. Each edge records the signal path attributes connecting two cores, including the total trace length, the number of PCB layers traversed, the relative permittivity of the dielectric material used, the characteristic impedance value, and the theoretical signal transmission delay reference value calculated from these. During system startup, the firmware module loads this topology description file and establishes a mapping table between core logic numbers and physical location coordinates. This mapping table is called by the scheduling and monitoring module during runtime to analyze the electrical and delay characteristics of the communication path between any two cores.

[0072] Once loaded, this mapping table remains static and does not change as the system runs, ensuring the determinism and timeliness of physical topology information.

[0073] Then, step S3 is executed: Based on the physical wiring topology data and the operating status data, a multi-core communication delay-dynamic power consumption joint feature graph is constructed, where graph nodes represent each computing core, and graph edge weights are determined by the product of the measured delay and instantaneous power consumption of the corresponding inter-core communication path.

[0074] The construction process first determines any two cores based on the physical cabling topology data. and The theoretical signal transmission delay reference value between This value is determined by the trace length. Dielectric constant of the medium and the speed of light The decision was made jointly, and the calculation formula is as follows: Secondly, combine the actual communication traffic in the operational status data. (per unit of time) Towards Number of data packets sent), operating voltage and communication frequency Calculate the dynamic power consumption on this communication path. Dynamic power consumption calculation uses the standard CMOS power consumption model, expressed as:

[0075] ;

[0076] in The switching activity factor is determined by communication traffic. The result after normalization; The equivalent load capacitance is determined by the trace length. With unit length capacitance parameters jointly determined, ; Take the average value of the power supply voltages for the two cores; The initial weights of the graph edges are derived by working backward from the communication event intervals. Defined as To suppress transient noise, a sliding time window mechanism is used, taking five consecutive sampling periods (totaling 10 milliseconds). The values ​​are then subjected to an exponentially weighted average, with the weight coefficients decaying over time. The weight for the most recent period is 0.4, decreasing sequentially to 0.05 to obtain the final edge weights. This constitutes a complete joint feature map of multi-core communication latency and dynamic power consumption. ,in For a set of nodes, Let be the set of edges. This is the edge weight matrix.

[0077] Next, step S4 is executed: graph convolutional encoding is performed on the multi-core communication delay-dynamic power consumption joint feature map to generate a high-dimensional embedding vector of the multi-core state containing spatial adjacency relationships and temporal evolution trends. The graph convolutional encoding adopts a three-layer stacked graph attention network structure, with each layer containing two sub-operations: node feature update and adaptive edge weight adjustment. Initial node feature vector. From the core The data is composed of seven dimensions: clock frequency, instruction throughput, cache hit rate, voltage, current, temperature, and task queue depth. These dimensions are then linearly projected into a 64-dimensional latent space. In the... layer( In the node feature update of ), the core New Embedded The calculation is as follows:

[0078] ;

[0079] in With core The set of first-order neighbors, For learnable weight matrix, It is the ReLU activation function. With core exist Embedded, The normalized attention coefficient is defined as follows:

[0080] ;

[0081] in For learnable vectors, This represents vector concatenation. With core exist Embedded, With core exist Embedded.

[0082] In the adaptive adjustment of edge weights, node embedding is based on the output of the current layer. and Calculate the new similarity score , and then with Perform linear interpolation to obtain the updated edge weights. ,in This is the time decay factor, initially set to 0.9, which increases with the cumulative system runtime. Exponential decay, , The time constant is set to 360 seconds. After processing by a three-layer graph attention network, the final output node embeddings are... This is a high-dimensional embedding vector of multi-core states, with a dimension of 64, which fully preserves the spatial adjacency structure and the temporal evolution trend within the last 10 milliseconds.

[0083] Synchronously execute step S5: Obtain task feature data of the current set of tasks to be scheduled, including task type identifier, memory access mode, computational intensity, communication dependency graph and expected execution time.

[0084] Task feature data is extracted and encapsulated by the operating system's task scheduler when tasks are enqueued. Task type identifiers use 8-bit integer encoding to distinguish between four categories: compute-intensive, memory-intensive, communication-intensive, and hybrid. Memory access patterns are quantified using page fault rate and TLB hit rate, forming a two-dimensional vector. Computational intensity is defined as the ratio of floating-point instructions to the total number of instructions. The communication dependency graph is represented as an adjacency matrix, recording explicit data dependencies between the task and other tasks. Expected execution time is estimated using the moving average of historical execution times for similar tasks, with a window size equal to the last 50 execution records. All task feature data is standardized before being input into the subsequent fusion module.

[0085] Then, step S6 is executed: the multi-core state high-dimensional embedding vector and the task feature data are input into the multi-head cross-attention fusion module to generate a task-core matching degree matrix. Each element of the matrix represents the comprehensive evaluation value of the communication overhead and heat accumulation effect caused by a specific task being executed on a specific core.

[0086] The multi-head cross-attention fusion module contains four parallel attention heads, each focusing on matching relationships in different dimensions.

[0087] The first focus is on the matching degree between the computational intensity of the task and the core computing power, with the inputs being the task's computational intensity and the core instruction throughput.

[0088] The second focus is on calculating the task's memory bandwidth requirements and the adaptation of the core cache level, with the inputs being the task's memory access mode and the core cache hit rate.

[0089] The third attention head calculates the task communication dependency and inter-core latency sensitivity, with the input being the edge weights of the task communication dependency graph and the multi-core communication latency-dynamic power consumption joint feature graph;

[0090] The fourth attention focus is on calculating the matching degree between the task's heat generation rate and the core's heat dissipation capacity. The inputs are the expected execution time of the task, the current core temperature, and the historical temperature rise rate.

[0091] Each attention head employs a standard scaled dot product attention mechanism to query the vector. Key vectors derived from task features AND value vector The results are derived from multi-core state embedding. The outputs of the four heads are concatenated and compressed into a 64-dimensional matching degree vector through a 128-dimensional fully connected layer. Then, the Softmax function is applied to each task-core pair to normalize along the core dimension, generating... Dimensional Task - Core Matching Degree Matrix ,in For the number of tasks, As the core number, The larger the value, the more tasks... At the core The lower the overall cost of execution.

[0092] Then, step S7 is executed: Based on the task-core matching degree matrix, a multi-objective integer programming model is constructed with the constraints of minimizing the total communication delay, minimizing the variance of dynamic power consumption of each core, and ensuring that the maximum core temperature is less than a preset threshold. The objective function of this model is defined as follows: ,in For binary decision variables, Indicates task Assigned to ; For the task exist The communication delay caused by the execution above is due to Obtained through inverse transformation, ; With core The dynamic power consumption is calculated by summing the power consumption contributions of all tasks allocated to this core; With core The real-time temperature is read directly from the sensor array; , , For preset weighting coefficients and Typical value , , .

[0093] The constraints include: (Each task is assigned to only one core); (The length of each core task queue is less than the preset limit) (usually set to 8). (At any given time, the temperature of all core components is less than the safety threshold V.) For the allocation scheme The resulting temperature rise is predicted by the heat conduction model. (The total power consumption of the system is less than the upper limit of the power supply).

[0094] Then, step S8 is executed: a policy gradient-based deep reinforcement learning agent is used to solve the multi-objective integer programming model, outputting the optimal task allocation scheme and thread migration instruction set. The state space of the deep reinforcement learning agent... It consists of three parts: a set of high-dimensional embedding vectors of multi-kernel states. Task-Core Matching Matrix Current task queue state vector Action space Assign combinations to all feasible tasks, i.e., those that satisfy the basic constraints. Matrix set; reward function Defined as a negative objective function value, i.e. The agent is trained using a near-end policy optimization algorithm. The policy network consists of two fully connected layers. The input... Output The probability distribution.

[0095] Training data is derived from historical scheduling logs and sensor sampling sequences during system operation. Online fine-tuning is triggered every 100 scheduling cycles (approximately 200 milliseconds). Fine-tuning employs mini-batch gradient descent with a batch size of 32 and a learning rate of 0.001. The agent outputs the optimal action. This is the optimal task allocation scheme. This generates a thread migration instruction set, indicating which tasks need to be migrated from the source core to the target core.

[0096] Finally, step S9 is executed: Based on the optimal task allocation scheme and thread migration instruction set, the operating system scheduler is controlled to perform task remapping and thread migration operations, and the task queues of each core are updated. Before the migration is executed, the scheduling monitoring module verifies the cache consistency status of the target core. If the data accessed by the task to be migrated exists in the source core cache but is inconsistent with the target core cache, the cache consistency protocol overhead table is queried. This table pre-stores the number of bus transactions required for MESI protocol state transitions under different migration paths; the path with the lowest overhead is selected first. If multiple paths have the same overhead, the one with the lowest target core temperature is selected.

[0097] Meanwhile, if the migration operation is expected to cause the target core temperature to exceed the safety threshold in the next sampling period. If the migration command is delayed, it will be added to the pending queue until the target core temperature drops back to a certain level. Below -5 degrees Celsius. During the migration process, the operating system scheduler suspends tasks on the source core, copies their context to the target core, updates the task queue pointer, and notifies the interrupt controller to redirect subsequent interrupts. After the migration is complete, the task queue depth of each core is updated, and the sensor array begins a new round of data acquisition, entering the next scheduling cycle.

[0098] The aforementioned method fully implements a closed-loop control process from physical topology awareness, multimodal data fusion, spatiotemporal feature modeling to multi-objective optimization scheduling, ensuring that while improving computational throughput, it effectively suppresses local overheating and energy efficiency degradation caused by asymmetrical wiring and concentrated communication load. The entire method runs in the operating system kernel space and firmware layer, requiring no application modifications and possessing good deployment compatibility.

[0099] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0100] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. An AI monitoring method for MODT motherboard onboard multi-core CPU performance prediction and scheduling system, characterized in that, include: The operating status data of each computing core of the multi-core central processing unit is collected in real time through an embedded sensor array on the motherboard. Obtain the motherboard physical wiring topology data; Based on the physical wiring topology data and the operating status data, a joint feature map of multi-core communication latency and dynamic power consumption is constructed. Graph convolutional encoding is performed on the multi-core communication delay-dynamic power consumption joint feature map to generate a high-dimensional embedding vector of multi-core states that includes spatial adjacency relationships and temporal evolution trends; Synchronously acquire task characteristic data of the current set of tasks to be scheduled; The multi-core state high-dimensional embedding vector and the task feature data are input into the multi-head cross-attention fusion module to generate a task-core matching degree matrix. Each element of the task-core matching degree matrix represents the comprehensive evaluation value of the communication overhead and heat accumulation effect caused by a specific task when it is executed on a specific core. Based on the task-core matching degree matrix, a multi-objective integer programming model is constructed with the constraints of minimizing the total communication delay, minimizing the variance of dynamic power consumption of each core, and ensuring that the maximum core temperature is less than a preset threshold. A deep reinforcement learning agent based on policy gradient is used to solve the multi-objective integer programming model, and the optimal task allocation scheme and thread migration instruction set are output. Based on the optimal task allocation scheme and thread migration instruction set, the operating system scheduler is controlled to perform task remapping and thread migration operations, and the task queues of each core are updated.

2. The AI ​​monitoring method for the MODT motherboard onboard multi-core CPU performance prediction and scheduling system according to claim 1, characterized in that, The method of acquiring real-time operational status data of each computing core of the multi-core central processing unit through an embedded sensor array on the motherboard includes: Distributed temperature sensors are deployed on the surface of the processor packaging substrate; The on-chip current detection unit is integrated into each core power supply branch and is used to sample instantaneous current waveforms; The voltage monitoring circuit is equipped with a 12-bit analog-to-digital converter; The performance counter interface reads the microarchitectural event counts of each core directly through the processor's internal performance monitoring unit.

3. The AI ​​monitoring method for the MODT motherboard onboard multi-core CPU performance prediction and scheduling system according to claim 2, characterized in that, The acquisition of motherboard physical wiring topology data includes: During the motherboard design phase, a structured topology description file is exported using electronic design automation tools and stored in non-volatile memory. During the system startup phase, the firmware module loads the structured topology description file and establishes a mapping table between core logic numbers and physical location coordinates. During runtime, the scheduling and monitoring module calls the mapping table to resolve the communication path characteristics between any two cores.

4. The AI ​​monitoring method for the MODT motherboard onboard multi-core CPU performance prediction and scheduling system according to claim 3, characterized in that, Based on the physical wiring topology data and the operating status data, a joint feature map of multi-core communication latency and dynamic power consumption is constructed, including: Determine the theoretical signal transmission delay baseline value between any two cores based on the physical cabling topology data; Calculate the dynamic power consumption value on this communication path by combining the actual communication traffic and voltage / current parameters in the operational status data. The calculation formula is: ,in For the switching activity factor, This is the equivalent load capacitance. Operating voltage For communication frequency; The theoretical delay baseline value is multiplied by the dynamic power consumption value as the initial weight of the corresponding graph edge, and the weighted average of 5 consecutive sampling periods within the sliding time window is used as the final edge weight.

5. The AI ​​monitoring method for the MODT motherboard onboard multi-core CPU performance prediction and scheduling system according to claim 4, characterized in that, The multi-core communication delay-dynamic power consumption joint feature map is subjected to graph convolutional encoding to generate a high-dimensional embedding vector of multi-core states containing spatial adjacency relationships and temporal evolution trends, including: A three-layer stacked graph attention network structure is adopted, with each layer containing two sub-operations: node feature update and edge weight adaptive adjustment. In node feature update, the embedding vector of each core is aggregated with the embedding information of its first-order neighbor cores, and the aggregation weight is obtained by normalizing the edge weights. In the adaptive adjustment of edge weights, a new similarity score is calculated based on the node embedding output by the current layer, and linearly interpolated with the original edge weights. The interpolation coefficient is controlled by a time decay factor, which decays exponentially with the system runtime.

6. The AI ​​monitoring method for the MODT motherboard onboard multi-core CPU performance prediction and scheduling system according to claim 5, characterized in that, The step of obtaining task feature data for the current set of tasks to be scheduled includes: The task type identifier uses an 8-bit integer code to distinguish between four types: computationally intensive, memory intensive, communication intensive, and hybrid. Memory access patterns are quantized into a two-dimensional vector using page fault rate and TLB hit rate; Computational intensity is defined as the ratio of the number of floating-point instructions to the total number of instructions. The communication dependency graph represents the explicit data dependencies between tasks in the form of an adjacency matrix; The expected execution time is estimated by the moving average of the execution times of similar historical tasks.

7. The AI ​​monitoring method for the MODT motherboard onboard multi-core CPU performance prediction and scheduling system according to claim 6, characterized in that, The high-dimensional embedding vector of the multi-core state and the task feature data are input into the multi-head cross-attention fusion module to generate a task-core matching degree matrix, including: The multi-head cross-attention fusion module contains four parallel attention heads, which focus on four dimensions: the matching degree between task computation intensity and core computing power, the matching degree between task memory bandwidth requirements and core cache level, the matching degree between task communication dependency and inter-core latency sensitivity, and the matching degree between task heat generation rate and core heat dissipation capability. The outputs of each attention head are concatenated and compressed into a matching degree vector of uniform dimension through a fully connected layer, and then normalized by the Softmax function to generate the task-core matching degree matrix.

8. The AI ​​monitoring method for the MODT motherboard onboard multi-core CPU performance prediction and scheduling system according to claim 7, characterized in that, Based on the task-core matching degree matrix, a multi-objective integer programming model is constructed with the constraints of minimizing the total communication delay, minimizing the variance of dynamic power consumption of each core, and ensuring that the maximum core temperature is less than a preset threshold. This model includes: The objective function is defined as follows: ,in For the task Assigned to core The resulting communication delay For binary decision variables, With core Dynamic power consumption, With core Real-time temperature, , , For preset weighting coefficients and ; The constraints include that each task is assigned to only one core, the length of the task queue for each core is less than the preset upper limit, the temperature of all cores is less than the safety threshold at any time, and the total power consumption of the system is less than the power supply limit.

9. The AI ​​monitoring method for the MODT motherboard onboard multi-core CPU performance prediction and scheduling system according to claim 8, characterized in that, A deep reinforcement learning agent based on policy gradients is used to solve the multi-objective integer programming model, outputting the optimal task allocation scheme and thread migration instruction set, including: The state space of a deep reinforcement learning agent consists of a high-dimensional embedding vector of multi-core states, a task-core matching degree matrix, and the current task queue. The action space represents all possible combinations of task assignments and thread migrations. The reward function is defined as the negative objective function value of a multi-objective integer programming model; The agent is trained using a near-end strategy optimization algorithm. The training data comes from historical scheduling logs and sensor sampling sequences during system operation. An online fine-tuning is triggered every 100 scheduling cycles.

10. The AI ​​monitoring method for the MODT motherboard onboard multi-core CPU performance prediction and scheduling system according to claim 9, characterized in that, Based on the optimal task allocation scheme and thread migration instruction set, the operating system scheduler is controlled to perform task remapping and thread migration operations, and the task queues of each core are updated, including: Before performing task remapping and thread migration operations, the cache consistency status of the target core is checked. If the cache lines of the target core and the source core have shared data, the migration path with the least cache consistency protocol overhead is selected first. If the migration operation is expected to cause the target core temperature to exceed the threshold in the next sampling period, the migration instruction will be delayed until the thermal condition is alleviated.

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