Data processing method and chip

Abstract

The embodiment of the invention discloses a data processing method, relates to the technical field of computers, and is used for improving the stability of a chip. The method is applied to a chip, the chip comprises a monitoring module, an adjusting module, a processor core and a storage module, and the method comprises the steps that the monitoring module obtains the number of first requests, and the first requests are data access requests sent by the processor core to the storage module; the adjusting module adjusts the data access request processing speed of at least one storage module of the chip according to the number of the first requests. According to the scheme, the data access request processing speed of the chip storage module is dynamically adjusted based on the number of the data access requests sent to the storage module by the chip processor core, so that the change speed of the bandwidth of the chip can be reduced, and the situation that the power consumption of the chip rapidly fluctuates due to the sharp change of the bandwidth of the chip is avoided; therefore, the voltage of the chip exceeds a normal working range, so that the chip cannot work normally, and the stability of the chip is improved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and more particularly to data processing methods and chips. Background Technology

[0002] As chips become larger and operate at higher frequencies, power consumption and temperature have become critical factors that cannot be ignored in chip design.

[0003] In multi-core computing scenarios, high parallelism places significant demands on chip bandwidth. When multiple cores of a chip simultaneously run demanding tasks, the chip's bandwidth fluctuates drastically, causing rapid fluctuations in power consumption. This can lead to the chip voltage exceeding its normal operating range, ultimately resulting in the chip malfunctioning. Summary of the Invention

[0004] This application provides a data processing method and a chip to improve chip stability. To achieve the above objectives, this application adopts the following technical solution:

[0005] In a first aspect, embodiments of this application provide a data processing method applied to a chip, the chip including a monitoring module, an adjustment module, a processor core, and a storage module. The method includes: the monitoring module acquiring the number of first requests, the first request being a data access request sent by the processor core to the storage module; and the adjustment module adjusting the data access request processing speed of at least one storage module of the chip according to the number of first requests.

[0006] The solution provided in this application dynamically adjusts the data access request processing speed of the chip's memory module based on the number of data access requests sent from the chip's processor core to the memory module. This reduces the rate of change in the chip's bandwidth, preventing drastic bandwidth fluctuations that could cause rapid power consumption fluctuations, leading to voltage spikes exceeding the normal operating range and causing the chip to malfunction. This improves the chip's stability.

[0007] In one possible implementation, the monitoring module can obtain the number of the first requests from the interface between the storage module and the bus.

[0008] It is understandable that the data access requests sent by the chip processor core to the storage module need to be transmitted through the interface between the storage module and the bus. Therefore, the number of data access requests sent by the chip processor core to the storage module can be obtained through the transmission of data through the interface between the storage module and the bus.

[0009] In another possible implementation, the monitoring module can obtain the number of the first requests mentioned above from the access controller of the storage module.

[0010] It is understandable that the access controller of the storage module is used to receive data access requests sent by the chip processor core to the storage module through the bus. Therefore, the number of data access requests sent by the chip processor core to the storage module can be obtained through the access controller of the storage module.

[0011] In one possible implementation, the adjustment module determines the power change rate of the chip based on the number of the first requests; the adjustment module adjusts the data access request processing speed based on the power change rate.

[0012] It is understandable that the number of data access requests sent by the chip's processor core to the memory module is positively correlated with the chip's power change rate. Therefore, the chip's power change rate can be determined by the number of data access requests sent by the chip's processor core to the memory module.

[0013] In one possible implementation, the adjustment module determines the bandwidth change rate of the chip based on the number of the first requests; the adjustment module determines the power change rate based on the bandwidth change rate.

[0014] It is understandable that the number of data access requests sent by the chip's processor core to the memory module is positively correlated with the rate of change of the chip's bandwidth. The rate of change of the chip's bandwidth is also positively correlated with the rate of change of the chip's power consumption. Therefore, the rate of change of the chip's bandwidth can be determined by the number of data access requests sent by the chip's processor core to the memory module, and the rate of change of the chip's power consumption can be determined based on the rate of change of the chip's bandwidth.

[0015] In one possible implementation, the monitoring module obtains the number of second requests, where the second requests are data access requests received by the target storage module, and the target storage module is any storage module of the chip; the adjustment module adjusts the data request processing speed of the target storage module according to the number of the first requests and the number of the second requests.

[0016] It's understandable that the number of data access requests received by the various memory modules within a chip is uneven. When some memory modules receive an excessive number of data access requests, the number of data access requests sent by the chip's processor core to these memory modules will also increase. In this situation, adjusting the data request processing speed of only the memory modules receiving an excessive number of data access requests, without needing to adjust the data request processing speed of the memory modules with a normal number of data access requests, can reduce the rate of bandwidth fluctuations in the chip and prevent the chip's voltage from exceeding its normal operating range, thus preventing the chip from malfunctioning.

[0017] In one possible implementation, the number of first requests is obtained by weighting the number of first requests of at least one type, including data access requests and no data access requests, with the weight of data access requests being greater than the weight of no data access requests.

[0018] Understandably, different types of data access requests consume different amounts of power, so different weights can be assigned to different types. For example, data access requests require data transmission and therefore consume more power, while no-data access requests do not require data transmission and consume less power. Therefore, the weight of data access requests can be higher than that of no-data access requests.

[0019] Optionally, the aforementioned data access requests may include read requests, write requests, atomic operations, or other data access requests.

[0020] Optionally, the aforementioned no-data access request may include a data invalidation operation, a make-unique (MU) status acquisition request, or other no-data access requests.

[0021] In one possible implementation, the storage module may include at least one of the following: cache, double data rate synchronous dynamic random access memory (DDR), high bandwidth memory (HBM), low power DDR (LPDDR), and graphics DDR (GDDR).

[0022] In one possible implementation, data access requests can include read (write) requests that hit the cache and read (write) requests that miss the cache. The weight of a read (write) request that misses the cache is greater than the weight of a read (write) request that hits the cache.

[0023] Understandably, read (write) requests are sent to different storage modules for access. When a read (write) request hits the cache, data can be accessed directly from the cache, consuming less power. When a read (write) request misses the cache, data needs to be read from other storage modules (such as DDR, HBM, GDDR, or LPDDR). Compared to accessing data from the cache, accessing data from other storage modules involves a longer transmission path, increasing power consumption. Therefore, the weight of read (write) requests that miss the cache can be greater than the weight of read (write) requests that hit the cache.

[0024] In one possible implementation, the processor core described above includes multiple processor cores.

[0025] In one possible implementation, the aforementioned plurality of processor cores may include at least one of a central processing unit (CPU) core, a graphics processing unit (GPU) core, an application processor (AP) core, a modem processor core, an image signal processor (ISP) core, a video codec core, a digital signal processor (DSP) core, a baseband processor core, or a neural network processing unit (NPU) core.

[0026] Secondly, embodiments of this application provide a chip including a monitoring module, an adjustment module, a processor core, and a storage module. The monitoring module is used to acquire the number of first requests, where the first request is a data access request sent by the processor core to the storage module. The adjustment module is used to adjust the data access request processing speed of at least one storage module of the chip based on the number of the first requests.

[0027] In one possible implementation, the monitoring module is specifically used to obtain the number of the first requests from the interface between the storage module and the bus or from the access controller of the storage module.

[0028] In one possible implementation, the adjustment module is specifically used to: determine the power change rate of the chip based on the number of the first requests; and adjust the data access request processing speed based on the power change rate.

[0029] In one possible implementation, the adjustment module is specifically used to: determine the bandwidth change rate of the chip based on the number of the first requests; and determine the power change rate based on the bandwidth change rate.

[0030] In one possible implementation, the monitoring module is further configured to: obtain the number of second requests, wherein the second requests are data access requests received by the target storage module, and the target storage module is any of the storage modules of the chip.

[0031] In one possible implementation, the adjustment module is specifically used to: adjust the data request processing speed of the target storage module according to the number of the first request and the number of the second request.

[0032] In one possible implementation, the number of the first requests is obtained by weighting the number of first requests of at least one type, including data access requests and no data access requests, with the weight of the data access requests being greater than the weight of the no data access requests.

[0033] Thirdly, embodiments of this application provide an electronic device including a chip for performing the method described in the first aspect or any possible implementation thereof.

[0034] Fourthly, embodiments of this application also provide a computer-readable storage medium for storing a computer program, the computer program including methods for implementing the first aspect or any possible implementation thereof.

[0035] Fifthly, embodiments of this application also provide a computer program product containing instructions that, when run on a computer, cause the computer to implement the method described in the first aspect or any possible implementation thereof.

[0036] The electronic device, computer storage medium, and computer program product provided in this embodiment are all used to execute the data processing method provided above. Therefore, the beneficial effects they can achieve can be referred to the beneficial effects in the data processing method provided above, and will not be repeated here. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a schematic diagram of the structure of a chip provided in an embodiment of this application;

[0039] Figure 2 A flowchart illustrating an embodiment of this application for adjusting the processing speed of data access requests;

[0040] Figure 3 A flowchart illustrating the process of determining the power change rate of a chip, provided as an embodiment of this application;

[0041] Figure 4 A flowchart illustrating another method for adjusting the processing speed of data access requests, provided in an embodiment of this application;

[0042] Figure 5 A flowchart illustrating another method for adjusting the processing speed of data access requests, provided in an embodiment of this application;

[0043] Figure 6 This is a schematic diagram of another chip structure provided in an embodiment of this application;

[0044] Figure 7 A flowchart illustrating a data processing method provided in an embodiment of this application;

[0045] Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0046] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the embodiments of this application.

[0047] In this article, the term "and / or" is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0048] The terms "first" and "second," etc., in the specification and drawings of the embodiments of this application are used to distinguish different objects or to distinguish different treatments of the same object, rather than to describe a specific order of objects.

[0049] Furthermore, the terms "comprising" and "having," and any variations thereof, used in the description of the embodiments of this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the steps or units listed, but may optionally include other steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0050] It should be noted that in the description of the embodiments of this application, the words "exemplarily" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design scheme described as "exemplarily" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design schemes. Specifically, the use of the words "exemplarily" or "for example" is intended to present the relevant concepts in a specific manner.

[0051] In multi-core computing scenarios, high parallelism places significant demands on chip bandwidth. When multiple cores of a chip simultaneously run demanding tasks, the chip's bandwidth fluctuates drastically, causing rapid fluctuations in power consumption. This can lead to the chip's voltage exceeding its normal operating range, ultimately resulting in the chip malfunctioning.

[0052] For example, if a chip's normal operating range is 0.8V to 1.5V, when multiple cores of the chip are running heavy tasks simultaneously, the chip's bandwidth will change drastically, causing rapid fluctuations in the chip's power consumption. This can cause the chip voltage to exceed 1.5V or fall below 0.8V, which can lead to the chip malfunctioning or even being damaged.

[0053] Therefore, this application provides a data processing method to improve the stability of a chip, and this data processing method is applicable to chips. Figure 1 A schematic diagram of a possible, non-limiting chip 10 is shown. (e.g.) Figure 1 As shown, chip 10 includes a power monitor module 100, a throttling module 200, a processor core 300, and a storage module 400. The processor core 300 and the storage module 400 can communicate via a bus 500.

[0054] For example, chip 10 can be a system on chip (SOC).

[0055] Monitoring module 100 is used to obtain the number of the first request.

[0056] The first request is a data access request sent by processor core 300 to storage module 400. This data access request is used to read data from or write data to storage module 400.

[0057] For example, the first request may be a data access request sent by the processor core 300 to the storage module 400 via the bus 500.

[0058] In one possible implementation, the monitoring module 100 is specifically used to obtain the number of the first requests mentioned above from the interface between the storage module 400 and the bus 500.

[0059] For example, the monitoring module 100 can obtain data access requests sent by the processor core 300 to the storage module 400 from the interface between the storage module 400 and the bus 500.

[0060] It is understandable that the data access requests sent by the chip processor core to the storage module need to be transmitted through the interface between the storage module and the bus. Therefore, the number of data access requests sent by the chip processor core to the storage module can be obtained through the transmission of data through the interface between the storage module and the bus.

[0061] In another possible implementation, the monitoring module 100 is specifically used to obtain the number of the first requests mentioned above from the access controller of the storage module 400.

[0062] For example, the monitoring module 100 can obtain the data access request sent by the processor core 300 to the storage module 400 from the access controller of the storage module 400.

[0063] It is understandable that the access controller of the storage module is used to receive data access requests sent by the chip processor core to the storage module. Therefore, the number of data access requests sent by the chip processor core to the storage module can be obtained through the access controller of the storage module.

[0064] In one possible implementation, the number of the first requests is obtained by weighting the number of first requests of at least one type, including data access requests and no data access requests, with the weight of the data access requests being greater than the weight of the no data access requests.

[0065] For example, the weight of a data access request can be set to 1, and the weight of a no-data access request can be set to 0.1. If the processor core 300 sends 500 data access requests and 1500 no-data access requests to the storage module 400 through the bus 500, then the number of first requests obtained by the monitoring module 100 with weight is 500×1+1500×0.1=650.

[0066] For example, the weight of a data access request can be set to 1, and the weight of a no-data access request can be set to 0.1. If the processor core 300 sends 1500 data access requests and 500 no-data access requests to the storage module 400 through the bus 500, then the number of first requests obtained by the monitoring module 100 with weight is 1500×1+500×0.1=1550.

[0067] Understandably, different types of data access requests consume different amounts of power, so different weights can be assigned to different types. For example, data access requests require data transmission and therefore consume more power, while no-data access requests do not require data transmission and consume less power. Therefore, the weight of data access requests can be higher than that of no-data access requests.

[0068] Optionally, the aforementioned data access requests may include read requests, write requests, atomic requests, or other data access requests.

[0069] Optionally, the above-mentioned no-data access request may include invalid, MU status acquisition request, or other no-data access request.

[0070] In one possible implementation, the storage module 400 may include at least one of the following: cache, double data rate synchronous dynamic random access memory (DDR), high bandwidth memory (HBM), low power DDR (LPDDR), and graphics DDR (GDDR).

[0071] For example, in some implementations, the storage module 400 described above may include cache, DDR, and HBM.

[0072] In one possible implementation, data access requests can include read (write) requests that hit the cache and read (write) requests that miss the cache. The weight of a read (write) request that misses the cache is greater than the weight of a read (write) request that hits the cache.

[0073] For example, the weight of a read (write) request that misses the cache can be set to 5, the weight of a read (write) request that hits the cache can be set to 1, and the weight of a request with no data access is 0.1. The processor core 300 sends 1,000 read (write) requests and 1,000 requests with no data access to the storage module 400 through the bus 500. Of the 1,000 read (write) requests, 800 hit the cache and 200 miss the cache. Then the number of first requests obtained by the monitoring module 100 with weight is 200×5+800×1+1000×0.1=1900.

[0074] For example, the weight of a read (write) request that misses the cache can be set to 5, the weight of a read (write) request that hits the cache can be set to 1, and the weight of a request with no data access is 0.1. The processor core 300 sends 1000 read (write) requests and 1000 requests with no data access to the storage module 400 through the bus 500. Of the 200 read (write) requests, 200 hit the cache and 800 missed the cache. Then the number of the first requests obtained by the monitoring module 100 is 800×5+200×1+1000×0.1=4300.

[0075] Understandably, read (write) requests are sent to different storage modules for access. When a read (write) request hits the cache, data can be accessed directly from the cache, consuming less power. When a read (write) request misses the cache, data needs to be read from other storage modules (such as DDR, HBM, GDDR, or LPDDR). Compared to accessing data from the cache, accessing data from other storage modules involves a longer transmission path, increasing power consumption. Therefore, the weight of read (write) requests that miss the cache can be greater than the weight of read (write) requests that hit the cache.

[0076] The adjustment module 200 is used to adjust the data access request processing speed of at least one storage module 400 of the chip 10 according to the number of the first requests.

[0077] The solution provided in this application dynamically adjusts the data access request processing speed of the chip's memory module based on the number of data access requests sent from the chip's processor core to the memory module. This reduces the rate of change in the chip's bandwidth, preventing drastic bandwidth fluctuations that could cause rapid power consumption fluctuations, leading to voltage spikes exceeding the normal operating range and causing the chip to malfunction. This improves the chip's stability.

[0078] In one possible implementation, the adjustment module 200 is specifically used to: determine the power change rate of the chip 10 based on the number of the first requests; and adjust the data access request processing speed of at least one storage module 400 of the chip 10 based on the power change rate.

[0079] like Figure 2 As shown, the adjustment module 200 can obtain the power change slope of the chip 10 based on the number of the first requests; determine the power change rate of the chip 10 based on the power change slope of the chip 10; and adjust the data access request processing speed of at least one storage module 400 of the chip 10 based on the power change rate of the chip 10.

[0080] It is understandable that the number of data access requests sent by the chip's processor core to the memory module is positively correlated with the chip's power change rate. Therefore, the chip's power change rate can be determined by the number of data access requests sent by the chip's processor core to the memory module.

[0081] The specific implementation method of adjusting the data access request processing speed of the storage module according to the power change rate can adopt any method that can be conceived by those skilled in the art, and the embodiments of this application do not limit it.

[0082] For example, multiple power change rate intervals can be defined, each interval corresponding to a data access request processing speed. The data access request processing speed of the storage module is then adjusted to match the data access request processing speed corresponding to the power change rate interval to which the power change rate belongs.

[0083] For example, if the data access request processing speed corresponding to the power change rate interval A1 is B1, then the data access request processing speed of the storage module can be adjusted to B1 if the power change rate interval to which the power change rate belongs is A1.

[0084] For example, multiple power change rate intervals can be defined, each interval corresponding to a certain proportion. The data access request processing speed of the storage module is then adjusted to the proportion corresponding to the power change rate interval to which the power change rate belongs, multiplied by the maximum data access request processing speed of the storage module.

[0085] For example, if the power change rate interval A1 corresponds to a proportion of 70%, and the power change rate interval to which the power change rate belongs is A1, then the data access request processing speed of the storage module can be adjusted to 70% of the maximum data access request processing speed of the storage module.

[0086] For example, if the power change rate interval A2 corresponds to a proportion of 50%, and the power change rate interval to which the power change rate belongs is A2, then the data access request processing speed of the storage module can be adjusted to 50% of the maximum data access request processing speed of the storage module.

[0087] As another example, the power change rate of the chip 10 can be input into the integrator of the adjustment module 200, and the adjustment module 200 adjusts the data access request processing speed of at least one storage module 400 according to the stored value in the integrator.

[0088] In one possible implementation, the adjustment module 200 is specifically used to: determine the bandwidth change rate of the chip 10 based on the number of the first requests; and determine the power change rate based on the bandwidth change rate.

[0089] like Figure 3 As shown, the adjustment module 200 can obtain the bandwidth change slope of chip 10 based on the number of the first requests; determine the bandwidth change rate of chip 10 based on the bandwidth change slope of chip 10; and determine the power change rate of chip 10 based on the bandwidth rate of chip 10.

[0090] It is understandable that the number of data access requests sent by the chip's processor core to the memory module is positively correlated with the rate of change of the chip's bandwidth. The rate of change of the chip's bandwidth is also positively correlated with the rate of change of the chip's power consumption. Therefore, the rate of change of the chip's bandwidth can be determined by the number of data access requests sent by the chip's processor core to the memory module, and the rate of change of the chip's power consumption can be determined based on the rate of change of the chip's bandwidth.

[0091] In one possible implementation, the data access request processing speed of the target storage module can be adjusted based on the power change rate and the cache size of the target storage module. Here, the target storage module is any storage module of chip 10, and the cache size of the storage module can be negatively correlated with the adjusted data access request processing speed of the storage module.

[0092] like Figure 4 As shown, the adjustment module 200 of chip 10 can adjust the data access request processing speed of the cache of chip 10 according to the power change rate of chip 10 and the cache size of chip 10, adjust the data access request processing speed of DDR of chip 10 according to the power change rate of chip 10 and the cache size of chip 10, and adjust the data access request processing speed of HBM of chip 10 according to the power change rate of chip 10 and the cache size of chip 10.

[0093] Understandably, the larger the buffer size of a storage module, the more data access requests it can cache. If two storage modules with different buffer sizes process data access requests at the same speed, the module with the smaller buffer might be unable to cache enough requests and thus drop some. In this case, to prevent the module with the smaller buffer from dropping requests, its data access request processing speed should be increased. This would make the buffer size of the storage module negatively correlated with its adjusted data access request processing speed.

[0094] In one possible implementation, the monitoring module 100 is further configured to: obtain the number of second requests, wherein the second requests are data access requests received by the target storage module, and the target storage module is any of the storage modules of the chip.

[0095] For example, the monitoring module 100 can obtain the number of data access requests received by the cache.

[0096] For example, monitoring module 100 can detect that the number of data access requests received by the cache is 1000.

[0097] For example, the monitoring module 100 can obtain the number of data access requests received by the DDR.

[0098] For example, monitoring module 100 can obtain the number of data access requests received by DDR as 2000.

[0099] For example, the monitoring module 100 can obtain the number of data access requests received by HBM.

[0100] For example, monitoring module 100 can detect that the number of data access requests received by HBM is 10,000.

[0101] In one possible implementation, the adjustment module 200 is specifically used to: adjust the data request processing speed of the target storage module according to the number of the first request and the number of the second request.

[0102] like Figure 5 As shown, the adjustment module 200 of chip 10 can adjust the data request processing speed of the cache of chip 10 according to the number of first requests and the number of data access requests received by the cache of chip 10, adjust the data request processing speed of the DDR of chip 10 according to the number of first requests and the number of data access requests received by the DDR of chip 10, and adjust the data request processing speed of the HBM of chip 10 according to the number of first requests and the number of data access requests received by the HBM of chip 10.

[0103] It's understandable that the number of data access requests received by the various memory modules within a chip is uneven. When some memory modules receive an excessive number of data access requests, the number of data access requests sent by the chip's processor core to these memory modules will also increase. In this situation, adjusting the data request processing speed of only the memory modules receiving an excessive number of data access requests, without needing to adjust the data request processing speed of the memory modules with a normal number of data access requests, can reduce the rate of bandwidth fluctuations in the chip and prevent the chip's voltage from exceeding its normal operating range, thus preventing the chip from malfunctioning.

[0104] For example, monitoring module 100 can detect that the processor core sends 13,000 data access requests to the storage module via the bus. Of these 13,000, the cache receives 1,000, the DDR receives 2,000, and the HBM receives 10,000. It can be seen that only the HBM in the chip's storage module receives an excessive number of data access requests. In this case, only the data request processing speed of the HBM, which receives an excessive number of data access requests, needs to be adjusted. There is no need to adjust the data request processing speed of the cache and DDR within the chip, which have normal data access request volumes. This reduces the rate of bandwidth fluctuation in the chip, preventing the chip voltage from exceeding its normal operating range and causing the chip to malfunction.

[0105] like Figure 6 As shown, in one possible implementation, the processor core 300 may include processor core 1 to processor core N, and the memory 500 may include cache, DDR and HBM.

[0106] It is understandable that when the processor core 300 includes multiple processor cores (processor core 1 to processor core N), the first request mentioned above is a data access request sent by multiple processor cores to the storage module through the bus.

[0107] In one possible implementation, the chip 10 may also include an input / output (IO) interface, such as a universal serial bus (USB), a peripheral component interconnect express (PCIE), or an Ethernet interface.

[0108] The I / O interface of the aforementioned chip 10 can communicate with printers, scanners, keyboards, mice, cameras, audio devices, monitors, network devices, or other devices.

[0109] In one possible implementation, the chip 10 may also include a consistency master agent (HA) node, which is responsible for data scheduling between the processor core and DDR and consistency maintenance of the SOC (chip 10).

[0110] In multi-core computing scenarios, high parallelism places extremely high demands on data path bandwidth. When a high-parallelism task is launched, the chip bandwidth may be instantly filled, causing numerous device flip-flops and resulting in drastic power consumption changes. These drastic power consumption changes are accompanied by drastic voltage fluctuations, which may momentarily exceed the chip's normal operating range, rendering it malfunctioning. The method provided in this application monitors internal chip information to implement reverse voltage control over data transmission on the chip. Without affecting the clock frequency, it slows down bandwidth growth, thereby achieving power consumption and voltage control.

[0111] Figure 7 This application illustrates a data processing method provided by an embodiment of the present application. This method can be executed by the aforementioned chip 10, such as... Figure 3 As shown, the method includes:

[0112] S701, The monitoring module obtains the number of first requests.

[0113] The first request is a data access request sent by the processor core to the storage module.

[0114] In one possible implementation, the monitoring module can obtain the number of the first requests from the interface between the storage module and the bus.

[0115] In another possible implementation, the monitoring module can obtain the number of the first requests mentioned above from the access controller of the storage module.

[0116] In one possible implementation, the number of first requests is obtained by weighting the number of first requests of at least one type, including data access requests and no data access requests, with the weight of data access requests being greater than the weight of no data access requests.

[0117] S702, The adjustment module adjusts the data access request processing speed of at least one storage module of the chip according to the number of first requests.

[0118] In one possible implementation, the adjustment module determines the power change rate of the chip based on the number of the first requests; the adjustment module adjusts the data access request processing speed based on the power change rate.

[0119] In one possible implementation, the adjustment module determines the bandwidth change rate of the chip based on the number of the first requests; the adjustment module determines the power change rate based on the bandwidth change rate.

[0120] In one possible implementation, the monitoring module acquires the number of second requests; the adjustment module adjusts the data request processing speed of the target storage module based on the number of first requests and the number of second requests. Here, the second request is a data access request received by the target storage module, and the target storage module is any storage module of the chip.

[0121] The solution provided in this application dynamically adjusts the data access request processing speed of the chip's memory module based on the number of data access requests sent from the chip's processor core to the memory module. This reduces the rate of change in the chip's bandwidth, preventing drastic bandwidth fluctuations that could cause rapid power consumption fluctuations, leading to voltage spikes exceeding the normal operating range and causing the chip to malfunction. This improves the chip's stability.

[0122] Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Figure 8 As shown, the electronic device 800 includes a chip 801, a transceiver 802, and a communication line 803.

[0123] Electronic devices 800 can be mobile phones, tablets, desktops, laptops, handheld computers, notebook computers, personal computers (PCs), netbooks, cellular phones, personal digital assistants (PDAs), wearable devices (such as smartwatches), smart home devices (such as internet protocol television (IPTV)), in-vehicle computers, game consoles, augmented reality (AR) and virtual reality (VR) devices, smart home devices (e.g., refrigerators, televisions, air conditioners, washing machines, rice cookers, table lamps, electricity meters, etc.), smart robots, robotic arms, workshop equipment, or other electronic devices.

[0124] Chip 801 is used to execute any step of the data processing method provided in the embodiments of this application, and during the execution of any step of the data processing method provided in the embodiments of this application, transceiver 802 and communication line 803 may be called to complete the corresponding operation.

[0125] Furthermore, the electronic device 800 may also include a memory 804. The chip 801, the memory 804, and the transceiver 802 can be connected via a communication line 803.

[0126] Transceiver 802 is used to communicate with other devices or other communication networks, such as Ethernet, radio access network (RAN), wireless local area network (WLAN), etc. Transceiver 802 can be a module, circuit, transceiver, or any device capable of enabling communication.

[0127] The transceiver 802 is mainly used for sending and receiving commands and information, and can include a transmitter and a receiver to send and receive commands and information, respectively; operations other than sending and receiving commands and information are implemented by the chip.

[0128] Communication line 803 is used to transmit information between the various components included in electronic device 800.

[0129] In one design, the chip can be viewed as a logic circuit, and the transceiver as an interface circuit.

[0130] The memory 804 is used to store instructions. These instructions can be computer programs.

[0131] The memory 804 can be volatile memory or non-volatile memory, or both. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDR SDRAM), enhanced synchronous DRAM (ESDRAM), synchronous linked DRAM (SLDRAM), and direct rambus RAM (DRRAM). Memory 804 can also be a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed discs, laser discs, optical discs, digital universal discs, Blu-ray discs, etc.), magnetic disk storage media, or other magnetic storage devices. It should be noted that the memory in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0132] It should be noted that the memory 804 can exist independently of the chip 801, or it can be integrated with the chip 801. The memory 804 can be used to store instructions, program code, or some data, etc. The memory 804 can be located inside or outside the electronic device 800, without limitation. The chip 801 is used to execute the instructions stored in the memory 804 to implement the method provided in the above embodiments of this application.

[0133] In one example, chip 801 may include one or more processor cores, for example Figure 8 The processor cores are 0 and 1.

[0134] As an optional implementation, the electronic device 800 includes multiple chips, for example, besides Figure 8 In addition to chip 801, it may also include chip 807.

[0135] As an optional implementation, the electronic device 800 also includes an output device 805 and an input device 806. For example, the input device 806 is a device such as a keyboard, mouse, microphone, or joystick, and the output device 805 is a device such as a display screen or speaker.

[0136] It should be noted that the electronic device 800 can be a chip system or... Figure 8 Devices with similar structures. The chip system can be composed of chips or include chips and other discrete components. Actions, terminology, etc., involved in the various embodiments of this application can be referenced interchangeably without limitation. The message names or parameter names in the messages used for interaction between devices in the embodiments of this application are merely examples; other names can be used in specific implementations without limitation. Furthermore, Figure 8 The structural composition shown does not constitute a limitation on the electronic device 800, except... Figure 8 In addition to the components shown, the electronic device 800 may include more than Figure 8 This may indicate more or fewer components, or combinations of certain components, or different component arrangements.

[0137] The chip and transceiver described in this application can be implemented on integrated circuits (ICs), analog ICs, radio frequency integrated circuits, mixed-signal ICs, application-specific integrated circuits (ASICs), printed circuit boards (PCBs), electronic devices, etc. The chip and transceiver can also be manufactured using various IC process technologies, such as complementary metal-oxide semiconductors (CMOS), n-metal-oxide-semiconductor (NMOS), positive-channel metal-oxide semiconductors (PMOS), bipolar junction transistors (BJTs), bipolar CMOS (BiCMOS), silicon germanium (SiGe), gallium arsenide (GaAs), etc.

[0138] This application also provides a data processing apparatus, which includes at least one processor. When the at least one processor executes program code or instructions, it implements the data processing method described above.

[0139] Optionally, the device may further include at least one memory for storing the program code or instructions.

[0140] This application also provides a computer storage medium storing computer instructions. When the computer instructions are executed on a data processing device, the data processing device performs the aforementioned related method steps to implement the data processing method described above.

[0141] This application also provides a computer program product that, when run on a computer, causes the computer to perform the aforementioned steps to implement the data processing method described in the above embodiments.

[0142] This application also provides a data processing apparatus, which may specifically be a chip, integrated circuit, component, or module. Specifically, the apparatus may include a connected processor and a memory for storing instructions, or the apparatus may include at least one processor for fetching instructions from external memory. When the apparatus is running, the processor can execute the instructions to cause the chip to perform the data processing methods described in the above method embodiments.

[0143] It should be understood that in various embodiments of this application, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of this application.

[0144] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this application.

[0145] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0146] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0147] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0148] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0149] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of this application embodiment, essentially, or the parts that contribute to the prior art, or parts of the technical solutions, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0150] The above description is merely a specific implementation of the embodiments of this application, but the protection scope of the embodiments of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the embodiments of this application should be included within the protection scope of the embodiments of this application. Therefore, the protection scope of the embodiments of this application should be determined by the protection scope of the claims.

Claims

1. A data processing method applied to a chip, the chip comprising a monitoring module, an adjusting module, a processor core and a storage module, characterized in that, The method comprises the steps of: The monitoring module obtains the number of first requests, wherein the first requests are data access requests sent by the processor core to the storage module; The adjusting module adjusts the data access request processing speed of at least one storage module of the chip according to the number of first requests.

2. The method of claim 1, wherein, The monitoring module obtains the number of first requests, comprising: The monitoring module obtains the number of first requests from an interface between the storage module and a bus or an access controller of the storage module.

3. The method according to claim 1 or 2, characterized in that, The adjusting module adjusts the data access request processing speed of at least one storage module of the chip according to the number of first requests, comprising: The adjusting module determines the power change speed of the chip according to the number of first requests; The adjusting module adjusts the data access request processing speed according to the power change speed.

4. The method of claim 3, wherein, The adjusting module determines the power change speed of the chip according to the number of first requests, comprising: The adjusting module determines the bandwidth change speed of the chip according to the number of first requests; The adjusting module determines the power change speed according to the bandwidth change speed.

5. The method according to any one of claims 1 to 4, characterized in that, The method further comprises: The monitoring module obtains the number of second requests, wherein the second requests are data access requests received by a target storage module, and the target storage module is any storage module of the chip; The adjusting module adjusts the data access request processing speed of at least one storage module of the chip according to the number of first requests, comprising: The adjusting module adjusts the data request processing speed of the target storage module according to the number of first requests and the number of second requests.

6. The method according to any one of claims 1 to 5, characterized in that, The number of first requests is obtained by weighting the number of at least one type of first requests, wherein the types of first requests include data access requests and non-data access requests, and the weight of the data access requests is greater than that of the non-data access requests.

7. A chip, characterized by The method comprises a monitoring module, an adjusting module, a processor core and a storage module; The monitoring module is configured to obtain the number of first requests, wherein the first requests are data access requests sent by the processor core to the storage module; The adjusting module is configured to adjust the data access request processing speed of at least one storage module of the chip according to the number of first requests.

8. The chip of claim 7, wherein, The monitoring module is specifically configured to: Obtain the number of first requests from an interface between the storage module and a bus or an access controller of the storage module.

9. The chip according to claim 7 or 8, characterized in that The adjusting module is specifically configured to: Determine the power change speed of the chip according to the number of first requests; Adjust the data access request processing speed according to the power change speed.

10. The chip of claim 9, wherein, The adjusting module is specifically configured to: Determine the bandwidth change speed of the chip according to the number of first requests; Determine the power change speed according to the bandwidth change speed.

11. The chip according to any one of claims 7 to 10, characterized in that, The monitoring module is further configured to: Obtain the number of second requests, wherein the second requests are data access requests received by a target storage module, and the target storage module is any storage module of the chip; The adjusting module is specifically configured to: Adjust a data request processing speed of the target storage module according to the number of the first requests and the number of the second requests.

12. The chip according to any one of claims 7 to 11, characterized in that, The number of the first requests is weighted according to the number of at least one type of first requests, and the types of the first requests include data access requests and non-data access requests, and the weight of the data access requests is greater than the weight of the non-data access requests.

13. An electronic device, comprising: The electronic device comprises a chip for executing the method of any one of claims 1 to 6.

14. A computer readable storage medium for storing a computer program, characterized in that, The computer program, when running on a computer or a processor, causes the computer or the processor to implement the method of any one of claims 1 to 6.

15. A computer program product, comprising instructions therein, wherein the computer program product is characterised in that, The instructions, when running on a computer or a processor, cause the computer or the processor to implement the method of any one of claims 1 to 6.

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