Decoder, decoding method, memory system, and memory controller

Abstract

The embodiment of the invention discloses a decoder, a decoding method, a memory system, a memory controller and a computer readable storage medium. The decoder comprises a first data processing circuit and a second data processing circuit coupled to the first data processing circuit. The first data processing circuit is configured to execute current check calculation by using a current column of a check matrix and a current sub-matrix of a current flag matrix, and execute current increment check calculation on a result of the current check calculation and a previous syndrome to generate a current syndrome; the second data processing circuitry is configured to: determine an error symbol in a next data block of the codeword using one of the current syndrome or a preceding syndrome and a next column of the check matrix based on the current syndrome not satisfying a check condition; wherein the preceding syndrome is generated prior to the current syndrome.

Description

Technical Field

[0001] This disclosure relates to the field of memory, and includes, but is not limited to, a decoder, a decoding method, a memory system, a memory controller, and a computer-readable storage medium. Background Technology

[0002] Memory controllers and one or more memories can be integrated into various types of storage devices, such as solid-state drives (SSDs), universal flash storage (UFS), and embedded multi-media cards (eMMC). As memory integration and bit density increase, the bit error rate of storage devices also increases, making data reliability issues increasingly prominent.

[0003] To enhance data reliability, Error Correcting Code (ECC) technology has been used to detect and correct errors during data transmission. ECC typically uses the BCH (Blockchain Chip) algorithm and the Low Density Parity Check (LDPC) algorithm for data encoding and decoding. LDPC offers stronger error correction capabilities compared to BCH. However, LDPC is more complex, resulting in longer data decoding times. Summary of the Invention

[0004] According to a first aspect of the present disclosure, a decoder is provided, comprising: a first data processing circuit and a second data processing circuit coupled to the first data processing circuit;

[0005] The first data processing circuit is configured to: perform a current check calculation using the current column of the check matrix and the current submatrix of the current flag matrix, and perform a current incremental check calculation with the result of the current check calculation and the previous syndrome to generate a current syndrome; wherein, the check matrix includes n columns, where n is an integer greater than 1; the current flag matrix includes n submatrices, which are related to the current data block of the flipped codeword; the codeword includes n data blocks, each of which includes k code elements, where k is a positive integer; the current submatrix includes k current flag bits, each of which is used to indicate whether the corresponding code element in the current data block of the codeword has been flipped;

[0006] The second data processing circuit is configured to: based on the fact that the current syntactic does not meet the check condition, use either the current syntactic or the previous syntactic and the next column of the check matrix to determine the erroneous code element in the next data block of the codeword; wherein the previous syntactic is generated before the current syntactic.

[0007] In some embodiments, the decoder further includes a bit-flipping processing circuit coupled to the first data processing circuit and the second data processing circuit, respectively; the bit-flipping processing circuit is configured to:

[0008] Flip the erroneous code elements in the next data block of the codeword and generate the next submatrix of the current flag matrix; wherein the next submatrix includes k next flag bits, each of the next flag bits being used to indicate whether the corresponding code element in the next data block of the codeword has been flipped;

[0009] The first data processing circuit is further configured to:

[0010] The next check calculation is performed using the next column of the check matrix and the next submatrix, and the result of the next check calculation is combined with the current syndrome to perform the next incremental check calculation to generate the next syndrome.

[0011] In some embodiments, the next syndrome is the nth syndrome; the second data processing circuit is further configured to:

[0012] Based on the fact that the next syntactic does not meet the verification condition and the weight of the next syntactic is less than or equal to the first preset threshold, in each verification calculation process of the next round of iteration verification, the previous syntactic generated by the previous verification calculation and the current column of the verification matrix are used to determine the erroneous code elements of the current data block of the codeword.

[0013] In some embodiments, the next syndrome is the nth syndrome; the second data processing circuit is further configured to:

[0014] Based on the fact that the next syndrome does not meet the verification condition and the weight of the next syndrome is greater than the first preset threshold, in each verification calculation process of the next round of iteration verification, the next syndrome and the current column of the verification matrix are used to determine the erroneous code elements of the current data block of the codeword.

[0015] In some embodiments, the decoder further includes a companion weight determination circuit coupled to the first data processing circuit and the second data processing circuit respectively; the companion weight determination circuit is configured to:

[0016] Determine whether the weight of the next complication is less than or equal to the first preset threshold.

[0017] In some embodiments, the bit-flipping processing circuit is specifically configured as follows:

[0018] Based on the flipping of the erroneous code element in the next data block of the codeword, the next flag bit corresponding to the erroneous code element in the next submatrix of the current flag matrix is ​​set to the flag logic value.

[0019] In some embodiments, the decoder further includes a data output circuit coupled to the first data processing circuit, the data output circuit being configured to:

[0020] Based on the next syntactic satisfying the verification condition, the reversed codeword is output.

[0021] In some embodiments, the first data processing circuit is further configured to: perform initial verification on the codeword using the verification matrix to generate an initial syndrome;

[0022] The second data processing circuit is further configured as follows:

[0023] Based on the fact that the initial syntactic does not meet the verification condition and the weight of the initial syntactic is less than or equal to the second preset threshold, in each verification calculation process of the first round of iterative verification or in each verification calculation process of each round of iterative verification in multiple rounds of iterative verification, the erroneous code elements of the current data block of the codeword are determined using the prior syntactic generated by the prior verification calculation and the current column of the verification matrix.

[0024] In some embodiments, the first data processing circuit is further configured to: perform initial verification on the codeword using the verification matrix to generate an initial syndrome;

[0025] The second data processing circuit is further configured as follows:

[0026] Based on the fact that the initial syntactic does not meet the verification condition and the weight of the initial syntactic is greater than the second preset threshold, in each verification calculation process of the first round of iterative verification, the initial syntactic and the current column of the verification matrix are used to determine the erroneous code elements of the current data block of the codeword.

[0027] In some embodiments, the second data processing circuit is further configured to:

[0028] Based on the fact that the weight of the initial syntactic is greater than the second preset threshold and the syntactic generated at the end of the first round of iterative verification does not meet the verification condition, in each verification calculation process of each round of iterative verification after the first round of iterative verification, the syntactic generated at the end of the previous round of iterative verification and the current column of the verification matrix are used to determine the erroneous code elements of the current data block of the codeword.

[0029] In some embodiments, the decoder further includes a companion buffer circuit coupled to the first data processing circuit and the second data processing circuit, respectively, the companion buffer circuit being configured as follows:

[0030] The initial syntactic or the syntactic generated at the end of each iteration is cached.

[0031] In some embodiments, the first data processing circuit is specifically configured to:

[0032] Calculate the product of the current column of the check matrix and the current submatrix of the current flag matrix to generate the current sub-adjoint expression;

[0033] Perform an XOR operation on the previous syndrome and the current subsynonym to generate the current syndrome.

[0034] In some embodiments, the verification condition includes a syndrome of 0.

[0035] According to a second aspect of the present disclosure, a decoding method is provided, comprising:

[0036] The current check calculation is performed using the current column of the check matrix and the current submatrix of the current flag matrix; wherein the check matrix includes n columns, where n is an integer greater than 1; the current flag matrix includes n submatrices, which are associated with the current data block of the flipped codeword; the codeword includes n data blocks, each of which includes k code elements, where k is a positive integer; the current submatrix includes k current flag bits, each of which indicates whether the corresponding code element in the current data block of the codeword has been flipped;

[0037] The result of the current check calculation is combined with the previous syndrome to perform the current incremental check calculation, generating the current syndrome.

[0038] Based on the fact that the current syntactic does not meet the check condition, the erroneous code elements in the next data block of the codeword are determined using either the current syntactic or the previous syntactic and the next column of the check matrix; wherein the previous syntactic is generated before the current syntactic.

[0039] In some embodiments, the decoding method further includes:

[0040] Flip the erroneous code elements in the next data block of the codeword and generate the next submatrix of the current flag matrix; wherein the next submatrix includes k next flag bits, each of the next flag bits being used to indicate whether the corresponding code element in the next data block of the codeword has been flipped;

[0041] The next check calculation is performed using the next column of the check matrix and the next submatrix, and the result of the next check calculation is combined with the current syndrome to perform the next incremental check calculation to generate the next syndrome.

[0042] In some embodiments, the next syndrome is the nth syndrome; the decoding method further includes:

[0043] Based on the fact that the next syntactic does not meet the verification condition and the weight of the next syntactic is less than or equal to the first preset threshold, in each verification calculation process of the next round of iteration verification, the previous syntactic generated by the previous verification calculation and the current column of the verification matrix are used to determine the erroneous code elements of the current data block of the codeword.

[0044] In some embodiments, the next syndrome is the nth syndrome; the decoding method further includes:

[0045] Based on the fact that the next syndrome does not meet the verification condition and the weight of the next syndrome is greater than the first preset threshold, in each verification calculation process of the next round of iteration verification, the next syndrome and the current column of the verification matrix are used to determine the erroneous code elements of the current data block of the codeword.

[0046] In some embodiments, the decoding method further includes:

[0047] Determine whether the weight of the next complication is less than or equal to the first preset threshold.

[0048] In some embodiments, generating the next submatrix of the current flag matrix includes:

[0049] Based on the flipping of the erroneous code element in the next data block of the codeword, the next flag bit corresponding to the erroneous code element in the next submatrix of the current flag matrix is ​​set to the flag logic value.

[0050] In some embodiments, the decoding method further includes:

[0051] Based on the next syntactic satisfying the verification condition, the reversed codeword is output.

[0052] In some embodiments, the decoding method further includes:

[0053] The codeword is initially checked using the parity-check matrix to generate an initial syndrome.

[0054] Based on the fact that the initial syntactic does not meet the verification condition and the weight of the initial syntactic is less than or equal to the second preset threshold, in each verification calculation process of the first round of iterative verification or in each verification calculation process of each round of iterative verification in multiple rounds of iterative verification, the erroneous code elements of the current data block of the codeword are determined using the prior syntactic generated by the prior verification calculation and the current column of the verification matrix.

[0055] In some embodiments, the decoding method further includes:

[0056] The codeword is initially checked using the parity-check matrix to generate an initial syndrome.

[0057] Based on the fact that the initial syntactic does not meet the verification condition and the weight of the initial syntactic is greater than the second preset threshold, in each verification calculation process of the first round of iterative verification, the initial syntactic and the current column of the verification matrix are used to determine the erroneous code elements of the current data block of the codeword.

[0058] In some embodiments, the decoding method further includes:

[0059] Based on the fact that the weight of the initial syntactic is greater than the second preset threshold and the syntactic generated at the end of the first round of iterative verification does not meet the verification condition, in each verification calculation process of each round of iterative verification after the first round of iterative verification, the syntactic generated at the end of the previous round of iterative verification and the current column of the verification matrix are used to determine the erroneous code elements of the current data block of the codeword.

[0060] In some embodiments, the decoding method further includes:

[0061] The initial syntactic or the syntactic generated at the end of each iteration is cached.

[0062] In some embodiments, performing the current check calculation using the current column of the check matrix and the current submatrix of the current flag matrix includes:

[0063] Calculate the product of the current column of the check matrix and the current submatrix of the current flag matrix to generate the current sub-adjoint expression;

[0064] The step of performing the current incremental check calculation by combining the result of the current check calculation with the previous syndrome to generate the current syndrome includes:

[0065] Perform an XOR operation on the previous syndrome and the current subsynonym to generate the current syndrome.

[0066] In some embodiments, the verification condition includes a syndrome of 0.

[0067] According to a third aspect of the present disclosure, a memory system is provided, comprising:

[0068] A memory configured to output read data;

[0069] The decoder described in any embodiment of the first aspect of this disclosure is coupled to the memory; the decoder is configured to perform a decoding operation on the codewords obtained by converting the read data.

[0070] In some embodiments, the memory system further includes:

[0071] An encoder configured to receive write data and perform an encoding operation on the write data;

[0072] The memory is also configured to receive the encoded write data.

[0073] According to a fourth aspect of the present disclosure, a memory controller is provided, comprising:

[0074] A memory interface configured to receive and read data;

[0075] The decoder described in any embodiment of the first aspect of this disclosure is coupled to the memory interface; the decoder is configured to perform a decoding operation on the codewords obtained by converting the read data.

[0076] According to a fifth aspect of the present disclosure, a computer-readable storage medium is provided, the computer-readable storage medium storing instructions that are executed by a processor to implement the decoding method as described in any embodiment of the second aspect of the present disclosure.

[0077] In this embodiment, the current check calculation can be performed using the current column of the parity check matrix and the current submatrix of the current flag matrix. The result of the current check calculation is then combined with the previous syndrome to perform the current incremental check calculation, generating the current syndrome. If the current syndrome satisfies the unchecked condition, the erroneous code elements in the next data block of the codeword are determined using either the current syndrome or a previous syndrome, along with the next column of the check matrix. Thus, the latest updated syndrome can be used to calculate the error count during decoding, reducing decoding time. This is especially beneficial when the codeword error rate is low, accelerating LDPC decoding. Attached Figure Description

[0078] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0079] Figure 1 This is a schematic diagram of an electronic device according to an embodiment of the present disclosure.

[0080] Figure 2a This is a schematic diagram of a memory card according to an embodiment of the present disclosure.

[0081] Figure 2b This is a schematic diagram of a solid-state drive according to an embodiment of the present disclosure.

[0082] Figure 3 This is a schematic block diagram of a three-dimensional NAND memory according to an embodiment of the present disclosure.

[0083] Figure 4 This is a schematic cross-sectional view of a memory according to an embodiment of the present disclosure.

[0084] Figure 5 This is a schematic diagram of a memory including a memory cell array and peripheral circuitry according to an embodiment of the present disclosure.

[0085] Figure 6 This is a schematic diagram of an LDPC iterative verification process according to an embodiment of the present disclosure.

[0086] Figure 7 This is a schematic block diagram of a decoder according to an embodiment of the present disclosure.

[0087] Figure 8 This is a schematic block diagram of another decoder shown according to an embodiment of the present disclosure.

[0088] Figure 9 This is a schematic diagram illustrating another LDPC iterative decoding process according to an embodiment of the present disclosure.

[0089] Figure 10 This is a flowchart illustrating a decoding method according to an embodiment of the present disclosure.

[0090] Figure 11 This is a schematic block diagram of a memory system according to an embodiment of the present disclosure. Detailed Implementation

[0091] To facilitate understanding of this disclosure, exemplary embodiments of the disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the disclosure are shown in the drawings, it should be understood that the disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the disclosure and to fully convey the scope of the disclosure to those skilled in the art.

[0092] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In some embodiments, to avoid confusion with this disclosure, certain technical features well-known in the art are not described; that is, not all features of the actual embodiments, nor well-known functions and structures, may be described herein.

[0093] Generally, terms can be understood at least in part from their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "described" can also be understood to convey either a singular or a plural usage, depending at least in part on the context. Additionally, the use of "based on" can be understood to not necessarily convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, also depending at least in part on the context.

[0094] Unless otherwise defined, the terminology used herein is intended only to describe particular embodiments and is not intended to limit the scope of this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0095] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0096] Figure 1This is a schematic diagram illustrating an electronic device according to an embodiment of the present disclosure. The electronic device 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having a memory device therein. See also... Figure 1 As shown, the electronic device 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memories 104 and a memory controller 106. The host 108 may be a processor of the electronic device (e.g., a central processing unit (CPU)) or a system-on-chip (SoC) (e.g., an application processor (AP)). The host 108 may be configured to send data to or receive data from the memory 104.

[0097] According to some embodiments, memory controller 106 is coupled to memory 104 and host 108 and is configured to control memory 104. Memory controller 106 can manage data stored in memory 104 and communicate with host 108. In some embodiments, memory controller 106 is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, memory controller 106 is designed to operate in high duty cycle environments, such as SSDs or eMMC, and SSDs or eMMC are used as data storage in mobile devices such as smartphones, tablets, laptops, and enterprise storage arrays.

[0098] The memory controller 106 can be configured to control the operation of the memory 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions regarding data stored or to be stored in the memory 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes regarding data read from or written to the memory 104. The memory controller 106 can also perform any other suitable functions, such as formatting the memory 104. The memory controller 106 can communicate with external devices (e.g., according to specific communication protocols) Figure 1 The memory controller 106 communicates with the host device 108. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Development Equipment (IDE), FireWire, etc.

[0099] The memory controller 106 and one or more memories 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., UFS package or eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products. Figure 2aIn one example shown, the memory controller 106 and a single memory 104 can be integrated into the memory card 202. The memory card 202 can include a PC card (Personal Computer Memory Card), CF card, Smart Media (SM) card, memory stick, Multimedia Card (MMC, RS-MMC (Reduced-Size MMC), MMCmicro), SD card (SD, miniSD, microSD, SDHC (Reduced-Size MMC)), UFS, etc. The memory card 202 may also include a connection between the memory card 202 and a host (e.g., Figure 1 The host 108) is coupled to the memory card connector 204. In such a... Figure 2b In another example shown, the memory controller 106 and multiple memories 104 can be integrated into the SSD 206. The SSD 206 may also include components for connecting the SSD 206 to a host computer (e.g., Figure 1 The SSD connector 208 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0100] Figure 3 This is a schematic block diagram illustrating a three-dimensional NAND memory according to an embodiment of the present disclosure. The memory 300 may be... Figure 1 An example of memory 104 is provided. Memory 300 may include a memory cell array 301 and peripheral circuitry 302 coupled to the memory cell array 301. The memory cell array 301 is illustrated as a three-dimensional NAND memory cell array, wherein the memory cells 306 are provided in the form of an array of NAND memory strings 308, each NAND memory string 308 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0101] In some implementations, each memory cell 306 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some implementations, each memory cell 306 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four memory states. For example, an MLC may store two bits per cell, three bits per cell (also known as a triple-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)). Each MLC can be programmed to take a range of possible nominal memory values. In one example, if each MLC stores two bits of data, the MLC can be programmed to write one of three possible nominal memory values ​​into the cell, while a fourth nominal memory value in addition to these three nominal memory values ​​can be used to indicate an erase state.

[0102] like Figure 3 As shown, each NAND memory string 308 may include a bottom select gate (BSG) 310 at its source end and a top select gate (TSG) 312 at its drain end. The BSG 310 and TSG 312 may be configured to activate the selected NAND memory string 308 during read and program operations. In some embodiments, the sources of the NAND memory strings 308 in the same memory block 304 are coupled via a common source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG 312 of each NAND memory string 308 is coupled to a corresponding bit line (BL) 316, from which data can be read or written via an output bus (not shown). In some implementations, each NAND memory string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having TSG 312) or a deselection voltage (e.g., 0V) to the corresponding TSG 312 via one or more TSG lines 313 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having BSG 310) or a deselection voltage (e.g., 0V) to the corresponding BSG 310 via one or more BSG lines 315.

[0103] like Figure 3 As shown, NAND memory strings 308 can be organized into multiple memory blocks 304, each of which may have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is the basic data unit for an erase operation, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase memory cells 306 in a selected memory block, an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)) biased and coupled to the source line of unselected memory blocks on the same plane as the selected memory block can be used. It should be understood that in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 306 of adjacent NAND memory strings 308 can be coupled via word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some implementations, memory cells 306 coupled to the same word line 318 in memory block 304 may constitute at least one physical page 320. Each word line 318 may include a plurality of control gates (gate electrodes) at each memory cell 306 of the corresponding physical page 320 and gate lines coupling the control gates.

[0104] Figure 4 This is a schematic cross-sectional view of a memory according to an embodiment of the present disclosure. (Refer to...) Figure 4 As shown, the NAND memory string 308 may include a stacked structure 410, which includes multiple gate layers 411 and multiple insulating layers 412 stacked alternately in sequence, and a memory string 308 perpendicularly penetrating the gate layers 411 and insulating layers 412. The gate layers 411 and insulating layers 412 may be stacked alternately, with adjacent gate layers 411 separated by an insulating layer 412. The number of pairs of gate layers 411 and insulating layers 412 in the stacked structure 410 determines the number of memory cells included in the memory cell array 301.

[0105] The constituent materials of the gate layer 411 may include conductive materials. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, such as a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stack 410 may extend laterally as an upper select gate line, the gate layer 411 at the bottom of the stack 410 may extend laterally as a lower select gate line, and the gate layer 411 extending laterally between the upper and lower select gate lines may serve as a word line layer.

[0106] In some embodiments, the stacked structure 410 may be disposed on the substrate 401. The substrate 401 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0107] In some embodiments, the NAND memory string 308 includes a channel structure extending vertically through the stacked structure 410. In some embodiments, the channel structure includes channel vias filled with one or more semiconductor materials (e.g., as a semiconductor channel) and one or more dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polysilicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trap / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0108] Return to reference Figure 3The peripheral circuitry 302 can be coupled to the memory cell array 301 via bit line 316, word line 318, source line 314, BSG line 315, and TSG line 313. The peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry to facilitate the operation of the memory cell array 301 by applying voltage and / or current signals to each target memory cell 306 via bit line 316, word line 318, source line 314, BSG line 315, and TSG line 313, and by sensing voltage and / or current signals from each target memory cell 306. The peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 5 Some exemplary peripheral circuitry is shown. Peripheral circuitry 302 includes a page buffer / sensor amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, control logic 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, additional peripheral circuitry may be included. Figure 5 Additional peripheral circuitry not shown.

[0109] Page buffer / sensor amplifier 504 can be configured to read data from and program (write) data to memory cell array 301 according to control signals from control logic 512. In one example, page buffer / sensor amplifier 504 can store a page of programming data (write data) to be programmed into a physical page of memory cell array 301. In another example, page buffer / sensor amplifier 504 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 306 coupled to selected word line 318. In yet another example, page buffer / sensor amplifier 504 can also sense a low-power signal from bit line 316 representing a data bit stored in memory cell 306 and amplify a small voltage swing to a recognizable logic level during read operations. Column decoder / bit line driver 506 can be configured to be controlled by control logic 512 and select one or more NAND memory strings 308 by applying a bit line voltage generated from voltage generator 510.

[0110] The row decoder / word line driver 508 can be configured to be controlled by control logic 512 and to select / deselect memory blocks 304 of the memory cell array 301 and to select / deselect word lines 318 of memory blocks 304. The row decoder / word line driver 508 can also be configured to drive word lines 318 using word line voltages generated from voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive BSG lines 315 and TSG lines 313. As described in detail below, the row decoder / word line driver 508 is configured to perform programming operations on memory cells 306 coupled to one or more selected word lines 318. The voltage generator 510 can be configured to be controlled by control logic 512 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, channel boost voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 301.

[0111] Control logic 512 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 514 can be coupled to control logic 512 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 516 can be coupled to control logic 512 and acts as a control buffer to buffer control commands received from the host (not shown) and relay them to control logic 512, as well as to buffer status information received from control logic 512 and relay it to the host. Interface 516 can also be coupled to column decoder / bitline driver 506 via data bus 518 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory cell array 301.

[0112] 3D NAND flash memory, as a storage medium that is more stable and faster than traditional disk storage, has been widely used in various storage devices. To meet the ever-increasing storage demands, the process size of 3D NAND flash memory is continuously shrinking, and the types of storage cells are evolving from SLC to MLC, TLC, and QLC. This has led to an increase in the bit error rate. The traditional Bit-Chip (BCH) algorithm is no longer sufficient to guarantee data reliability. The LDPC algorithm, as an error correction method with error correction capabilities approaching the Shannon limit, is gradually replacing BCH and becoming the next-generation error correction coding method.

[0113] LDPC decoding determines whether to flip the corresponding codeword by multiplying the syndrome by the parity-check matrix (PCM). Specifically, the PCM is used to perform an initial check on the codeword, generating an initial syndrome. If the initial syndrome is 0, decoding is successful and the decoding process ends; otherwise, the initial syndrome is multiplied by the PCM to obtain the error count, and the corresponding codeword is flipped based on the error count to obtain the flipped codeword. At least one round of iterative verification is performed on the flipped codeword until the generated syndrome is 0 or the maximum number of iterations is reached. A codeword typically consists of multiple data blocks, each containing multiple bits. During iterative verification, the initial syndrome or the syndrome from the previous iteration can be multiplied by a column of the PCM to obtain the error count for a corresponding data block. Based on the error count, the erroneous codewords for a corresponding data block can be determined. The following will combine... Figure 6 An illustrative example is provided.

[0114] Figure 6 This is a schematic flowchart illustrating an LDPC iterative verification process according to an embodiment of this disclosure. (Refer to...) Figure 6 As shown, if the previous iteration's adjoint (or initial adjoint) is not 0, then the previous iteration's adjoint (or initial adjoint) is multiplied by the first column of the parity check matrix to obtain the error count of the first data block. Based on the error count of the first data block, the error symbol 0 in the first data block is determined. The error symbol 0 is flipped and the first submatrix 0 of the current round's flag matrix is ​​generated. The product S of the first column of the parity check matrix and the first submatrix 0 is calculated. U0 and S U0 The first syndrome _0 is obtained by summing it with the syndrome from the previous iteration (or the initial syndrome).

[0115] If the first syndrome _0 is 0, decoding is successful, and decoding exits; otherwise, the error count of the second data block is obtained by multiplying the syndrome of the previous iteration (or the initial syndrome) with the second column of the parity check matrix. Based on the error count of the second data block, the error symbol 1 in the second data block is determined. The error symbol 1 is flipped and the second sub-matrix 1 of the current round's flag matrix is ​​generated. The product S of the second column of the parity check matrix and the second sub-matrix 1 is calculated. U1 and S U1 The second syndrome, _1, is obtained by summing it with the first syndrome _0.

[0116] If the second appendage _1 is 0, decoding is successful and the decoding process exits; otherwise, incremental verification similar to that of the first appendage _0 and the second appendage _1 continues until the obtained incremental appendage is 0 or the current iteration ends. It is understandable that if the initial appendage is not 0, the current iteration verification can be the first iteration verification.

[0117] It should be noted that each submatrix in this round of the flag matrix is ​​used to indicate whether the code elements of the corresponding data block have been flipped. For example, the first submatrix 0 is used to indicate whether the code elements of the first data block of the codeword have been flipped, ..., and the nth submatrix n-1 is used to indicate whether the code elements of the nth data block of the codeword have been flipped.

[0118] Figure 6 The paper demonstrates that after each incremental calculation, checking whether the corresponding syndrome is 0 to determine whether decoding is successful can reduce the complexity of LDPC decoding to some extent and allow for timely exit from decoding, especially in scenarios requiring the decoding of large amounts of data. However, this scheme uses the syndrome generated after the previous iteration (e.g., the initial syndrome or the syndrome of the previous iteration) to calculate the number of errors in each data block of the codeword during each incremental calculation, resulting in a long decoding time, especially when the codeword error rate is low.

[0119] Based on one or more of the above-mentioned technical problems, this disclosure provides a decoder.

[0120] Figure 7 This is a schematic block diagram of a decoder according to an embodiment of the present disclosure. (Refer to...) Figure 7 As shown, the decoder 600 includes: a first data processing circuit 604 and a second data processing circuit 609 coupled to the first data processing circuit 604;

[0121] The first data processing circuit 604 is configured to: perform a current check calculation using the current column of the check matrix and the current submatrix of the current flag matrix, and perform a current incremental check calculation with the result of the current check calculation and the previous syndrome to generate a current syndrome; wherein, the check matrix includes n columns, where n is an integer greater than 1; the current flag matrix includes n submatrices, which are related to the current data block of the flipped codeword; the codeword includes n data blocks, each data block including k bits, where k is a positive integer; the current submatrix includes k current flag bits, each current flag bit being used to indicate whether the corresponding bit in the current data block of the codeword has been flipped;

[0122] The second data processing circuit 609 is configured to: determine the erroneous code element in the next data block of the codeword using either the current syndrome or the previous syndrome and the next column of the parity check matrix, based on the fact that the current syndrome does not meet the check condition; wherein the previous syndrome is generated before the current syndrome.

[0123] In this embodiment of the disclosure, the codewords include, but are not limited to, quasi-cyclic (QC) LDPC codes. The parity check matrix of a quasi-cyclic (QC) LDPC code may include multiple sub-parity check matrices, each of which may be a zero matrix or a cyclic permutation matrix. The cyclic permutation matrix may be an identity matrix or a sub-parity check matrix obtained by performing a predetermined number of cyclic shifts on the identity matrix.

[0124] For example, a codeword may consist of 512 bits, which can be divided into four data blocks, each containing 128 bits. Accordingly, the current submatrix may include 128 current flag bits, each used to indicate whether a bit in the current data block has been flipped. For instance, if a bit in the current data block is flipped, the corresponding current flag bit in the current submatrix can be set to logic "1"; if other bits in the current data block are not flipped, the corresponding current flag bits in the current submatrix can be set to logic "0". Here, an example of n being 4 and k being 128 is used, but this does not constitute a limitation on the scope of this disclosure.

[0125] In this embodiment of the disclosure, if the synastry is updated in real time, the second data processing circuit 609 can use the next column of the current synastry and parity check matrix to determine the erroneous code elements in the next data block of the codeword; if there is a delay in the update of the synastry, the second data processing circuit 609 can use the next column of the earlier synastry and parity check matrix to determine the erroneous code elements in the next data block of the codeword. That is, the second data processing circuit 609 can determine the erroneous code elements in the next data block based on the next column of the latest updated synastry and parity check matrix. Here, in the case of a delay in the synastry update, the earlier synastry can be a synastry generated before the current synastry.

[0126] It is understood that the current iteration of the check includes at least one incremental check calculation. In this embodiment, the current check calculation can be performed using the current column of the check matrix and the current submatrix of the current flag matrix, and the result of the current check calculation can be combined with the previous syndrome to perform the current incremental check calculation, generating the current syndrome. If the current syndrome satisfies the unchecked condition, the erroneous code elements in the next data block of the codeword are determined using either the current syndrome or the previous syndrome and the next column of the check matrix. In this way, the error count can be calculated using the latest updated syndrome during the decoding process, reducing the decoding time. Especially when the codeword error rate is low, LDPC decoding can be accelerated.

[0127] In some embodiments, the decoder 600 further includes a bit-flipping processing circuit 610 coupled to the first data processing circuit 604 and the second data processing circuit 609 respectively; the bit-flipping processing circuit 610 is configured to: flip the erroneous code elements in the next data block of the codeword and generate the next submatrix of the current flag matrix; wherein the next submatrix includes k next flag bits, each next flag bit being used to indicate whether the corresponding code element in the next data block of the codeword has been flipped; the first data processing circuit 604 is further configured to: perform the next check calculation using the next column of the check matrix and the next submatrix, and perform the next incremental check calculation with the result of the next check calculation and the current syndrome to generate the next syndrome.

[0128] In this embodiment of the disclosure, when an erroneous code element is determined in the next data block of the codeword, the bit-flipping processing circuit 610 can flip the erroneous code element in the next data block of the codeword and generate the next sub-matrix of the current flag matrix. For example, the next data block includes 128 code elements, and the next sub-matrix may include 128 next flag bits. If a code element in the next data block is flipped, the next flag bit in the next sub-matrix corresponding to the flipped code element can be set to the logic value "1"; if other code elements in the next data block are not flipped, the current flag bits corresponding to the unflipped code elements in the next sub-matrix can all be set to the logic value "0".

[0129] In this embodiment, the first data processing circuit 604 can use the next column and the next submatrix of the parity check matrix to perform the next parity check calculation, and then perform the next incremental parity check calculation with the current syndrome to generate the next syndrome. If the next syndrome satisfies the parity check condition, it indicates successful decoding, and the flipped codeword is output. In this way, decoding can be exited in a timely manner, reducing decoding time and avoiding unnecessary erroneous flips.

[0130] In some embodiments, the decoder 600 further includes a data output circuit 614 coupled to the first data processing circuit 604, the data output circuit 614 being configured to output a flipped codeword based on the next syntactic satisfying the check condition.

[0131] It should be noted that the current incremental check calculation and the next incremental check calculation are different stages of the current iterative check. If the syndrome generated in the initial iterative check does not meet the check condition, the codeword can be flipped at least once, and at least one round of iterative check can be performed accordingly. Each time a codeword is flipped and enters iterative check, a flag matrix associated with the flipped codeword can be generated, and at least one column of the check matrix and at least one submatrix of the flag matrix are used to perform at least one incremental check calculation to obtain at least one incremental syndrome. When the incremental syndrome meets the check condition, decoding is exited promptly, which not only reduces decoding time but also avoids erroneous flips caused by redundant incremental check calculations. For example, in related schemes, each iteration requires n incremental check calculations to determine whether decoding is successful, which is time-consuming and may also involve redundant incremental check calculations.

[0132] In this embodiment of the disclosure, the verification condition includes the adjoint being 0. The verification condition is met if the calculated initial adjoint or incremental adjoint is 0; otherwise, the verification condition is not met if the calculated initial adjoint or incremental adjoint is not 0. The following will use the verification condition of the adjoint being equal to 0 as an example for illustrative explanation. The initial adjoint will be described in detail in the following embodiments and will not be repeated here.

[0133] In some embodiments, the next syndrome is the nth syndrome; the second data processing circuit 609 is further configured to: based on the fact that the next syndrome does not meet the verification condition and the weight of the next syndrome is less than or equal to a first preset threshold, in each verification calculation process of the next round of iterative verification, use the previous syndrome generated by the previous verification calculation and the current column of the verification matrix to determine the erroneous code element of the current data block of the codeword.

[0134] The weight of the syndrome (also known as the Hamming weight) is used to characterize the number of codewords in a codeword that do not satisfy the parity check equation. Typically, the weight of the syndrome gradually decreases as iterative decoding progresses. If the weight of the syndrome generated at the end of the current iteration is less than or equal to a certain preset threshold, it indicates that the bit error rate of the current codeword is low, and the latest updated syndrome can be used to calculate the error count in each parity check calculation in the next iteration. If the weight of the syndrome generated at the end of the current iteration is greater than a certain preset threshold, it indicates that the bit error rate of the current codeword is high, and the error count generated by the syndrome at the end of the current iteration will be used to calculate the error count in each parity check calculation in the next iteration.

[0135] In this embodiment of the disclosure, if the next syndrome is the nth syndrome and the nth syndrome is not 0, it indicates that the current iteration verification has failed, and the codeword needs to be flipped again, and the next round of iteration verification is performed on the flipped codeword. At the beginning of the next round of iteration verification, based on whether the weight of the nth syndrome is less than or equal to a first preset threshold, it can be selected whether to use the previously generated syndrome and the current column of the verification matrix to calculate the error count in each verification calculation process of the next round of iteration verification.

[0136] In this embodiment, if the weight of the nth syndrome is less than or equal to a first preset threshold, in each check calculation process of the next round of iteration check, the previously generated syndrome and the current column of the check matrix are used to determine the erroneous code elements of the current data block of the codeword. Thus, when the codeword error rate is low, using the latest updated syndrome to calculate the error count of the next data block each time can accelerate LDPC decoding and greatly reduce decoding time. Here, the previously generated syndrome can be the latest updated syndrome, and the first preset threshold can be reasonably set according to the actual situation; this embodiment does not have any special limitations on this.

[0137] For example, if the weight of the nth syndrome is less than or equal to a first preset threshold, the second data processing circuit 609 can use the nth syndrome and the first column of the parity check matrix to determine the erroneous code elements in the first data block of the codeword; the bit flipping processing circuit 610 can flip the erroneous code elements in the first data block of the codeword and generate the first sub-matrix of the next flag matrix; the first data processing circuit 604 can use the first column of the parity check matrix and the first sub-matrix of the next flag matrix to perform a first parity check calculation, and perform a first incremental parity check calculation with the result of the first parity check calculation and the nth syndrome to generate the first syndrome of the next round of iterative parity check. If the first syndrome of the next round of iterative parity check is 0, decoding is exited; otherwise, the second data processing circuit 609 uses either the first syndrome of the next round of iterative parity check or the nth syndrome of the current iterative parity check and the second column of the parity check matrix to determine the erroneous code elements in the second data block of the codeword. That is, in each parity check calculation process of the next round of iterative parity check, the erroneous code elements of the current data block of the codeword are determined using the prior syndrome generated by the prior parity check calculation and the current column of the parity check matrix. Here, if the first syntactic of the next iteration is updated in real time, the error count in the second data block of the codeword is calculated using the first syntactic of the next iteration.

[0138] In some embodiments, the next syndrome is the nth syndrome; the second data processing circuit 609 is further configured to: based on the fact that the next syndrome does not meet the verification condition and the weight of the next syndrome is greater than the first preset threshold, in each verification calculation process of the next round of iterative verification, use the next syndrome and the current column of the verification matrix to determine the erroneous code element of the current data block of the codeword.

[0139] In this embodiment, if the weight of the nth syndrome is greater than a first preset threshold, in each check calculation process of the next round of iteration, the next syndrome and the current column of the check matrix are used to determine the erroneous code elements of the current data block of the codeword. Thus, when the codeword error rate is high, the error count of each data block is calculated using the syndrome updated in the previous round of iteration, reducing decoding time while avoiding code element error flipping.

[0140] For example, if the weight of the nth syndrome is greater than a first preset threshold, the second data processing circuit 609 can use the nth syndrome and the first column of the parity check matrix to determine the erroneous code elements in the first data block of the codeword; the bit flipping processing circuit 610 can flip the erroneous code elements in the first data block of the codeword and generate the first sub-matrix of the next flag matrix; the first data processing circuit 604 can use the first column of the parity check matrix and the first sub-matrix of the next flag matrix to perform a first parity check calculation, and perform a first incremental parity check calculation with the result of the first parity check calculation and the nth syndrome to generate the first syndrome of the next round of iterative parity check. If the first syndrome of the next round of iterative parity check is 0, decoding is exited; otherwise, the second data processing circuit 609 continues to use the nth syndrome and the second column of the parity check matrix to determine the erroneous code elements in the second data block of the codeword. That is, in each parity check calculation process of the next round of iterative parity check, the nth syndrome of the current iterative parity check and the current column of the parity check matrix are used to determine the erroneous code elements in the current data block of the codeword.

[0141] In some embodiments, the decoder 600 further includes an accompanying weight determination circuit 608 coupled to the first data processing circuit 604 and the second data processing circuit 609 respectively; the accompanying weight determination circuit 608 is configured to determine whether the weight of the next accompanying element is less than or equal to a first preset threshold.

[0142] In this embodiment of the disclosure, the syntactic weight judgment circuit 608 can generate a first judgment result based on the weight of the next syntactic being less than or equal to a first preset threshold; the second data processing circuit 609, based on the first judgment result, uses the previous syntactic generated by the previous check calculation and the current column of the check matrix to determine the erroneous code elements of the current data block of the codeword in each check calculation process of the next round of iterative check; the syntactic weight judgment circuit 608 can also generate a second judgment result based on the weight of the next syntactic being greater than the first preset threshold; the second data processing circuit 609, based on the second judgment result, uses the next syntactic and the current column of the check matrix to determine the erroneous code elements of the current data block of the codeword in each check calculation process of the next round of iterative check.

[0143] It is understandable that the accompanying weight judgment circuit 608 can determine whether the weight generated at the end of the initial verification or each round of iterative verification is less than or equal to a certain preset threshold after the initial verification or each round of iterative verification, and generate the corresponding judgment result; the second data processing circuit 609, based on the judgment result generated by the accompanying weight judgment circuit 608, executes different error count calculation strategies in each verification calculation process of the next round of iterative verification.

[0144] In some embodiments, the bit-flipping processing circuit 610 is specifically configured to: flip the erroneous code in the next data block of the codeword and set the next flag bit of the corresponding erroneous code in the next submatrix of the current flag matrix to the flag logic value.

[0145] For example, the next data block includes 128 bits, and the next submatrix may include 128 next flag bits. If a bit in the next data block is flipped, the bit flipping processing circuit 610 sets the corresponding next flag bit in the next submatrix to a logic value "1" according to the position of the flipped erroneous bit. The logic value "1" is used to indicate that the erroneous bit has been flipped.

[0146] It should be noted that the number of submatrices in the current flag matrix can be the same as the number of data blocks in the codeword, that is, the current flag matrix includes n submatrices, and the number of flag bits in each submatric can be the same as the number of code elements in each data block, that is, each submatric includes k flag bits. In some embodiments, when the codeword is not flipped, each submatric of the current flag matrix can be an all-zero matrix, and the flag bits in the current flag matrix corresponding to the unflipped code elements are logical values ​​"0".

[0147] In this embodiment of the disclosure, the next submatrix is ​​generated by setting the next flag bit of the corresponding erroneous code element in the next submatrix of the current flag matrix to the flag logic value, and the next column of the check matrix and the next submatrix are used for check calculation. Since the number of bits of the flipped code element in the codeword is usually much smaller than the number of bits of the unflipped code element, the number of logic values ​​"1" in each submatrix of the flag matrix is ​​small and the number of logic values ​​"0" is large. This simplifies the complexity of iterative check calculation and speeds up the decoding process, thereby reducing the decoding time.

[0148] In some embodiments, the first data processing circuit 604 is further configured to: perform an initial check on the codeword using a check matrix to generate an initial syntactic; the second data processing circuit 609 is further configured to: determine the erroneous code elements of the current data block of the codeword using the prior syntactic generated by the prior check calculation and the current column of the check matrix, based on the fact that the initial syntactic does not meet the check condition and the weight of the initial syntactic is less than or equal to a second preset threshold, in each check calculation process of the first round of iterative check or in each check calculation process of each round of iterative check in multiple rounds of iterative check.

[0149] In this embodiment of the disclosure, conventional calculation methods can be used during the initial verification process. For example, S = HC T S represents the initial syndrome, H represents the parity-check matrix, and C represents the codeword. If the initial syndrome S is 0, decoding is successful. If the initial syndrome S is not 0, at least one round of iterative parity-checking is performed. It is understandable that the initial parity-checking generates an initial syndrome, while the iterative parity-checking generates at least one incremental syndrome. The calculation method for the initial syndrome is different from the calculation method for the at least one incremental syndrome generated in each round of iterative parity-checking.

[0150] In this embodiment, if the initial collocation is not 0, it indicates that the initial verification failed, the codeword needs to be flipped, and at least one round of iterative verification is performed on the flipped codeword. At the beginning of the iterative verification, based on whether the weight of the initial collocation is less than or equal to a second preset threshold, it can be selected whether to use the prior collocation generated by the prior verification calculation and the current column of the verification matrix to calculate the error count in each verification calculation process of the first round of iterative verification or in each verification calculation process of each round of iterative verification in multiple rounds of iterative verification. Here, the second preset threshold can be reasonably set according to the actual situation. The second preset threshold and the first preset threshold can be the same or different, and this embodiment does not have any special restrictions on this.

[0151] For example, if the weight of the initial syndrome is less than or equal to a second preset threshold, the second data processing circuit 609 can use the latest updated syndrome to calculate the error count of the next data block during each check calculation in the first round of iterative check. It is understood that if the weight of the initial syndrome is less than or equal to the second preset threshold, it indicates that the bit error rate of the original codeword to be decoded is low. Therefore, using the latest updated syndrome to calculate the error count of the next data block can accelerate LDPC decoding and significantly reduce decoding time.

[0152] For example, if the weight of the initial syndrome is less than or equal to a second preset threshold, the second data processing circuit 609 can use the latest updated syndrome to calculate the error count of the next data block in each verification calculation process of each round of multi-round iterative verification. That is, during the execution of multi-round iterative verification, the syndrome determination circuit 613 only needs to determine whether the weight of the initial syndrome is less than or equal to the second preset threshold, and there is no need to determine the weight of the syndrome again after other iterative verifications are completed. In this way, the number of syndrome determinations can be reduced, LDPC decoding can be accelerated, decoding time can be further shortened, and the overhead of software and / or hardware resources can be reduced.

[0153] In some embodiments, the second data processing circuit 609 is further configured to: based on the initial syntactic not meeting the verification condition and the weight of the initial syntactic being greater than a second preset threshold, in each verification calculation process of the first round of iterative verification, use the initial syntactic and the current column of the verification matrix to determine the erroneous code elements of the current data block of the codeword.

[0154] In this embodiment of the disclosure, if the weight of the initial synastry is greater than a second preset threshold, the second data processing circuit 609 can use the initial synastry and the current column of the parity check matrix in each check calculation process of the first round of iterative verification to determine the erroneous code elements of the current data block of the codeword. It is understood that an initial synastry weight greater than the second preset threshold indicates a high bit error rate in the original codeword to be decoded. Therefore, when the bit error rate of the codeword is high, each check calculation process of the first round of iterative verification uses the initial synastry to calculate the error count of each data block, reducing decoding time while avoiding code element error flipping.

[0155] In some embodiments, the second data processing circuit 609 is further configured to: based on the weight of the initial syntactic being greater than a second preset threshold and the syntactic generated at the end of the first round of iterative verification not meeting the verification conditions, in each verification calculation process of each round of iterative verification after the first round of iterative verification, use the syntactic generated at the end of the previous round of iterative verification and the current column of the verification matrix to determine the erroneous code elements of the current data block of the codeword.

[0156] In this embodiment of the disclosure, if the syndrome generated at the end of the first round of iterative verification does not meet the verification conditions, it indicates that the first round of iterative verification has failed. Since the weight of the initial syndrome is greater than the second preset threshold, this indicates that the bit error rate of the original codeword to be decoded is high. The second data processing circuit 609 can use the syndrome generated at the end of the previous round of iterative verification and the current column of the verification matrix in each verification calculation process of each round of iterative verification after the first round of iterative verification to determine the erroneous code elements of the current data block of the codeword. For example, in each verification calculation process of the second round of iterative verification, the syndrome generated at the end of the first round of iterative verification and the current column of the verification matrix are used to determine the erroneous code elements of the current data block of the codeword.

[0157] In some embodiments, the decoder 600 further includes an adjoint cache circuit 606 coupled to the first data processing circuit 604 and the second data processing circuit 609 respectively. The adjoint cache circuit 606 is configured to cache the initial adjoint or the adjoint generated at the end of each round of iteration verification.

[0158] In some embodiments, the first data processing circuit 604 is specifically configured to: calculate the product of the current column of the parity check matrix and the current submatrix of the current flag matrix to generate the current sub-compound; and perform an XOR operation on the previous compound and the current sub-compound to generate the current compound.

[0159] In this embodiment of the disclosure, the first data processing circuit 604 may include a matrix multiplier and a matrix adder; wherein, the matrix multiplier is used to calculate the product of the current column of the check matrix and the current submatrix of the current flag matrix, which is implemented by AND operation and XOR operation; the matrix adder is used to calculate the sum of the previous adjoint and the current subadjoint, which is implemented by XOR operation.

[0160] In some embodiments, the decoder 600 further includes a codeword buffer circuit 602 coupled to the first data processing circuit 604. The codeword buffer circuit 602 is configured to buffer codewords or inverted codewords. For example, when the original codeword to be decoded is input into the decoder 600, the codeword buffer circuit 602 can buffer the input original codeword to be decoded (i.e., the codeword). As another example, if the initial verification fails or one round of iterative verification fails, the codeword buffer circuit 602 can buffer the iteratively decoded codeword (i.e., the inverted codeword). The first data processing circuit 604 can obtain the input original codeword to be decoded from the codeword buffer circuit 602 to perform the initial verification, or obtain the iteratively decoded codeword from the codeword buffer circuit 602 to perform the next round of iterative verification.

[0161] In some embodiments, the decoder 600 further includes a symptom determination circuit 613 coupled to the first data processing circuit 604 and the data output circuit 614 respectively. The symptom determination circuit 613 is configured to determine whether the current symptom satisfies the verification condition.

[0162] In this embodiment of the present disclosure, the syndrome determination circuit 613 can receive the current syndrome generated by the first data processing circuit 604. If the current syndrome is 0, the syndrome determination circuit 613 generates a third determination result, and the data output circuit 614 outputs the reversed codeword cached in the codeword buffer circuit 602 based on the third determination result; if the current syndrome is not 0, the syndrome determination circuit 613 generates a fourth determination result, and the first data processing circuit 604 performs the next check calculation and the next incremental check calculation based on the fourth determination result. Figure 7 In this circuit, a logic value of "0" represents the third judgment result, and a logic value of "1" represents the fourth judgment result. Of course, the syndrome judgment circuit 613 can also be used to determine whether the initial syndrome or other incremental syndromes (e.g., the next syndrome) are 0.

[0163] It should be noted that if the initial syndrome is not 0 or the nth syndrome in each round of iteration is not 0, the bit flipping processing circuit 610 flips the codeword based on the fourth judgment result.

[0164] Figure 8 This is a schematic block diagram of another decoder according to embodiments of this disclosure. Besides Figure 7 In addition to the codeword buffer circuit 602, first data processing circuit 604, syndication buffer circuit 606, syndication weight judgment circuit 608, second data processing circuit 609, bit flipping processing circuit 610, syndication judgment circuit 613, and data output circuit 614 shown, the decoder 600 may also include a first selection circuit 601, a second selection circuit 603, a matrix buffer circuit 605, a third selection circuit 607, a flipped codeword generation circuit 611, and a delay circuit 612. Of course, the decoder 600 may also include other circuits known in the art.

[0165] The first selection circuit 601 is configured to output either the original codeword to be decoded or the iteratively decoded codeword based on a first control signal. For example, if the first control signal indicates that the current check is an initial check, the first selection circuit 601 outputs the original codeword to be decoded; if the first control signal indicates that the current check is an iterative check, the first selection circuit 601 outputs the iteratively decoded codeword. It is understood that the iteratively decoded codeword is different from the original codeword to be decoded; the iteratively decoded codeword can be a flipped codeword that is flipped at least once based on the original codeword to be decoded. The first selection circuit 601 includes, but is not limited to, a multiplexer.

[0166] The codeword buffer circuit 602 is coupled to the first selection circuit 601. The codeword buffer circuit 602 is configured to buffer the original codeword to be decoded or the iteratively decoded codeword, that is, the codeword output by the first selection circuit 601 can be buffered in the codeword buffer circuit 602.

[0167] The second selection circuit 603 is coupled to the codeword buffer circuit 602 and the bit-flipping processing circuit 610, respectively. The second selection circuit 603 is configured to output either the original codeword to be decoded or the current sub-matrix of the current flag matrix based on the second control signal. For example, if the second control signal indicates that the current check is the initial check, the second selection circuit 603 outputs the original codeword to be decoded; if the second control signal indicates that the current check is the current iteration check, the second selection circuit 603 outputs the current sub-matrix of the current flag matrix. The second selection circuit 603 includes, but is not limited to, a multiplexer. The following description uses the example of the second selection circuit 603 outputting the current sub-matrix of the current flag matrix as an example.

[0168] The first data processing circuit 604 is coupled to the second selection circuit 603 and the matrix cache circuit 605. The first data processing circuit 604 is configured to: perform a current check calculation using the current column of the check matrix and the current submatrix of the current flag matrix; and perform a current incremental check calculation by combining the result of the current check calculation with the previous syndrome to generate the current syndrome. The check matrix can be cached in the matrix cache circuit 605. Each time an incremental check calculation needs to be performed, the first data processing circuit 604 can obtain a column of the check matrix from the matrix cache circuit 605. Of course, during the initial check process, the first data processing circuit 604 can obtain the entire check matrix from the matrix cache circuit 605, that is, obtain n columns of the check matrix.

[0169] The syndrome determination circuit 613 is coupled to the first data processing circuit 604, the data output circuit 614, and the bit flipping processing circuit 610. The syndrome determination circuit 613 is configured to determine whether the current syndrome is 0. If the current syndrome is 0, the data output circuit 614 outputs the iterative decoding codeword cached in the codeword buffer circuit 602, i.e., exits decoding; otherwise, the first data processing circuit 604 performs the next check calculation and the next incremental check calculation to generate the next syndrome. This process continues until the obtained incremental syndrome is 0 or the current iteration ends.

[0170] The syndication cache circuit 606 is coupled to the first data processing circuit 604. The syndication cache circuit 606 is configured to cache the initial syndication or the syndication generated at the end of each iteration verification, that is, the nth syndication generated at the end of each iteration verification.

[0171] The syndic weight determination circuit 608 is coupled to the first data processing circuit 604. The syndic weight determination circuit 608 is configured to determine whether the weight of the initial syndic is less than or equal to a second preset threshold. Of course, when the codeword error rate is high, the syndic weight determination circuit 608 is also configured to determine whether the weight of the syndic generated at the end of each iteration is less than or equal to a first preset threshold. Here, the first preset threshold and the second preset threshold can be reasonably set according to actual conditions. The first preset threshold and the second preset threshold can be the same or different, and this embodiment does not have any special limitations in this regard.

[0172] The third selection circuit 607 is coupled to the first data processing circuit 604, the accompaniment buffer circuit 606, and the accompaniment weight judgment circuit 608. The third selection circuit 607 is configured to output the accompaniment generated by the first data processing circuit 604 or the accompaniment buffer circuit 606 based on the judgment result generated by the accompaniment weight judgment circuit 608. For example, if the weight of the accompaniment generated at the end of the previous iteration is less than or equal to a first preset threshold, the third selection circuit 607 outputs the accompaniment generated by the first data processing circuit 604 in real time during the current iteration verification process; if the weight of the accompaniment generated at the end of the previous iteration is greater than the first preset threshold, the third selection circuit 607 always outputs the accompaniment buffer circuit 606 during the current iteration verification process. The third selection circuit 607 includes, but is not limited to, a multiplexer.

[0173] The second data processing circuit 609 is coupled to the third selection circuit 607 and the matrix buffer circuit 605 respectively. The second data processing circuit 609 is configured to use the next column of the syndrome and parity check matrix output by the third selection circuit 607 to determine the erroneous code elements in the next data block of the codeword.

[0174] The bit-flipping processing circuit 610 is coupled to the second data processing circuit 609. The bit-flipping processing circuit 610 is configured to: flip the erroneous code elements in the next data block of the codeword and generate the next submatrix of the current flag matrix. Of course, the bit-flipping processing circuit 610 is also configured to: flip the erroneous code elements in the first data block of the codeword based on the initial syntactic not satisfying the check condition and generate the first submatrix of the first flag matrix.

[0175] The flip codeword generation circuit 611 is coupled to the codeword buffer circuit 602 and the bit-flipping processing circuit 610, respectively. The flip codeword generation circuit 611 is configured to generate the next iteration decoded codeword based on the flipped erroneous codeword and the codeword buffered in the codeword buffer circuit 602. In one example, the flip codeword generation circuit 611 includes, but is not limited to, an XOR logic gate circuit.

[0176] The delay circuit 612 is coupled to the flip codeword generation circuit 611 and the first selection circuit 601, respectively. The delay circuit 612 is configured to delay the next iteration of the decoded codeword by a preset time. It should be noted that the calculation time of the first data processing circuit 604 and the synergistic judgment circuit 613 is relatively long. If the next iteration of the decoded codeword is immediately input into the first selection circuit 601, it will cause excess data to be written back to the codeword buffer circuit 602, which may lead to undesirable decoding errors. Therefore, by delaying the next iteration of the decoded codeword by a preset time, data write-back can be avoided. Here, the preset time can be reasonably set according to the calculation delay of the data processing circuit, and this disclosure does not have any special limitations in this regard.

[0177] Figure 9 This is a schematic diagram of another LDPC iterative decoding process according to an embodiment of this disclosure. The following example uses the case where the weight of the previous iteration's adjoint is less than or equal to a first preset threshold (or the weight of the initial adjoint is less than or equal to a second preset threshold), and combines... Figure 9 The process of performing one iteration of the decoder provided in the embodiments of this disclosure will be described by way of example.

[0178] In one iteration, using the previous iteration's syndrome (or initial syndrome) and the first column of the parity check matrix, the error symbol 0 in the first data block is determined; the error symbol 0 is flipped and the first submatrix 0 of the current flag matrix is ​​generated; the first parity check is performed using the first column of the parity check matrix and the first submatrix 0 of the current flag matrix to generate the first subsynonym S. U0 And the first sub-compound S U0 Perform the first incremental verification calculation with the previous iteration's syndrome (or the initial syndrome) to generate the first syndrome _0; determine whether the first syndrome _0 is 0; if the first syndrome _0 is 0, then decoding is successful and exit decoding.

[0179] If the first syndrome _0 is not zero, use one of the previous iteration syndrome (or the initial syndrome) and the first syndrome _0, along with the second column of the parity check matrix, to determine the error symbol 1 in the second data block; flip the error symbol 1 and generate the second submatrix 1 of the current flag matrix; use the second column of the parity check matrix and the second submatrix 1 of the current flag matrix to perform the second parity check calculation, generating the second subsynthesis S. U1 And the second sub-associative S U1The second incremental check is calculated using the first syndrome_0 to generate the second syndrome_1. The second syndrome_1 is then checked for 0. If the second syndrome_1 is 0, decoding is successful, and the decoding process exits. This process continues until the resulting incremental syndrome is 0 (e.g., the (i+1)th syndrome), or until the nth syndrome is still not 0 at the end of the current iteration. Then, the codeword is flipped, and the next iteration begins. Here, if the first syndrome_0 is updated in real time, the first syndrome_0 and the second column of the check matrix are used to determine the erroneous codeword 1 in the second data block.

[0180] It should be noted that, Figure 9 In this context, x represents the delay period, where x is an integer greater than or equal to 1. When x equals 1, it means that there is no delay in updating the syndrome, and the previous syndrome (i.e., syndrome i-1) can be used to calculate the error count of the current data block, thereby determining the error symbols of the current data block. When x is greater than 1, it means that there is a delay in updating the syndrome, and the syndrome generated before the previous syndrome can be used to calculate the error count of the current data block, thereby determining the error symbols of the current data block.

[0181] Based on the decoder described above, this disclosure provides a decoding method. Figure 10 This is a flowchart illustrating a decoding method according to an embodiment of the present disclosure. (Refer to...) Figure 10 As shown, the decoding method includes:

[0182] S701: Perform current check calculation using the current column of the check matrix and the current submatrix of the current flag matrix; wherein, the check matrix includes n columns, where n is an integer greater than 1; the current flag matrix includes n submatrices, which are associated with the current data block of the flipped codeword; the codeword includes n data blocks, each data block including k code elements, where k is a positive integer; the current submatrix includes k current flag bits, each current flag bit indicating whether the corresponding code element in the current data block of the codeword has been flipped;

[0183] S702: Perform the current incremental check calculation by combining the result of the current check calculation with the previous syndrome, and generate the current syndrome;

[0184] S703: Based on the fact that the current syntactic does not meet the check condition, use either the current syntactic or the previous syntactic and the next column of the check matrix to determine the erroneous code element in the next data block of the codeword; wherein, the previous syntactic is generated before the current syntactic.

[0185] In some embodiments, the above decoding method further includes: flipping the erroneous code elements in the next data block of the codeword and generating the next submatrix of the current flag matrix; wherein the next submatrix includes k next flag bits, each next flag bit being used to indicate whether the corresponding code element in the next data block of the codeword has been flipped; performing the next check calculation using the next column of the check matrix and the next submatrix, and performing the next incremental check calculation with the result of the next check calculation and the current syndrome to generate the next syndrome.

[0186] In some embodiments, the next synesthetic is the nth synesthetic; the above decoding method further includes: based on the fact that the next synesthetic does not meet the verification condition and the weight of the next synesthetic is less than or equal to a first preset threshold, in each verification calculation process of the next round of iterative verification, using the previous synesthetic generated by the previous verification calculation and the current column of the verification matrix, to determine the erroneous code elements of the current data block of the codeword.

[0187] In some embodiments, the next syndrome is the nth syndrome; the above decoding method further includes: based on the fact that the next syndrome does not meet the verification condition and the weight of the next syndrome is greater than a first preset threshold, in each verification calculation process of the next round of iterative verification, the next syndrome and the current column of the verification matrix are used to determine the erroneous code elements of the current data block of the codeword.

[0188] In some embodiments, the above decoding method further includes: determining whether the weight of the next complication is less than or equal to a first preset threshold.

[0189] In some embodiments, generating the next submatrix of the current flag matrix includes: flipping the erroneous code in the next data block of the codeword and setting the next flag bit of the corresponding erroneous code in the next submatrix of the current flag matrix to a flag logic value.

[0190] In some embodiments, the above decoding method further includes: outputting a reversed codeword based on the next syntactic satisfying the check condition.

[0191] In some embodiments, the above decoding method further includes: performing an initial check on the codeword using a check matrix to generate an initial syntactic; based on the initial syntactic not satisfying the check condition and the weight of the initial syntactic being less than or equal to a second preset threshold, in each check calculation process of the first round of iterative check or in each check calculation process of each round of iterative check in multiple rounds of iterative check, using the prior syntactic generated by the prior check calculation and the current column of the check matrix to determine the erroneous code elements of the current data block of the codeword.

[0192] In some embodiments, the above decoding method further includes: performing an initial check on the codeword using the check matrix to generate an initial syntactic; based on the initial syntactic not meeting the check conditions and the weight of the initial syntactic being greater than a second preset threshold, in each check calculation process of the first round of iterative check, the initial syntactic and the current column of the check matrix are used to determine the erroneous code elements of the current data block of the codeword.

[0193] In some embodiments, the above decoding method further includes: based on the fact that the weight of the initial syntactic is greater than a second preset threshold and the syntactic generated at the end of the first round of iterative verification does not meet the verification conditions, in each verification calculation process of each round of iterative verification after the first round of iterative verification, the syntactic generated at the end of the previous round of iterative verification and the current column of the verification matrix are used to determine the erroneous code elements of the current data block of the codeword.

[0194] In some embodiments, the above decoding method further includes: caching the initial comma or the comma generated at the end of each round of iteration verification.

[0195] In some embodiments, S701 includes: calculating the product of the current column of the parity check matrix and the current submatrix of the current flag matrix to generate the current sub-compound; S702 includes: performing an XOR operation on the previous compound and the current sub-compound to generate the current compound.

[0196] In some embodiments, the verification condition includes a syndrome of 0.

[0197] In this embodiment, the decoding method can be executed by the decoder in any of the foregoing embodiments, and the decoding method can also achieve the technical effects that the decoder in the foregoing embodiments can achieve, which will not be repeated here. Regarding the decoding methods in the above embodiments, the specific implementation methods of each step have been described in detail in the relevant decoder embodiments, and will not be elaborated upon here.

[0198] Based on the decoder described above, this disclosure also provides a memory system. The memory system includes a memory and a decoder coupled to the memory. The memory is configured to output read data; the decoder is configured to perform a decoding operation on the codewords obtained by converting the read data.

[0199] In some embodiments, the memory system further includes: an encoder configured to: receive write data and perform encoding operations on the write data; the memory is also configured to: receive the encoded write data.

[0200] Based on the decoder described above, this disclosure also provides a memory controller, including:

[0201] The memory interface is configured to receive and read data.

[0202] The decoder is coupled to the memory interface; the decoder is configured to perform a decoding operation on the codewords obtained by converting the read data.

[0203] Figure 11 This is a schematic block diagram of a memory system according to an embodiment of the present disclosure. The following will be combined with… Figure 11 The memory system and memory controller provided in the embodiments of this disclosure will be described by way of example.

[0204] Reference Figure 11 As shown, the memory system 800 includes a memory controller 810 and a memory 820. The memory controller 810 controls the memory 820 to perform read and write operations. Here, the memory controller 810 and the memory 820 can be coupled in any suitable manner. The memory controller 810 includes a processor (CPU) 813, a cache 815, an error correction circuit 814, a host I / F 811, and a memory I / F 812. In this embodiment, the memory 820 can be a non-volatile semiconductor memory for storing data, such as a NAND flash memory. The memory system 800 is connected to a host. The host I / F 811 outputs commands received from the host, valid data (write data), etc., to the internal bus 816, and sends valid data read from the memory 820 (read data), responses from the processor 813, etc., back to the host.

[0205] The processor 813 can instruct the memory I / F 812 to write valid data, parity data, and parity matrix to the memory 820 according to commands from the host. In addition, the control unit can instruct the memory I / F 812 to read valid data, parity data, and parity matrix from the memory according to commands from the host.

[0206] The error correction circuit 814 here includes an encoder 817 and the decoder 600 described above. The encoder 817 encodes the written valid data of a predetermined size to generate parity check data (e.g., low-density parity check code LDPC) and a corresponding parity check matrix. The parity check data and the corresponding parity check matrix generated by the encoder 817 can be stored in a memory. The decoder 600 uses the parity check data and the corresponding parity check matrix to decode. The decoder 600 here includes a decoder, and the parity check code and the corresponding parity check matrix during decoding can be obtained from the memory.

[0207] Based on the decoder described above, this disclosure also provides a computer-readable storage medium storing instructions that are executed by a processor to implement the decoding method of any of the above embodiments.

[0208] Here, implementing all or part of the decoding methods in the above embodiments can be accomplished by instructing relevant hardware through instructions. These instructions can be stored in a computer-readable storage medium, and when executed, they can include the processes of the embodiments of the methods described above. The storage medium can be a magnetic random access memory (FRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic surface memory, an optical disc or a compact disc read-only memory (CD-ROM), etc.; the storage medium can also include combinations of the above types of memory.

[0209] The features disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.

[0210] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0211] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0212] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0213] The above description is merely an embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A decoder, characterized by The decoder comprises a first data processing circuit and a second data processing circuit coupled to the first data processing circuit; The first data processing circuit is configured to perform a current check calculation using a current column of a check matrix and a current sub-matrix of a current flag matrix, perform a current incremental check calculation using a result of the current check calculation and a previous syndrome, and generate a current syndrome; wherein the check matrix comprises n columns, n being an integer greater than 1; the current flag matrix comprises n sub-matrices, the current sub-matrix being related to a current data block of a flipped codeword; the codeword comprises n data blocks, each of the data blocks comprising k symbols, k being a positive integer; the current sub-matrix comprises k current flag bits, each of the current flag bits being used to indicate whether a corresponding symbol in the current data block of the codeword is flipped or not; The second data processing circuit is configured to determine an error symbol in a next data block of the codeword based on the current syndrome not satisfying a check condition, using one of the current syndrome or a previous syndrome and a next column of the check matrix; wherein the previous syndrome is generated before the current syndrome.

2. The decoder of claim 1, wherein, The decoder further comprises a bit flipping processing circuit coupled to the first data processing circuit and the second data processing circuit respectively; the bit flipping processing circuit is configured to: flip the error symbol in the next data block of the codeword, and generate a next sub-matrix of the current flag matrix; wherein the next sub-matrix comprises k next flag bits, each of the next flag bits being used to indicate whether a corresponding symbol in the next data block of the codeword is flipped or not; The first data processing circuit is further configured to: perform a next check calculation using the next column of the check matrix and the next sub-matrix, perform a next incremental check calculation using a result of the next check calculation and the current syndrome, and generate a next syndrome.

3. The decoder of claim 2, wherein, The next syndrome is an nth syndrome; the second data processing circuit is further configured to: based on the next syndrome not satisfying the check condition and a weight of the next syndrome being less than or equal to a first preset threshold, determine the error symbol in the current data block of the codeword using a previous syndrome generated in a previous check calculation and a current column of the check matrix in each check calculation process of a next round of iterative check.

4. The decoder of claim 2, wherein, The next syndrome is an nth syndrome; the second data processing circuit is further configured to: based on the next syndrome not satisfying the check condition and the weight of the next syndrome being greater than the first preset threshold, determine the error symbol in the current data block of the codeword using the next syndrome and the current column of the check matrix in each check calculation process of the next round of iterative check.

5. The decoder according to claim 3 or 4, characterized in that, The decoder further comprises a syndrome weight judgment circuit coupled to the first data processing circuit and the second data processing circuit respectively; the syndrome weight judgment circuit is configured to: judge whether the weight of the next syndrome is less than or equal to the first preset threshold.

6. The decoder of claim 2, wherein, The bit flipping processing circuit is specifically configured to: flip, based on an error symbol in a next data block of the codeword, a next flag bit corresponding to the error symbol in a next sub-matrix of the current flag matrix to a flag logic value.

7. The decoder of claim 2, wherein, The decoder further includes a data output circuit coupled to the first data processing circuit, and the data output circuit is configured to: output the flipped codeword based on the next syndrome satisfying the check condition.

8. The decoder of claim 1, wherein, The first data processing circuit is further configured to perform initial check on the codeword using the check matrix to generate an initial syndrome. The second data processing circuit is further configured to: determine, based on the initial syndrome not satisfying the check condition and a weight of the initial syndrome being less than or equal to a second preset threshold, an error symbol of a current data block of the codeword using a previous syndrome generated in a previous check calculation and a current column of the check matrix in each check calculation process of a first round of iterative check or in each check calculation process of each round of iterative check after the first round of iterative check.

9. The decoder of claim 1, wherein, The first data processing circuit is further configured to perform initial check on the codeword using the check matrix to generate an initial syndrome; and the second data processing circuit is further configured to: determine, based on the initial syndrome not satisfying the check condition and a weight of the initial syndrome being greater than a second preset threshold, an error symbol of a current data block of the codeword using the initial syndrome and a current column of the check matrix in each check calculation process of a first round of iterative check.

10. The decoder of claim 9, wherein, The second data processing circuit is further configured to: determine, based on the weight of the initial syndrome being greater than the second preset threshold and a syndrome generated at the end of the first round of iterative check not satisfying the check condition, an error symbol of a current data block of the codeword using a syndrome generated at the end of a previous round of iterative check and a current column of the check matrix in each check calculation process of each round of iterative check after the first round of iterative check.

11. The decoder according to claim 8 or 10, characterized in that, The decoder further includes a syndrome buffer circuit coupled to the first data processing circuit and the second data processing circuit respectively, and the syndrome buffer circuit is configured to: buffer the initial syndrome or the syndrome generated at the end of each round of iterative check.

12. The decoder of claim 1, wherein, The first data processing circuit is specifically configured to: calculate a product of the current column of the check matrix and a current sub-matrix of the current flag matrix to generate a current sub-syndrome; perform exclusive or operation on the previous syndrome and the current sub-syndrome to generate the current syndrome.

13. The decoder of claim 1, wherein, The check condition includes that the syndrome is 0.

14. A decoding method, comprising: The method includes: performing a current check calculation using a current column of a check matrix and a current sub-matrix of a current syndrome matrix; wherein the check matrix comprises n columns, n being an integer greater than 1; the current syndrome matrix comprises n sub-matrices, the current sub-matrix being associated with a current data block of a flipped codeword; the codeword comprises n data blocks, each of the data blocks comprising k symbols, k being a positive integer; the current sub-matrix comprises k current flag bits, each of the current flag bits being used to indicate whether a corresponding symbol in the current data block of the codeword is flipped; performing a current incremental check calculation on a result of the current check calculation and a previous check syndrome, to generate a current check syndrome; based on the current check syndrome not satisfying a check condition, determining an error symbol in a next data block of the codeword using one of the current check syndrome or a previous check syndrome and a next column of the check matrix, wherein the previous check syndrome is generated before the current check syndrome.

15. The decoding method of claim 14, wherein, The decoding method further comprises: flipping the error symbol in the next data block of the codeword, and generating a next sub-matrix of the current syndrome matrix; wherein the next sub-matrix comprises k next flag bits, each of the next flag bits being used to indicate whether a corresponding symbol in the next data block of the codeword is flipped; performing a next check calculation using the next column of the check matrix and the next sub-matrix, and performing a next incremental check calculation on a result of the next check calculation and the current check syndrome, to generate a next check syndrome.

16. The decoding method of claim 15, wherein, The next check syndrome is an nth check syndrome; the decoding method further comprises: based on the next check syndrome not satisfying the check condition and a weight of the next check syndrome being less than or equal to a first preset threshold, in each check calculation process of a next round of iterative check, determining an error symbol in the current data block of the codeword using a previous check syndrome generated in a previous check calculation and a current column of the check matrix.

17. The decoding method of claim 15, wherein, The next check syndrome is an nth check syndrome; the decoding method further comprises: based on the next check syndrome not satisfying the check condition and the weight of the next check syndrome being greater than the first preset threshold, in each check calculation process of the next round of iterative check, determining an error symbol in the current data block of the codeword using the next check syndrome and the current column of the check matrix.

18. The decoding method of claim 16 or 17, wherein, The decoding method further comprises: determining whether the weight of the next check syndrome is less than or equal to the first preset threshold.

19. The decoding method of claim 15, wherein, The generating the next sub-matrix of the current syndrome matrix comprises: based on the error symbol in the next data block of the codeword being flipped, setting a next flag bit corresponding to the error symbol in the next sub-matrix of the current syndrome matrix to a flag logic value.

20. The decoding method of claim 15, wherein, The decoding method further comprises: based on the next check syndrome satisfying the check condition, outputting the flipped codeword.

21. The decoding method of claim 14, wherein, The decoding method further comprises: performing an initial check on the codeword using the check matrix, to generate an initial check syndrome; based on the initial syndrome not satisfying the check condition and the weight of the initial syndrome being less than or equal to a second preset threshold, in each check calculation process of the first round of iterative checking or in each check calculation process of each round of iterative checking of the multiple rounds of iterative checking, a previous syndrome generated by a previous check calculation and a current column of the check matrix are used to determine an error symbol of a current data block of the codeword.

22. The decoding method of claim 14, wherein, The decoding method further includes: performing initial checking on the codeword using the check matrix to generate an initial syndrome; based on the initial syndrome not satisfying the check condition and the weight of the initial syndrome being greater than the second preset threshold, in each check calculation process of the first round of iterative checking, the initial syndrome and a current column of the check matrix are used to determine an error symbol of a current data block of the codeword.

23. The decoding method of claim 22, wherein, The decoding method further includes: based on the weight of the initial syndrome being greater than the second preset threshold and a syndrome generated at the end of the first round of iterative checking not satisfying the check condition, in each check calculation process of each round of iterative checking after the first round of iterative checking, a syndrome generated at the end of a previous round of iterative checking and a current column of the check matrix are used to determine an error symbol of a current data block of the codeword.

24. The decoding method of claim 20 or 23, wherein, The decoding method further includes: caching the initial syndrome or the syndrome generated at the end of each round of iterative checking.

25. The decoding method of claim 14, wherein, The performing of the current check calculation using the current column of the check matrix and the current sub-matrix of the current flag matrix includes: calculating a product of the current column of the check matrix and the current sub-matrix of the current flag matrix to generate a current sub-syndrome; The performing of the current incremental check calculation on the result of the current check calculation and the previous syndrome to generate a current syndrome includes: performing an exclusive OR operation on the previous syndrome and the current sub-syndrome to generate the current syndrome.

26. The decoding method of claim 14, wherein, The check condition includes that the syndrome is 0.

27. A memory system, comprising: includes: a memory configured to output read data; The decoder of any one of claims 1 to 13, wherein the decoder is coupled to the memory; The decoder is configured to perform a decoding operation on a codeword converted from the read data.

28. A memory controller, comprising: includes: a memory interface configured to receive read data; The decoder of any one of claims 1 to 13, wherein the decoder is coupled to the memory interface; The decoder is configured to perform a decoding operation on a codeword converted from the read data.

29. A computer-readable storage medium, characterized in that, The computer readable storage medium has stored thereon instructions which, when executed by a processor, implement the decoding method of any one of claims 14 to 26.

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