Embedded real-time reliable information interface design method for manned carrier rocket

Abstract

The invention discloses an embedded real-time reliable information interface design method for a manned carrier rocket, and the method comprises the steps: designing a data transmission link among TTE Soc, PCIe and CPU through employing a double-layer annular buffer and time stamp cooperation mechanism; determining a timestamp-based multi-stage CRC (Cyclic Redundancy Check) framework, and establishing a binding relationship between a layered CRC check code and a global logic time reference through the multi-stage CRC framework; and a deterministic data flow path is constructed between the PCIe bus and the time-triggered network, so that data transmission across heterogeneous domains is realized. According to the invention, a set of uniform, efficient and high-speed communication interface framework can be constructed among a plurality of key subsystems such as rocket flight control, remote measurement, fault diagnosis and disposal and the like, and support for complex rocket embedded software is realized.

Description

Technical Field

[0001] This invention relates to a design method for an embedded real-time reliable information interface for manned launch vehicles, belonging to the field of equipment software design technology. Background Technology

[0002] With the development of new-generation manned launch vehicles, the requirements for the real-time performance, determinism, and reliability of communication and interaction between multiple subsystems, such as flight control systems, telemetry systems, and fault diagnosis systems, are continuously increasing. Especially in manned missions, data exchange between systems not only needs to meet microsecond-level latency constraints but also requires fault-tolerant mechanisms and redundancy guarantees to ensure accurate transmission and processing of mission data in complex flight environments. Traditional bus communication technologies (such as 1553B) are insufficient to meet the demands of current rocket missions for high-speed, real-time, and concurrent multi-channel data transmission due to limitations in bandwidth and the limited number of communication nodes. Meanwhile, new communication technologies, such as TTE (Time-Triggered Ethernet), are gradually being introduced into aerospace system design to replace traditional protocols.

[0003] In manned rocket systems, data transmission between different functional units is relatively complex, involving multiple processes such as sensor data transmission, control command issuance, status monitoring and feedback, fault diagnosis, and redundancy switching. The latency and reliability of data transmission directly impact mission success rates. Therefore, an interface design method is needed to construct a scheduling mechanism with deterministic latency and a reliable transmission mechanism with redundancy handling between the application layer and the communication layer.

[0004] Current interface design methods suffer from several shortcomings, including a lack of clarity regarding timestamp alignment and data consistency management, inability to access TTE network data, unclear system data processing links, CPU scheduling, buffer structure design, and transmission reliability mechanisms. There is an urgent need for an embedded software information interface design scheme that offers high reliability, low latency, and strong robustness, capable of meeting the requirements for accurate data transmission across high bandwidth and multiple nodes in complex flight environments. This will support the safe, stable, and efficient execution of next-generation manned launch vehicles' flight missions. Summary of the Invention

[0005] The purpose of this invention is to overcome the aforementioned shortcomings and provide a design method for an embedded real-time reliable information interface for manned launch vehicles. This method solves the technical problems of insufficient communication nodes, low communication bandwidth, insufficient data reliability, and inconsistent TTE data in existing embedded information interfaces used in next-generation manned launch vehicle applications. This invention can construct a unified, efficient, and high-speed communication interface framework among multiple key subsystems such as rocket flight control, telemetry, and fault diagnosis and handling, enabling support for complex rocket embedded software.

[0006] To achieve the above-mentioned objectives, the present invention provides the following technical solution:

[0007] An embedded real-time reliable information interface design method for manned launch vehicles includes:

[0008] A dual-layer ring buffer and time stamping collaborative mechanism is adopted to design the data transmission link between TTE SoC, PCIe and CPU; the data transmission link is used to provide the original data input with timestamps for multi-level CRC check and to provide the physical channel foundation for the PCIe bus;

[0009] A multi-level CRC check architecture based on timestamps is established; based on the timestamp markers provided by the data transmission link, a binding relationship between the hierarchical CRC check code and the global logical time base is established through the multi-level CRC check architecture; when the CRC check fails, fault tolerance processing is performed and the deterministic data path of the corresponding time window is frozen.

[0010] A deterministic data flow path is constructed between the PCIe bus and the time-triggered network. By inheriting the buffer structure of the data transmission link and integrating the verification results of CRC check, data transmission across heterogeneous domains is achieved.

[0011] Furthermore, the data transfer links between the TTE SoC, PCIe, and CPU include:

[0012] The TTE Soc-side software interface captures control frames, telemetry frames, and other data frames sent from various rocket subsystems within a predetermined window at the arrival of each scheduling cycle, and immediately timestamps each frame.

[0013] All frames are written to a first-level circular buffer located inside the TTE Soc;

[0014] When the number of valid frames in the primary ring buffer reaches a preset threshold or the timeout protection is reached according to the preset timeliness, the TTE SoC side software interface initiates a PCIe transaction through hardware DMA to write the entire slot of valid frames in batches into the secondary ring buffer in the application-side CPU shared memory.

[0015] The application-side CPU software polls the secondary buffer according to the application layer business requirements. When it finds that the slot has been written with data, the application-side CPU software uses DCACHE to ensure that the data read is the latest DMA written data. At the same time, it checks whether the timestamp falls within the time window allowed by the current scheduling cycle. If the verification is successful and the timing meets the requirements, the application-side CPU software immediately unpacks the frame content and writes it to the application layer software.

[0016] Furthermore, the first-level circular buffer adopts a fixed slot length and an auto-incrementing pointer method to support multi-way concurrent writes without locking, thus avoiding bus blockage caused by sudden network traffic.

[0017] The size of the secondary buffer slots corresponds one-to-one with that of the primary buffer, and additionally stores the frame verification results and a copy of the received timestamp for subsequent integrity and timing verification.

[0018] Furthermore, when the TTE SoC-side software interface initiates PCIe transactions via hardware DMA and writes the entire slot of valid frames in batches to the secondary circular buffer in the application-side CPU shared memory, the entire PCIe transfer process uses the control-side BAR register to update the number of bytes transferred in real time, ensuring that the write progress can still be accurately reported under high bandwidth and avoiding buffer overflow.

[0019] Furthermore, in the data transmission link, a backpressure-preemption strategy is employed to prevent rate imbalance between the sending and receiving ends in the two-level buffer. The backpressure-preemption strategy includes:

[0020] The TTE SoC-side software continuously monitors the remaining slots in the L1 buffer through an internal state machine. When the remaining space is below a threshold, it sends a high-water mark interrupt to the CPU side via a PCIe MSI interrupt. The CPU-side software immediately increases the current scheduling priority, preempts low-priority tasks, and ensures that critical control frames are processed and the slots are released before the start of the next TTE cycle. When the CPU-side processing speed is too fast while PCIe is still transmitting, the TTE SoC-side software raises a custom receive signal to postpone the injection of new frames and prevent the L2 buffer write pointer from catching up with the read pointer, which could lead to out-of-order transmission.

[0021] Furthermore, the multi-level CRC check architecture employs a three-level verification mechanism:

[0022] A timestamp-based CRC generation model is built in the driver layer, protocol parsing layer, and business layer respectively, and the refresh of the check polynomial initial vector of each layer is triggered by time synchronization.

[0023] The driver layer CRC check is completed in the SoC-side software, while the protocol layer and application layer CRC check are completed in the CPU-side software. When each time trigger window is closed, each level of the verification module will inject a timestamp hash value as a dynamic perturbation factor, so that the subsequently generated CRC check sequence has a timestamp. The system can trace the source of errors by using the timestamp offset in the verification failure event.

[0024] The driver-level CRC performs error detection and noise suppression, the protocol parsing-level CRC performs frame structure integrity verification, and the application-level CRC performs business logic semantic correctness verification. The three-level CRC performs verification based on the same timestamp synchronization mechanism. When any level detects a CRC verification failure, the system synchronously reports an anomaly with a timestamp identifier. The SoC-side software and CPU-side software analyze the timestamp in the anomaly and the current scheduling cycle to achieve rapid fault location and handling: if the timing deviation is within the single-cycle tolerance range, a local state rollback is triggered; when the timing deviation exceeds a preset threshold, it is identified as a network boundary transmission anomaly and the hardware and software are reinitialized to avoid error propagation.

[0025] Furthermore, all three levels of CRC use a reconfigurable mechanism, which has two modes: a high-entropy anti-interference polynomial is used in strong interference environments, and a low-complexity verification polynomial is used when energy efficiency constraints are met.

[0026] According to the pre-set flight sequence, the dynamic update of the CRC check method is driven by the time-triggered cumulative value; the switching process is coordinated by the TTE global timing synchronization signal, and the mode is switched according to the scheduling cycle boundary to ensure that the CRC check strategy conversion is aligned with the service flow timing.

[0027] Furthermore, methods for constructing a deterministic data flow path between the PCIe bus and the time-triggered network to achieve data transmission across heterogeneous domains include:

[0028] The behavior is uniformly abstracted into a token state transition process, which includes network communication, bus transactions and memory operations; through a globally unified token scheduling strategy and execution sequence, cross-domain transmission behavior is transformed into atomic token acquisition, resource binding and state release operations; heterogeneous units maintain the independence of their respective physical clocks, and deterministic timing synchronization across clock domains is achieved through a unified scheduling strategy.

[0029] Furthermore, methods for constructing a deterministic data flow path between the PCIe bus and the time-triggered network to achieve data transmission across heterogeneous domains include:

[0030] During software scheduler initialization, the token sequence is compiled. The SoC-side software sets up a windowed execution verification mechanism based on the time-triggered principle. When the logical timeline reaches the preset trigger threshold, network frame operation is activated. PCIe calls implement timeout monitoring and priority preemption decisions by comparing the physical clock count with the token sequence timestamp in real time.

[0031] By decoupling the time base from the physical clock, a cross-domain synchronization mechanism is constructed: as long as the token sequence satisfies the timing monotonicity constraint, the transmission buffer can be ensured to maintain a dynamic balance.

[0032] When the token is used as a carrier of transmission strategy to realize the reconstruction of transmission parameters or the dynamic adjustment of control bandwidth, the system realizes the strategy iteration by dynamically adding and deleting token items, and completes the dynamic change of system configuration while ensuring the continuity of transmission service.

[0033] The tokens also support a semantic integrity verification mechanism to monitor the consistency of business processing. The application CPU-side software continuously verifies the running status of each token by tracking the token lifecycle. When a high-priority control frame fails to complete the token acquisition operation within the predetermined time window, a fault-tolerant processing procedure is immediately triggered: first, the low-priority token resources in the current transmission queue are frozen, and transmission channel isolation is implemented; then, a semantic integrity violation event is generated, and a timestamped exception context is pushed to the SoC-side software via the bus; the SoC-side software processes the event according to a predetermined response strategy to ensure the reliability of data transmission.

[0034] Furthermore, when transmitting data across heterogeneous domains:

[0035] The scheduler uses a three-level configuration-driven architecture to implement hardware and business abstraction design: the top-level configuration uses the YAML structured description language to define the mission profile, system function partitions, and transmission data characteristic parameters of different stages of the rocket; the intermediate conversion layer configuration syntax defines the time characteristics of the business and establishes the logical mapping relationship between transmission strategies and scheduling resources; the bottom-level configuration encapsulates the handling methods for problems such as excessive transmission load rate, and finally generates a scheduling sequence that meets the current constraints.

[0036] Compared with the prior art, the present invention has at least one of the following advantages:

[0037] (1) This invention proposes a high-speed and reliable data transmission scheme based on dual-ring buffer and timestamp synchronization, which solves the problem of rate mismatch between TTE network data reception and PCIe bus data transmission. Through the design of a ring-free buffer, it realizes the reduction of end-to-end transmission delay and deterministic transmission channel.

[0038] (2) This invention proposes a multi-level dynamic fault-tolerant verification method with timestamp binding, which realizes rapid fault location and recovery when rocket data transmission is abnormal. At the same time, it supports dynamic adjustment of the required verification strategy at different stages, ensuring the reliable transmission of key control commands in extreme environments.

[0039] (3) This invention designs a hardware-independent spatiotemporal constraint scheduling process, solving the problem of resource configuration updates for dynamic mission profiles. Through a scheduling token model and a YAML configuration-driven architecture, it realizes dynamic reconfiguration of transmission strategies and dynamic adjustment of transmission bandwidth, providing technical support for online mission reconfiguration of manned launch vehicles. Attached Figure Description

[0040] Figure 1This is a diagram of the embedded real-time reliable data interface architecture of the present invention. Detailed Implementation

[0041] The features and advantages of the present invention will become clearer and more apparent from the following detailed description.

[0042] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments. Although various aspects of embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated otherwise.

[0043] This invention aims to address the problems of insufficient communication nodes, low communication bandwidth, insufficient data reliability, and inconsistent TTE data in existing embedded information interfaces used in next-generation manned launch vehicles. Specifically, traditional designs cannot simultaneously accommodate the transmission capabilities of high-speed communication interfaces and the global timing consistency control of time-triggered buses, making it difficult for the system to meet the comprehensive requirements of synchronous data transmission triggering, high-speed data processing, and consistent data transmission. This invention proposes a novel design method that effectively integrates internal PEIe path processing, software ring buffer design, TTE bus scheduling, and multi-level CRC (Cyclic Redundancy Check) verification processes. Through interface layer protocol conversion, unified scheduling modeling, and enhanced data transmission reliability, it achieves support for complex rocket embedded software.

[0044] This invention discloses a design method for an embedded real-time reliable information interface for a new generation of manned launch vehicles, specifically comprising:

[0045] 1) The dual-layer ring buffer structure and frame time stamping mechanism improve data reliability and data frame consistency under TTE scheduling constraints;

[0046] 2) The CRC redundancy protection strategy based on multi-level verification effectively enhances the fault identification and recovery capability, while supporting strategy switching under different business scenarios;

[0047] 3) A deterministic transmission path between heterogeneous domains is achieved through hardware and software collaboration to bridge the protocol between PCIe and TTE, providing a reliable channel for real-time remote control and status feedback in flight software.

[0048] This invention provides a design method for embedded software real-time reliable information interfaces for next-generation manned launch vehicles. It enables the construction of a unified, efficient, and high-speed communication interface framework among multiple key subsystems such as rocket flight control, telemetry, and fault diagnosis and handling. Figure 1 .

[0049] Step 1) Proposes a fast and reliable data transmission scheme based on TTE data processing SoC (System on Chip), PCIe high-speed transmission, and application software CPU. The entire link includes a two-layer ring buffer and a time-stamping coordination mechanism. The TTE SoC side software interface is responsible for the concurrent reception and processing of time-triggered external network data. The processed data is then rapidly transmitted to the application layer CPU's secondary ring buffer via DMA-initiated PCIe. Subsequently, the CPU completes the parsing calculation under the constraint of global time-triggered consistency, effectively coupling deterministic transmission at the network layer with high-speed data processing.

[0050] First, the TTE SoC-side software interface captures control frames, telemetry frames, and other data frames from various rocket subsystems within a predetermined window at the arrival of each scheduling cycle, and immediately timestamps each frame with a 64-bit high-precision timestamp. All frames are written to a primary circular buffer located inside the SoC. This buffer uses a fixed slot length and an auto-incrementing pointer design, which can support multiple concurrent writes without locking, avoiding bus congestion caused by sudden network traffic.

[0051] When the number of valid frames in the primary circular buffer reaches a preset threshold or the timeout protection is triggered according to a pre-defined timeliness rule, the TTE SoC-side software interface initiates a PCIe transaction via hardware DMA, batch writing all valid frames in the slot to the secondary circular buffer in the application-side CPU shared memory. The secondary buffer slot size corresponds one-to-one with the primary buffer, but additionally stores a copy of the frame verification result and the received timestamp for subsequent integrity and timing verification. The entire PCIe transfer process uses the control-side BAR register to update the number of bytes transferred in real time, ensuring accurate reporting of write progress even under high bandwidth conditions and preventing buffer overflow.

[0052] Secondly, the application-side CPU software polls the secondary buffer according to the application layer's business requirements. Upon detecting that a slot has already been written to, the application-side CPU software uses DCACHE to ensure that it reads only the latest DMA-written data, while simultaneously checking if the timestamp falls within the allowed time window of the current scheduling cycle. If the verification is successful and the timing requirements are met, the application-side CPU software immediately unpacks the frame content and writes it to the application layer software.

[0053] To prevent a rate imbalance between the sending and receiving ends of the two-level buffer from causing one level of buffer to be continuously and rapidly emptied or filled, thus triggering resource preemption, this invention also implements a backpressure-preemption strategy. The TTE SoC-side software continuously monitors the remaining slots in the first-level buffer through an internal state machine. When the remaining space falls below a threshold, a high-water mark interrupt is sent to the CPU side via a PCIe MSI interrupt. The CPU-side software immediately increases the current scheduling priority, preempting lower-priority tasks to ensure that critical control frames are processed and slots are released before the start of the next TTE cycle. Conversely, when the CPU processing speed is too fast while PCIe is still transmitting, the TTE SoC-side software raises a custom receive signal to postpone new frame injection, preventing the second-level buffer write pointer from catching up with the read pointer and causing out-of-order delivery.

[0054] Step 2) proposes a timestamp-based multi-level CRC check architecture, establishing a binding relationship between layered CRC check codes and a global logical time base. The system employs a three-level verification mechanism: timestamp-based CRC generation models are constructed at the driver layer, protocol parsing layer, and business layer, respectively, with time synchronization triggering the refresh of the initial vectors of the check polynomials at each level. Driver-level CRC check is performed in software on the SoC side, while protocol-level and application-level CRC check are performed in software on the CPU side. When each time trigger window closes, each level of the verification module injects a timestamp hash value as a dynamic perturbation factor, ensuring that the subsequently generated CRC check sequences have timestamps. Even if the same physical bits are affected by flipping in different periods, due to the differences in the embedded time characteristics of the CRC check codes in each period, the system can trace the source of errors through the timestamp offset in the check failure event.

[0055] In the three-layer collaborative verification system, the driver-layer CRC performs error detection and noise suppression, the protocol parsing layer CRC performs frame structure integrity verification, and the application layer CRC performs business logic semantic correctness verification. All three CRC levels are verified based on the same timestamp synchronization mechanism. When any level detects a CRC verification failure, the system synchronously reports an anomaly with a timestamp identifier. The SoC-side software and CPU-side software analyze the timestamp in the anomaly and the current scheduling cycle to achieve rapid fault location and handling: if the timing deviation is within the single-cycle tolerance range, a local state rollback is triggered; if the timing deviation exceeds a preset threshold, it is identified as a network boundary transmission anomaly, and the hardware and software are reinitialized to prevent error propagation.

[0056] All three layers of CRC employ a reconfigurable mechanism with two modes: a high-entropy anti-interference polynomial (for environments with strong electromagnetic interference) and a low-complexity check polynomial (for energy efficiency constraints). The system supports dynamic updates of the CRC check method driven by time-triggered cumulative values, according to a pre-set flight sequence. The switching process is coordinated by the TTE global timing synchronization signal, switching modes based on scheduling cycle boundaries to ensure that the CRC check strategy conversion aligns with the service flow timing.

[0057] Step 3) Establish a deterministic data flow path between the PCIe bus and the time-triggered network to achieve seamless data transmission across heterogeneous domains. This module constructs a software scheduler for data transmission between heterogeneous hardware. Its core function is to uniformly map the TTE's time-triggered mechanism and the PCIe transaction burst transmission model to the same logical time base. Time windows are configured based on the real-time level and priority characteristics of data streams from services such as flight control and telemetry, enabling upper-layer services to obtain deterministic latency guarantees without being aware of the underlying hardware architecture. The scheduler abstracts network communication, bus transactions, memory operations, and other behaviors into a unified token state transition process. Through a globally unified token scheduling strategy and execution sequence, cross-domain transmission behavior is transformed into atomic token acquisition, resource binding, and state release operations. Heterogeneous units maintain the independence of their respective physical clocks, achieving deterministic timing synchronization across clock domains through a unified scheduling strategy.

[0058] During system initialization, a token sequence compilation operation is performed. The SoC-side software sets up a windowed execution verification mechanism based on the time-triggered principle. When the logical timeline reaches a preset trigger threshold, network frame operations are activated. PCIe calls implement timeout monitoring and priority preemption decisions by comparing the physical clock count with the token sequence timestamp in real time. By decoupling the time base from the physical clock, a cross-domain synchronization mechanism is constructed: as long as the token sequence meets the timing monotonicity constraint, the transmission buffer can be ensured to maintain a dynamically balanced state. When the token serves as the carrier of transmission strategy to reconstruct transmission parameters or dynamically adjust control bandwidth, the system can achieve strategy iteration through the dynamic addition and deletion of token items, completing dynamic changes to the system configuration while ensuring the continuity of transmission services.

[0059] The tokens also support semantic integrity verification mechanisms to monitor the consistency of business processing. The application CPU-side software continuously verifies the operational status of each token by tracking its lifecycle. When a high-priority control frame fails to complete the token acquisition operation within a predetermined time window, a fault-tolerant processing procedure is immediately triggered: first, low-priority token resources in the current transmission queue are frozen, implementing transmission channel isolation; then, a semantic integrity violation event is generated, and a timestamped exception context is pushed to the SoC-side software via the bus. The SoC-side software processes this event according to a predetermined response strategy, ensuring the reliability of data transmission. The tokens directly map the monitored object to the task-level semantic unit, avoiding the complex hardware-software interaction state inference process, thus reducing the latency of exception detection and response decision-making. Data consistency can still be guaranteed when the system faces non-deterministic interference.

[0060] The scheduler employs a three-tier configuration-driven architecture to implement hardware and business abstraction design: the top-level configuration uses the YAML structured description language to define the mission profiles, system functional partitions, and transmission data characteristic parameters for different stages of the rocket; the intermediate transformation layer configuration syntax defines the temporal characteristics of the business and establishes a logical mapping relationship between transmission strategies and scheduling resources; the bottom-level configuration encapsulates handling methods for problems such as excessive transmission load, ultimately generating a scheduling sequence that meets the current constraints. The configuration process does not require hardware description language to solidify transmission strategies and firmware image updates, and supports hot updates of scheduling strategies.

[0061] The present invention has been described in detail above with reference to specific embodiments and exemplary examples; however, these descriptions should not be construed as limiting the present invention. Those skilled in the art will understand that various equivalent substitutions, modifications, or improvements can be made to the technical solutions and embodiments of the present invention without departing from the spirit and scope of the invention, and all such modifications and improvements fall within the scope of the present invention. The scope of protection of the present invention is defined by the appended claims.

[0062] The contents not described in detail in this specification are common knowledge to those skilled in the art.

Claims

1. A design method of embedded real-time reliable information interface for manned launch vehicle, characterized in that, The application relates to a time-triggered Ethernet (TTE) Soc, a PCIe bus and a CPU, and relates to a data transmission link between the TTE Soc, the PCIe bus and the CPU. The data transmission link is used for providing time-stamped original data input for multi-level CRC (Cyclic Redundancy Check) checking and providing a physical channel basis for the PCIe bus. A time-stamped multi-level CRC checking architecture is determined. Based on the time stamp provided by the data transmission link, a binding relationship between a layered CRC check code and a global logical time reference is established through the multi-level CRC checking architecture, and when the CRC checking fails, fault tolerance processing is performed and the deterministic data path of the corresponding time window is frozen. A deterministic data flow path is constructed between the PCIe bus and the time-triggered Ethernet, and through inheriting the buffer structure of the data transmission link and fusing the verification result of the CRC checking, data transmission across heterogeneous domains is realized. The data transmission link between the TTE Soc, the PCIe bus and the CPU comprises the following steps:

2. The method for designing an embedded real-time reliable information interface for manned launch vehicle according to claim 1, wherein, A TTE Soc side software interface captures control frames, telemetry frames and other data frames sent by each subsystem of a rocket according to a predetermined window when each scheduling period arrives, and immediately time stamps each frame; All the frames are written into a first level ring buffer located in the TTE Soc; When the number of valid frames in the first level ring buffer reaches a preset threshold or a pre-set timeliness timeout protection is reached, the TTE Soc side software interface initiates a PCIe transaction through a hardware DMA to batch write the whole slot of valid frames into a second level ring buffer in the application side CPU shared memory; An application side CPU software accesses the second level buffer according to the application layer service demand beat, and when it is found that the slot has been written by data, the application side CPU software ensures that the read data is the latest DMA written data through a DCACHE operation, and simultaneously checks whether the time stamp falls within the time window allowed in the current scheduling period, if the checking is successful and the timing requirement is met, the application side CPU software immediately unpacks and writes the frame content into the application layer software. The first level ring buffer adopts a fixed slot length and a pointer increment mode, supports multi-channel concurrent writing without locking, and avoids bus blocking caused by network burst traffic; 3. The method for designing an embedded real-time reliable information interface for manned launch vehicle according to claim 2, wherein, The slot size of the second level buffer corresponds to the first level buffer, and additionally saves frame checking results and a copy of the receiving time stamp for subsequent integrity and timing verification. When the TTE Soc side software interface initiates a PCIe transaction through a hardware DMA to batch write the whole slot of valid frames into the second level ring buffer in the application side CPU shared memory, the whole PCIe carrying process updates the number of transmitted bytes in real time by means of the control side BAR register, ensures that the writing progress can be accurately reported under high bandwidth, and avoids buffer overflow.

4. The method for designing an embedded real-time reliable information interface for manned launch vehicle according to claim 2, wherein, In the data transmission link, a back pressure-preemption strategy is adopted to prevent rate imbalance between the sending end and the receiving end of the two level buffers, and the back pressure-preemption strategy comprises the following steps:

5. The method for designing a real-time reliable information interface embedded in a manned launch vehicle according to claim 2, wherein, ​ The TTE Soc-side software continuously monitors the remaining slots of the first-level buffer through an internal state machine. When the remaining space is lower than a threshold, a high-water interrupt is sent to the CPU side through a PCIe MSI interrupt. The CPU-side software immediately increases the current scheduling priority to preempt low-priority tasks, ensuring that critical control frames are processed and released before the next TTE cycle begins. When the CPU-side processing speed is too fast and the PCIe is still transmitting, the TTE Soc-side software pulls up a custom receive signal to temporarily suspend new frame injection, preventing the second-level buffer write pointer from catching up with the read pointer and causing out-of-order.

6. The method for designing a real-time reliable information interface embedded in a manned launch vehicle according to claim 1, wherein, The multi-level CRC verification architecture adopts a three-level verification mechanism: A timestamp-based CRC generation model is constructed at the driver layer, protocol analysis layer, and service layer. The refresh of the initial vector of the verification polynomial at each level is triggered by time synchronization. The driver layer CRC verification is completed by the Soc-side software, and the protocol layer and application layer CRC verification are completed by the CPU-side software. When each time trigger window closes, each level of the verification module injects a timestamp hash value as a dynamic disturbance factor, so that the subsequently generated CRC verification sequence has a time marker. The system realizes error tracing through the timestamp offset in the verification failure event. The driver layer CRC realizes error detection and noise suppression, the protocol analysis layer CRC realizes frame structure integrity verification, and the application layer CRC realizes business logic semantic correctness verification. The three levels of CRC are verified based on the same timestamp synchronization mechanism. When any level detects a CRC verification failure event, the system synchronously reports the exception with a time identifier. The Soc-side software and CPU-side software analyze the timestamp in the exception and the current scheduling period to realize rapid fault localization and processing: if the timing deviation is within the single-cycle tolerance range, it is determined that the local state rollback is triggered; when the timing deviation exceeds the preset threshold, it is identified as a network boundary transmission exception and the hardware and software are reinitialized to avoid error propagation.

7. The method for designing an embedded real-time reliable information interface for manned launch vehicle according to claim 6, wherein, The three levels of CRC use a reconfigurable mechanism, which has two modes: a high-entropy anti-interference polynomial is used in a strong interference environment, and a low-complexity verification polynomial is used when the energy efficiency constraint is met. According to the pre-bound flight timing, the dynamic update of the CRC verification mode is driven by the time trigger cumulative value. The switching process is coordinated by the TTE global timing synchronization signal, and the mode switching is performed based on the scheduling period boundary to ensure that the CRC verification strategy conversion is aligned with the business flow timing.

8. The method for designing a real-time reliable information interface embedded in a manned launch vehicle according to claim 1, wherein, The method for building a deterministic data flow path between a PCIe bus and a time-triggered network to realize cross-heterogeneous domain data transmission includes: The behavior is abstracted as a token state transition process, including network communication, bus transaction, and memory operation. Through a globally unified token scheduling strategy and execution sequence, cross-domain transmission behavior is converted into atomic token acquisition, resource binding, and state release operations. Heterogeneous units maintain their own physical clock independence, and through a unified scheduling strategy, deterministic timing synchronization across clock domains is realized.

9. The method for designing an embedded real-time reliable information interface for manned launch vehicle according to claim 8, wherein, The method for building a deterministic data flow path between a PCIe bus and a time-triggered network to realize cross-heterogeneous domain data transmission includes: The software scheduler initializes the token sequence compilation operation, and the Soc side software sets the windowed execution verification mechanism according to the time trigger principle. When the logical time axis reaches the preset trigger threshold, the network frame operation is activated. The PCIe call implements timeout monitoring and priority preemption decision by comparing the physical clock count with the token sequence timestamp in real time. By decoupling the time reference and the physical clock, a cross-domain synchronization mechanism is constructed: as long as the token sequence meets the timing monotonicity constraint, the transmission buffer can maintain a dynamic balance state. When the token is used as a transmission strategy carrier to realize transmission parameter reconstruction or control bandwidth dynamic adjustment, the system realizes strategy iteration through the dynamic addition and deletion of token items, and completes the dynamic change of system configuration under the condition of ensuring the continuity of transmission service. The token also supports semantic integrity verification mechanism to monitor the consistency of business processing. The application CPU side software tracks the token life cycle to continuously check the running state of each token. When the high priority control frame fails to complete the token acquisition operation within the predetermined time window, the fault handling process is triggered immediately: first, freeze the low priority token resources in the current transmission queue to implement transmission channel isolation; then generate semantic integrity violation events and push the timestamped exception context to the Soc side software through the bus; the Soc side software processes according to the predetermined response strategy based on the event, ensuring the reliability of data transmission.

10. The method for designing a real-time reliable information interface embedded in a manned launch vehicle according to claim 8, wherein, When transmitting data across heterogeneous domains: The scheduler uses a three-level configuration driving architecture to realize hardware and business abstraction design: the top-level configuration uses YAML structured description language to define the task profile, system function partition and transmission data characteristic parameters of different stages of the rocket; the intermediate conversion layer configuration syntax defines the time characteristics of the business, establishes the logical mapping relationship between the transmission strategy and the scheduling resources; the bottom-level configuration binds the processing mode of the transmission load rate and other problems, and finally generates a scheduling sequence that meets the current constraint conditions.

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