Hardware verification method, electronic equipment, storage medium and program product

Abstract

The invention provides a hardware verification method, electronic equipment, a storage medium and a program product, and the method comprises the steps: estimating the required number of hardware verification boards needed for hardware verification of a to-be-tested design, and determining whether the decimal part of the required number is smaller than a threshold value or not; and in response to determining that the decimal part of the required quantity is smaller than a threshold value, cutting the to-be-tested design and distributing the to-be-tested design to a hardware verification board and an expansion circuit board for hardware verification. Wherein when the scale of the design to be tested slightly exceeds the capacity of a single hardware verification board, hardware verification is realized by matching the expansion circuit board with the hardware verification board, and an additional whole hardware verification board does not need to be occupied, so that the cost is saved, and the utilization rate of the hardware verification board is improved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of chip verification, and in particular, to a hardware verification method, an electronic device, a storage medium and a program product. BACKGROUND

[0002] This section is intended to provide background information to facilitate a better understanding of embodiments of the present disclosure. Information in this section is not admitted to be prior art.

[0003] A hardware emulation tool (e.g., a hardware verification board or a hardware emulator) can prototype and debug a logic system design including one or more modules. The logic system design can be, for example, a design for an Application Specific Integrated Circuit (ASIC) or a System-On-Chip (SOC) for a specific application. Thus, the logic system design being tested in the emulation tool can also be referred to as a Design Under Test (DUT). The emulation tool can emulate the DUT through one or more configurable components (e.g., a Field Programmable Gate Array (FPGA)), including performing various operations of the DUT, to test and verify the functionality of various modules of the DUT before manufacturing. The DUT can also be tested for its effect of running with various peripherals as a complete system by externally connecting various peripheral daughter cards to the emulation tool.

[0004] In the related art, for a design whose scale exceeds that of a single hardware verification board, a solution of interconnecting multiple hardware verification boards is usually used.

[0005] However, when the scale of the design only slightly exceeds the capacity of a single hardware verification board, an additional whole hardware verification board must also be occupied, which is costly and has a low utilization rate of the hardware verification board. SUMMARY

[0006] In view of this, the present disclosure aims to provide a hardware verification method, an electronic device, a storage medium and a program product, which at least partially solve one of the technical problems in the related art.

[0007] To achieve the above object, in a first aspect, the present disclosure provides a hardware verification method, comprising: estimating a required number of hardware verification boards required for hardware verification of a DUT, and determining whether a decimal part of the required number is less than a threshold value; cutting and allocating the design under test to hardware verification boards and extension circuit boards for hardware verification in response to determining that the decimal part of the required number of hardware verification boards is less than a threshold value.

[0008] In some example embodiments, the estimating a required number of hardware verification boards needed for hardware verification of the design under test comprises: simulating cutting of the design under test based on a total amount of resources needed for hardware verification of the design under test and an amount of resources provided by the hardware verification boards to obtain the required number of hardware verification boards needed for hardware verification of the design under test.

[0009] In some example embodiments, the cutting and allocating the design under test to hardware verification boards and extension circuit boards for hardware verification comprises: cutting the design under test into a first portion allocated to the hardware verification boards and a second portion allocated to the extension circuit boards; generating a first executable file corresponding to the first portion and generating a second executable file corresponding to the second portion; allocating the first executable file to the hardware verification boards and allocating the second executable file to the extension circuit boards; running the first executable file on the hardware verification boards and running the second executable file on the extension circuit boards.

[0010] In some example embodiments, the cutting the design under test into a first portion allocated to the hardware verification boards and a second portion allocated to the extension circuit boards comprises: cutting the design under test into the first portion allocated to the hardware verification boards and the second portion allocated to the extension circuit boards based on a total amount of resources needed for hardware verification of the design under test, an amount of resources provided by the hardware verification boards, and an amount of resources provided by the extension circuit boards.

[0011] In some example embodiments, the generating the second executable file corresponding to the second portion comprises: determining idle ports on the hardware verification boards; generating a connection scheme of the hardware verification boards and the extension circuit boards based on the idle ports; generating the second executable file corresponding to the second portion based on the connection scheme.

[0012] In some example embodiments, the allocating the second executable file to the extension circuit boards comprises: connecting the hardware verification boards and the extension circuit boards based on the connection scheme; The second executable file is assigned to the connected extension circuit board.

[0013] In some example embodiments, the connecting the hardware verification board and the extension circuit board based on the connection scheme comprises: connecting a port of the extension circuit board and the idle port of the hardware verification board through an interconnection cable based on the connection scheme; wherein one of a pin header or a pin socket is arranged on the interconnection cable, and the other of the pin header or the pin socket is arranged on the port of the extension circuit board and the idle port of the hardware verification board.

[0014] Based on the same inventive concept, a second aspect of the example embodiments of the present disclosure provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the method of the first aspect when executing the program.

[0015] Based on the same inventive concept, a third aspect of the example embodiments of the present disclosure provides a non-transitory computer-readable storage medium, which stores computer instructions for causing a computer to execute the method of the first aspect.

[0016] Based on the same inventive concept, a fourth aspect of the example embodiments of the present disclosure provides a computer program product, comprising computer program instructions, which, when executed on a computer, cause the computer to execute the method of the first aspect.

[0017] As can be seen from the above, the hardware verification method, the electronic device, the storage medium, and the program product provided by the embodiments of the present disclosure, the method comprises: estimating the required number of hardware verification boards required for hardware verification of a design under test, determining whether the decimal part of the required number is less than a threshold value; in response to determining that the decimal part of the required number is less than the threshold value, cutting and assigning the design under test to hardware verification boards and extension circuit boards for hardware verification. Wherein when the size of the design under test is only slightly larger than the capacity of a single hardware verification board, hardware verification is realized by the extension circuit board cooperating with the hardware verification board, without occupying an additional whole hardware verification board, saving the cost and improving the utilization rate of the hardware verification board. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the present disclosure or the related art, the drawings needed to be used in the embodiments or the related art description will be briefly introduced below. Obviously, the drawings in the following description are only embodiments of the present disclosure, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.

[0019] Figure 1 A structural schematic diagram of an exemplary host according to embodiments of the present application is shown.

[0020] Figure 2 A schematic diagram of an exemplary simulation system according to embodiments of the present application is shown.

[0021] Figure 3a A schematic diagram of an exemplary hardware simulation resource according to embodiments of the present application is shown.

[0022] Figure 3b A schematic diagram of an exemplary IO port and interconnect cable macro according to embodiments of the present application is shown.

[0023] Figure 3c A schematic diagram of an exemplary IO port and interconnect cable micro according to embodiments of the present application is shown.

[0024] Figure 4 A flowchart of an exemplary hardware verification method according to embodiments of the present application is shown. DETAILED DESCRIPTION

[0025] In order to make the objects, technical solutions and advantages of the present disclosure clearer, the principles and spirits of the present disclosure will be described below with reference to several exemplary embodiments. It should be understood that these embodiments are only given to enable those skilled in the art to better understand and implement the present disclosure, and do not limit the scope of the present disclosure in any way. On the contrary, these embodiments are provided to make the present disclosure more thorough and complete, and to fully convey the scope of the present disclosure to those skilled in the art.

[0026] In this document, it should be understood that any number of elements in the drawings are used for illustration only and not limitation, and any naming is only for distinction and does not have any limiting meaning.

[0027] It should be noted that, unless otherwise defined, technical terms or scientific terms used in the embodiments of the present disclosure shall have the common meaning understood by one of ordinary skill in the art to which the present disclosure belongs. The terms "first", "second", and similar terms used in the embodiments of the present disclosure do not denote any order, quantity, or importance, but are used to distinguish different components. The terms "include", "contain", and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms "connect" or "connected" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right", and the like are used only to represent relative positional relationships, and when the absolute positions of the described objects are changed, the relative positional relationships can also be changed accordingly. The article "a" or "an" before an element does not exclude the presence of multiple such elements.

[0028] The principles and spirits of the present disclosure will be explained in detail below with reference to several representative embodiments of the present disclosure.

[0029] As described in the background, in the related art, for a design whose scale exceeds a single hardware verification board, a solution of interconnection of multiple hardware verification boards is usually used.

[0030] However, the inventors of the present disclosure find that when the scale of the design is only slightly larger than the capacity of a single hardware verification board, an additional whole hardware verification board must be occupied, which is costly and has a low utilization rate of the hardware verification board.

[0031] The term involved in the present application: FPGA: field programmable gate array, is a semi-custom digital integrated circuit, whose function can be defined by changing the configuration information. It combines the advantages of custom circuits and programmable devices, has flexibility and reconfigurability, and is widely used in communication, image processing, medical treatment, and EDA field.

[0032] Hardware verification includes prototype verification and hardware simulation. Among them, hardware simulation is an application focusing on simulating the function of DUT; prototype verification is a function focusing on running embedded system on the board and developing embedded system. The carriers of prototype verification and hardware simulation are hardware verification board and expansion subcard.

[0033] Hardware simulation: using a dedicated, FPGA-based hardware system to simulate the entire chip or system.

[0034] Prototype verification: FPGA prototype verification is a hardware verification technology based on FPGA. By converting RTL code into bitstream and transplanting it into FPGA, the functionality and timing correctness of ASIC, SoC and other chips can be verified to shorten the development cycle, reduce costs and improve design reliability.

[0035] DUT: Device Under Test, which refers to the device being tested (or device) in this application, specifically refers to digital integrated circuits, which are manufactured products such as chips, electronic components, etc. that are measured, analyzed or verified for performance during testing, as part of functional testing and calibration.

[0036] Peripheral: hardware devices connected to the host (here referring to the hardware verification system), such as monitors, keyboards and other USB devices, Ethernet cards, graphics cards and other PCIe devices, signal generation / collection / transmission devices, etc.

[0037] Sub-card: Daughter Board, which refers to an additional card attached to the host, which transmits information through an interconnection cable connected to the host or directly inserted into the host's slot.

[0038] IO slot: refers to the interface on the host for connecting and expanding input / output (I / O) devices. It allows users to increase the functionality of the host by inserting a sub-card, and is an important channel for communication and data exchange between the host and external devices. IO slot can also be used for connection and data exchange between FPGAs.

[0039] Logical partitioning: the process of dividing a large digital integrated circuit into multiple relatively independent modules or subsystems according to certain capacity. These modules or subsystems are logically related to each other and collectively implement the functionality of the overall circuit, helping to divide the system into multiple parts for physical design and implementation, reducing design complexity, and also allowing large digital integrated circuits to be implemented in multiple sub-chips (such as multiple FPGAs).

[0040] Existing FPGA hardware verification technology uses FPGAs to implement the functionality of the design under test (DUT), allowing functional verification to be carried out on this technology and allowing external devices (such as DDR, USB, PCIe, Ethernet, etc.) to be connected for interconnection communication. Each FPGA prototype verification device typically has thousands of IO (input / output) pins, and is divided into dozens of IO slots with dozens of pins per group. In practice, some IO slots are used for interconnection between FPGAs, and some IO slots are used for expansion functions such as DDR sub-cards. These devices that implement interconnection functions and expansion functions are typically designed based on certain standards, including the shape of the IO slot, the number of signals, the voltage of the signal, the address of the signal connected to the IO pin of the FPGA, etc.

[0041] FPGA chip of hardware verification device has various resources that can be dynamically programmed, such as digital logic circuits (LUT, FF, etc.), memory resources (BRAM, URAM, etc.). The total amount of resources in the FPGA is fixed and limited. After the DUT is compiled into a bitstream file, it is burned into the FPGA. In fact, it is to select specific resources in the FPGA and route and interconnect them to form an integrated circuit with hardware verification capability, providing hardware verification services such as running software on the device and communicating with external devices.

[0042] The prior art realizes hardware verification of a DUT with an actual capacity greater than one FPGA by interconnecting multiple FPGAs. Even if the actual capacity of a design just exceeds one FPGA, it has to be divided into two FPGAs, causing resource waste, because two FPGAs can be allocated to two DUTs for hardware verification tasks respectively, and the cost of each FPGA is high and scarce (the cost of a flagship hardware verification FPGA is generally tens of thousands of yuan per chip). Using a larger capacity hardware verification FPGA often costs more, and usually there is no larger capacity because the flagship model already uses the largest FPGA on the market. Therefore, in order to save costs and improve the utilization rate of hardware verification FPGAs, "reducing the number of hardware verification FPGAs used" is an important requirement, especially for designs with a capacity just exceeding one FPGA, such as 1%~20%. A low-cost implementation solution is needed.

[0043] In addition, the FPGA selected by the hardware verification device is usually an FPGA model with more digital logic circuits (LUT, FF, etc.) resources, but less memory resources (BRAM, URAM, etc.) on the chip. There may be a DUT whose digital logic circuit usage ratio is less than one FPGA, but its memory usage ratio exceeds one FPGA, so it cannot be implemented using only one FPGA. The user may therefore truncate the memory and only implement part of the DUT memory in the FPGA, discarding the memory space exceeding the capacity. The disadvantage of this is that the complete software cannot be run, and the software needs to be limited to using the memory address space available in one FPGA, or the software use case that requires large memory is discarded, thereby reducing the coverage of the hardware verification. There are actually some small and medium-sized FPGA chips on the market with less digital logic circuit resources and more memory resources, which can complement the existing hardware verification devices.

[0044] In addition, in general engineering implementation schemes, the development progress of the DUT development engineer is usually first run through the hardware verification implementation based on a piece of FPGA (i.e., FPGA hardware verification implementation version 1) on the basis of DUT version 1, and the peripherals and other interconnections have been configured and optimized based on version 1. Then the DUT development engineer iteratively generates DUT version 2, but DUT version 2 is slightly larger and cannot be implemented in one FPGA. At this time, if it needs to be changed to 2 FPGAs, various peripherals and interconnections need to be redesigned and implemented. If a technology can slightly expand the available resources of one FPGA without additional configuration of peripherals and other interconnections, the hardware verification engineering reuse rate of version 2 will be higher, and the deployment efficiency can be improved.

[0045] The above, 1 FPGA, 2 FPGA are examples, can be N FPGA, N+1 FPGA, such as a DUT that occupies 2.1 FPGA resources in total, can still use 2 FPGA (N=2) plus one "circuit board for expanding hardware verification device logic and memory unit" to implement, otherwise 3 FPGA (N+1=3) should be used to implement this 2.1 FPGA resource requirement design.

[0046] In addition, the present technology can also be used in parallel with multiple blocks at the same time, such as a design that occupies 2.6 FPGA resources in total, which can use 2 FPGA plus 3 "circuit boards for expanding hardware verification device logic and memory unit" (0.2 resources per board).

[0047] However, if a commonly used general-purpose FPGA development board on the market is manually used to interconnect with the hardware verification FPGA through the GPIO port or the port based on the Serdes interface, the scheme can be implemented in principle. However, they need to be deeply customized and developed by hand, and each time a new iteration version is generated, it needs to be manually adjusted according to the design of the DUT; and there is no uniform specification for interface pins on the FPGA development board on the market, making it not easy to develop general-purpose software for automatic segmentation and implementation; and the interface timing of the GPIO connection in this scheme is often worse, which is not conducive to the implementation of high-speed hardware verification, and the development difficulty of the Serdes connection is higher and more complex, and the cost is high, and the verification difficulty is large, so there are disadvantages.

[0048] In summary, in order to solve the above problems, the present disclosure provides a hardware verification scheme, specifically including: The number of hardware verification boards required for hardware verification of the design under test is estimated, and it is determined whether the fractional part of the number is less than a threshold value; in response to determining that the fractional part of the number is less than the threshold value, the design under test is cut and allocated to hardware verification boards and extension circuit boards for hardware verification.

[0049] When the size of the design under test is only slightly larger than the capacity of a single hardware verification board, hardware verification is implemented by the extension circuit board in cooperation with the hardware verification board, without occupying an additional whole hardware verification board, thereby saving costs and improving the utilization rate of the hardware verification board.

[0050] The exemplary hardware verification method of the embodiments of the present application can be applied to, but is not limited to, the following products: HuaPro P1 / P2E / P3 and HuaEmu E1 produced by ChipChina.

[0051] After introducing the basic principles of the present disclosure, various non-limiting embodiments of the present disclosure will be specifically introduced below.

[0052] Figure 1 A structural schematic diagram of a host 100 according to an embodiment of the present application is shown.

[0053] The host 100 can be an electronic device running a simulation system. As shown in Figure 1 The host 100 can include a processor 102, a memory 104, a network interface 106, a peripheral interface 108, and a bus 110. The processor 102, the memory 104, the network interface 106, and the peripheral interface 108 are communicatively connected to each other inside the electronic device through the bus 110.

[0054] The processor 102 can be a central processing unit (CPU), a graphics processor, a neural network processor (NPU), a microcontroller (MCU), a programmable logic device, a digital signal processor (DSP), an application specific integrated circuit (ASIC), or one or more integrated circuits. The processor 102 can be used to perform functions related to the techniques described in the present application. In some embodiments, the processor 102 can also include multiple processors integrated as a single logical component. As shown in Figure 1 The processor 102 can include multiple processors 102a, 102b, and 102c.

[0055] The memory 104 can be configured to store data (e.g., instruction sets, computer code, intermediate data, etc.). In some embodiments, a simulation test system for simulating a test design can be a computer program stored in the memory 104. As shown inFigure 1 As shown, the memory stores data, which can include program instructions (e.g., program instructions for implementing the hardware verification method of the present application) and data to be processed (e.g., the memory can store temporary code generated in a compilation process). The processor 102 can also access the program instructions and data stored by the memory and execute the program instructions to operate on the data to be processed. The memory 104 can include volatile storage or non-volatile storage. In some embodiments, the memory 104 can include random access memory (RAM), read-only memory (ROM), optical disc, magnetic disc, hard disc, solid state disc (SSD), flash memory, memory stick, etc.

[0056] The network interface 106 can be configured to provide communication with other external devices to the host 100 via a network. The network can be any wired or wireless network capable of transmitting and receiving data. For example, the network can be a wired network, a local wireless network (e.g., Bluetooth, WiFi, near field communication (NFC), etc.), a cellular network, the Internet, or a combination thereof. It can be understood that the type of network is not limited to the specific examples described above. In some embodiments, the network interface 106 can include any combination of any number of network interface controllers (NICs), radio frequency modules, transceivers, modems, routers, gateways, adapters, cellular network chips, etc.

[0057] The peripheral interface 108 can be configured to connect the host 100 with one or more peripheral devices to enable information input and output. For example, the peripheral devices can include input devices such as keyboards, mice, touchpads, touchscreens, microphones, various sensors, etc. and output devices such as displays, speakers, vibrators, indicator lights, etc.

[0058] The bus 110 can be configured to transmit information between various components (e.g., the processor 102, the memory 104, the network interface 106, and the peripheral interface 108) of the host 100, such as internal buses (e.g., processor-memory buses), external buses (USB ports, PCI-E buses), etc.

[0059] It should be noted that although the above electronic device architecture only shows the processor 102, the memory 104, the network interface 106, the peripheral interface 108, and the bus 110, in the specific implementation process, the electronic device architecture can also include other components necessary for normal operation. In addition, those skilled in the art can understand that the above electronic device architecture can also only include components necessary for implementing the embodiments of the present application, and does not necessarily include all the components shown in the figure.

[0060] Figure 2 A schematic diagram of a simulation system 200 according to an embodiment of the present application is shown.

[0061] As shown in Figure 2 the simulation system 200 can include a simulation tool 202 and the host 100 connected to the simulation tool 202.

[0062] The simulation tool 202 is a hardware system for simulating a design under test (DUT). The simulation tool 202 can be a hardware verification board or a hardware emulator. A design under test can include multiple modules. The design under test can be combinational logic circuit, sequential logic circuit, or a combination of the two. The simulation tool 202 can include one or more configurable circuits (e.g., FPGA) for simulating the design under test.

[0063] The simulation tool 202 can include an interface unit 2022 for communicatively coupling with the host 100 for communication between the host 100 and the simulation tool 202. In some embodiments, the interface unit 2022 can include one or more interfaces with electrical connection capability. For example, the interface unit 2022 can include an RS232 interface, a USB interface, a LAN port, a fiber interface, an IEEE 1394 (Firewire interface), etc. In some embodiments, the interface unit 2022 can be a wireless network interface. For example, the interface unit 2022 can be a WIFI interface, a Bluetooth interface, etc.

[0064] The host 100 can transmit the compiled DUT, debug instructions, etc. to the simulation tool 202 via the interface unit 2022. The simulation tool 202 can also transmit simulation data, etc. to the host 100 via the interface unit 2022.

[0065] The simulation tool 202 can also include a memory 2024 for storing simulation data (e.g., various signal values) generated by the design under test during simulation. In some embodiments, the signal values generated by the design under test during simulation can be directly read by the host 100. It can be appreciated that the memory 2024 can also be independent of the simulation tool 202, e.g., using an external memory.

[0066] The simulation tool 202 can also include an FPGA 2026 for hardware implementation of a logic system design onto an FPGA. It can be appreciated that the simulation tool 202 can include multiple FPGAs, as shown in the example.

[0067] In addition to being connected to the host 100, the simulation tool 202 can also be connected to one or more daughter cards 204 via the interface unit 2022.

[0068] The daughter card is used to provide peripherals to the DUT to form a complete electronic system when using the simulation tool 202 for hardware verification. Hardware verification refers to a verification method that, before a chip is taped out, restores the real use scenario of the chip as much as possible to verify whether the functions of the chip are accurate and complete. The daughter card 204 can include a memory daughter card (e.g., providing a DDR memory interface), a communication daughter card (e.g., providing a plurality of network interfaces or a wireless network card interface), and the like.

[0069] The host 100 can be used to configure the simulation tool 202 to simulate a design under test. The design under test can be a complete logic system design or one or more modules of a complete logic system design. In some embodiments, the host 100 can be a virtual host in a cloud computing system. The logic system design (e.g., an ASIC or a System-On-Chip) can be designed by a hardware description language (e.g., Verilog, VHDL, System C, or System Verilog).

[0070] The host 100 can receive a request to debug a design under test from a user. As described above, the design under test can include one or more modules. The description of the design under test can be done in a hardware description language. The host 100 can perform synthesis based on the description of the design under test to generate, for example, a gate-level circuit netlist (not shown) of the design under test. The gate-level circuit netlist of the design under test can be loaded into the simulation tool 202 to run, and thus a circuit structure corresponding to the design under test can be formed in the simulation tool 202. Therefore, the circuit structure of the design under test can be obtained according to the description, and accordingly, the circuit structure of each block in the design under test can also be similarly obtained.

[0071] Figure 3a A schematic diagram of a hardware simulation resource 300 according to embodiments of the present application is shown.

[0072] The simulation tool 202 performs a hardware verification function through the hardware simulation resource 300.

[0073] The hardware simulation resource 300 includes one or more hardware verification boards (e.g., hardware verification board 3011, hardware verification board 3012, and hardware verification board 3013), and one or more extension circuit boards (e.g., extension circuit board 3021, extension circuit board 3022, and extension circuit board 3023).

[0074] As an example, the hardware verification board includes an FPGA board.

[0075] In some embodiments, the hardware simulation resource 300 further includes a daughter card (e.g., daughter card 3031).

[0076] When the simulation tool 202 performs hardware verification on the design, the host 100 can invoke the configuration file to configure the hardware simulation resource 300. The amount of resources of the hardware simulation resource 300 can be measured by the number of hardware verification boards, the number of expansion circuit boards, and the number of daughter cards.

[0077] As an example, the hardware verification boards (for example, the hardware verification board 3011, the hardware verification board 3012, and the hardware verification board 3013) and the daughter card (for example, the daughter card 3031) are all traditional hardware verification systems, which tend to generate idle IO ports. The present application utilizes these idle IO ports to externally connect to the expansion circuit boards (for example, the expansion circuit board 3021, the expansion circuit board 3022, and the expansion circuit board 3023) to supplement digital logic circuits or memory resources, so as to achieve the verification effect that originally requires 4-5 hardware verification boards by using only 3 relatively expensive and scarce hardware verification boards plus 3 relatively low-cost expansion circuit boards.

[0078] In some embodiments, the hardware verification boards (for example, the hardware verification board 3011, the hardware verification board 3012, and the hardware verification board 3013), the expansion circuit boards (for example, the expansion circuit board 3021, the expansion circuit board 3022, and the expansion circuit board 3023), and the daughter card (for example, the daughter card 3031) are connected through interconnection cables.

[0079] As an example, reference is made to Figure 3b to illustrate by connecting hardware device 1 and hardware device 2 through interconnection cables.

[0080] Among them, the hardware device 1 and the hardware device 2 include the hardware verification board (for example, the hardware verification board 3011, the hardware verification board 3012, and the hardware verification board 3013), the expansion circuit board (for example, the expansion circuit board 3021, the expansion circuit board 3022, and the expansion circuit board 3023), and the daughter card (for example, the daughter card 3031).

[0081] Among them, the hardware device 1 includes IO port 1-1, IO port 1-2, and IO port 1-3, the hardware device 2 includes IO port 2-1, IO port 2-2, and IO port 2-3, and IO port 1-1 and IO port 2-1 are connected through interconnection cables.

[0082] As an example, reference is made to Figure 3c to illustrate by connecting hardware device 1 and hardware device 2 through interconnection cables.

[0083] The hardware device 1 and the hardware device 2 include hardware verification boards (for example, hardware verification board 3011, hardware verification board 3012, and hardware verification board 3013), extension circuit boards (for example, extension circuit board 3021, extension circuit board 3022, and extension circuit board 3023), and daughter cards (for example, daughter card 3031).

[0084] The interconnection cable has M signals (for example, the value of M can be dozens to hundreds), one end of the M signals is connected to the signals (for example, signals 1-1~1-M and signals 2-1~1-M) of the hardware device (for example, the hardware device 1 and the hardware device 1) through PCB wiring, and the other end is connected to the interconnection cable. The IO port (for example, IO port 1-1 and IO port 2-1) on the hardware device (for example, the hardware device 1 and the hardware device 1) adopts the form of a pin (for example, pin 1~M), and a section of the interconnection cable adopts the form of a female header (for example, female header 1~M) (there is a shielded cable between the two rows of female headers connected with the IO port 1-1 and the IO port 2-1, respectively).

[0085] In some embodiments, the connection between the interconnection cable and the two hardware devices is axisymmetric, which facilitates subsequent development work.

[0086] In some embodiments, the IO port (for example, IO port 1-1 and IO port 2-1) on the hardware device (for example, the hardware device 1 and the hardware device 1) adopts the form of a female header (for example, female header 1~M), and a section of the interconnection cable adopts the form of a pin (for example, pin 1~M) (there is a shielded cable between the two rows of pins connected with the IO port 1-1 and the IO port 2-1, respectively).

[0087] Figure 4 A flowchart of an exemplary hardware verification method 400 according to an embodiment of the present application is shown, wherein the method 400 can be executed by the simulation system 200 as shown in Figure 2 The simulation tool 202 as shown in Figure 2 The method 400 can include the following steps.

[0088] In step 401, the number of hardware verification boards required for hardware verification of the to-be-tested design is estimated, and it is determined whether the decimal part of the number is less than a threshold value.

[0089] In some exemplary embodiments, the number of hardware verification boards required for hardware verification of the to-be-tested design is estimated, including: Based on the total amount of resources required for hardware verification of the design under test and the amount of resources provided by the hardware verification board, the design under test is simulated to be cut, and the required number of hardware verification boards for hardware verification of the design under test is obtained.

[0090] In some embodiments, the amount of resources provided by a hardware verification board is defined as a, the amount of resources provided by an extension circuit board is defined as b, the total amount of resources required for hardware verification of the design under test is defined as c, and the number of hardware verification boards included in a hardware verification device is defined as d.

[0091] Wherein, 0.05a ≤ b ≤ 0.67a (wherein, 0.05 and 0.67 are values preset by users according to experience, which can be adjusted according to actual conditions, and the upper limit (for example, 0.67) can be between 0.5 and 0.8), and d is a positive integer not less than 1, and optionally, d is not greater than 4.

[0092] As an example, according to the amount of resources a provided by a hardware verification board, the design under test with a total amount of required resources c is simulated to be cut, and the amount of resources required by each part of the design under test after cutting is not greater than the amount of resources a provided by a hardware verification board, and the required number of hardware verification boards for hardware verification of the design under test is obtained, which can be composed of an integer part and a decimal part.

[0093] It should be understood that the simulated cutting refers to the simulation of cutting the design under test before the actual cutting, so as to estimate the required number of hardware verification boards for hardware verification of the design under test.

[0094] In some embodiments, the cutting can be performed by the simulation tool 202 or the host 100.

[0095] It should be understood that the cutting here does not mean actually cutting the design under test into multiple separated designs, but only determines the signals to be probed through virtual "cutting".

[0096] A design under test can include multiple nodes that generate signal outputs. For example, the nodes of the design under test can include sequential logic circuits, combinational logic circuits, memories, or external signal sources. The connection lines between the nodes can be referred to as edges.

[0097] Cutting the design under test is to cut the edges with virtual cutting lines. The method of cutting the design under test can be any cutting method. In some embodiments, the design under test can be cut according to the minimum cutting method. The minimum cutting method can ensure that the number of edges between each block is the smallest while keeping the number of sequential logic circuits in each block substantially the same.

[0098] In some embodiments, the min-cut method can employ any of the following exemplary methods: Heavy Edge Matching (HEM), Greedy Graph Growing Partition (GGGP), Fiduccia-Mattheyses (FM) algorithm, etc. By min-cut, the number of sequential logic circuits (e.g., flip-flops) associated with each block can be minimized, and thus the number of signals of the sequential logic circuits required for probing each block can also be minimized.

[0099] In some embodiments, the partitioning of the design under test can be performed recursively in a binary manner. For example, the design under test can be partitioned into 2 blocks, each of which can be further partitioned into 2 blocks, and the process can be repeated until the number of blocks meets the requirement. The number of blocks after the final partitioning depends on the design under test and the design requirements. In some embodiments, the partitioning can be performed in an equal, unequal, or a combination of both manner.

[0100] In some exemplary embodiments, the determination of whether the fractional part of the required number is less than a threshold value, which is a value pre-set by the user based on experience, can be adjusted according to actual conditions, for example, it can be between 0.5 and 0.8, for example, 0.67.

[0101] When the granularity of the user is a piece of hardware verification board, that is, as long as a piece of hardware verification board is saved, it is saved. Then: Definition: such as n×a<c ≤ n×a + m×b, m is the maximum positive integer that satisfies the condition m×b ≤ 0.67a, n is a positive integer, and 0.67 is the threshold value.

[0102] Where 0.67 is an empirical value, which can be adjusted according to actual conditions, for example, it can be between 0.5 and 0.8.

[0103] Where a is the amount of resources provided by a piece of hardware verification board, b is the amount of resources provided by a piece of extension circuit board, c is the total amount of resources required for hardware verification of the design under test, n is the number of hardware verification boards, and m is the number of extension circuit boards.

[0104] When the granularity of the user is a piece of hardware verification board (i.e., d pieces of hardware verification board), that is, as long as a piece of hardware verification board is saved, it is saved. Then: Definition: such as n×d×a<c ≤ n×d×a + m×b, m is the maximum positive integer that satisfies the condition m×b ≤ 0.67×d×a, n is a positive integer, and 0.67 is the threshold value.

[0105] wherein 0.67 is an empirical value, which can be adjusted according to actual conditions, for example, can be between 1 / d~0.8.

[0106] wherein a is the resource amount provided by a piece of hardware verification board, b is the resource amount provided by a piece of extension circuit board, c is the total resource amount required for hardware verification of the design under test, d is the number of pieces of hardware verification board contained in a hardware verification device, n is the number of hardware verification boards, and m is the number of extension circuit boards.

[0107] At step 402, in response to determining that the decimal part of the required quantity is less than a threshold value, the design under test is cut and allocated to hardware verification boards and extension circuit boards for hardware verification.

[0108] In some example embodiments, the hardware verification includes prototype verification and hardware simulation.

[0109] wherein the hardware simulation is an application focusing on simulating the function of the DUT; the prototype verification is a function focusing on running the embedded system on the board to develop the embedded system. The carriers of the prototype verification and the hardware simulation are both hardware verification boards and extension sub-cards.

[0110] In some example embodiments, the cutting and allocating of the design under test to hardware verification boards and extension circuit boards for hardware verification includes: cutting the design under test into a first part allocated to the hardware verification boards and a second part allocated to the extension circuit boards; generating a first executable file corresponding to the first part and generating a second executable file corresponding to the second part; allocating the first executable file to the hardware verification boards and allocating the second executable file to the extension circuit boards; running the first executable file on the hardware verification boards and running the second executable file on the extension circuit boards.

[0111] In some example embodiments, the cutting of the design under test into a first part allocated to the hardware verification boards and a second part allocated to the extension circuit boards includes: cutting the design under test into the first part allocated to the hardware verification boards and the second part allocated to the extension circuit boards based on the total resource amount required for hardware verification of the design under test, the resource amount provided by the hardware verification boards, and the resource amount provided by the extension circuit boards.

[0112] When the granularity of the user is a hardware verification board, that is, as long as a hardware verification board can be saved, it is saved. The cutting method is to cut the to-be-tested design which needs a total of c resources into n first parts distributed on hardware verification boards with a resource of a and m second parts distributed on extension circuit boards with a resource of b: c ≤ n×a + m×b, m is the maximum positive integer satisfying the condition m×b ≤ 0.67a, n is a positive integer, and 0.67 is a threshold value.

[0113] 0.67 is an empirical value and can be adjusted according to actual conditions, for example, it can be between 0.5 and 0.8.

[0114] a is the resource provided by a hardware verification board, b is the resource provided by an extension circuit board, c is the total resource needed for hardware verification of the to-be-tested design, n is the number of hardware verification boards, and m is the number of extension circuit boards.

[0115] When the granularity of the user is a hardware verification device (that is, d pieces of hardware verification boards), that is, as long as a hardware verification device can be saved, it is saved. The cutting method is to cut the to-be-tested design which needs a total of c resources into n first parts distributed on hardware verification devices (that is, d pieces of hardware verification boards) with a resource of d×a and m second parts distributed on extension circuit boards with a resource of b: c ≤ n×d×a + m×b, m is the maximum positive integer satisfying the condition m×b ≤ 0.67×d×a, n is a positive integer, and 0.67 is a threshold value.

[0116] 0.67 is an empirical value and can be adjusted according to actual conditions, for example, it can be between 1 / d and 0.8.

[0117] a is the resource provided by a hardware verification board, b is the resource provided by an extension circuit board, c is the total resource needed for hardware verification of the to-be-tested design, d is the number of hardware verification boards contained in a hardware verification device, n is the number of hardware verification boards, and m is the number of extension circuit boards.

[0118] In some example embodiments, the generating the second executable file corresponding to the second part comprises: determining an idle port on the hardware verification board; generating a connection scheme of the hardware verification board and the extension circuit board based on the idle port; generating the second executable file corresponding to the second part based on the connection scheme.

[0119] In some example embodiments, the distributing the second executable file to the extension circuit board comprises: connect the hardware verification board and the extension circuit board based on the connection scheme; allocate the second executable file to the connected extension circuit board.

[0120] In some example embodiments, the connecting the hardware verification board and the extension circuit board based on the connection scheme comprises: connecting a port of the extension circuit board and the idle port of the hardware verification board through an interconnection cable based on the connection scheme; wherein one of a pin header or a pin socket is arranged on the interconnection cable, and the other of the pin header or the pin socket is arranged on the port of the extension circuit board and the idle port of the hardware verification board.

[0121] As can be seen from the above, the hardware verification method provided by the embodiments of the present disclosure comprises: estimating a required number of hardware verification boards required for hardware verification of a design under test, determining whether a decimal part of the required number is less than a threshold value; and in response to determining that the decimal part of the required number is less than the threshold value, cutting and allocating the design under test to hardware verification boards and extension circuit boards for hardware verification.

[0122] When the size of the design under test only slightly exceeds the capacity of a single hardware verification board, hardware verification can be realized by the extension circuit board cooperating with the hardware verification board, without occupying an additional whole hardware verification board, thereby saving cost and improving the utilization rate of the hardware verification board.

[0123] The embodiments of the present disclosure further provide an electronic device. The electronic device can be a host 100. Figure 1 The host 100 can include a memory configured to store a set of instructions, and at least one processor configured to execute the set of instructions to cause the electronic device to perform the method 400.

[0124] The embodiments of the present disclosure further provide a non-transitory computer-readable storage medium. The non-transitory computer-readable storage medium stores a set of instructions of a computer, and the set of instructions is configured to cause the electronic control device to perform the method 400 when executed.

[0125] The above describes some embodiments of the present disclosure. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims can be performed in a different order than the order in which they are recited and still achieve desirable results. In addition, the processes depicted in the figures do not necessarily require the particular order shown, or sequential order, to achieve the desired results. In certain implementations, multitasking and parallel processing can be advantageous. Those of ordinary skill in the art will realize and understand that the discussion of any of the above embodiments is merely exemplary and is not intended to suggest that the scope of the application, including the claims, is in any way limited to such examples; the embodiments or technical features from different embodiments can be combined, the steps can be implemented in any order, and there are many other variations of the different aspects of the application as described above, which are not expressly mentioned in detail but which are within the scope of the application. For the sake of brevity, the numerous details of construction and operation, and the specific preferred embodiments, are not set forth in detail in the description above and are considered to be within the scope of the application.

[0126] Although the application has been described in conjunction with specific embodiments thereof, numerous alternatives, modifications, and variations will be readily apparent to those of ordinary skill in the art. For example, other memory architectures (e.g., dynamic RAM (DRAM)) can use the embodiments discussed.

[0127] It is therefore intended that the application be deemed to include all such alternatives, modifications and variations as falling within the broad scope of the appended claims. Accordingly, any and all such modifications, variations or equivalents that fall within the scope of the application are intended to be embraced by the claims.

Claims

1. A hardware verification method, characterized by, The method comprises: estimating the required number of hardware verification boards required for hardware verification of a design under test, and determining whether the decimal part of the required number is less than a threshold value; in response to determining that the decimal part of the required number is less than the threshold value, cutting and distributing the design under test to hardware verification boards and extension circuit boards for hardware verification.

2. The method of claim 1, wherein, The estimation of the required number of hardware verification boards required for hardware verification of a design under test comprises: based on the total amount of resources required for hardware verification of the design under test and the amount of resources provided by the hardware verification boards, simulating cutting of the design under test to obtain the required number of hardware verification boards required for hardware verification of the design under test.

3. The method of claim 1, wherein, The cutting and distributing of the design under test to hardware verification boards and extension circuit boards for hardware verification comprises: cutting the design under test into a first part distributed to the hardware verification boards and a second part distributed to the extension circuit boards; generating a first executable file corresponding to the first part and generating a second executable file corresponding to the second part; distributing the first executable file to the hardware verification boards and distributing the second executable file to the extension circuit boards; running the first executable file on the hardware verification boards and running the second executable file on the extension circuit boards.

4. The method of claim 3, wherein, The cutting of the design under test into a first part distributed to the hardware verification boards and a second part distributed to the extension circuit boards comprises: based on the total amount of resources required for hardware verification of the design under test, the amount of resources provided by the hardware verification boards, and the amount of resources provided by the extension circuit boards, cutting the design under test into the first part distributed to the hardware verification boards and the second part distributed to the extension circuit boards.

5. The method of claim 3, wherein, The generation of the second executable file corresponding to the second part comprises: determining idle ports on the hardware verification boards; generating a connection scheme of the hardware verification boards and the extension circuit boards based on the idle ports; based on the connection scheme, generating the second executable file corresponding to the second part.

6. The method of claim 5, wherein, The distribution of the second executable file to the extension circuit boards comprises: based on the connection scheme, connecting the hardware verification boards and the extension circuit boards; distributing the second executable file to the connected extension circuit boards.

7. The method of claim 6, wherein, The connection of the hardware verification boards and the extension circuit boards based on the connection scheme comprises: based on the connection scheme, connecting ports of the extension circuit boards and the idle ports of the hardware verification boards through interconnection cables; wherein one of a pin header or a pin socket is arranged on the interconnection cables, and the other of the pin header or the pin socket is arranged on the ports of the extension circuit boards and the idle ports of the hardware verification boards.

8. An electronic device, comprising: A computer program product comprises a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the processor executes the program to implement the method of any one of claims 1 to 7.

9. A non-transitory computer-readable storage medium, comprising: The non-transitory computer readable storage medium stores computer instructions for causing a computer to perform the method of any one of claims 1 to 7.

10. A computer program product, characterised in that, Computer program instructions are included which, when run on a computer, cause the computer to perform the method of any one of claims 1 to 7.

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