Memory management method and memory controller

Abstract

The invention discloses a memory management method and a memory controller. The method comprises the steps that a writing instruction is received, the writing instruction comprises to-be-written data and a corresponding first data attribute, and the to-be-written data is cached; according to the first data attribute, configuring a corresponding weight factor for the cached to-be-written data; when it is monitored that the data size of the cached to-be-written data meets a preset starting condition, the number of access times of the cached to-be-written data is counted in a preset statistical period; calculating an effective access value according to the access times and the weight factor; comparing the effective access value with at least one preset threshold value to determine a second data attribute of the cached to-be-written data; and according to the second data attribute, storing the cached to-be-written data to a corresponding storage area. According to the method and the device, the pre-judgment result of the host end and the actual access statistics of the memory end are combined, and the data attribute is reconfirmed before the data is written into the memory module, so that storage resource waste caused by data placement errors is reduced.

Description

Technical Field

[0001] This disclosure relates to the field of data storage technology, and in particular to a memory management method and memory controller for optimizing hierarchical data storage. Background Technology

[0002] In the field of data storage, "hot data" refers to data that is frequently accessed and requires a fast response time; it is typically placed on high-performance storage media. "Cold data," on the other hand, refers to data that is rarely accessed but needs to be retained for a long time; it is typically placed on high-density storage media. By classifying data into hot and cold categories and storing it in the corresponding storage areas, storage space utilization efficiency can be improved while meeting access performance requirements.

[0003] Currently, to achieve hot and cold data separation, the host typically determines the hot / cold attribute of data based on file attributes (such as file type, application source, etc.) and writes the data stream with the corresponding tag to the storage device. However, the hot / cold data determination based on file attributes on the host only represents the intended use of the data and cannot reflect the actual user access behavior. When the actual access behavior is inconsistent with the intended use, it may lead to incorrect hot / cold data partitioning and improper data placement. For example, high-performance caches may be occupied by data with low actual access frequency, or data with high actual access frequency may be degraded to low-speed areas, ultimately leading to increased write amplification of the storage device and a decrease in overall performance. Summary of the Invention

[0004] In view of this, the present disclosure provides a memory management method and a memory controller, which, by combining the first data attributes issued by the host with the actual access statistics at the memory end, reconfirms the data attributes before writing data to the memory module, thereby improving the accuracy of hot and cold data classification, reducing data placement errors caused by inaccurate predictions at the host end, and thus improving the performance of the storage device and the utilization efficiency of storage resources.

[0005] One or more embodiments of this disclosure provide a memory management method, including: receiving a write instruction, the write instruction including data to be written and a corresponding first data attribute, and caching the data to be written; configuring a corresponding weight factor for the cached data to be written according to the first data attribute; when the amount of cached data to be written is detected to meet a preset start condition, counting the number of accesses to the cached data to be written within a preset statistical period; calculating a valid access value based on the number of accesses and the weight factor; comparing the valid access value with at least one preset threshold to determine a second data attribute of the cached data to be written; and storing the cached data to be written in a corresponding storage area according to the second data attribute.

[0006] One or more embodiments of this disclosure provide a memory controller suitable for a storage device configured with a memory module. The memory controller includes: a memory interface control circuit electrically connected to the memory module; and a processor electrically connected to the memory interface control circuit. The processor is configured to: receive a write instruction, the write instruction including data to be written and a corresponding first data attribute, and cache the data to be written; configure a corresponding weight factor for the cached data to be written according to the first data attribute; when the amount of cached data to be written is detected to meet a preset start condition, count the number of accesses to the cached data to be written within a preset statistical period; calculate a valid access value based on the number of accesses and the weight factor; compare the valid access value with at least one preset threshold to determine a second data attribute of the cached data to be written; and store the cached data to be written in a corresponding storage area according to the second data attribute.

[0007] Based on the above, the memory management method provided in this disclosure, by receiving a write instruction containing a first data attribute and converting it into a weighting factor to correct the actual number of accesses in the buffer memory, effectively improves the accuracy of data classification by combining prior judgment on the host side with real-time statistics on the memory side. Furthermore, this disclosure completes the final determination of the data attribute (second data attribute) during the caching stage before the data is written to the non-volatile memory, and accordingly distributes the data to the corresponding storage area. This strategy avoids subsequent data migration due to misjudgment, thereby reducing write amplification, optimizing the allocation of storage resources, and extending the lifespan of the storage device while improving system performance. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of the system architecture of the storage device and host system according to an embodiment of the present disclosure;

[0009] Figure 2 This is a main flowchart of a memory management method according to an embodiment of the present disclosure;

[0010] Figure 3 This is a schematic diagram illustrating the first data attribute determination criteria according to an embodiment of this disclosure;

[0011] Figure 4 This is a schematic diagram illustrating the calculation of valid access values ​​according to an embodiment of this disclosure;

[0012] Figure 5 This is a schematic diagram illustrating the weight factor configuration and second data attribute determination according to an embodiment of this disclosure;

[0013] Figure 6 This is a schematic diagram illustrating a layered writing strategy according to an embodiment of the present disclosure;

[0014] Figure 7 This is a flowchart illustrating a dynamic threshold adjustment mechanism according to an embodiment of the present disclosure;

[0015] Figure 8 This is a timing diagram of a memory management method according to an embodiment of the present disclosure;

[0016] Figure 9 This is a schematic diagram showing the triggering of a preset start-up condition according to an embodiment of the present disclosure;

[0017] Figure 10 This is a schematic diagram of the time axis for dynamic threshold adjustment according to an embodiment of the present disclosure. Detailed Implementation

[0018] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component reference numerals are used in the drawings and description to denote the same or similar parts.

[0019] Figure 1 This is a block diagram illustrating a host system and storage device according to embodiments of the present disclosure. Please refer to... Figure 1 The host system 10 is, for example, a personal computer, a laptop computer, or a server. The host system 10 includes a processor 110 (also called a second processor), host memory 120 (also called host RAM), and a data transfer interface circuit 130. In this embodiment, the processor 110 is coupled (also called electrically connected) to the host memory 120 and the data transfer interface circuit 130. In another embodiment, the processor 110, host memory 120, and data transfer interface circuit 130 are electrically connected to each other via a system bus. In this embodiment, the processor 110, host memory 120, and data transfer interface circuit 130 may be disposed on the motherboard of the host system 10.

[0020] The storage device 20 includes a memory controller 210, a memory module 220 (also known as a rewritable non-volatile memory module), and a connection interface circuit 230. The memory controller 210 includes a processor 211 (also known as a first processor), a data management circuit 212, a memory interface control circuit 213, and a buffer memory 214.

[0021] In this embodiment, the host system 10 is electrically connected to the storage device 20 via a data transmission interface circuit 130 and a connection interface circuit 230 to perform data access operations. For example, the host system 10 can store data to or read data from the storage device 20 via the data transmission interface circuit 130.

[0022] In this embodiment, the number of data transmission interface circuits 130 can be one or more. Through the data transmission interface circuits 130, the motherboard can be electrically connected to the storage device 20 via wired or wireless means. The storage device 20 can be, for example, a USB flash drive, memory card, solid-state drive (SSD), or wireless storage device. The wireless storage device can be, for example, a Near Field Communication (NFC) storage device, a WiFi storage device, a Bluetooth storage device, or a Bluetooth Low Energy storage device (e.g., iBeacon), or other storage devices based on various wireless communication technologies. Furthermore, the motherboard can also be electrically connected via the system bus to various I / O devices such as a Global Positioning System (GPS) module, network interface card, wireless transmission device, keyboard, screen, and speaker.

[0023] In this embodiment, the data transmission interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with the Peripheral Component Interconnect Express (PCI Express) standard. Furthermore, data transmission between the data transmission interface circuit 130 and the connection interface circuit 230 utilizes the Non-Volatile Memory Express (NVMe) communication protocol.

[0024] In another embodiment, the connection interface circuit 230 may be packaged in a chip with the memory controller 210, or the connection interface circuit 230 may be disposed outside a chip containing the memory controller 210.

[0025] In this embodiment, the host memory 120 is used to temporarily store instructions or data executed by the processor 110. In this embodiment, the host memory 120 may be Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), etc. However, it should be understood that this disclosure is not limited to this, and the host memory 120 may also be other suitable memories.

[0026] The memory controller 210 is used to execute multiple logic gates or control instructions implemented in hardware or firmware, and to perform operations such as writing, reading and erasing data in the memory module 220 according to the instructions of the host system 10, and to execute the memory management method provided in this disclosure.

[0027] More specifically, the processor 211 in the memory controller 210 is hardware with computing capabilities, used to control the overall operation of the memory controller 210. Specifically, the processor 211 is programmed with multiple control instructions / program codes, and these control instructions / program codes are executed when the storage device 20 is operating to perform operations such as writing, reading, and erasing data.

[0028] Furthermore, the processor 211 is configured to execute the memory management method provided in this disclosure. Specifically, the processor 211 receives a write instruction, which includes data to be written and a corresponding first data attribute, and controls the buffer memory 214 to cache the data to be written; the processor 211 configures a corresponding weight factor for the cached data to be written according to the first data attribute; when the processor 211 detects that the amount of cached data to be written meets a preset start condition, the processor 211 counts the number of accesses to the cached data to be written within a preset statistical period; the processor 211 calculates a valid access value based on the number of accesses and the weight factor; the processor 211 compares the valid access value with at least one preset threshold to determine a second data attribute of the cached data to be written; and the processor 211 stores the cached data to be written into the corresponding storage area according to the second data attribute.

[0029] It should be noted that in this disclosure, "data attribute" is used to characterize the activity level, access frequency, or importance level of data in the storage system. Specifically, the first data attribute and the second data attribute may refer to the data's popularity level (e.g., hot attribute, warm attribute, cold attribute), access frequency level (e.g., high-frequency access, low-frequency access), or data lifecycle characteristics. In some embodiments, it may also be directly referred to as "data attribute". In the following description of embodiments, for ease of understanding of the technical solution, "data attribute" is mainly used as a specific example of a data attribute for illustration, but this does not constitute a limitation on the scope of protection of this disclosure.

[0030] In this disclosure, the memory module 220 includes multiple different types of storage areas for storing data with thermal, warm, and cold attributes according to a second data attribute. Specifically, the storage areas may include single-level cell (SLC) storage areas, multi-level cell (MLC) storage areas, triple-level cell (TLC) storage areas, and quad-level cell (QLC) storage areas. Here, a single-level cell refers to each storage cell configured to store 1 bit of data with 2 different voltage states; a multi-level cell refers to each storage cell configured to store 2 bits of data with 4 different voltage states; a triple-level cell refers to each storage cell configured to store 3 bits of data with 8 different voltage states; and a quad-level cell refers to each storage cell configured to store 4 bits of data with 16 different voltage states. Generally, as the number of bits that each storage cell can store increases, the storage density increases and the unit cost decreases, but its read / write speed and erase / write durability usually decrease accordingly. Therefore, this disclosure utilizes the high performance characteristics of single-layer or multi-layer cells to store thermal attribute data, and utilizes the high density characteristics of three-layer or four-layer cells to store cold attribute data.

[0031] However, it must be understood that the embodiments of this disclosure are not limited to the specific flash memory types described above. With the evolution of semiconductor memory technology, the memory module 220 may also include a five-level cell (PLC) memory area or a higher-level memory cell area capable of storing more bits of data. For example, in a five-level cell architecture, each memory cell is configured to store 5 bits of data, corresponding to 32 voltage states. The memory management method provided in this disclosure is also applicable to these higher-density storage media. By allocating extremely cold data to ultra-high-density areas such as five-level cells, the cost-effectiveness and capacity utilization of the storage device 20 can be further optimized.

[0032] It is worth mentioning that, in this embodiment, the processor 110 and the processor 211 are, for example, a central processing unit (CPU), a microprocessor, or other programmable processing units (microprocessor), digital signal processor (DSP), programmable controller, application specific integrated circuits (ASIC), programmable logic device (PLD), or other similar circuit components, and this disclosure is not limited thereto.

[0033] In this embodiment, as described above, the memory controller 210 further includes a data management circuit 212 and a memory interface control circuit 213. It should be noted that the operations performed by each component of the memory controller 210 can also be considered as operations performed by the memory controller 210 itself.

[0034] The data management circuit 212 is electrically connected to the processor 211, the memory interface control circuit 213, and the connection interface circuit 230. The data management circuit 212 receives instructions from the processor 211 to perform data transmission. For example, it reads data from the host system 10 (e.g., host memory 120) via the connection interface circuit 230 and writes the read data to the memory module 220 via the memory interface control circuit 213. Alternatively, it performs a read operation according to a read instruction from the host system 10, reads data from one or more physical units of the memory module 220 via the memory interface control circuit 213, and writes the read data to the host system 10 via the connection interface circuit 230. In one embodiment, the data management circuit 212 receives a write instruction under the instruction of the processor 211 and writes the data to be written to the buffer memory 214. Simultaneously, within a preset statistical period, it works with the processor 211 to count the number of read hits and write hits of the cached data to be written to form an access count, and provides the access count to the processor 211 for calculating the valid access value and determining the second data attribute.

[0035] In another embodiment, the data management circuit 212 may also be integrated into the processor 211. The memory interface control circuit 213 is used to receive instructions from the processor 211 and cooperate with the data management circuit 212 to perform write (also known as programming) operations, read operations, or erase operations on the memory module 220.

[0036] Furthermore, data to be written to memory module 220 is converted into a format acceptable to memory module 220 via memory interface control circuit 213. Specifically, if processor 211 needs to access memory module 220, processor 211 transmits a corresponding instruction sequence to memory interface control circuit 213 to instruct memory interface control circuit 213 to perform the corresponding operation. For example, these instruction sequences may include write instruction sequences indicating the writing of data, read instruction sequences indicating the reading of data, erase instruction sequences indicating the erasure of data, and corresponding instruction sequences for indicating various memory operations. These instruction sequences may include one or more signals, or data on the bus. These signals or data may include instruction codes or program codes. For example, a read instruction sequence may include information such as the read identification code, memory address, and physical address.

[0037] Furthermore, the memory controller 210 establishes a logical-to-physical address mapping table and a physical-to-logical address mapping table to record the mapping relationship between the logical addresses of logical units (e.g., logical blocks, logical pages) and the physical addresses (physical addresses) of physical units (e.g., physical erase units / physical blocks, physical pages) configured for the memory module 220. In other words, the memory controller 210 can use the logical-to-physical address mapping table (also called the logical-to-physical mapping table) to find the physical unit mapped to a logical unit (e.g., find the physical page mapped to a logical page; find the physical address mapped to a logical address), and the memory controller 210 can use the physical-to-logical address mapping table (also called the physical-to-logical mapping table) to find the logical unit mapped to a physical unit (e.g., find the logical page mapped to a physical page; find the logical address mapped to a physical address).

[0038] Buffer memory 214 is electrically connected to processor 211 and is used to temporarily store data and instructions from host system 10, data from memory module 220, and various system data for managing storage device 20. In this embodiment, buffer memory 214 is also used to store cached data to be written, a first data attribute corresponding to the cached data to be written, a weighting factor, access count, valid access value, at least one preset threshold, and a second data attribute required by this disclosure.

[0039] The memory module 220 is electrically connected to the memory controller 210 (specifically, electrically connected to the memory interface control circuit 213) and is used to store user data sent by the host system 10. In this disclosure, the memory module 220 includes a storage area for storing cached data to be written according to a second data attribute.

[0040] In one embodiment, the memory cell structure of the memory module 220 can be understood as a multi-layered physical organization architecture. Specifically, the memory module 220 includes multiple chips, each chip has multiple planes, and each plane contains multiple physical blocks, each physical block consisting of multiple physical pages. It should be noted that this disclosure is not limited to the specific size of each physical page and logical page.

[0041] Figure 2 This is a main flowchart of a memory management method according to an embodiment of the present disclosure. Please refer to... Figure 2 , Figure 2 This is a main flowchart of a memory management method according to an embodiment of the present disclosure. In one embodiment, the memory management method provided by the present disclosure (the process includes steps S210 to S260) is executed by a memory controller 210, which can be implemented by a processor 211 in the memory controller 210 executing corresponding control instructions / program modules.

[0042] In step S210, the memory controller 210 receives a write instruction, which includes the data to be written and the corresponding first data attribute, and caches the data to be written. Specifically, in one embodiment, the host system 10 sends a write instruction to the storage device 20 through the data transmission interface circuit 130, and the memory controller 210 receives the write instruction through the connection interface circuit 230. In addition to the data to be written itself, the write instruction also carries the first data attribute pre-determined by the host system 10. The first data attribute is a classification result (such as hot / cold rating) pre-determined by the host system 10 based on the relevant attribute information of the data to be written, used to characterize the host system 10's expectation of the access frequency of the data. After receiving the write instruction, the memory controller 210 stores the data to be written in the buffer memory 214, making the data to be written cached data. By caching the data to be written in the buffer memory 214 instead of immediately writing it to the memory module 220, the memory controller 210 can observe and statistically analyze the actual access behavior of the cached data to be written in subsequent processes.

[0043] In step S220, the memory controller 210 configures a corresponding weight factor for the cached data to be written based on the first data attribute. Specifically, in one embodiment, the memory controller 210 pre-establishes a correspondence between the first data attribute and the weight factor. When the memory controller 210 receives a write instruction carrying the first data attribute, it queries the corresponding weight factor based on the first data attribute and associates the weight factor with the cached data to be written. The configuration of the weight factor enables the memory controller 210 to take into account the prediction information of the host system 10 when calculating the effective access value, thereby achieving a combination of host-side prediction and memory-side statistics.

[0044] In one embodiment, the host system 10 classifies the first data attribute into three levels—hot, warm, and cold—based on the attribute information of the data to be written. Hot attributes typically correspond to data with a high expected access frequency, warm attributes to data with a medium expected access frequency, and cold attributes to data with a low expected access frequency. Upon receiving a write instruction carrying the first data attribute, the memory controller 210 configures corresponding weight factors for the cached data to be written, based on the specific category of the first data attribute. Specifically, when the first data attribute corresponding to the cached data to be written is a hot attribute, the memory controller 210 configures a first value as the weight factor for that cached data; when the first data attribute is a warm attribute, the memory controller 210 configures a second value as the weight factor; and when the first data attribute is a cold attribute, the memory controller 210 configures a third value as the weight factor. In this embodiment, the first value is greater than the second value, and the second value is greater than the third value, so that data predicted by the host system 10 to be hot receives a higher weight adjustment in subsequent calculations, while data predicted to be cold receives a lower weight adjustment.

[0045] In step S230, when the amount of cached data to be written meets the preset start condition, the memory controller 210 counts the number of accesses to the cached data to be written within a preset statistical period. Specifically, in one embodiment, the memory controller 210 continuously monitors the cumulative amount of cached data to be written in the buffer memory 214. When the cumulative amount of data reaches the threshold specified by the preset start condition, the memory controller 210 starts the statistical mechanism and begins recording the number of times the cached data to be written is accessed by the host system 10 within the preset statistical period. The setting of the preset start condition ensures that the statistical mechanism is started only after a certain amount of data has accumulated, avoiding the lack of representativeness of the statistical results due to insufficient data. The preset statistical period provides a clear time range for the statistics of access counts, enabling the statistical results to reflect the actual access frequency of the cached data to be written within a specific time window.

[0046] In step S240, the memory controller 210 calculates the effective access value based on the access count and weighting factor. Specifically, in one embodiment, after the preset statistical period ends, the memory controller 210 obtains the access count of the cached data to be written within the preset statistical period, and performs an operation (e.g., multiplication) with the previously configured weighting factor to obtain the effective access value. The calculation of the effective access value integrates the actual access behavior and the host-side prediction information, enabling subsequent data attribute determination to simultaneously consider the actual access frequency of the data and the prediction results provided by the host system 10 based on the attribute information.

[0047] In step S250, the memory controller 210 compares the valid access value with at least one preset threshold to determine a second data attribute of the cached data to be written. Specifically, in one embodiment, the memory controller 210 pre-sets at least one preset threshold as a boundary standard for data attribute determination. The memory controller 210 compares the calculated valid access value with at least one preset threshold and determines the second data attribute of the cached data to be written based on the comparison result. The second data attribute is the final classification result determined by the memory controller 210 after comprehensively considering the host-side prediction information and the actual access statistics. Compared with the first data attribute that only relies on the host-side prediction, the second data attribute can more accurately reflect the actual access frequency of the cached data to be written.

[0048] In step S260, the memory controller 210 stores the cached data to be written to the corresponding storage area according to the second data attribute. Specifically, in one embodiment, the memory module 220 includes multiple storage areas, each with different access performance characteristics. The memory controller 210 selects the storage area in the memory module 220 corresponding to the second data attribute of the cached data to be written, and writes the cached data to be written from the buffer memory 214 to the selected storage area. By storing the cached data to be written to the corresponding storage area according to the second data attribute, the memory controller 210 can store data with high access frequency in the storage area with better access performance, while storing data with low access frequency in the storage area with higher storage density, thereby improving the utilization efficiency of storage space while meeting access performance requirements.

[0049] In another embodiment, after step S210 is executed, step S230 is executed first, and then step S220 is executed.

[0050] In another embodiment, the memory controller 210 may execute steps S220 to S260 for each of the multiple cached data entries to be written in the buffer memory 214, to determine the second data attribute of each cached data entry and store each cached data entry to its corresponding storage area. Through this memory management method, the memory controller 210 can reconfirm the data attributes of the data before writing it to the memory module 220, combining the host's prediction results with the actual access statistics of the memory, thereby reducing improper data placement caused by host-side prediction bias and improving the overall performance of the storage device 20. Figure 3 This is a schematic diagram illustrating the first data attribute determination criterion according to an embodiment of this disclosure. Please refer to... Figure 3 In one embodiment, the first data attribute CHV carried in the write instruction WCMD is pre-determined by the host system 10 based on the attribute information INF of the data to be written. As the execution end of the file system and application layer, the host system 10 can obtain the multi-dimensional attribute information INF of the data to be written and predict the access frequency of the data to be written based on the attribute information INF.

[0051] In another embodiment, the attribute information INF includes at least one of file type FT, file attribute FA, and application source AS. For example... Figure 3 As shown on the left, the file type (FT) represents the data format category of the data to be written, which may include media files (such as photos, videos, and audio), database files (such as files with the extension .db or .log), or cache files (such as system cache or application cache). The file attribute (FA) represents the storage nature of the data to be written, which may include temporary files or long-term files. The application source (AS) represents the type of program that initiated the write request, which may include system processes, background services, or user applications. The host system 10 executes the determination logic (DL) to comprehensively determine the first data attribute (CHV) of the data to be written based on one or more of the file type (FT), file attribute (FA), and application source (AS) in the attribute information (INF).

[0052] More specifically, in one embodiment, the host system 10 performs a determination operation on the first data attribute CHV through determination logic DL. For example... Figure 3As shown in the lower left, the decision logic DL receives the file type FT, file attribute FA, and application source AS from the attribute information INF, and queries the mapping rule table T31 according to the attribute information INF to obtain the first data attribute CHV corresponding to the attribute information INF. As shown by arrow A31, the decision logic DL outputs the result of the decision to the first data attribute CHV. The first data attribute CHV includes three levels: hot attribute, warm attribute, and cold attribute, which correspond to data categories with different expected access popularity. After the decision is completed, as shown by arrow A32, the host system 10 encapsulates the first data attribute CHV and the data to be written into a write instruction WCMD. The write instruction WCMD includes the data to be written and its corresponding first data attribute CHV. The host system 10 sends the write instruction WCMD to the storage device 20 through the data transmission interface circuit 130, so that the memory controller 210 can receive and execute subsequent memory management methods.

[0053] For example, when the database management program in host system 10 needs to write a transaction log, host system 10 collects the attribute information INF of the data to be written. In this example, the file type FT is a database file (with the extension .log), the file attribute FA is a temporary file, and the application source AS is a system process. After receiving the above attribute information INF, the decision logic DL queries the mapping rule table T31 for the record corresponding to the database log and obtains the first data attribute CHV as a hot attribute. Host system 10 then encapsulates the hot attribute as the first data attribute CHV, along with the transaction log, into a write instruction WCMD and sends it to memory controller 210. As another example, when the camera application in host system 10 needs to write a photo taken by a user, the file type FT is a media file (photo), the file attribute FA is a long-term storage file, and the application source AS is the user application. The decision logic DL queries the mapping rule table T31 based on the above attribute information INF, obtains the first data attribute CHV as a cold attribute, and encapsulates the cold attribute and the photo into a write instruction WCMD and sends it to memory controller 210. In this way, the host system 10 can pre-determine the corresponding first data attribute CHV for the data to be written with different attribute information INF, so that the memory controller 210 can refer to it in the subsequent process.

[0054] It is worth mentioning that, in another embodiment, when determining the first data attribute CHV through the decision logic DL, the host system 10 can employ a multi-dimensional weighted evaluation mechanism. Specifically, considering that the contribution of attribute information INF of different dimensions to data popularity varies, the decision logic DL can pre-configure different decision weights for file type FT, file attribute FA, and application source AS. For example, application source AS usually reflects the real-time urgency of the data more directly, and therefore can be given a higher weight; while file type FT only represents the format characteristics of the data and can be given a lower weight. When attribute information of different dimensions points to conflicting hot and cold results (for example, file type FT indicates a video file with a cold attribute, but application source AS indicates a system backend service with a hot attribute), the host system 10 determines the final first data attribute CHV based on the weighted calculation result of the score corresponding to each attribute and the decision weight, or according to a preset priority order (such as application source taking precedence over file type). This weighted or priority mechanism ensures that, in complex scenarios, the host system 10 can still output a prediction result that best matches the current system state.

[0055] In another embodiment, the host system 10 pre-establishes a mapping rule table T31 between attribute information and first data attributes to define the correspondence between various attribute information INF and the first data attribute CHV. For example... Figure 3 As shown in the upper right corner, the mapping rule table T31 includes an attribute information field and a first data attribute field. The attribute information field records the specific content of various attribute information INFs; the first data attribute field records the first data attribute CHV corresponding to each type of attribute information INF. The explanatory fields in the mapping rule table T31 are only for explaining the various classification criteria in this embodiment. Specifically, for attribute information such as database logs, system caches, and system process files, which have the characteristics of high-frequency updates and real-time access, the mapping rule table T31 records them as hot attributes in the first data attribute field; for attribute information such as download caches, intermediate processing files, and background service files, which have the characteristics of periodic activity and moderate access frequency, the mapping rule table T31 records them as warm attributes in the first data attribute field; for attribute information such as photos, audio, video, archived documents, and long-term stored files, which have the characteristics of remaining unchanged for a long time after being written and infrequent access, the mapping rule table T31 records them as cold attributes in the first data attribute field. In this embodiment, the host system 10 maintains an attribute information and a first data attribute mapping rule table T31, and executes a judgment logic DL to query the mapping rule table T31 based on the attribute information INF to obtain the first data attribute CHV. After the judgment is completed, the host system 10 encapsulates the first data attribute CHV and the data to be written into a write instruction WCMD, as shown by arrow A32, and sends the write instruction WCMD to the storage device 20 through the data transmission interface circuit 130 for use in subsequent data writing processes.

[0056] It should be noted that this disclosure is not limited to the implementation where the host system 10 determines the first data attribute. In another embodiment, the write command may be generated internally by the storage device 20 or sent to the memory controller 210 by other external devices. In this case, the first data attribute may be determined by the memory controller 210 according to a preset default configuration. Specifically, the memory controller 210 may pre-store a default data attribute configuration. When the write command received by the memory controller 210 does not carry the first data attribute, or when the write command does not originate from the host system 10, the memory controller 210 may assign the first data attribute to the data to be written according to the preset default configuration. In one embodiment, the memory controller 210 may set the default data attribute configuration to a warm attribute, so that data of unknown origin or without data attribute tags receives a moderate weight factor configuration. In another embodiment, the memory controller 210 may also determine the first data attribute itself based on the source type of the write command, data size, or other identifiable characteristics. Through the above configuration, the memory management method of this disclosure can be applied to application scenarios with various write command sources, and is not limited to the case where the host system 10 actively provides the first data attribute.

[0057] Figure 4 This is a schematic diagram illustrating the calculation of valid access values ​​according to an embodiment of this disclosure. Please refer to... Figure 4 In one embodiment, the memory controller 210 counts the number of accesses (SUM) of cached data to be written within a preset statistical period, and calculates the effective access value (EAV) based on the number of accesses (SUM) and the weighting factor (WF). Figure 4 As shown on the left, the access count SUM includes the sum of read hit counts (RHC) and write hit counts (WHC). Read hit counts (RHC) refer to the number of times cached data awaiting write is hit by read commands sent by the host system 10 within a preset statistical period; that is, the number of times the host system 10 requests to read data that is exactly the cached data awaiting write in the buffer memory 214. Write hit counts (WHC) refer to the number of times cached data awaiting write is hit by write commands sent by the host system 10 within a preset statistical period; that is, the number of times the host system 10 requests to write data that corresponds exactly to the cached data awaiting write in the buffer memory 214. In this case, the memory controller 210 updates the cached data awaiting write with new write data.

[0058] In more detail, such as Figure 4As shown, the memory controller 210 records the number of read hits (RHC) and the number of write hits (WHC) within a preset statistical period, using the logical address (e.g., logical block address LBA) corresponding to each cached data to be written as the index for the hit statistics. As shown by arrow A41, the number of read hits (RHC) is input into an addition operation; as shown by arrow A42, the number of write hits (WHC) is also input into an addition operation. The memory controller 210 adds the number of read hits (RHC) and the number of write hits (WHC) to obtain the number of accesses (SUM). The number of accesses (SUM) reflects the total number of times the cached data to be written is actually accessed by the host system 10 within the preset statistical period, regardless of whether the access is a read operation or a write operation, all are included in the statistics. By combining the number of read hits (RHC) and the number of write hits (WHC) for calculation, the memory controller 210 can obtain a comprehensive access frequency index for the cached data to be written.

[0059] In another embodiment, as shown by arrow A43, the access count SUM is input to the multiplication operation MTP. The memory controller 210 simultaneously acquires the weighting factor WF previously configured according to the first data attribute CHV and inputs it to the multiplication operation MTP. The multiplication operation MTP multiplies the access count SUM by the weighting factor WF, as shown by arrow A44, and the result of the multiplication operation MTP is output as the valid access value EAV. The valid access value EAV integrates actual access behavior and host-side predictive information, and its calculation formula can be expressed as: the valid access value EAV equals the access count SUM multiplied by the weighting factor WF, that is, the valid access value EAV equals the sum of the read hit count RHC and the write hit count WHC, multiplied by the weighting factor WF. The memory controller 210 then compares the valid access value EAV with at least one preset threshold to determine the second data attribute of the cached data to be written.

[0060] It is worth mentioning that, in another embodiment, the memory controller 210 can apply the access count SUM to the dynamic adjustment mechanism of the weight factor WF. The memory controller 210 establishes a historical statistics record table in the buffer memory 214 to record the access count SUM of cached data to be written corresponding to each first data attribute CHV within multiple preset statistical periods. Specifically, for each cached data to be written, after the end of its corresponding preset statistical period, the memory controller 210 records the first data attribute CHV and its access count SUM of that cached data to be written in the historical statistics record table. When the historical statistics record table accumulates a certain number of records, the memory controller 210 can calculate the historical average access count corresponding to each first data attribute CHV. The historical average access count refers to the arithmetic mean of the access count SUM of multiple cached data to be written for the same first data attribute CHV within their respective preset statistical periods. The memory controller 210 compares the historical average access count of each first data attribute CHV with a preset expected access count range. When the historical average access count exceeds the expected access count range, the memory controller 210 adjusts the weight factor WF corresponding to the first data attribute CHV accordingly. The aforementioned dynamic adjustment mechanism is an optional implementation method used to further improve the consistency between weight factor configuration and actual access behavior, and does not affect the basic process of configuring corresponding weight factors for cached data to be written based on the first data attribute.

[0061] For example, suppose the memory controller 210 pre-sets the expected number of accesses corresponding to the hot attribute to be 25, and the initial configuration of the weight factor WF corresponding to the hot attribute is 1.4. In the historical statistics record table, the memory controller 210 records 10 cached data entries with the first data attribute CHV as the hot attribute, and their respective access counts (SUM) within the preset statistical period are 18, 22, 20, 19, 21, 23, 17, 20, 22, and 18 times. The memory controller 210 calculates the historical average access count of the above 10 access counts (SUM) to be 20 times. Since the historical average access count of 20 times is lower than the expected number of accesses of 25 times, the memory controller 210 determines that the host system 10's prediction of the hot attribute data deviates from the actual access behavior, and the actual access frequency is lower than expected. Accordingly, the memory controller 210 lowers the weight factor WF corresponding to the hot attribute from 1.4 to 1.2, so that the cached data to be written with the first data attribute CHV as the hot attribute will receive a lower weight adjustment when calculating the effective access value EAV, so that the effective access value EAV can more accurately reflect the actual access frequency of the data.

[0062] In another embodiment, the memory controller 210 can send back the access count SUM and the determination result of the second data attribute to the host system 10, so that the host system 10 can optimize its determination logic DL and mapping rule table T31. Specifically, after completing the determination of the second data attribute of the cached data to be written, the memory controller 210 encapsulates the attribute information INF, the first data attribute CHV, the access count SUM, and the second data attribute of the cached data to be written into feedback information, and sends it back to the host system 10 through the connection interface circuit 230. After receiving the feedback information, the host system 10 compares whether the first data attribute CHV and the second data attribute are consistent. When they are inconsistent, the host system 10 determines that its previous prediction result for the data to be written deviates from the actual access behavior, and generates a corresponding adjustment suggestion notification according to the direction of the deviation. The above-mentioned feedback and optimization mechanism is an optional implementation method used to improve the prediction accuracy on the host side, and does not affect the basic process of the memory controller 210 determining the second data attribute and executing the storage area placement control based on the valid access value and at least one preset threshold.

[0063] More specifically, when the heat level of the second data attribute is higher than that of the first data attribute CHV, the host system 10 generates a heat-up suggestion notification, instructing the judgment logic DL to classify the data to be written with similar attribute information INF as the first data attribute CHV with a higher heat level. When the heat level of the second data attribute is lower than that of the first data attribute CHV, the host system 10 generates a heat-down suggestion notification, instructing the judgment logic DL to classify the data to be written with similar attribute information INF as the first data attribute CHV with a lower heat level. The host system 10 can adjust the first data attribute CHV record with corresponding attribute information INF in the mapping rule table T31 according to the heat-up suggestion notification or the heat-down suggestion notification, so that subsequent data to be written with similar attribute information INF can obtain a more accurate first data attribute CHV judgment result.

[0064] For example, suppose host system 10 has a piece of data to be written with certain attribute information: INF is file type, FT is media file (video), FA is long-term storage file, and AS is user application source. Based on mapping rule table T31, it determines that its first data attribute CHV is a cold attribute. After receiving this data to be written, memory controller 210 counts its access count SUM within a preset statistical period, which is 45 times. Memory controller 210 multiplies the access count SUM by the weighting factor WF to obtain the effective access value EAV, and compares the effective access value EAV with at least one preset threshold to determine that the second data attribute of the cached data to be written is a hot attribute. Memory controller 210 encapsulates the first data attribute CHV (cold attribute), the access count SUM (45 times), and the second data attribute (hot attribute) into feedback information and sends it back to host system 10. After comparison, host system 10 finds that the heat level of the second data attribute (hot attribute) is higher than that of the first data attribute CHV (cold attribute), and therefore generates a heat-up suggestion notification. Based on the temperature rise recommendation notification, the host system 10 adjusts the corresponding record in the mapping rule table T31, where the file type FT is media file (video), the file attribute FA is long-term storage file, and the application source AS is user application, changing its first data attribute CHV from cold to warm or hot. Through the above feedback mechanism, the host system 10 can continuously optimize the accuracy of its judgment of the first data attribute CHV based on the actual access statistics provided by the memory controller 210.

[0065] In one embodiment, to conserve system resources, the processor 211 does not continuously count the actual number of accesses to cached data awaiting writing. The following utilizes... Figure 9 Let me explain in detail.

[0066] Figure 9 This is a schematic diagram illustrating the triggering of a preset start-up condition according to an embodiment of this disclosure. (Refer to...) Figure 9 In one embodiment, the memory controller 210 caches the cached data to be written corresponding to the write instruction in the buffer memory 214 and manages it in the form of data blocks, such as data blocks 1 to 5 and subsequent data blocks as shown in the figure. At the same time, the memory controller 210 continuously monitors the data volume status of the cached data to be written in the buffer memory 214. As shown by arrow A91, the memory controller 210 counts the cumulative capacity CAP and the number of cached valid data blocks CNT for the cached data to be written to determine whether the preset start condition SC is met. The cumulative capacity CAP is the sum of the capacities of all cached data to be written in the current buffer memory 214, and the valid data block refers to the data block that is still valid in the buffer memory 214 and has not yet been written to the corresponding storage area of ​​the memory module 220. When a write hit occurs, the count is updated with the latest written content as the valid content.

[0067] When the cumulative capacity CAP reaches the preset capacity threshold TH_CAP, the preset startup condition SC satisfies condition A; or, when the number of cached valid data blocks CNT reaches the preset quantity threshold TH_CNT, the preset startup condition SC satisfies condition B. Conditions A and B are ORed, allowing the memory controller 210 to initiate subsequent statistical mechanisms based on either the capacity or quantity dimension trigger scenario. As shown by arrow A92, when the preset startup condition SC is determined to be satisfied, the memory controller 210 enters a preset statistical cycle and performs access count statistics on the cached data to be written, for use in subsequent valid access value calculation and second data attribute determination.

[0068] Figure 5 This is a schematic diagram illustrating the weight factor configuration and second data attribute determination according to an embodiment of the present disclosure.

[0069] Reference Figure 5 In one embodiment, the processor 211 of the memory controller 210 performs calculation of valid access values ​​and determination of a second data attribute for cached data to be written. The valid access value is used to combine the number of accesses within a preset statistical period with the weighting factor corresponding to the first data attribute, serving as the basis for determining the second data attribute. Specifically, the processor 211 obtains the first data attribute CHV carried by the write instruction and, as shown by arrow A51, inputs the first data attribute CHV to the weighting factor configuration WFC to configure the corresponding weighting factor. For example, when the first data attribute CHV is a hot attribute, the weighting factor configuration WFC configures a first value as the weighting factor; when the first data attribute CHV is a warm attribute, the weighting factor configuration WFC configures a second value as the weighting factor; when the first data attribute CHV is a cold attribute, the weighting factor configuration WFC configures a third value as the weighting factor, wherein the first value is greater than the second value, and the second value is greater than the third value. Meanwhile, the processor 211 counts the number of accesses SUM of cached data to be written within a preset statistical period, and as shown by arrow A53, inputs the number of accesses SUM into the effective access value calculation AC2. The number of accesses SUM is obtained by summing the number of read hits and the number of write hits, so that the number of accesses SUM can reflect the overall access frequency of cached data to be written in the buffer memory 214 when read hits and write hits are achieved. As shown by arrow A52, the weight factor WF output by the weight factor configuration WFC is also input into the effective access value calculation AC2, so that the processor 211 obtains the effective access value according to the product relationship of "effective access value = number of accesses × weight factor".

[0070] For ease of understanding Figure 4 For practical applications of the calculation mechanism shown, please refer to... Figure 5 The calculation example T51 and threshold determination description T52 are used to illustrate the logic for determining the second data attribute. The calculation example T51 and threshold determination description T52 are for illustration only. In actual operation, the processor 211 performs the operations of weight factor configuration, effective access value AC2 calculation and second data attribute determination for each cached data to be written, without having to establish the above-mentioned tabular data structure.

[0071] For example, suppose the cached data to be written corresponds to "system cache (hot attribute)", "processed file (warm attribute)", "photo file (cold attribute)" and "archive file" respectively, and the processor 211 counts the number of accesses for each of these data within a preset statistical period as 20, 25, 50 and 5 respectively. At the same time, the weight factor configuration WFC configures the first value of 1.4, the second value of 1.2 and the third value of 1.0 for hot attribute, warm attribute and cold attribute respectively. Then the processor 211 can calculate the effective access values ​​as 28, 30, 50 and 5 respectively.

[0072] Next, the processor 211 compares the valid access value with multiple preset thresholds to determine the second data attribute. For example, when the first preset threshold shown in the threshold determination description T52 is 10 and the second preset threshold is 30, if the valid access value is less than or equal to the first preset threshold, the processor 211 determines the second data attribute as a cold attribute; if the valid access value is greater than the first preset threshold and less than or equal to the second preset threshold, the processor 211 determines the second data attribute as a warm attribute; if the valid access value is greater than the second preset threshold, the processor 211 determines the second data attribute as a hot attribute.

[0073] Continuing with the four data entries in the aforementioned calculation example table T51, the memory controller 210 determines the second data attribute of each cached data entry to be written according to the comparison rules in the second data attribute determination table T52. For the first data entry (system cache), its effective access value AC2 is 28, which is greater than the first preset threshold 10 and less than or equal to the second preset threshold 30. Therefore, the memory controller 210 determines its second data attribute to be warm. For the second data entry (processed file), its effective access value AC2 is 30, which is equal to the second preset threshold 30. Therefore, the memory controller 210 determines its second data attribute to be warm. For the third data entry (photo file), its effective access value AC2 is 50, which is greater than the second preset threshold 30. Therefore, the memory controller 210 determines its second data attribute to be hot. For the fourth data entry (archived file), its effective access value AC2 is 5, which is less than or equal to the first preset threshold 10. Therefore, the memory controller 210 determines its second data attribute to be cold. This result indicates that although the photo file was initially identified as a cold attribute based on the attribute information INF, its actual access behavior showed a high access frequency. Based on this, the memory controller 210 reclassified it as a hot attribute, enabling subsequent data storage to more accurately reflect the actual access frequency of the data.

[0074] In summary, by using the first data attribute CHV to provide the initial weight difference and the access count AC1 to reflect the actual access status within the statistical period, the processor 211 can re-determine the cached data to be written based on the valid access value, and output the second data attribute accordingly to support subsequent storage area placement control.

[0075] Figure 6 This is a schematic diagram illustrating a layered writing strategy according to an embodiment of the present disclosure.

[0076] Please refer to Figure 6 In one embodiment, after determining the second data attribute of the cached data to be written, the memory controller 210 executes a hierarchical writing strategy B61 based on the second data attribute, sequentially storing the cached data to be written in the buffer memory 214 into the corresponding storage area in the memory module 220. For example... Figure 6 As shown on the left, buffer memory 214 stores multiple cached data entries awaiting write. Each cached data entry is marked as cold attribute data, warm attribute data, or hot attribute data based on its second data attribute. As indicated by arrow A60, the cached data entries in buffer memory 214 are stored in memory module 220 according to a hierarchical write strategy B61, following a determined storage order.

[0077] like Figure 6As shown in the middle, the hierarchical write strategy B61 defines the time order in which cached data to be written is stored in the memory module 220. In step S610, the memory controller 210 prioritizes storing the first cached data to be written whose second data attribute is "cold" into the corresponding storage area (e.g., the first storage area) in the memory module 220. After all the first cached data to be written with the "cold" attribute has been stored in the memory module 220, in step S620, the memory controller 210 then stores the second cached data to be written whose second data attribute is "warm" into the corresponding storage area in the memory module 220. After all the second cached data to be written with the "warm" attribute has been stored in the memory module 220, in step S630, the memory controller 210 finally stores the third cached data to be written whose second data attribute is "hot" into the corresponding storage area (e.g., the second storage area) in the memory module 220.

[0078] Through the aforementioned hierarchical write strategy B61, data with a cold attribute as the second data attribute is written to memory module 220 first and leaves buffer memory 214, while data with a hot attribute as the second data attribute is written to memory module 220 last and remains in buffer memory 214 for a longer period. Since hot attribute data has a higher access frequency, retaining it in buffer memory 214 for a longer period helps improve the cache hit rate of subsequent access requests; while cold attribute data has a lower access frequency, prioritizing its writing to memory module 220 frees up available capacity in buffer memory 214, preventing low-frequency data from occupying cache space.

[0079] Furthermore, the tiered write strategy B61 allows hot attribute data to be retained in the buffer memory 214 for a longer period, which also reduces write amplification and extends the lifespan of the memory module 220. Because hot attribute data has a high access frequency, it is highly likely that it will be modified again by the host system 10 while it resides in the buffer memory 214. When hot attribute data is modified in the buffer memory 214, the memory controller 210 can directly update the data in the buffer memory 214 without first writing the original data to the memory module 220. If the memory controller 210 writes hot attribute data to the memory module 220 too early, when the host system 10 subsequently sends a write hit for that data, the memory controller 210 needs to write the new data to a new physical page of the memory module 220 and mark the old data in the original physical page as invalid data. This process increases the number of writes to the memory module 220 and the amount of invalid data, thereby increasing the burden on subsequent garbage collection operations. By employing the tiered write strategy B61, hot-attribute data is retained in the buffer memory 214 for a longer period. This allows multiple modification operations on the same data to be merged within the buffer memory 214, ultimately requiring only a single write operation to the memory module 220. This approach reduces the actual number of write operations to the memory module 220, mitigates write amplification, and extends the lifespan of the flash memory cells within the memory module 220.

[0080] For example, suppose a piece of hot attribute data is modified five times consecutively by the host system 10 while it is retained in buffer memory 214. If the memory controller 210 writes this data to the memory module 220 immediately after the first modification, then each of the subsequent four modifications will trigger a write operation to the memory module 220, resulting in a total of five write operations performed by the memory controller 210. Furthermore, the data written in the first four write operations becomes invalid due to subsequent modifications, and the memory controller 210 needs to process this invalid data during subsequent garbage collection. In contrast, if the memory controller 210 retains the hot attribute data in buffer memory 214 until the hierarchical write strategy B61 is completed, all five modification operations are completed in buffer memory 214, and the memory controller 210 ultimately only needs to perform one write operation to the memory module 220, without generating invalid data. In this example, the tiered write strategy B61 reduces the number of writes to memory module 220 from 5 to 1, a reduction of 80%, while avoiding the generation of 4 invalid data entries and their associated garbage collection burden.

[0081] On the other hand, such as Figure 6As shown on the right, the memory module 220 includes multiple storage areas, each corresponding to a different flash memory type area. In this embodiment, the memory module 220 includes at least two of the following: Single-Level Cell (SLC), Multi-Level Cell (MLC), Triple-Level Cell (TLC), and Quad-Level Cell (QLC). Each storage cell in a Single-Level Cell stores 1 bit of data, offering high access speed and a long lifespan; each storage cell in a Multi-Level Cell stores 2 bits of data; each storage cell in a Triple-Level Cell stores 3 bits of data; and each storage cell in a Quad-Level Cell stores 4 bits of data, offering high storage density but relatively low access speed. The memory controller 210 selects the flash memory type area in the memory module 220 corresponding to the second data attribute for storage based on the second data attribute of the cached data to be written.

[0082] In one embodiment, the correspondence between each storage region in the memory module 220 and the second data attribute is as follows: Figure 6 As shown on the right. The memory module 220 includes a first storage area and a second storage area, wherein the first storage area corresponds to the TLC / QLC storage area R223 and the second storage area corresponds to the SLC / MLC storage area R221.

[0083] More specifically, the second storage area (SLC / MLC storage area R221) consists of a single-level cell storage area or a multi-level cell storage area. Each storage cell in a single-level cell storage area stores 1 bit of data, while each storage cell in a multi-level cell storage area stores 2 bits of data. The second storage area has a high access speed and a long erase / write lifetime, making it suitable for storing frequently accessed, hot-attribute data. When the second data attribute of the cached data to be written is a hot attribute, as shown by arrow A63, the memory controller 210 stores the cached data to be written that has a hot attribute into the second storage area (SLC / MLC storage area R221).

[0084] Furthermore, the MLC / TLC storage area R222 consists of a multi-level cell storage area or a three-level cell storage area, achieving a balance between access speed and storage density, making it suitable for storing warm-attribute data with moderate access frequency. When the second data attribute of the cached data to be written is a warm attribute, as shown by arrow A62, the memory controller 210 stores the cached data to be written with the warm attribute in the MLC / TLC storage area R222.

[0085] The first storage area (TLC / QLC storage area R223) consists of a three-level cell storage area or a four-level cell storage area. Each storage cell in the three-level cell storage area stores 3 bits of data, and each storage cell in the four-level cell storage area stores 4 bits of data. The first storage area has a high storage density and is suitable for storing cold attribute data that is accessed infrequently and needs to be retained for a long time. When the second data attribute of the cached data to be written is a cold attribute, as shown by arrow A61, the memory controller 210 stores the cached data to be written that has a cold attribute into the first storage area (TLC / QLC storage area R223).

[0086] Since each storage cell in the first storage area (TLC / QLC storage area R223) stores 3 to 4 bits of data, while each storage cell in the second storage area (SLC / MLC storage area R221) stores 1 to 2 bits of data, the number of bits stored in each storage cell of the first storage area is greater than the number of bits stored in each storage cell of the second storage area.

[0087] For example, suppose buffer memory 214 stores five cached data entries awaiting writing, of which two entries have a cold attribute as their second data attribute, one entry has a warm attribute, and two entries have a hot attribute. When memory controller 210 executes the hierarchical write strategy B61, it first prioritizes storing the two cold attribute data entries in the first storage area (TLC / QLC storage area R223) in step S610; then, in step S620, it stores the one warm attribute data entry in the MLC / TLC storage area R222; finally, in step S630, it stores the two hot attribute data entries in the second storage area (SLC / MLC storage area R221). Through the aforementioned hierarchical write strategy B61, cold attribute data is preferentially written to the first storage area to quickly release the available capacity of the buffer memory 214, while hot attribute data is retained in the buffer memory 214 for a longer period of time. If the host system 10 sends a read request to access the two hot attribute data during the execution of the hierarchical write strategy B61, the memory controller 210 can directly return the data from the buffer memory 214 without reading from the memory module 220, thereby reducing access latency and improving cache hit rate.

[0088] In another embodiment, the combination of the various flash memory type regions in the memory module 220 is not limited to... Figure 6The configuration is shown. The memory controller 210 can adjust the correspondence between each second data attribute and the flash memory type area according to the actual hardware configuration of the memory module 220. For example, when the memory module 220 only contains three-level cell storage areas and four-level cell storage areas, the memory controller 210 can store hot attribute data in the three-level cell storage area and warm attribute data and cold attribute data in the four-level cell storage area. As another example, when the memory module 220 contains single-level cell storage areas, three-level cell storage areas, and four-level cell storage areas, the memory controller 210 can store hot attribute data in the single-level cell storage area, warm attribute data in the three-level cell storage area, and cold attribute data in the four-level cell storage area. Through the above flexible configuration, the memory management method of this disclosure can be applied to memory modules 220 with different hardware configurations.

[0089] It should be noted that, in another embodiment, the combination of the various flash memory type regions in the memory module 220 is not limited to... Figure 6 The configuration shown. Figure 6 The SLC / MLC storage area R221, MLC / TLC storage area R222, and TLC / QLC storage area R223 shown are identified using a mixed designation to indicate that each storage area can be composed of any or a combination of the listed flash memory types, thus covering memory modules 220 with different hardware configurations. In practical applications, the memory controller 210 can adjust the correspondence between each second data attribute and the flash memory type area according to the specific hardware configuration of the memory module 220.

[0090] In another embodiment, when the memory module 220 includes a single-level cell storage area, a multi-level cell storage area, and a three-level cell storage area, the memory controller 210 can configure a one-to-one correspondence between each second data attribute and a single flash memory type area. Specifically, the memory controller 210 stores cached data to be written with the second data attribute being hot in the single-level cell storage area, stores cached data to be written with the second data attribute being warm in the multi-level cell storage area, and stores cached data to be written with the second data attribute being cold in the three-level cell storage area. The single-level cell storage area has a high access speed and a long erase / write life, making it suitable for storing hot attribute data that is accessed frequently and updated frequently; the multi-level cell storage area strikes a balance between access speed and storage density, making it suitable for storing warm attribute data that is accessed moderately; and the three-level cell storage area has a high storage density, making it suitable for storing cold attribute data that is accessed less frequently and retained for a long time.

[0091] In another embodiment, when the memory module 220 includes a multi-layer cell storage area, a three-layer cell storage area, and a four-layer cell storage area, the memory controller 210 can store cached data to be written with the second data attribute being hot in the multi-layer cell storage area, store cached data to be written with the second data attribute being warm in the three-layer cell storage area, and store cached data to be written with the second data attribute being cold in the four-layer cell storage area.

[0092] In another embodiment, when the memory module 220 includes only a three-level cell storage area and a four-level cell storage area, the memory controller 210 can store cached data to be written with the second data attribute being hot or warm in the three-level cell storage area, and store cached data to be written with the second data attribute being cold in the four-level cell storage area. In this configuration, hot and warm data share the same flash memory type area, while cold data is stored in the higher-density four-level cell storage area.

[0093] Through the above flexible configuration, the memory management method disclosed herein can be applied to memory modules 220 with different hardware configurations. The memory controller 210 can dynamically adjust the correspondence between each second data attribute and the storage area according to the flash memory type area contained in the memory module 220.

[0094] It is worth noting that although the foregoing embodiments primarily define different storage regions based on the physical type of flash memory cells (such as SLC, MLC, TLC, etc.), this is not the only limitation of this disclosure. In other embodiments, the division of storage regions may also be based on other performance characteristics or configuration parameters of the storage medium.

[0095] For example, storage areas can be partitioned based on the strength of the Error Correction Code (ECC) or the decoding mode. Specifically, considering that cold attribute data usually needs to be stored for a long time and is prone to bit flipping due to charge leakage, the controller can store it in a "high-reliability storage area" configured with a high-strength error correction algorithm (e.g., enabling the soft-decision mode of low-density parity-check codes LDPC); while for hot attribute data, in order to pursue extremely fast read and write response, the controller can store it in a "low-latency storage area" configured with a low-latency error correction algorithm (e.g., enabling only the hard-decision mode or using BCH codes).

[0096] Furthermore, storage areas can also be divided based on data redundancy protection mechanisms (such as RAID levels). For example, critical hot or warm attribute data can be written to RAID group areas with parity protection to prevent data loss due to frequent operations; while non-critical cold attribute data can be written to storage areas without redundancy protection to maximize storage capacity utilization. In short, any technical solution that distributes data to physical or logical storage areas with different performance, lifespan, reliability, or error correction capabilities based on data attributes is covered within the scope of this disclosure.

[0097] Figure 7 This is a flowchart illustrating a dynamic threshold adjustment mechanism according to an embodiment of the present disclosure.

[0098] Please refer to Figure 7In one embodiment, after entering a preset statistical period, the processor 211 of the memory controller 210 executes step S710 to monitor the available capacity of the cache space of the buffer memory 214 in real time. Specifically, the processor 211 can continuously obtain the remaining capacity of the buffer memory 214 that is not currently occupied by cached data to be written, and determine whether the statistical operation is still suitable to continue within the preset statistical period. Next, the processor 211 executes step S720 to determine whether the available capacity is lower than a preset capacity threshold; when the processor 211 determines that the available capacity is not lower than the preset capacity threshold, it means that the buffer memory 214 still has sufficient cache space to continue to maintain the statistical operation and caching behavior, so the process returns to step S710 to continue the statistics. Conversely, when the processor 211 determines that the available capacity is lower than a preset capacity threshold, it indicates that the available cache space of the buffer memory 214 is becoming insufficient. If the processor continues to wait for the preset statistical period to end completely, the cache usage may further increase, affecting the cache processing of subsequent write instructions. Therefore, the processor 211 executes step S730 to end the preset statistical period early, and obtains the actual statistical duration in step S740. In another embodiment, in step S750, the processor 211 adjusts at least one preset threshold according to the ratio of the actual statistical duration to the preset total duration to generate a dynamic threshold, so that subsequent data attribute determination can maintain a reasonable comparison benchmark in the case of a forced shortening of the statistical period. Specifically, when the preset statistical period ends early due to step S730, the processor 211 can scale at least one preset threshold according to the ratio of "actual statistical duration / preset total duration", so that the dynamic threshold can reflect the situation of low access frequency caused by the reduction of statistical sample duration, thereby reducing the risk of skewed determination results due to insufficient statistical duration. Next, the processor 211 executes step S760, replacing at least one preset threshold with a dynamic threshold for comparison, so that when the processor 211 determines the second data attribute of the cached data to be written, it can still complete the comparison operation between the valid access value and the threshold according to the adjusted threshold system, and use the comparison result for subsequent storage area placement control.

[0099] The following utilizes Figure 10 This will visually illustrate how to dynamically adjust preset thresholds.

[0100] Figure 10 This is a time-axis schematic diagram of dynamic threshold adjustment according to an embodiment of this disclosure. Please refer to... Figure 10In one embodiment, when the memory controller 210 performs access count statistics within a preset statistical period, it monitors the available capacity of the cache space used to cache data to be written in real time. When the available capacity of the cache space is lower than a preset capacity threshold, the memory controller 210 ends the statistical period early and dynamically adjusts at least one preset threshold according to the actual statistical duration, so as to ensure that the second data attribute of the cached data to be written can still be accurately determined even when the cache space is tight.

[0101] like Figure 10 As shown, the gray area on the timeline represents the actual statistical duration, the area enclosed by the dashed box represents the actual statistical period, and the preset end point indicates the original end time of the preset statistical period. Under normal circumstances, the memory controller 210 should stop the statistics and calculate the valid access value at the preset end point. However, when the memory controller 210 detects that the available capacity of the buffer memory 214 is lower than the preset capacity threshold during the statistical process, the trigger condition is met, and the memory controller 210 ends the statistical period prematurely. At this time, the actual statistical duration is shorter than the preset total duration of the preset statistical period. If the memory controller 210 still uses at least one of the original preset thresholds to determine the second data attribute, the determination result may be biased due to insufficient statistical duration.

[0102] To address the aforementioned issues, after prematurely ending the statistical period, the memory controller 210 acquires the actual statistical duration and adjusts at least one preset threshold based on the ratio of the actual statistical duration to the preset total duration of the preset statistical period, thereby generating at least one dynamic threshold. For example... Figure 10 As shown in the lower right corner, the dynamic threshold is calculated as follows: the dynamic threshold equals the preset threshold multiplied by a ratio, where the ratio equals the actual statistical duration divided by the preset total duration. The memory controller 210 then replaces at least one preset threshold with at least one dynamic threshold and compares the valid access value with the dynamic threshold to determine the second data attribute of the cached data to be written.

[0103] For example, assuming the preset total duration of the statistical period is 30 minutes, the memory controller 210 presets a first preset threshold of 10 and a second preset threshold of 30. When the memory controller 210 performs statistics for 6 minutes, it detects that the available capacity of the buffer memory 214 is lower than the preset capacity threshold, triggering the condition, and the memory controller 210 ends the statistical period early. At this time, the actual statistical duration is 6 minutes, and the ratio is equal to 6 minutes divided by 30 minutes, i.e., 0.2. The memory controller 210 calculates the dynamic thresholds according to the above ratios: the first dynamic threshold is equal to the first preset threshold 10 multiplied by the ratio 0.2, resulting in a first dynamic threshold of 2; the second dynamic threshold is equal to the second preset threshold 30 multiplied by the ratio 0.2, resulting in a second dynamic threshold of 6. The memory controller 210 then replaces the original first preset threshold 10 and second preset threshold 30 with the first dynamic threshold 2 and the second dynamic threshold 6, and compares the valid access value with the dynamic thresholds. If a cached piece of data to be written has a valid access value of 4 within 6 minutes, since 4 is greater than the first dynamic threshold 2 and less than or equal to the second dynamic threshold 6, the memory controller 210 determines that the second data attribute of the cached piece of data to be written is the temperature attribute.

[0104] Through the aforementioned dynamic threshold adjustment mechanism, the memory controller 210 can complete the determination of the second data attribute in advance when cache space is tight, and store the cached data to be written to the memory module 220 according to the hierarchical write strategy B61, thereby freeing up the available capacity of the buffer memory 214. The dynamic threshold is calculated by scaling the original preset threshold proportionally to the ratio of the actual statistical duration to the preset total duration, so that the number of accesses obtained within a shorter statistical duration can be reasonably compared with the adjusted dynamic threshold, avoiding the second data attribute determination result being biased towards cold attributes due to insufficient statistical duration.

[0105] Reference Figure 8 , Figure 8 The process involves three stages: write command reception and data caching stage (S810), startup condition monitoring and access statistics stage (S820), and attribute determination and hierarchical writing stage (S830).

[0106] In the first stage (S810), the host system 10 first sends a write command to the memory controller 210 (step S811). It is worth noting that the write command not only includes the data to be written but also carries a first data attribute pre-determined by the host system 10. Upon receiving the command, the memory controller 210 does not immediately write the data to the non-volatile memory module 220 but temporarily stores it in the buffer memory 214 (step S812). Simultaneously, the memory controller 210 parses the first data attribute and configures a corresponding weighting factor for the data accordingly (step S813), preparing for subsequent weighted calculations.

[0107] The second phase (S820) then begins, which is the core of this disclosure: the "observation and statistics cycle." The memory controller 210 continuously monitors the data status in the buffer memory 214. Once the amount of cached data meets preset start conditions (e.g., total capacity or number of data blocks reaches a certain threshold), the memory controller 210 immediately initiates the access statistics mechanism for that batch of data (step S821). Within the preset statistics cycle, the host system 10 may initiate read or overwrite requests for the cached data (step S822). The memory controller 210 responds to these requests, accesses the buffer memory 214 (step S823), and updates the data access count counter in real time (step S824).

[0108] During this phase, this disclosure also designs a protection mechanism to cope with sudden high loads (i.e. Figure 8 (The process is shown in the opt box). If, before the statistical period ends, the memory controller 210 detects that the available capacity of the buffer memory 214 is lower than a preset capacity threshold, in order to prevent cache overflow from causing system blocking, the memory controller 210 will perform an operation to end the statistical period early and calculate a dynamic threshold based on the actual statistical duration (step S825). This protection mechanism ensures that even when the statistical period is forcibly shortened, the consistency of the effective access value comparison benchmark can still be maintained through the dynamic threshold, so as to support subsequent second data attribute determination and storage area placement control.

[0109] Finally, the third stage begins (S830). After the statistical period ends normally or is prematurely terminated, the memory controller 210 calculates the valid access value based on the counted accesses and the configured weighting factors, and determines the second data attribute of the data accordingly (step S831). Subsequently, the memory controller 210 executes a hierarchical write strategy, moving the data from the buffer memory 214 to the corresponding storage area in the memory module 220 in the order of "cold data first, warm data second, and hot data last" (step S832). When the memory module 220 sends a confirmation of storage completion (step S833), the memory controller 210 returns a write completion status to the host system 10 (step S834), thus completing the entire data write process.

[0110] In one embodiment, the memory controller 210 may employ a two-stage determination mechanism to mitigate the determination bias that may result from a single weight factor configuration. Specifically, in the first stage, the memory controller 210 performs a preliminary determination based on the number of accesses (SUM) and at least one initial threshold to obtain preliminary data attributes. In the second stage, it determines whether to use a weight factor for correction based on the consistency between the first data attribute (CHV) and the preliminary data attributes. When the first data attribute (CHV) is consistent with the preliminary data attributes, the memory controller 210 determines that the host's prediction matches the actual access behavior. In this case, the memory controller 210 directly uses the preliminary data attributes as the second data attributes without needing to perform weight factor correction. When the first data attribute (CHV) is inconsistent with the preliminary data attributes, the memory controller 210 determines that there is a deviation between the host's prediction and the actual access behavior. In this case, the memory controller 210 uses a weight factor to calculate the effective access value (EAV) and determines the second data attribute based on the comparison result between the effective access value (EAV) and at least one preset threshold.

[0111] For example, suppose a cached piece of data awaiting writing is pre-determined as a "cold" attribute by the host system 10 and accessed 35 times within a preset statistical period. In the first stage, the memory controller 210 compares the access count of 35 with initial thresholds. Assuming the first initial threshold is 10 and the second initial threshold is 30, since 35 is greater than the second initial threshold 30, the memory controller 210 initially determines the data attribute to be a "hot" attribute. After comparing the first data attribute CHV (cold attribute) with the initial data attribute (hot attribute), the memory controller 210 determines they are inconsistent. Because the host pre-determined it as a cold attribute but the actual access behavior shows it as a hot attribute, the memory controller 210 enters the second stage, using the weight factor 1.0 corresponding to the cold attribute to calculate the effective access value EAV as 35, and determines the second data attribute as a hot attribute. Through this two-stage determination mechanism, when the host's prediction is accurate, the weight factor correction can be skipped to reduce computational overhead; when the host's prediction is inaccurate, the weight factor is used for correction to ensure the accuracy of the determination result.

[0112] In another embodiment, when configuring weighting factors, the memory controller 210 further considers the current operating state of the host system 10 to provide "trust compensation" for the first data attribute. Specifically, the inventors discovered that the first data attribute represents the essential characteristics of the data type and its future access potential, while the actual access counts recorded in the buffer memory 214 only represent the current instantaneous state. Under certain specific system states (e.g., when the host system 10 is in low-power mode, power-saving mode, or overheating and frequency reduction state), some critical processes (such as system processes) may be temporarily restricted, resulting in an abnormally low actual access count for their corresponding files within the statistical period. However, once the host system 10 returns to normal, these files will quickly return to a high-frequency access state.

[0113] To avoid misclassifying critical data as cold under such "pseudo-cold states," the memory controller 210 can receive status indications from the host system 10 (or monitor power / performance status itself). When the host system 10 is determined to be in a constrained state (such as a low-power state), the memory controller 210 applies additional weight compensation to data whose first data attribute is "hot" or "warm." For example, under normal circumstances, the weight factor corresponding to a hot attribute is 1.4; however, in a low-power state, the memory controller 210 can significantly increase the weight factor corresponding to a hot attribute to 2.0 (or configure a fixed compensation value).

[0114] Through this mechanism, even if a system process file is accessed only a few times (e.g., 3 times) within a statistical period, the effective access value (6) after correction by a high weighting factor (2.0) may still be higher than that of an ordinary file that is accessed only 5 times but has a lower weight (1.0). This design reflects the memory controller 210's "trust" in the host-side tags, ensuring that critical data with high future access potential is not mistakenly degraded to low-speed storage areas during periods of low system activity, thereby guaranteeing the response speed after the system recovers to normal.

[0115] In another embodiment, the memory controller 210 may employ a time-varying weight factor mechanism to improve the adaptability of the fixed weight factor configuration to changes in access behavior. Specifically, the memory controller 210 divides a preset statistical period into multiple sub-periods and counts the number of accesses to cached data to be written in each sub-period. The memory controller 210 dynamically adjusts the value of the weight factor based on the changing trend of the access count in each sub-period. When the access count in each sub-period shows an increasing trend, the memory controller 210 determines that the access frequency of the data is rising, and at this time, the memory controller 210 increases the value of the weight factor; when the access count in each sub-period shows a decreasing trend, the memory controller 210 determines that the access frequency of the data is decreasing, and at this time, the memory controller 210 decreases the value of the weight factor; when the access count in each sub-period shows a stable trend, the memory controller 210 maintains the original value of the weight factor.

[0116] For example, assuming a preset statistical period of 30 minutes, the memory controller 210 divides it into three sub-periods, each lasting 10 minutes. A cached piece of data awaiting write is pre-determined as "warm" by the host system 10, and the memory controller 210 configures the initial weight factor for this warm attribute to be 1.2. In the first sub-period (0 to 10 minutes), this data is accessed 5 times; in the second sub-period (10 to 20 minutes), it is accessed 8 times; and in the third sub-period (20 to 30 minutes), it is accessed 12 times. The memory controller 210 determines that the number of accesses in each sub-period shows an increasing trend (5 times, 8 times, 12 times), indicating that the access frequency of this data is rising. Based on this, the memory controller 210 increases the weight factor from 1.2 to 1.3. The total number of accesses (SUM) within the preset statistical period is 25 times. The memory controller 210 calculates the effective access value (EAV) as the number of accesses (25) multiplied by the adjusted weight factor of 1.3, resulting in an effective access value (EAV) of 32.5. If the second preset threshold is 30, since the effective access value 32.5 is greater than the second preset threshold 30, the memory controller 210 determines that the second data attribute of the cached data to be written is a hot attribute. Through the time-varying weight factor mechanism, the memory controller 210 can dynamically adjust the weight factor according to the changing trend of access behavior, so that the determination result of the second data attribute not only reflects the cumulative number of accesses within the statistical period, but also reflects the changing direction of access popularity.

[0117] Continuing the example above, consider a scenario where access activity is decreasing. Suppose a cached piece of data awaiting writing is accessed 12 times, 8 times, and 5 times in three sub-cycles, respectively. The memory controller 210 determines that the number of accesses in each sub-cycle shows a decreasing trend, indicating that the access activity of this data is declining (i.e., the data is gradually becoming less popular). In this scenario, to avoid misclassifying data that is about to become less popular as popular data, the memory controller 210 implements a weight reduction strategy, lowering the weight factor of this data from the initial value of 1.2 to 1.0 (or lower, such as 0.8). By reducing the weight, the Effective Access Value (EAV) will decrease accordingly, making the data more likely to be classified as warm or cold, thus reserving valuable high-performance storage resources for data with increasing access activity.

[0118] Furthermore, to address the issue of irregular fluctuations in the number of accesses in each sub-cycle, the memory controller 210 can employ a "time-weighted evaluation mechanism" to determine the direction of weight factor adjustments. Specifically, the memory controller 210 considers that the closer a sub-cycle is to the current time point, the higher its statistical data reference value (reliability). Therefore, the memory controller 210 presets an increasing "time coefficient" for sub-cycles in different time periods. For example, the time coefficient for the first sub-cycle (farthest) is 1.0, the time coefficient for the second sub-cycle (middle) is 1.1, and the time coefficient for the third sub-cycle (most recent) is 1.2.

[0119] For example, suppose a piece of data is accessed 3 times, 10 times, and 5 times in three sub-periods (showing irregular fluctuations). The memory controller 210 first calculates the original total number of accesses as 18 times (3+10+5). Next, the memory controller 210 calculates the "time-weighted sum" based on the time factor: 3 multiplied by 1.0 plus 10 multiplied by 1.1 plus 5 multiplied by 1.2, resulting in 20 times (3+11+6). The memory controller 210 compares the "time-weighted sum" (20 times) with the "original total number of accesses" (18 times). Since the time-weighted sum is greater than the original total number of accesses, it indicates that the overall performance of the access activity of this data after weighting is better than the average level (or it indicates that the access is mainly distributed in the period with higher weight), and the memory controller 210 determines that the data should be given positive weight compensation, so it increases the weight factor of the data (for example, from 1.2 to 1.25). Conversely, if different timeliness coefficient configurations (e.g., 0.8, 1.0, 1.2) result in a timeliness-weighted sum that is less than the original total number of accesses, it is determined that the accesses are mainly concentrated in earlier, low-reliability periods, and the memory controller 210 will lower the weighting factor. Through this mechanism, even when there is no obvious pattern in the access patterns, the memory controller 210 can still make weight adjustments that best match the current trend based on the time distribution characteristics of the accesses.

[0120] In another embodiment, the memory controller 210 may employ a workload-aware threshold adjustment mechanism to dynamically adjust the preset threshold setting based on the overall system access count. Specifically, the memory controller 210 maintains a system access counter in the buffer memory 214 to count the total number of read and write requests (i.e., access counts) issued by the host system 10 to the storage device 20 within a preset monitoring period, serving as a quantitative indicator of system workload. The memory controller 210 compares the total number of read and write requests with at least one load threshold to determine the memory load status and adjusts at least one preset threshold for data attributes based on the load status.

[0121] More specifically, the memory controller 210 presets two thresholds, a first preset threshold and a second preset threshold, which serve as criteria for distinguishing between cold and warm attributes, and between warm and hot attributes, respectively. The memory controller 210 also sets a lower load threshold and a higher load threshold to classify the system workload into low load, medium load, and high load states. When the system workload is below the lower load threshold, the memory controller 210 determines that it is currently in a low load state; when the system workload is between the lower and upper load thresholds, the memory controller 210 determines that it is currently in a medium load state; and when the system workload is above the upper load threshold, the memory controller 210 determines that it is currently in a high load state.

[0122] When the memory controller 210 determines that the system is under high load, the overall system access frequency is high, indicating that the host system 10 is in a period of intensive access. In this state, even if a particular cached piece of data awaiting write is accessed frequently, it may only reflect a general increase in overall access activity, rather than the data itself having high access frequency. Accordingly, the memory controller 210 adjusts the preset threshold upwards, making the criteria for determining the second data attribute more stringent. For example, the memory controller 210 can adjust the first baseline threshold 10 to the first dynamic threshold 15, and the second baseline threshold 30 to the second dynamic threshold 45. By increasing the preset threshold, the memory controller 210 can filter out data with truly high access frequency under high load conditions, avoiding the misclassification of a large amount of data as hot attributes due to increased overall access frequency.

[0123] When the memory controller 210 determines that the system is in a low-load state, the overall access frequency is low, indicating that the host system 10 is in an idle or low-activity phase. In this state, even if a cached piece of data awaiting writing is accessed infrequently, it may still be considered relatively active data relative to the overall access activity. Accordingly, the memory controller 210 adjusts the preset threshold downwards, making the criteria for determining the second data attribute more lenient. For example, the memory controller 210 can adjust the first baseline threshold 10 to the first dynamic threshold 6, and the second baseline threshold 30 to the second dynamic threshold 18. By lowering the preset threshold, the memory controller 210 can identify relatively active data under low-load conditions, avoiding misjudging data with a certain level of access frequency as a cold attribute due to the overall reduced access frequency.

[0124] When the memory controller 210 determines that it is currently in a medium load state, the memory controller 210 maintains the baseline preset threshold unchanged and uses the first baseline threshold and the second baseline threshold as the determination criteria for the second data attribute.

[0125] For example, suppose the memory controller 210 sets a preset monitoring period of 10 minutes, a lower load threshold of 500 access requests per minute, and a higher load threshold of 2000 access requests per minute. The first baseline threshold is 10, and the second baseline threshold is 30. Within a certain preset monitoring period, if the memory controller 210 counts 2500 access requests per minute as the system access counter, exceeding the upper load threshold of 2000, the memory controller 210 determines that it is currently in a high-load state. The memory controller 210 calculates dynamic thresholds based on a load adjustment factor. Assuming the adjustment factor for a high-load state is 1.5, then the first dynamic threshold is 10 multiplied by 1.5, which equals 15, and the second dynamic threshold is 30 multiplied by 1.5, which equals 45. A cached data entry with an EAV of 35 would be classified as hot (greater than the second baseline threshold of 30) under the baseline preset threshold, but as warm (less than the second dynamic threshold of 45) under the dynamic threshold of a high-load state. Through the workload-aware threshold adjustment mechanism, the memory controller 210 can dynamically adjust the judgment criteria according to the current actual operating status of the system, so that the judgment result of the second data attribute can more accurately reflect the access frequency of each data relative to the overall system access activity.

[0126] In another embodiment, the memory controller 210 can separately calculate the workload for different types of access requests. Specifically, the memory controller 210 maintains read request counters and write request counters respectively, and adjusts preset thresholds according to the ratio of read requests to write requests. When the proportion of read requests is high, it indicates that the system is currently mainly engaged in data reading, and the memory controller 210 can appropriately lower the preset threshold to make frequently read data more likely to be judged as having a higher "hotness" level. When the proportion of write requests is high, it indicates that the system is currently mainly engaged in data writing, and the memory controller 210 can appropriately raise the preset threshold to prevent newly written data from being mistakenly judged as having "hotness" due to repeated writing in a short period of time.

[0127] In another embodiment, the memory controller 210 may employ an access ratio determination mechanism, using the ratio of the number of accesses to a specific cached data item to the total number of system accesses within a statistical period as the basis for determining the second data attribute. Specifically, within a preset statistical period, the memory controller 210, in addition to counting the individual access counts of each cached data item, also counts the total number of accesses by the host system 10 to all cached data items in the buffer memory 214. After the preset statistical period ends, the memory controller 210 calculates the access ratio of each cached data item, which is equal to the number of accesses to that cached data item divided by the total number of system accesses. The memory controller 210 compares the access ratio with at least one ratio threshold to determine the second data attribute of that cached data item.

[0128] More specifically, the memory controller 210 pre-sets a first percentage threshold and a second percentage threshold, wherein the first percentage threshold is less than the second percentage threshold. When the access percentage of a cached data to be written is less than or equal to the first percentage threshold, the memory controller 210 determines that the second data attribute of the cached data to be written is a cold attribute; when the access percentage is greater than the first percentage threshold and less than or equal to the second percentage threshold, the memory controller 210 determines that the second data attribute is a warm attribute; when the access percentage is greater than the second percentage threshold, the memory controller 210 determines that the second data attribute is a hot attribute.

[0129] For example, suppose the memory controller 210 sets a first percentage threshold of 5% and a second percentage threshold of 20%. Within a preset statistical period, the buffer memory 214 contains 100 cached data entries awaiting writing, and the host system 10 accesses these 100 data entries a total of 500 times. Among them, data A is accessed 120 times, data B is accessed 25 times, and data C is accessed 3 times. The memory controller 210 calculates the access percentage for each data entry: the access percentage for data A is 120 divided by 500, which equals 24%; the access percentage for data B is 25 divided by 500, which equals 5%; and the access percentage for data C is 3 divided by 500, which equals 0.6%. The memory controller 210 compares each access percentage with a percentage threshold: the access percentage of data A is 24%, which is greater than the second percentage threshold of 20%, so the memory controller 210 determines that the second data attribute of data A is a hot attribute; the access percentage of data B is 5%, which is equal to the first percentage threshold of 5%, so the memory controller 210 determines that the second data attribute of data B is a cold attribute; the access percentage of data C is 0.6%, which is less than the first percentage threshold of 5%, so the memory controller 210 determines that the second data attribute of data C is a cold attribute.

[0130] The access percentage determination mechanism has the following technical characteristics compared to the absolute access count determination mechanism. Under the previous absolute access count determination mechanism, the memory controller 210 determined the second data attribute based on a fixed preset threshold. When the overall system access activity is relatively high, multiple data items may simultaneously meet the criteria for a "hot" attribute; when the overall system access activity is relatively low, even relatively active data may be determined as a "cold" attribute because its access count has not reached the preset threshold. The access percentage determination mechanism, by converting individual access counts into a percentage relative to the total system access count, allows the determination result to reflect the relative "hotness" of each data item in the overall system access activity, rather than relying solely on the absolute access count.

[0131] For example, suppose that under low load conditions, the total number of system accesses is only 50 within a preset statistical period, and data D is accessed 8 times. If an absolute access count determination mechanism is used and the first preset threshold is 10, then the access count of data D (8 times) is less than the first preset threshold of 10, and it will be determined as a cold attribute. However, the access ratio of data D is 8 divided by 50, which equals 16%, accounting for a considerable proportion of access activity in the 50 total accesses. If an access ratio determination mechanism is used, and the second ratio threshold is 20% and the first ratio threshold is 5%, then the access ratio of data D (16%) is greater than the first ratio threshold of 5% and less than the second ratio threshold of 20%, and it will be determined as a warm attribute. Through the access ratio determination mechanism, the memory controller 210 can identify relatively active data under low load conditions, avoiding misjudging relatively active data as cold attributes due to the sparse overall system access activity.

[0132] It should be noted that in the above embodiments, only the access percentage and multiple percentage thresholds are used to determine the data attributes of cached data to be written, but this disclosure is not limited thereto. For example, in another embodiment, the memory controller 210 can combine the access percentage with a weighting factor. Specifically, the memory controller 210 first calculates the access percentage of each cached data to be written, and then multiplies the access percentage by the corresponding weighting factor to obtain the effective access percentage. The memory controller 210 compares the effective access percentage with at least one percentage threshold to determine the second data attribute. By combining the access percentage with the weighting factor, the memory controller 210 can reflect the relative popularity of each data item relative to the overall system access activity, and can also incorporate the first data attribute CHV provided by the host system 10 based on the attribute information INF as an auxiliary determination basis.

[0133] In another embodiment, the memory controller 210 may employ a weighted access percentage determination mechanism to assign different counting weights to different types of access requests. Specifically, the memory controller 210 multiplies the read hit count by the read weight and the write hit count by the write weight, summing the results to obtain the weighted access count for the cached data awaiting writing. The memory controller 210 also weights the total number of system accesses to calculate the weighted total number of accesses. The weighted access percentage equals the weighted access count divided by the weighted total number of accesses. For example, if the memory controller 210 sets the read weight to 1.0 and the write weight to 1.5, and a piece of data is read 10 times and written 5 times within a preset statistical period, then the weighted access count is 10 multiplied by 1.0 plus 5 multiplied by 1.5, which equals 17.5. By assigning a higher weight to write hits, the memory controller 210 can identify frequently updated data, which typically has high timeliness requirements and is suitable for storage in high-performance storage areas.

[0134] In another embodiment, considering that the host system 10 may have more complex application-layer monitoring mechanisms or machine learning-based traffic prediction models, the host system 10 is not limited to sending only qualitative first data attributes (such as "hot," "warm," and "cold" labels), but can directly calculate and specify precise weighting factors. In this scenario, when sending a write command, the host system 10 directly encapsulates the calculated specific value (e.g., 0.95 or 1.5) as metadata in the command. After receiving the command, the memory controller 210 does not need to perform table lookup mapping, but directly extracts the calculated specific value as a weighting factor and applies it to the subsequent calculation of valid access values. This mechanism gives the host system 10 greater control, enabling it to finely adjust the statistical sensitivity of the memory side according to the real-time needs of the application scenario.

[0135] Furthermore, regarding the specific numerical configuration of the weighting factor, in addition to the gain configuration greater than or equal to 1.0 used in the aforementioned embodiments, the weighting factor can also be configured as a decreasing factor (or attenuation coefficient) with a value less than 1.0. Especially when the first data attribute is indicated as a "cold attribute," the memory controller 210 can be configured with a smaller decreasing factor (e.g., 0.5). This means that even if the data generates a small number of random accesses in the buffer memory 214 (e.g., the actual number of accesses is 4), after correction by the weighting factor (0.5), its effective access value is only 2, making it difficult to reach the threshold for determining it as a "hot attribute." This decreasing mechanism effectively acts as a "low-pass filter," effectively suppressing cold data from being misjudged as hot data due to accidental, non-continuous access operations, thereby ensuring that only truly frequently accessed data can be promoted to the high-performance storage area, further reducing write amplification and saving valuable SLC cache resources.

[0136] This disclosure also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the various steps of the memory management method described above. The computer-readable storage medium can be a non-transitory computer-readable storage medium, such as a read-only memory, random access memory, optical disc read-only memory, magnetic tape, flash memory, hard disk, or solid-state drive. The computer program includes computer-readable instructions, which, when executed by the processor 211, cause the memory controller 210 to perform the memory management method described in the above embodiments.

[0137] In summary, the memory management method and memory controller provided in this disclosure observe and statistically analyze access behavior during the caching stage before data is written to the memory module. By combining the first data attribute determined by the host based on attribute information and the effective access value calculated by the memory based on the actual number of accesses, the second data attribute of the cached data to be written is re-determined, and the cached data to be written is stored in the corresponding storage area in the memory module accordingly.

[0138] Compared with existing technologies that rely solely on static prediction on the host side or solely on memory access frequency statistics, the technical solution disclosed herein has the following technical advantages.

[0139] First, this disclosure integrates host-side predictive information with actual access statistics from the storage side through a weighted factor mechanism. This ensures that effective access values ​​simultaneously reflect the intended use of the data and actual access behavior, thereby improving the accuracy of data attribute classification and reducing improper data placement caused by host-side predictive bias. Second, this disclosure performs access statistics during the caching phase rather than the migration phase, enabling accurate data attribute determination before data is written to the storage module. This avoids the additional write operations and invalid data generated by writing first and then migrating.

[0140] Furthermore, the tiered write strategy provided in this disclosure determines the storage order and target area of ​​data based on the second data attribute. Specifically, the controller prioritizes writing data with a "cold" second data attribute to the first storage area, which has a higher number of bits per storage cell (i.e., higher storage density), to quickly release cache space; subsequently, it writes data with a "hot" attribute to the second storage area, which has a lower number of bits per storage cell (i.e., better performance and durability). This strategy not only achieves optimal matching of storage medium characteristics but also allows frequently accessed "hot" attribute data to remain in the buffer memory for a longer period, thereby directly responding to subsequent access requests and improving cache hit rate. At the same time, multiple modification operations of "hot" attribute data during its stay in the buffer memory can be combined into a single write operation to the memory module, reducing the actual number of writes to the memory module, reducing write amplification effect, and extending the lifespan of flash memory cells.

[0141] Furthermore, this disclosure introduces a threshold adjustment mechanism based on system load status. By statistically analyzing the total number of access requests issued by the host system within a preset monitoring period, the overall system workload is assessed, and the judgment threshold is dynamically adjusted under high or low load conditions. This mechanism effectively avoids misjudging the hotness or coldness of individual data due to fluctuations in overall system traffic (e.g., a general increase in overall access frequency), ensuring that the memory controller maintains the stability and accuracy of data attribute determination under various operating conditions.

[0142] Finally, the dynamic threshold adjustment mechanism provided in this disclosure can terminate the statistical period early when cache space is tight, and scale the preset threshold proportionally based on the ratio of the actual statistical duration to the preset total duration. This allows for a reasonable comparison between the access counts obtained within a shorter statistical duration and the adjusted dynamic threshold. This avoids deviations in the second data attribute determination results due to insufficient statistical duration, ensuring that the memory controller can still release cache space in a timely manner and maintain accurate classification even under sudden high-load write conditions. In summary, this disclosure optimizes cache resource utilization efficiency, reduces write amplification of storage devices, and extends the lifespan of storage devices while meeting access performance requirements.

[0143] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory management method suitable for a storage device, characterized by, The method comprises: receiving a write instruction, the write instruction comprising to-be-written data and a corresponding first data attribute, and caching the to-be-written data; configuring a corresponding weight factor for the cached to-be-written data according to the first data attribute; when it is monitored that a data amount of the cached to-be-written data meets a preset starting condition, counting an access frequency of the cached to-be-written data within a preset statistical period; calculating an effective access value according to the access frequency and the weight factor; comparing the effective access value with at least one preset threshold to determine a second data attribute of the cached to-be-written data; and storing the cached to-be-written data to a corresponding storage area according to the second data attribute. The first data attribute is determined according to attribute information of the to-be-written data, and the attribute information comprises at least one of a file type, a file attribute and an application source.

2. The memory management method of claim 1, wherein, The step of configuring the corresponding weight factor for the cached to-be-written data according to the first data attribute comprises:

3. The memory management method of claim 1, wherein, when the first data attribute is a hot attribute, configuring a first numerical value as the weight factor; when the first data attribute is a warm attribute, configuring a second numerical value as the weight factor; and when the first data attribute is a cold attribute, configuring a third numerical value as the weight factor; wherein the first numerical value is greater than the second numerical value, and the second numerical value is greater than the third numerical value. The step of comparing the effective access value with at least one preset threshold to determine the second data attribute of the cached to-be-written data comprises:

4. The memory management method of claim 1, wherein, comparing the effective access value with a first preset threshold in the at least one preset threshold; if less than the first preset threshold, determining that the second data attribute is a cold attribute. The step of storing the cached to-be-written data to the corresponding storage area according to the second data attribute comprises:

5. The memory management method of claim 1, wherein, the storage area comprises a first storage area and a second storage area; preferentially storing the cached to-be-written data with a cold attribute to the first storage area; subsequently storing the cached to-be-written data with a hot attribute to the second storage area; and a bit number stored in each storage unit of the first storage area is greater than a bit number stored in each storage unit of the second storage area. The preset starting condition comprises:

6. The memory management method of claim 1, wherein, a cumulative capacity of the cached to-be-written data reaches a preset capacity threshold; or a number of cached effective data blocks reaches a preset number threshold. The effective access value is a product of the access frequency and the weight factor.

7. The memory management method of claim 1, wherein, The method further comprises:

8. The memory management method of claim 1, wherein, counting a total number of access requests issued by a host system to the storage device within a preset monitoring period; comparing the total number with a load threshold to determine a system load state of the storage device; and dynamically adjusting the at least one preset threshold according to the system load state. Further comprising:

9. The memory management method of claim 1, wherein, monitoring an available capacity of a cache space used for caching the to-be-written data in real time; ​ ending the preset statistical period in advance when the available capacity is lower than a preset capacity threshold, and obtaining an actual statistical duration that has been counted; and adjusting the at least one preset threshold according to a ratio of the actual statistical duration to a preset total duration of the statistical period, to generate at least one dynamic threshold; and replacing the at least one preset threshold with the at least one dynamic threshold.

10. The memory management method of claim 9, wherein, The dynamic threshold is equal to a product of the at least one preset threshold and a ratio of the actual statistical duration to the preset total duration.

11. A memory controller adapted for use with a storage device configured with a memory module, the memory controller comprising: Comprise: a memory interface control circuit electrically connected to the memory module; and a processor electrically connected to the memory interface control circuit, wherein the processor is configured to: receive a write instruction including to-be-written data and a corresponding first data attribute, and cache the to-be-written data; configure a corresponding weight factor for the cached to-be-written data according to the first data attribute; count a number of accesses to the cached to-be-written data within a preset statistical period when it is monitored that a data amount of the cached to-be-written data meets a preset starting condition; calculate an effective access value according to the number of accesses and the weight factor; compare the effective access value with at least one preset threshold to determine a second data attribute of the cached to-be-written data; and store the cached to-be-written data to a corresponding storage area according to the second data attribute. The first data attribute is determined according to attribute information of the to-be-written data, and the attribute information includes at least one of a file type, a file attribute, and an application source.

12. The memory controller of claim 11, wherein, The processor is configured to configure the corresponding weight factor for the cached to-be-written data by performing the following steps:

13. The memory controller of claim 11, wherein, when the first data attribute is a hot attribute, configure a first numerical value as the weight factor; when the first data attribute is a warm attribute, configure a second numerical value as the weight factor; and when the first data attribute is a cold attribute, configure a third numerical value as the weight factor; wherein the first numerical value is greater than the second numerical value, and the second numerical value is greater than the third numerical value. The processor is configured to determine the second data attribute of the cached to-be-written data by performing the following steps: compare the effective access value with a first preset threshold in the at least one preset threshold; 14. The memory controller of claim 11, wherein, if the effective access value is less than the first preset threshold, determine that the second data attribute is a cold attribute. The storage area includes a first storage area and a second storage area; and the processor is configured to store the cached to-be-written data to the corresponding storage area by performing the following steps: preferentially store the cached to-be-written data with a cold attribute to the first storage area; 15. The memory controller of claim 11, wherein, subsequently store the cached to-be-written data with a hot attribute to the second storage area; wherein a number of bits stored in each storage unit of the first storage area is greater than a number of bits stored in each storage unit of the second storage area. The preset starting condition includes: ​ 16. The memory controller of claim 11, wherein, ​ the accumulated capacity of the buffered to-be-written data reaches a preset capacity threshold; or the number of the buffered valid data blocks reaches a preset number threshold.

17. The memory controller of claim 11, wherein, The valid access value is a product of the access number and the weight factor.

18. The memory controller of claim 11, wherein, The processor is further configured to: count a total number of access requests issued by the host system to the storage device within a preset monitoring period; compare the total number with a load threshold to determine a system load state of the storage device; and adjust the at least one preset threshold dynamically according to the system load state. The processor is further configured to:

19. The memory controller of claim 11, wherein, monitor an available capacity of a cache space for caching the to-be-written data in real time; when the available capacity is lower than a preset capacity threshold, end the preset statistical period in advance and obtain an actual statistical duration that has been counted; adjust the at least one preset threshold according to a ratio of the actual statistical duration to a preset total duration of the statistical period to generate at least one dynamic threshold; and replace the at least one preset threshold with the at least one dynamic threshold. The dynamic threshold is equal to a product of the at least one preset threshold and a ratio of the actual statistical duration divided by the preset total duration. ​ 20. The memory controller of claim 19, wherein, ​

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