Radar signal processing system and method, chip, equipment and storage medium

Abstract

The invention discloses a radar signal processing system and method, a chip, equipment and a storage medium. The system comprises a pipeline structure formed by sequentially connecting a data cache module, an FFT module, an IMAT module and an IFFT module; the data caching module comprises a plurality of caching units, and each caching unit corresponds to one radar signal receiving channel; each cache unit is configured to store to-be-processed data of the corresponding radar signal receiving channel; the FFT module is set to convert input data to be processed into frequency domain data; the IMAT module is set to carry out self-adaptive iterative threshold value iterative algorithm IMAT processing on the frequency domain data output in the FFT mode; the IFFT module is configured to convert the frequency domain data output by the IMAT module into time domain data. According to the scheme of the embodiment of the invention, the multi-stage assembly line structure is constructed based on a plurality of hardware modules, each stage of hardware module can be fully utilized, the hardware waste is avoided, the operation time efficiency requirement of iterative processing is met, and finally the performance of a radar chip is remarkably improved.

Description

Technical Field

[0001] This article relates to radar technology, and in particular to a radar signal processing system, method, chip, device and storage medium. Background Technology

[0002] Radar signal processing systems involve numerous functionally defined hardware modules, such as FFT (Fast Fourier Transform), IFFT (Inverse Fast Fourier Transform), ADC (Analog-to-Digital Converter), DAC (Digital-to-Analog Converter), DFT (Discrete Fourier Transform), IDFT (Inverse Discrete Fourier Transform), IMAT (Iterative Methods Adaptive Threshold), and CFAR (Constant False Alarm Rate). Different operational functions require multiple hardware modules to work collaboratively. Therefore, selecting the optimal hardware architecture for specific functional characteristics while meeting application requirements is crucial for improving radar system processing efficiency and effectively reducing / controlling hardware size and cost. Summary of the Invention

[0003] This application provides a radar signal processing system, method, chip, device, and storage medium. For the implementation of radar signal processing based on iterative computation, a multi-level pipeline structure built on multiple hardware modules can make full use of each hardware module, avoiding hardware waste and meeting the runtime efficiency requirements of iterative processing, ultimately significantly improving the performance of the radar chip.

[0004] This application provides a radar signal processing system, including:

[0005] The pipeline structure consists of a data caching module, a Fast Fourier Transform (FFT) module, an Adaptive Iterative Threshold Algorithm (IMAT) module, and an Inverse Fast Fourier Transform (IFFT) module connected in sequence.

[0006] The data caching module includes multiple caching units, each corresponding to a radar signal receiving channel; each caching unit is configured to store the data to be processed for the corresponding radar signal receiving channel; wherein, the data to be processed is updated according to the output data of the IFFT module after each iteration, and the initial value of the data to be processed is the preprocessed analog-to-digital converter (ADC) data of the corresponding receiving channel;

[0007] The FFT module is configured to convert the input data to be processed into frequency domain data;

[0008] The IMAT module is configured to perform adaptive iterative threshold algorithm (IMAT) processing on the frequency domain data output by the FFT mode.

[0009] The IFFT module is configured to convert the frequency domain data output by the IMAT module into time domain data.

[0010] This application also provides a radar signal processing method, including:

[0011] The data to be processed from multiple radar signal receiving channels is fed into the IMAT adaptive threshold iteration algorithm pipeline structure, and the signal processing is performed iteratively according to the preset maximum number of iterations.

[0012] The IMAT pipeline structure is a multi-stage pipeline structure, comprising, in sequence: a data buffer module, a Fast Fourier Transform (FFT) module, an IMAT module, and an Inverse Fast Fourier Transform (IFFT) module. The data buffer module includes multiple buffer units, each storing the data to be processed for one radar signal receiving channel. The IMAT module is configured to process the frequency domain data output by the FFT module using the Adaptive Iterative Threshold Algorithm (IMAT), and then input the processed data into the IFFT module to convert it into time domain data. The data to be processed is updated after each iteration based on the output data of the IFFT module.

[0013] This application also provides a chip, including the radar signal processing system as described in any embodiment of this application.

[0014] This application also provides a chip including a processor configured to implement the radar signal processing method as described in any embodiment of this application.

[0015] This application also provides an electronic device, including:

[0016] One or more processors;

[0017] Storage device for storing one or more programs.

[0018] When the one or more programs are executed by the one or more processors, the one or more processors implement the radar signal processing method as described in any embodiment of this application.

[0019] This application also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the radar signal processing method as described in any embodiment of this application.

[0020] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings. Attached Figure Description

[0021] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0022] Figure 1 This is a schematic diagram of a radar signal interference recovery process in an embodiment of this application;

[0023] Figure 2 This is a schematic diagram of a radar signal interference recovery system according to an embodiment of this application;

[0024] Figure 3 This is a parallel processing timing sequence for recovering jammed signals from a 4-channel radar in a feasible scheme.

[0025] Figure 4 This is a schematic diagram of a radar signal processing system structure according to an embodiment of this application;

[0026] Figure 5 This is a schematic diagram of an iterative pipelined processing method for recovering jammed signals from a 4-channel radar, as described in an embodiment of this application.

[0027] Figure 6 This application provides a pipelined processing timing sequence for recovering jammed signals from a 4-channel radar.

[0028] Figure 7 This is a flowchart of a radar signal processing embodiment of this application;

[0029] Figure 8 This is another radar signal processing flowchart in an embodiment of this application;

[0030] Figure 9 This is another radar signal processing flowchart in an embodiment of this application. Detailed Implementation

[0031] This application describes several embodiments, but these descriptions are exemplary and not restrictive, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0032] This application includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this application may also be combined with any conventional features or elements to form a unique inventive scheme as defined by the claims. Any feature or element of any embodiment may also be combined with features or elements from other inventive schemes to form another unique inventive scheme as defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in this application may be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.

[0033] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that it does not depend on such a specific order. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims concerning the method and / or process should not be limited to the steps performed in the written order, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments of this application.

[0034] In the field of radar technology, the transmitting end sends a transmitted signal, which is reflected by the target object to form an echo signal (received signal) that can be received by the receiving end. The radar then performs mixing and discrete sampling on the transmitted signal and the echo signal to obtain signal data containing target information.

[0035] When two or more radars with the same or similar transmission frequencies exist in an environment, co-channel and / or adjacent-channel interference occurs. Similarly, the presence of multiple signal and interference sources in the external environment can also cause co-channel and / or adjacent-channel interference with a certain bandwidth to be included in the echo signal. Such interference includes cross-channel interference and parallel interference. Cross-channel interference increases the noise floor, making weaker target signals undetectable, while parallel interference can produce false alarms. Therefore, identifying and eliminating interference is an important aspect of improving radar performance.

[0036] Radar systems are widely used in target detection. With the increasing demand for higher detection accuracy and performance, multi-transmitter and multi-receiver radar systems are becoming increasingly prevalent. Multi-transmitter and multi-receiver schemes mean a larger volume of radar signal data to process and higher processing performance requirements. Taking interference signal recovery as an example, the interference signal recovery function in a radar SoC recovers the interfered signal segment from the radar echo signal in the fast time domain. The index position of the sampling point of the interfered signal segment is obtained from the upper-level interference detection module. The sampling point of the interfered signal segment is then recovered through iterative calculation using the recovered signal sampling point, thus completing the recovery of the interfered signal.

[0037] In a radar signal processing system (System-on-a-Chip, SoC), interference signal processing mainly consists of two steps: interference identification and interference recovery. The main process is as follows: Figure 1 As shown, interference recovery includes preprocessing and IMAT iterative processing. Preprocessing truncates or replaces detected interference data in the received signal, while IMAT iterative processing performs multiple rounds of iterative recovery of the interfered data based on the IMAT algorithm. Interference recovery aims to eliminate or reduce interference in the detected data to restore the data to its original state as much as possible. For multi-channel radar systems, signal recovery is required for each receiving channel. In some exemplary interference signal recovery schemes, the radar ADC data of each receiving channel first passes through a preprocessing module to zero out the interfered sampling points, then is stored in a buffer, and enters an FFT module for time-domain to frequency-domain conversion. Next, it enters an IMAT module for threshold detection; data exceeding the threshold enters an IFFT model for frequency-domain to time-domain conversion. Finally, the signal converted to the time domain replaces the interfered signal sampling points in the buffer, thus performing one round of iterative processing. To effectively recover the interfered signal, multiple rounds of iteration are typically required. In radar systems with multiple receiving channels, the radar ADC data of each receiving channel requires multiple rounds of iteration.

[0038] Taking a radar system with four receiving channels as an example, such as Figure 2As shown, to achieve multiple iterations, the operating clock of the following processing logic is four times the ADC sampling clock. The radar ADC input signals from the four RX channels first pass through the `imat_pre` module to zero out the interfered sampling points. Then, the data from the four RX channels is stored in a buffer, and simultaneously, the data enters the FFT module for time-domain to frequency-domain conversion. Next, the data enters the IMAT module for threshold detection. Data exceeding the threshold enters the IFFT module for frequency-domain to time-domain conversion. Finally, the signal converted to the time domain replaces the interfered sampling points in the buffer, thus completing one data iteration. The IMAT module includes: an `imat_buffer` unit, an `imat_thr` unit, and a threshold-over-threshold processing unit (`set 0`). The `imat_buffer` unit buffers the data to be processed input to the IMAT module; the `imat_thr` unit calculates (updates) the threshold in the IMAT iteration algorithm; and the threshold-over-threshold processing unit determines whether the input signal data to the IMAT module exceeds the current threshold, zeroing out signal data that does not exceed the threshold.

[0039] Some feasible solutions employ parallel iterative structures or fully serial iterative architectures. Fully parallel iterative structures require multiple sets of [facilities / systems] to process signals from multiple receiving channels simultaneously. Figure 1 The hardware shown requires significant hardware logic costs. For example... Figure 3 The parallel processing timing diagram for recovering interference signals from four channels shows that four sets of hardware resources perform three iterations of processing on each received channel signal. In each iteration, only one level of hardware resources is active at any given time, while the others are idle, resulting in significant waste of hardware resources. In contrast, the fully serial iterative architecture processes only one received (RX) channel at a time, requiring only one set of hardware resources, but the time required for three iterations is significantly increased, failing to meet processing requirements. With more received channels and more iterations, the fully parallel scheme places higher demands on hardware resources, significantly increasing hardware costs; while the fully serial approach requires more execution cycles, necessitating a significantly higher clock frequency for iteration execution to ensure processing efficiency meets time requirements, also significantly increasing hardware costs.

[0040] This application proposes a pipelined iterative architecture for radar signal processing. The entire processing architecture requires only one set of hardware resources and performs serial iterations on each channel signal in a pipelined manner. It eliminates the need to specifically increase the operating clock frequency for iteration execution and to configure multiple sets of hardware resources, thus balancing execution efficiency and hardware cost advantages.

[0041] This application provides a radar signal processing system, such as... Figure 4 As shown, it includes:

[0042] A pipeline structure consisting of a data cache module 410, an FFT module 420, an IMAT module 430, and an IFFT module 440 connected in sequence;

[0043] The data caching module 410 includes multiple caching units 4110, each caching unit corresponding to a radar signal receiving channel; each caching unit is configured to store the data to be processed for the corresponding radar signal receiving channel; wherein, the data to be processed is updated according to the output data of the IFFT module after each iteration, and the initial value of the data to be processed is the preprocessed ADC data of the corresponding receiving channel.

[0044] The FFT module 420 is configured to convert the input data to be processed into frequency domain data;

[0045] The IMAT module 430 is configured to perform adaptive iterative threshold IMAT processing on the frequency domain data output by the FFT mode 420.

[0046] The IFFT module 440 is configured to convert the frequency domain data output by the IMAT module 430 into time domain data.

[0047] As can be seen, the output of the IFFT module 440 is connected to the data cache module 410 to update the corresponding cache unit, and the updated data is used as the data to be processed in the next iteration.

[0048] In some exemplary embodiments, the radar signal processing system further includes a preprocessing module 400, configured to replace the corresponding data of the interfered sampling point in the ADC data of the radar signal receiving channel with a cache unit corresponding to a preset data input.

[0049] In some exemplary embodiments, the preset data is 0, that is, the interfered sampling points in the ADC data are set to zero. Alternatively, the preset data is other values.

[0050] In some exemplary embodiments, the preprocessing module 400 preprocesses the power value of the interference signal portion in the received signal (echo signal) by performing operations such as zeroing or setting it to a preset value, and then uses the preprocessed echo signal as the signal to be processed. That is, the interference signal is preprocessed in the time domain first. The preprocessing operation is applied to a portion of the echo signal, specifically to a processing unit of the received echo signal where only a portion of the signal is interfered with. For example, if the sensor is an FMCW sensor and the received echo signal processing unit is a chirp, the interference signal portion is a portion of the frequency points within the chirp. Preprocessing is performed on all the interfered frequency points within the current chirp (i.e., using the frequency point as the smallest preprocessing unit). This is exemplified by 1D-FFT (such as range-dimensional FFT) interference recovery implemented for burst interference within a pulse. Similarly, if the received echo signal processing unit is a frame signal... When the interference signal is a frame, the interference signal is a portion of the chirp in that frame signal. That is, preprocessing is performed on all the chirps that are interfered with in the current frame (i.e., the chirp is the smallest preprocessing unit). For example, 2D-FFT (such as Doppler FFT) interference recovery is implemented for burst interference in the frame. When the received echo signal processing unit contains multiple frames, such as a group containing 12 frames, the interference signal is a portion of the frame signal in that group. That is, preprocessing is performed on all the frame signals that are interfered with in the current group (i.e., the frame signal is the smallest preprocessing unit).

[0051] In some exemplary embodiments, the IMAT module 430 is further configured to determine whether the current iteration has converged; if convergence is determined, set the convergence flag corresponding to the current radar signal receiving channel to converged, so as to indicate that the radar signal channel will no longer perform subsequent iteration processing.

[0052] It should be noted that the IMAT module executes the corresponding steps in each iteration according to the IMAT algorithm. For example, in the k-th iteration, the IMAT module executes the steps for the k-th iteration, including: data caching, threshold calculation, threshold exceeding judgment, and resetting to zero if the threshold is not exceeded, etc. The detailed aspects of the IMAT algorithm are not discussed in detail in this application; please refer to relevant implementations.

[0053] In some exemplary embodiments, the IMAT module 430 determines whether the current iteration operation meets a preset convergence condition. If not, it continues to execute the IFFT module 440 function to obtain the recovered data of this iteration and update the corresponding data in the cache unit, keeping the convergence flag as non-converged to continue the next iteration. If the convergence condition is met, it sets the convergence flag as converged and ends the continued iteration of the radar signal receiving channel. The convergence condition can be determined based on whether at least one of the energy change and noise floor change between two adjacent iterations meets the preset convergence condition.

[0054] It is understandable that the IFFT module performs its function when the iteration corresponding to the current radar signal receiving channel has not converged, converting the frequency domain data into time domain data and updating the data to be processed in the buffer unit corresponding to that channel; when the iteration corresponding to the current radar signal receiving channel has converged, this module does not perform its function.

[0055] In some exemplary embodiments, the radar signal processing system further includes a convergence flag storage unit for storing the convergence flag of each radar signal receiving channel. It is understood that the initial value of the convergence flag for each radar signal receiving channel is "not converged." During the iteration process, the IMAT module determines whether the iterative processing of the current radar signal receiving channel has converged according to the set convergence conditions. If convergence is determined, the value in the convergence flag storage unit corresponding to that radar signal receiving channel is updated to indicate that the channel has converged.

[0056] In some exemplary embodiments, after the data in the data cache module is output when the iteration termination condition is met, the convergence flag storage unit is initialized and restored to non-converged.

[0057] In some exemplary embodiments, the convergence flag storage unit includes multiple convergence flag registers, each corresponding to a radar signal receiving channel. For example, in each register, 0 indicates non-convergence and 1 indicates convergence, with an initial value of 0. When the convergence condition is met, it is updated to 1; after reinitialization, it is also restored to 0; the specific settings are not limited to the aspects of the examples.

[0058] In some exemplary embodiments, the FFT module 420, the IMAT module 430, and the IFFT module 440 are further configured to not execute the function of this module in the current execution cycle when the convergence flag corresponding to the current radar signal receiving channel is converged.

[0059] As can be seen, when the data of each channel in multiple radar signal receiving channels is processed in a pipeline for interference recovery, it first determines whether the current channel has converged. If it has not converged, it needs to continue iterating. If it has converged, there is no need to execute the subsequent pipeline function for the data corresponding to that receiving channel. That is, the above three functional modules will no longer perform the custom basic module function processing for the input data of that channel in the current execution cycle.

[0060] It is understandable that in a multi-level pipelined architecture, the total execution time of a first-level pipeline function is also called the execution cycle of that pipeline level. Depending on the complexity of the functions at each pipeline level, an execution cycle includes one or more system clock cycles T. s In some exemplary embodiments, the execution cycle of the first-level pipeline function is also referred to as execution latency.

[0061] In some exemplary embodiments, the IFFT module 440 is further configured to convert the frequency domain data output by the IMAT module 330 into time domain data, and then update the data of the location of the interfered sampling point in the time domain data to the buffer unit of the corresponding radar signal receiving channel. That is, the data of the location of the interfered sampling point in the time domain data obtained by the IFFT module is used to update the data cached in the buffer unit of the radar signal receiving channel corresponding to the data at the location of the interfered sampling point.

[0062] As can be seen, when recovering radar jammed signals using the radar signal processing system provided in this application embodiment, no additional hardware is required. It employs a multi-stage pipelined structure to implement iterative calculations, fully utilizing the hardware resources of each stage. Taking a radar SoC with four radar signal receiving channels as an example, the four channel ADC signals are input serially. In each iteration, each stage of the hardware pipeline processes the ADC signals of the four channels. In this processing architecture, each stage of hardware resources is in a working state, improving hardware utilization and saving hardware resources while meeting performance requirements.

[0063] In some exemplary embodiments, the multiple cache units in the data cache module 410 store the data to be processed for multiple radar signal receiving channels; the FFT module 420, the IMAT module 430 and the IFFT module 440 are all configured to perform data processing for one receiving channel in each execution cycle, that is, each of these three modules processes only the data of one receiving channel in each execution cycle.

[0064] For example, the pipelined processing flow of the four receiving channels (rx0-rx3) in this four-stage radar signal processing system is as follows: Figure 5 For example, its flow processing sequence is as follows: Figure 6As shown. The FFT / IFFT module has 4 parallel channels, meaning that the FFT / IFFT module performs 4-channel parallel FFT / IFFT processing on the signal data corresponding to the current radar signal receiving channel.

[0065] Compared to the fully parallel iterative architecture and the fully serial iterative architecture in some feasible solutions, the radar signal processing scheme provided in this application is also called a pipelined iterative architecture. Taking a 4-channel radar SoC iterating 3 times as an example, the required resources and processing time are shown in the table below:

[0066]

[0067] Each radar receiving channel corresponds to one memory channel. As can be seen, for a signal processing system with four radar signal receiving channels, when using a fully parallel iterative architecture, four memory channels are configured in parallel, and the FFT / IFFT of each radar signal receiving channel uses four channels for parallel processing. Under this architecture, the total number of FFT / IFFT parallel channels is 4×4, the total number of memory channels is 4, and the time required for three iterations is 11 units of time. When using a fully serial iterative architecture, the signal data of the four radar signal receiving channels are processed serially, with a total of one memory channel configured. The FFT / IFFT of each radar signal receiving channel uses four channels for parallel processing. The architecture employs parallel processing, with a total of 4 parallel FFT / IFFT channels and 1 memory channel. The time required for 3 iterations is 44 units of time. When using the pipelined iterative architecture provided in this application, the signal data from 4 radar signal receiving channels are processed in a pipelined iterative manner, with a total of 4 memory channels configured. Each radar signal receiving channel's FFT / IFFT uses 4-channel parallel processing. Under this architecture, the total number of parallel FFT / IFFT channels and memory channels is 4, and the time required for 3 iterations is 15 units of time. Each unit of time is 1 / 16 × a chirp cycle, meaning the unit of time is 1 / 16 of a chirp cycle.

[0068] As can be seen, while the fully parallel iterative structure has a shorter total hardware iteration time, it has greater hardware redundancy; the fully serial iterative architecture has no hardware redundancy, but its overall processing time is too long. To reduce the overall processing time, the working clock cycle of the entire iterative process needs to be shortened, i.e., the clock frequency of the process needs to be increased to meet application requirements. According to the radar signal processing system proposed in the embodiments of this application, the entire processing architecture utilizes a single set of hardware resources to perform serial iteration on each channel signal in a pipelined manner. Multiple channel ADC signals are input serially, and each stage of hardware pipelines four channels of ADC signals in each iteration. During the iterative processing, each hardware module / resource in the architecture is in a working state, improving hardware utilization and saving hardware resources while meeting performance requirements.

[0069] In some exemplary embodiments, increasing the number of cache units in the data cache module 410 can support data processing for more radar signal receiving channels. For example, 6 cache units support 6-channel radar signal processing, 8 cache units support 8-channel radar signal processing, and more examples are not described here.

[0070] This disclosure also provides a radar signal processing method, such as... Figure 7 As shown, it includes:

[0071] Step 710: Send the data to be processed from multiple radar signal receiving channels into the IMAT pipeline structure, and perform signal processing iteratively according to the preset maximum number of iterations.

[0072] The IMAT pipeline structure is a multi-stage pipeline structure, comprising, in sequence, a data buffer module, an FFT module, an IMAT module, and an IFFT module. The data buffer module includes multiple buffer units, each storing the data to be processed for one radar signal receiving channel. The IMAT module is configured to perform adaptive iterative threshold IMAT processing on the frequency domain data output by the FFT module, and then input it into the IFFT module to convert it into time domain data. The data to be processed is updated according to the output data of the IFFT module after each iteration.

[0073] In some exemplary embodiments, the IMAT pipeline structure is also referred to as the IMAT iterative pipeline.

[0074] It is understood that in some exemplary embodiments, a higher number of iterations is more beneficial for improving signal reconstruction accuracy; that is, performing more iterations is more likely to yield the optimal solution and a better recovered signal. Iterations should be performed within the set maximum number of iterations.

[0075] In some exemplary embodiments, the method further includes:

[0076] The IMAT module determines whether the current iteration has converged; if it has converged, it sets the convergence flag of the current radar signal receiving channel to converged, so as to indicate that no further iterative processing steps will be performed for the radar signal channel.

[0077] Therefore, in a multi-channel radar system, the actual number of iterations for each radar signal receiving channel is controlled independently. Once it is determined that the iteration of a channel has converged, the data for that channel will no longer continue to iterate, and the data in the corresponding buffer unit of that channel will be retained. The data of other radar signal receiving channels that have not converged will continue to iterate. After all channels have completed their iterations, the data in the buffer unit will be output as the final recovered received data.

[0078] In some exemplary embodiments, the method further includes:

[0079] Before executing the function of this module, the FFT module, the IMAT module, and the IFFT module determine whether the convergence flag of the current radar signal receiving channel has converged. If it is determined that the convergence has not occurred, the function of this module is executed.

[0080] If convergence is not achieved, each module executes its own hardware function to perform the current iteration and continue to calculate a better recovered signal; if convergence is achieved, the module does not execute its function so that the radar signal receiving channel no longer performs iterations.

[0081] In some exemplary embodiments, the method further includes: step 720, whereby, if the iteration termination condition is determined to be met, the data in the data cache module is output;

[0082] The iteration termination condition includes one of the following:

[0083] The number of iterations reaches the preset maximum number of iterations;

[0084] All radar signal receiving channels are now marked as converged.

[0085] In some exemplary embodiments, step 710 is also referred to as IMAT iterative processing, such as... Figure 8 As shown, the method further includes:

[0086] Step 712: Determine if the iteration of the current radar signal receiving channel has converged. If it has converged, set the convergence flag of the channel to converged; if it has not converged, keep the convergence flag of the channel as non-converged.

[0087] Step 713: Determine whether the iteration termination condition has been met. If not, wait to enter the next iteration. If it has been met, output the data in the data cache module as the data after interference recovery.

[0088] In some exemplary embodiments, such as Figure 9 As shown, the method further includes:

[0089] Step 711: Determine whether the iteration termination condition has been met. If not, start the current iteration. If it has been met, output the data in the data cache module as the data after interference recovery.

[0090] Step 712: Determine if the iteration of the current radar signal receiving channel has converged. If it has converged, set the convergence flag of the channel to converged; if it has not converged, keep the convergence flag of the channel as non-converged.

[0091] It is understood that in some exemplary embodiments, step 712 is executed in the IMAT module 430 of the pipeline iterative structure of the radar signal processing system; in some exemplary embodiments, step 711 is executed in the FFT module 420 of the pipeline iterative structure, or step 713 is executed in the IFFT module 440. In some exemplary embodiments, the radar signal processing system further includes an iterative decision module, in which steps 711, 712, and 713 are executed to control the iterative control of each radar signal receiving channel and the iterative control of the entire radar signal processing system.

[0092] In some exemplary embodiments, the maximum number of iterations is preset according to the following constraints:

[0093] The total processing time for all multiple radar signal receiving channels to complete the set maximum number of iterations is less than or equal to one chirp cycle.

[0094] In some exemplary embodiments, the maximum number of iterations, Niter, is determined according to the following method:

[0095]

[0096] Among them, T c h irp For one chirp cycle, T IMAT This represents the time required for one iteration.

[0097] In some exemplary embodiments, the chirp period T c h irp ≥N adc ×N rx ×T s +T idle ;

[0098] Where, N adc N represents the number of ADC points corresponding to the signal data of one radar signal receiving channel. rxT represents the number of radar signal receiving channels. idle T is the idle time during a chirp cycle. s The clock cycle.

[0099] For example, N rx =4,T idle 3000us; T c h irp ≥N adc ×4×T s +3000.

[0100] In some exemplary embodiments, T IMAT =(N fft +N latency )×T s ;

[0101] Where, N fft N represents the number of FFT points corresponding to the signal data of one radar signal receiving channel. latency This represents the number of clock cycles required for one iteration corresponding to the number of FFT points.

[0102] In some exemplary embodiments, the method further includes:

[0103] Step 700: Replace the corresponding data of the interfered sampling points in the ADC data of multiple radar signal receiving channels with preset data to obtain the data to be processed for the multiple radar signal receiving channels.

[0104] In some exemplary embodiments, the waveform received by the radar signal receiving channel is a continuous wave whose frequency changes linearly with time. This continuous wave can be an FMCW wave or an SFCW wave.

[0105] This application also provides a chip, including the radar signal processing system as described in any embodiment of this application.

[0106] This application also provides a chip including a processor configured to implement the radar signal processing method as described in any embodiment of this application.

[0107] In some exemplary embodiments, the chip is a millimeter-wave radar chip or a lidar chip (such as an FMCW lidar chip).

[0108] In some exemplary embodiments, the chip may also be packaged with an inner antenna (AiP) chip structure, an antenna-on-package (AoP) chip structure, or an antenna-on-chip (AoC) chip structure, etc.

[0109] This application also provides an electronic device, including:

[0110] One or more processors;

[0111] Storage device for storing one or more programs.

[0112] When the one or more programs are executed by the one or more processors, the one or more processors implement the radar signal processing method as described in any embodiment of this application.

[0113] In some exemplary embodiments, the electronic device is a millimeter-wave radar device or a lidar device. Alternatively, in some exemplary embodiments, the electronic device is a vehicle-mounted radar device.

[0114] This application also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the radar signal processing method as described in any embodiment of this application.

[0115] The radar signal processing system provided in this application utilizes a single hardware module with a pipelined architecture to support multi-channel radar signal processing. It fully leverages each stage of the pipelined hardware to complete multi-channel radar signal processing without altering the operating clock frequency, ensuring efficient multi-channel radar signal processing, significantly reducing hardware costs while meeting performance requirements. Using the radar signal processing scheme provided in this application to recover interfered signals allows for a higher maximum number of iterations within a lower-cost radar chip hardware framework, thereby improving the accuracy of interfered signal recovery.

[0116] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

Claims

1. A radar signal processing system, characterized by The radar signal processing system comprises a pipeline structure formed by sequentially connecting a data buffering module, a fast Fourier transform (FFT) module, an iterative mean and adaptive threshold (IMAT) module and an inverse fast Fourier transform (IFFT) module. The data buffering module comprises a plurality of buffering units, each buffering unit corresponding to a radar signal receiving channel. Each buffering unit is configured to store to-be-processed data of the corresponding radar signal receiving channel, wherein the to-be-processed data is updated according to output data of the IFFT module after each iteration, and an initial value of the to-be-processed data is pre-processed analog-to-digital converter (ADC) data of the corresponding receiving channel. The FFT module is configured to convert the input to-be-processed data into frequency domain data. The IMAT module is configured to perform IMAT processing on the frequency domain data output by the FFT module. The IFFT module is configured to convert the frequency domain data output by the IMAT module into time domain data.

2. The radar signal processing system according to claim 1, further comprising a preprocessing module configured to replace corresponding data of a jammed sampling point in ADC data of a radar signal receiving channel with preset data and input the corresponding data into a corresponding buffering unit.

3. The radar signal processing system according to claim 1 or 2, wherein the IMAT module is further configured to determine whether the current iteration converges, and in a case where it is determined that the current iteration converges, set a convergence identifier corresponding to the current radar signal receiving channel as having converged to indicate that the radar signal channel no longer performs subsequent iteration processing.

4. The radar signal processing system according to claim 3, wherein the FFT module, the IMAT module and the IFFT module are further configured to, in a case where the convergence identifier corresponding to the current radar signal receiving channel is set as having converged, not perform the function of the module in the current execution cycle.

5. The radar signal processing system according to claim 2, wherein the IFFT module is further configured to, after converting the frequency domain data output by the IMAT module into time domain data, update data at a position of a jammed sampling point in the time domain data to the buffering unit of the corresponding radar signal receiving channel. The radar signal processing system comprises a pipeline structure formed by sequentially connecting a data buffering module, a fast Fourier transform (FFT) module, an iterative mean and adaptive threshold (IMAT) module and an inverse fast Fourier transform (IFFT) module. The data buffering module comprises a plurality of buffering units, each buffering unit corresponding to a radar signal receiving channel. Each buffering unit is configured to store to-be-processed data of the corresponding radar signal receiving channel, wherein the to-be-processed data is updated according to output data of the IFFT module after each iteration, and an initial value of the to-be-processed data is pre-processed analog-to-digital converter (ADC) data of the corresponding receiving channel. The FFT module is configured to convert the input to-be-processed data into frequency domain data. The IMAT module is configured to perform IMAT processing on the frequency domain data output by the FFT module.

6. A radar signal processing method, characterized by, The IFFT module is configured to convert the frequency domain data output by the IMAT module into time domain data. ​ The IMAT pipeline structure is a multi-stage pipeline structure, and includes, which are connected in sequence: a data buffer module, a fast Fourier transform (FFT) module, an IMAT module, and an inverse fast Fourier transform (IFFT) module; the data buffer module includes a plurality of buffer units, each buffer unit corresponding to storage of data to be processed of a radar signal receiving channel; the IMAT module is configured to perform IMAT processing on frequency domain data output by the FFT module, and then input the IFFT module to convert the data into time domain data; the data to be processed is updated according to output data of the IFFT module after each iteration.

7. The radar signal processing method of claim 6, wherein, The method further comprises: The IMAT module determines whether the current iteration converges; in the case of determining that the current iteration converges, setting a convergence identifier of the current radar signal receiving channel as converged, to indicate that subsequent iteration processing steps are not performed for the radar signal channel.

8. The radar signal processing method of claim 7, wherein, The method further comprises: Before performing the functions of the FFT module, the IMAT module, and the IFFT module, the method determines whether the convergence identifier of the current radar signal receiving channel is converged, and in the case of determining that the convergence identifier is not converged, the method performs the functions of the FFT module, the IMAT module, and the IFFT module.

9. The radar signal processing method of claim 6, wherein, The method further comprises: In the case of determining that the iteration end condition is met, outputting data in the data buffer module; The iteration end condition includes one of the following: The number of iterations reaches the preset maximum number of iterations. The convergence identifiers of all radar signal receiving channels are converged.

10. The radar signal processing method of any one of claims 6-9, wherein, The maximum number of iterations is preset according to the following constraint condition: The total processing time of all radar signal receiving channels completing the preset maximum number of iterations is less than or equal to a chirp period.

11. The radar signal processing method of any one of claims 6-9, wherein, The method further comprises: Replacing corresponding data of jammed sampling points in analog-to-digital converter (ADC) data of a plurality of radar signal receiving channels with preset data to obtain data to be processed of the plurality of radar signal receiving channels.

12. A chip, characterized by The radar signal processing system of any one of claims 1-5.

13. A chip, characterized by The processor is configured to implement the radar signal processing method of any one of claims 6-11.

14. An electronic device, comprising: One or more processors; A storage device for storing one or more programs, When the one or more programs are executed by the one or more processors, the one or more processors implement the radar signal processing method of any one of claims 6-11. The program is executed by the processor to implement the radar signal processing method of any one of claims 6-11.

15. A computer readable storage medium having stored thereon a computer program, characterized in that, ​

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