Standard cell time sequence data processing method and device, electronic equipment and storage medium

Abstract

The invention provides a standard unit time sequence data processing method and device, electronic equipment and a storage medium, and is applied to the technical field of computers.The method comprises the steps that after at least one standard unit and a plurality of process corners are obtained, unit information of all the standard units is extracted, and any standard unit serves as a target standard unit; configuring operation conditions according to unit information of the target standard unit, determining a target time sequence path of the target standard unit, and finally performing static time sequence analysis on the target time sequence path under each process corner according to the operation conditions of the target standard unit to obtain delay data of the target standard unit under different preset working voltages. Compared with the prior art, the method has the advantages that the delay data of each standard unit under different preset working voltages can be obtained before the physical design of the integrated circuit is carried out, and accurate and reliable reference bases meeting project design requirements are provided for the physical design as soon as possible.

Description

Technical Field

[0001] This application relates to the field of computer technology, specifically to a standard unit timing data processing method, apparatus, electronic device, and storage medium. Background Technology

[0002] During integrated circuit operation, the delay of signal propagation along the timing path includes cell delay and interconnect delay. Cell delay is the sum of the delays of each standard cell along the timing path. Due to factors such as line impedance, the actual operating voltage of a standard cell is often lower than the power supply voltage provided by the power supply unit. The magnitude of the operating voltage affects the cell delay of the standard cell, thereby affecting the timing characteristics of the timing path.

[0003] To ensure the stable operation of integrated circuits, a certain timing margin is usually reserved during the design process based on project design requirements to avoid timing violations caused by delays in standard cells due to changes in the obtained operating voltage. However, as the scale of integrated circuits continues to increase, reserving timing margins greatly increases the design difficulty and cost. Although static timing analysis based on voltage drop simulation results can obtain more accurate delay data for standard cells, it can only be performed in the middle and late stages of physical design. If the delay data used in the early stages of design is not accurate enough, it will lead to a lot of design modifications and seriously waste human and material resources.

[0004] Therefore, how to obtain the delay data of standard cells under different operating voltages as early as possible, and provide accurate and reliable reference for physical design that meets the project design requirements, has become one of the problems that urgently need to be solved by those skilled in the art. Summary of the Invention

[0005] In view of this, this application aims to provide a standard cell timing data processing method, apparatus, electronic device and storage medium to obtain the delay data of the standard cell under different operating voltages as early as possible, so as to provide accurate and reliable reference for physical design that meets the project design requirements.

[0006] In a first aspect, this application provides a standard cell timing data processing method, including: Obtain at least one standard cell and multiple process corners, wherein each process corner includes a preset operating voltage and other process corner parameters, the preset operating voltages included in each process corner are different, and the other process corner parameters are the same; Extract the unit information of each of the aforementioned standard units; Configure the operating conditions of the target standard unit according to the unit information of the target standard unit, and determine the target timing path of the target standard unit, wherein the target standard unit is any one of the standard units; Static timing analysis is performed on the target timing path under the operating conditions of the target standard unit at each of the process angles to obtain the delay data of the target standard unit under different preset operating voltages.

[0007] In one optional implementation, the extraction of the unit information of each of the standard units includes: A netlist file is created for each of the standard cells, and the netlist file is used to record the cell information of the standard cells; Load the netlist file corresponding to each of the standard units, and extract the unit information recorded in the netlist file.

[0008] In one alternative implementation, the process of creating a netlist file for any of the said standard units includes: Create a blank netlist file for the standard unit, and configure an instance name for the blank netlist file that uniquely corresponds to the standard unit; Obtain a preset string variable, and use the preset string variable to store the port information of each external port in the standard unit; The port information stored in the preset string variable is recorded in the blank netlist file to obtain the netlist file corresponding to the standard unit.

[0009] In an optional implementation, the method provided by the first aspect of this application further includes: clearing the preset string variable after completing the creation of the netlist file of any of the standard units.

[0010] In one optional implementation, configuring the operating conditions of the target standard unit based on the unit information of the target standard unit and determining the target timing path of the target standard unit includes: The cell type of the target standard cell is determined based on the cell information of the target standard cell; Configure the operating conditions of the target standard unit according to the unit type of the target standard unit, and determine the target timing path of the target standard unit.

[0011] In one optional implementation, the unit type includes sequential logic units and combinational logic units; Configure the operating conditions of the target standard unit according to its unit type, and determine the target timing path of the target standard unit, including: If the target standard unit is a sequential logic unit, a clock signal source is configured at the clock port of the target standard unit, timing constraints are configured at the data port of the target standard unit, and the input signal transition time and output load are configured. And, determine the target timing path based on the port type of the target standard unit; If the target standard unit is a combinational logic unit, timing constraints are configured for each input port and each output port of the target standard unit, and the input signal transition time and output load are configured. Furthermore, the combination of each input port and each output port in the target standard unit is respectively used as the target timing path.

[0012] In one optional implementation, the step of performing static timing analysis on the target timing path according to the operating conditions of the target standard unit at each of the process corners to obtain the delay data of the target standard unit under different preset operating voltages includes: Obtain the process library file corresponding to the target process corner. The process library file includes a reference operating voltage, delay data corresponding to the reference operating voltage, and other process corner parameters of the target process corner. The target process corner is any one of the process corners. Under the target process angle, static timing analysis is performed on the target timing path according to the operating conditions of the target standard unit and the delay data corresponding to the reference operating voltage, to obtain the delay data of the target standard unit under the preset operating voltage corresponding to the target process angle.

[0013] Secondly, this application provides a standard cell timing data processing apparatus, comprising: An acquisition unit is used to acquire at least one standard unit and multiple process corners, wherein the process corners include a preset operating voltage and other process corner parameters, the preset operating voltages included in each process corner are different, and the other process corner parameters are the same; Processing unit, used for: Extract the unit information of each of the aforementioned standard units; Configure the operating conditions of the target standard unit according to the unit information of the target standard unit, and determine the target timing path of the target standard unit, wherein the target standard unit is any one of the standard units; Static timing analysis is performed on the target timing path under the operating conditions of the target standard unit at each of the process angles to obtain the delay data of the target standard unit under different preset operating voltages.

[0014] Thirdly, this application provides an electronic device including a memory, a processor, and a computer program stored in the memory and executed by the processor, wherein the processor executes the computer program to implement the steps of the standard cell timing data processing method provided in any embodiment of the first aspect of this application.

[0015] Fourthly, this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the standard cell timing data processing method provided in any embodiment of the first aspect of this application.

[0016] Based on the above, the standard cell timing data processing method provided in this application, after acquiring at least one standard cell and multiple process corners, extracts the cell information of each standard cell, takes any one standard cell as the target standard cell, configures the operating conditions according to the cell information of the target standard cell, and determines the target timing path of the target standard cell. Finally, static timing analysis is performed on the target timing path according to the operating conditions of the target standard cell under each process corner to obtain the delay data of the target standard cell under different preset operating voltages. Compared with related technologies, the process of obtaining the delay data of the standard cell under different preset operating voltages in this method no longer relies on the voltage drop simulation data that can only be obtained in the later stages of physical design. Therefore, the delay data of each standard cell under different preset operating voltages can be obtained before the physical design of the integrated circuit, providing accurate and reliable reference for the physical design as early as possible to meet the project design requirements, thereby predicting and controlling the risk of timing violations, and helping to ensure the integrity of timing while ensuring the entire physical design cycle. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a flowchart of a standard cell timing data processing method provided in an embodiment of this application.

[0019] Figure 2 This is a flowchart of another standard cell timing data processing method provided in the embodiments of this application.

[0020] Figure 3 This is a flowchart of another standard cell timing data processing method provided in the embodiments of this application.

[0021] Figure 4 This is a structural block diagram of a standard unit timing data processing device provided in an embodiment of this application.

[0022] Figure 5 This is a structural block diagram of an electronic device provided in an embodiment of this application. Detailed Implementation

[0023] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0024] To obtain delay data of standard cells at different operating voltages as early as possible before the actual physical design work, and to provide accurate and reliable reference data that meets project requirements for the physical design, this application provides a standard cell timing data processing method. The process of obtaining delay data of standard cells at different preset operating voltages no longer relies on voltage drop simulation data that can only be obtained in the later stages of the physical design. Therefore, the delay data of each standard cell at different preset operating voltages can be obtained before the integrated circuit physical design, providing accurate and reliable reference data that meets project design requirements as early as possible. This allows for the prediction and control of timing violation risks, and helps to ensure the integrity of timing while ensuring the entire physical design cycle.

[0025] The standard cell timing data processing method provided in this application can be applied to electronic devices, such as laptops, personal computers (PCs), and tablets. It can also be other electronic devices capable of running the application program corresponding to the standard cell timing data processing method provided in this application; these will not be listed here. In some cases, it can also be applied to network-side servers. See also... Figure 1 As shown, the standard cell timing data processing method provided in this application includes the following steps.

[0026] S100, Obtain at least one standard cell and multiple process corners.

[0027] Standard cells are a core component of integrated circuit physical design. They are pre-designed, functionally and electrically verified basic logic units. Designers use highly standardized standard cells to build complex functional units, which in turn construct the integrated circuit architecture. In current applications, standard cells mainly include two types: first, combinational logic units, such as AND gates, OR gates, and inverters, which implement basic logic operations; and second, sequential logic units, such as flip-flops and latches, which are used to store circuit states. These standard cells together constitute the physical foundation of integrated circuits.

[0028] In the physical design process, timing verification is an essential sign-off step. As mentioned earlier, the delay duration of a signal propagating along the timing path includes cell delay and interconnect delay. Cell delay is obtained by summing the delays of each standard cell along the timing path. Therefore, it is necessary to accurately determine the delay data of each standard cell. Furthermore, in actual designs, standard cells are placed in different locations on the integrated circuit, and the distance between each standard cell and the power supply module varies. Due to interconnect impedance, the actual operating voltage of each standard cell differs. Based on the underlying physical implementation of the standard cells, the delay duration of the same standard cell transmitting signals under different operating voltages (assuming other influencing factors are the same) is not the same. Therefore, it is necessary to obtain the delay data of the standard cells under different operating voltages.

[0029] The method provided in this application embodiment can acquire the delay data of any one standard unit, or acquire the delay data of multiple standard units in batches. Therefore, this step can acquire at least one standard unit.

[0030] In one optional implementation, the standard unit is recorded in a standard unit library file. Based on this, one or more standard unit library files can be obtained, and each standard unit recorded in each standard unit library file can be extracted. Considering that there may be duplicate standard units stored, the obtained standard units can also be deduplicated, that is, duplicate standard units in each standard unit are deleted, and only one of the multiple identical standard units is retained.

[0031] In practical applications, the delay duration of a standard cell is affected by a variety of factors that are difficult to measure and determine. These mainly include the junction temperature of the standard cell, the actual operating voltage after transmission through interconnects, and disturbances during the manufacturing process, i.e., minor deviations between the structures of the standard cells. These physical quantities usually change continuously, and it is impossible to simulate and calculate every case when performing timing verification. Therefore, usually only a few extreme cases are considered, such as the delay duration at a junction temperature of 0℃ and an operating voltage of 1V, or the delay duration at a junction temperature of 125℃ and an operating voltage of 0.95V. The combination of typical values ​​of these different influencing factors is considered as a process corner.

[0032] To fully obtain the delay data of the standard cell, this step acquires multiple process corners. As mentioned earlier, the delay data of the standard cell is affected by the parameters of each process corner. To accurately obtain the delay data of the standard cell under different operating voltages and eliminate the influence of different process corner parameters, all process corner parameters other than the operating voltage are the same in each process corner acquired in this step. Correspondingly, the preset operating voltages included in each process corner are different. With this setting, the delay data of the standard cell under different operating voltages can be accurately obtained when acquiring delay data based on different process corners.

[0033] It should be noted that in practical applications, the process library files used in the physical design process record typical process corners. To facilitate the explanation of this method, the working voltage in the process corners recorded in the process library files can be defined as the reference working voltage. At the same time, the process library files also record the delay data corresponding to each process corner, that is, the delay data of the standard cell under different reference working voltages. The purpose of the method provided in this application is to determine the delay data of the standard cell under a preset working voltage that is not recorded in the existing process library files. It can be understood that the preset working voltage mentioned in this embodiment is the working voltage configured in combination with the physical design requirements. It can be determined in combination with the actual integrated circuit project requirements. This application does not limit the specific value of the preset working voltage.

[0034] Based on the above, in one optional implementation, the process corner obtained in this step can be determined based on the records in the process library file. The difference is that the reference operating voltage in the process corner needs to be replaced with a preset operating voltage to determine the delay data of the standard unit under different preset operating voltages in subsequent steps.

[0035] S110. Extract the element information of each standard element.

[0036] The unit information of a standard unit includes the unit name, port name, and signal direction of the port. Of course, in practical applications, the unit information may also include other information, which will not be detailed here.

[0037] In one optional implementation, considering the large number of standard cells, to improve the efficiency of cell information extraction, a unique netlist file can be created for each standard cell. The netlist file records the cell information of the standard cell. Then, a static timing analysis tool loads the netlist file corresponding to each standard cell to extract the cell information recorded in the netlist file, thus obtaining the cell information of each standard cell. The specific implementation of the static timing analysis tool extracting the content of the netlist file can be found in relevant technologies and will not be detailed here.

[0038] See Figure 2As shown, this application embodiment provides an optional implementation process for creating a netlist file for any standard unit, which mainly includes the following steps.

[0039] S1101. Create a blank netlist file for the standard cell and configure an instantiation name for the blank netlist file that uniquely corresponds to the standard cell.

[0040] First, create a blank netlist file for the standard cell. When processing standard cells in batches, in order to facilitate the differentiation of the netlist files corresponding to each standard cell and to achieve unified management of the netlist files, each netlist file can be configured with an instantiation name that uniquely corresponds to the standard cell, ensuring a one-to-one correspondence between the standard cell and the netlist file.

[0041] As mentioned earlier, the cell information of the standard cell includes the cell name. Based on this, as an optional implementation, the cell name can be used as a part of the instantiation name when configuring the instantiation name of the netlist file. This way, the instantiation name of the netlist file contains the cell name of the corresponding standard cell. When the static timing analysis tool loads the netlist file, it can determine the cell name of the standard cell corresponding to the netlist file through the instantiation name of the netlist file.

[0042] S1102. Obtain a preset string variable and use the preset string variable to store the port information of each external port in the standard unit.

[0043] Before extracting cell information, a preset string variable is created to store the port information of each external port in the standard cell. Specifically, a static timing analysis tool is used to obtain any cell port of the standard cell, and it is determined whether the cell port is an external port or an internal port. If it is an internal port, it is ignored, and the process continues to obtain the next cell port. If it is an external port, its port information is stored in the preset string variable, until the port information of all external ports in the standard cell is stored through the preset string variable.

[0044] S1103. Record the port information stored in the preset string variable into a blank netlist file to obtain the netlist file corresponding to the standard cell.

[0045] After storing the port information of all external ports in the standard unit using a preset string, the port information stored in the preset string variable is recorded in the blank netlist file created in the previous steps, thus obtaining the netlist file that uniquely corresponds to the standard unit.

[0046] At this point, the creation process of a standard cell's netlist file has been completed.

[0047] S1104. After completing the creation of the netlist file for any standard cell, clear the preset string variables.

[0048] After creating the netlist file for the standard element, the preset string variable is cleared so that it can be used in creating the netlist file for the next standard element, until the netlist files for all standard elements are created.

[0049] S120. Configure the operating conditions of the target standard unit according to the unit information of the target standard unit, and determine the target timing path of the target standard unit.

[0050] The standard cells obtained in S100 are used as target standard cells in sequence, and the processing procedures of this step and subsequent steps are performed on each target standard cell.

[0051] Based on the working principle of the standard cell, its operating conditions include at least input / output conditions and the preset operating voltage defined in the aforementioned process corner. The input / output conditions include the signal transition time at the input terminal and the load resistance and capacitance at the output terminal, i.e., the output load. These input / output conditions, besides the operating voltage, are the key factors directly determining the delay characteristics of the standard cell.

[0052] In practical applications, the input and output conditions of standard cells can be flexibly adjusted according to the design process. For example, in the early stages of physical design, the same input and output conditions can be specified for all standard cells to initially observe and compare the delay characteristics of different standard cells. In the later stages of physical design, different input and output conditions can be set in a targeted manner based on the usage and operating conditions of each standard cell. As for the specific configuration of input and output conditions, please refer to relevant technologies for implementation, which will not be detailed here.

[0053] Of course, in order to test the delay data of the standard cell, the process corner parameters defined in the aforementioned process corner are also essential for performing static timing analysis on the standard cell. As mentioned earlier, in any process corner, the process corner parameters other than the preset operating voltage can be determined based on the records in the process library file. The preset operating voltage needs to be set according to the project requirements of the integrated circuit physical design. The only limitation of the preset operating voltage is that it cannot exceed the voltage range defined by the standard cell library to avoid overvoltage damage to the standard cell.

[0054] Furthermore, in practical applications, some standard units have multiple input ports and multiple output ports. Different input ports can be combined to obtain different timing paths. Therefore, it is necessary to test all possible timing paths of the standard unit to obtain comprehensive delay data. Taking an adder unit with carry as an example, the delays of its two output ports are significantly different and cannot be treated as the same; their delay data need to be obtained separately.

[0055] Based on the above, this application provides an optional implementation method for configuring the operating conditions of a target standard unit and determining the target timing path. See [link to relevant documentation]. Figure 3 As shown, this method may include the following steps: S1201. Determine the element type of the target standard element based on the element information of the target standard element.

[0056] As mentioned earlier, standard units can be broadly categorized into two types: combinational logic units and sequential logic units. These two types of units have different signal processing methods during operation, thus requiring separate acquisition of their delay data. As also mentioned earlier, the unit information of a standard unit includes the unit name. When a supplier creates a standard unit, the unit name is directly related to the unit type. For example, for combinational logic units, INV is an abbreviation for "Inverter," explicitly indicating that it is an inverter whose function is to invert the output and input; NAND2 is "NAND" (NAND) plus the number "2," representing a 2-input NAND gate; AOI21 is a slightly more complex combinational unit, an abbreviation for "AND-OR-Invert," representing a fixed structure that first performs an AND-OR operation and then inverts the output. For sequential logic units, DFF is an abbreviation for "D-Type Flip-Flop," corresponding to a D-type flip-flop; SDFFQ is more about load, where "S" usually stands for "Scan," used for testing; "DFF" is a flip-flop; and "Q" indicates that it has a Q output. The corresponding functional unit is a D flip-flop with scan functionality. Based on this, the unit type of the target standard unit can be determined according to the unit name of the target standard unit.

[0057] Furthermore, the operating conditions of the target standard unit can be configured according to the unit type of the target standard unit, and the target timing path can be determined.

[0058] S1202. The target standard unit is a sequential logic unit. A clock signal source is configured on the clock port of the target standard unit, timing constraints are configured on the data port of the target standard unit, and the input signal transition time and output load are configured.

[0059] When the target standard cell is a sequential logic cell, a clock signal source needs to be configured at the clock port of the target standard cell to provide the clock signal required for its operation, based on the operational requirements of the sequential logic cell. Simultaneously, timing constraints, such as timing margin values, need to be configured at the data port of the target standard cell. Based on this, the input transition time and output load are configured. The input transition time refers to the time required for the input signal of the standard cell to change from one level (e.g., low or high) to another. Specifically, it typically represents the time difference for the input signal voltage to change from 10% to 90% (or vice versa) of the supply voltage range. The output load mainly refers to the output load capacitance, i.e., the capacitor connected to the output of the standard cell. It is one of the key factors affecting signal propagation delay, transition time, and power consumption. In static timing analysis and delay calculation, the output load usually refers to all capacitors connected to the output, including the input capacitors and wiring capacitors of subsequent units.

[0060] As for the timing constraints of the target standard unit data port, the specific configuration process and specific configuration values ​​of the input signal transition time and the output load, they can all be implemented with reference to relevant technologies, and will not be described in detail here.

[0061] S1203. Determine the target timing path based on the port type of the target standard unit.

[0062] When the target standard unit is a sequential logic unit, the determination of its target timing path needs to be further determined in conjunction with the specific function of the target standard unit. Taking a register as an example, it is equipped with a clock input terminal, a scan enable terminal, a scan signal input terminal, a signal input terminal, and a signal output terminal (there may be more than one). In practical applications, it is necessary to determine the target timing path in combination with the specific port type and signal transmission path. As for the specific process of determining the target timing path, please refer to the relevant technical implementation, which will not be detailed here.

[0063] S1204 The target standard unit is a combinational logic unit. Timing constraints are configured on each input port and each output port of the target standard unit, and the input signal transition time and output load are configured.

[0064] When the target standard unit is a combinational logic unit, timing constraints need to be configured for each input port and each output port of the target standard unit according to the operational requirements of the combinational logic unit. Input signal transition time and output load also need to be configured. The specific configuration process can be implemented in conjunction with the aforementioned content and related technologies, and will not be detailed here.

[0065] S1205. Take the combination of each input port and each output port in the target standard unit as the target timing path.

[0066] Based on the operating characteristics of combinational logic units, when the target standard unit has multiple input ports and / or multiple output ports, each combination of input port and each combination of output port can be used as a timing path. In practical applications, it is necessary to take the timing path obtained by combining each input port and output port as the target timing path in sequence, and perform static timing analysis on the target timing path according to the subsequent steps.

[0067] S130. Perform static timing analysis on the target timing path according to the operating conditions of the target standard unit under each process corner to obtain the delay data of the target standard unit under different preset operating voltages.

[0068] As mentioned earlier, the process corner is limited to the process corner parameters when performing static timing analysis on the target timing path of the target standard cell. In other words, each process corner can be understood as a static timing analysis scenario. By using the static timing analysis tool to load the process corner parameters corresponding to the process corner in S100, and performing static timing analysis on the target timing path according to the operating conditions of the target standard cell, the delay data of the target standard cell under the preset operating voltage of any process corner can be obtained. Since the process corner parameters other than the preset operating voltage are the same, after traversing all process corners, the delay data of the target standard cell under different preset operating voltages can be obtained.

[0069] As mentioned earlier, the process library file also records the process corners. Therefore, as an optional implementation, the process corners defined in S100 can be sequentially used as target process corners. The process library file corresponding to the target process corner can be obtained from the process library file, and the obtained process library file can be used as a process library file set. The process library files in the same process library file set all include a reference operating voltage, the delay data corresponding to the reference operating voltage, and other process corner parameters other than the reference operating voltage. It should be emphasized that the other process corner parameters in the process library file are the same as the other process corner parameters of the target process corner. In other words, any process library file in the process library file set is the same as its corresponding process corner, except that the operating voltage is different.

[0070] Based on the above, under the target process angle, static timing analysis tools can be used to perform static timing analysis on the target timing path according to the operating conditions of the target standard cell and the delay data corresponding to the reference operating voltage in the corresponding process library file. This will obtain the delay data of the target standard cell under the preset operating voltage corresponding to the target process angle. For example, interpolation calculations can be performed based on the reference operating voltage and the preset operating voltage, and then the delay data corresponding to the preset operating voltage can be determined based on the delay data corresponding to the reference operating voltage.

[0071] In summary, compared with related technologies, the standard cell timing data processing method provided in this application, which obtains the delay data of standard cells under different preset operating voltages, no longer relies on voltage drop simulation data that can only be obtained in the later stages of physical design. Therefore, the delay data of each standard cell under different preset operating voltages can be obtained before the physical design of integrated circuits, providing accurate and reliable reference data that meets the project design requirements as early as possible. This helps to predict and control the risk of timing violations and ensure the integrity of timing while ensuring the entire physical design cycle.

[0072] The method provided in this embodiment can also be used to quickly organize the delay data of standard cells from different processes and manufacturers under different operating voltages, and can also be used to conduct more detailed analysis on a certain type of standard cell, providing more detailed reference for physical design.

[0073] Furthermore, in practical applications, timing margins are set to eliminate the impact of standard cell delay durations and ensure correct timing. Based on this, in existing physical design processes, manufacturers typically conduct experiments and evaluations on the process and performance of standard cells, providing a parameter value (derate) to characterize the degree of influence of various factors on timing. The magnitude of this parameter value varies with the manufacturing process and differs depending on the type of standard cell, the type of timing check, and the timing path. Physical designers can use this parameter value to select standard cells and set timing margins. Therefore, the accuracy of this parameter value may affect the progress of the entire physical design process.

[0074] After obtaining the delay data of the standard unit under different preset operating voltages using the method provided in the embodiments of this application, the aforementioned parameter values ​​can be corrected based on the obtained delay data.

[0075] Specifically, the delay data of the standard unit under different preset operating voltages is used to determine the delay data of the standard unit at the standard voltage. The delay value is used as a benchmark for normalization, and the specific calculation formula is as follows: in, This represents the normalized value, used to characterize the extent to which the delay of a standard cell is affected by the power supply voltage drop; This indicates that the standard unit operates at a preset voltage. The following delay duration; Indicates the standard unit at standard voltage The duration of the delay.

[0076] In practical applications, the preset operating voltage is used. Empirical values ​​can be selected from physical design projects, taking the average operating voltage of a subset of standard units with relatively large power supply voltage drops. Depending on the design, different values ​​can be chosen. or .

[0077] if Greater than the empirical coefficient If the standard cell is considered to have certain risks, the derate value of the standard cell in the place and route tool will be reset to encourage the place and route tool to use other standard cells to replace this standard cell, thereby reducing its number or leaving timing margin in related paths, so as to reduce design risks.

[0078] Specifically, according to The methods for setting derate can be: or: in, This indicates the corrected value of the derate parameter; This indicates the value of the derate parameter before the correction.

[0079] The derate parameter values ​​obtained by correcting them according to the above method can more accurately reflect the delay characteristics of the standard unit, thus providing a more accurate reference for physical design.

[0080] The standard cell timing data processing apparatus provided by this invention is described below. This apparatus belongs to the same conceptual framework as the standard cell timing data processing method provided in the embodiments of this application. It can execute the standard cell timing data processing method provided in any embodiment of this application and possesses the corresponding functional modules and beneficial effects of the standard cell timing data processing method. Technical details not described in detail in this embodiment can be found in the standard cell timing data processing method provided in the embodiments of this application, and will not be repeated here.

[0081] See Figure 4As shown, the standard unit timing data processing apparatus provided in this application embodiment includes: The acquisition unit 10 is used to acquire at least one standard unit and multiple process corners, wherein the process corners include a preset working voltage and other process corner parameters, and the preset working voltages included in each process corner are different, while the other process corner parameters are the same. Processing unit 20 is used for: Extract the unit information of each of the aforementioned standard units; Configure the operating conditions of the target standard unit according to the unit information of the target standard unit, and determine the target timing path of the target standard unit, wherein the target standard unit is any one of the standard units; Static timing analysis is performed on the target timing path under the operating conditions of the target standard unit at each of the process angles to obtain the delay data of the target standard unit under different preset operating voltages.

[0082] Below, for reference Figure 5 The electronic device provided in this embodiment of the invention may include: at least one processor 100, at least one communication interface 200, at least one memory 300, and at least one communication bus 400. In this embodiment of the invention, the number of processor 100, communication interface 200, memory 300, and communication bus 400 is at least one, and the processor 100, communication interface 200, and memory 300 communicate with each other through communication bus 400; obviously, Figure 5 The communication connections shown for the processor 100, communication interface 200, memory 300, and communication bus 400 are optional. Optionally, the communication interface 200 can be an interface of a communication module, such as the interface of a GSM module; the processor 100 may be a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement embodiments of the present invention.

[0083] The memory 300 may include high-speed RAM memory, and may also include non-volatile memory, such as at least one disk storage device.

[0084] Specifically, the processor 100 is used to execute the application program in the memory to implement the steps of the standard cell timing data processing method described above.

[0085] In some embodiments, this embodiment also provides a computer-readable storage medium, such as a floppy disk, optical disk, hard disk, flash memory, USB flash drive, SD (Secure Digital Memory Card), MMC (Multimedia Card), etc., in which one or more instructions implementing the above steps are stored. When these one or more instructions are executed by one or more processors, the processors perform the standard unit timing data processing method described above. For specific implementation details, please refer to the foregoing description; further elaboration is not provided here.

[0086] In addition to the methods and apparatus described above, embodiments of this application may also be computer program products, which include computer program instructions that, when executed by a processor, cause the processor to perform the steps of the standard cell timing data processing method according to various embodiments of this application as described above.

[0087] Computer program products can be written in any combination of one or more programming languages ​​to perform the operations of the embodiments of this application. The programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0088] Those skilled in the art will understand that the contents disclosed herein can be varied and modified in many ways. For example, the various devices or components described above can be implemented in hardware, or in software, firmware, or a combination of some or all of the three.

[0089] Furthermore, while this disclosure makes various references to certain elements of systems according to embodiments of this disclosure, any number of different elements may be used and operated on clients and / or servers. Elements are merely illustrative, and different aspects of the system and method may use different elements.

[0090] This disclosure uses flowcharts to illustrate the steps of a method according to embodiments of this disclosure. It should be understood that the preceding or following steps are not necessarily performed in exact order. Instead, the steps can be processed in reverse order or simultaneously. Furthermore, other operations can be added to these processes.

[0091] Those skilled in the art will understand that all or part of the steps in the above methods can be implemented by a computer program instructing related hardware, and the program can be stored in a computer-readable storage medium, such as a read-only memory. Optionally, all or part of the steps in the above embodiments can also be implemented using one or more integrated circuits. Accordingly, each module / unit in the above embodiments can be implemented in hardware or as a software functional module. This disclosure is not limited to any particular combination of hardware and software.

[0092] Unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that terms such as those defined in a common dictionary should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or highly formalized meaning, unless expressly defined herein.

[0093] The foregoing description is intended to illustrate the present disclosure and should not be construed as limiting it. While several exemplary embodiments of the present disclosure have been described, those skilled in the art will readily understand that many modifications may be made to the exemplary embodiments without departing from the novel teachings and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure as defined by the claims. It should be understood that the foregoing description is intended to illustrate the present disclosure and should not be construed as limiting it to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The present disclosure is defined by the claims and their equivalents.

Claims

1. A standard cell timing data processing method, characterized by, The method comprises the following steps: obtaining at least one standard cell and a plurality of process corners, wherein the process corners comprise preset working voltages and other process corner parameters, the preset working voltages of the process corners are different, and the other process corner parameters are the same; extracting cell information of each standard cell; configuring operation conditions of a target standard cell according to the cell information of the target standard cell, and determining a target timing path of the target standard cell, wherein the target standard cell is any one of the standard cells; respectively performing static timing analysis on the target timing path under the operation conditions of the target standard cell at each process corner to obtain delay data of the target standard cell under different preset working voltages.

2. The method of claim 1, wherein, The step of extracting the cell information of each standard cell comprises the following steps: creating a netlist file for each standard cell, wherein the netlist file is used to record the cell information of the standard cell; loading the netlist file corresponding to each standard cell, and extracting the cell information recorded in the netlist file.

3. The method of claim 2, wherein, The process of creating a netlist file for any standard cell comprises the following steps: creating a blank netlist file for the standard cell, and configuring an instantiation name corresponding to the standard cell for the blank netlist file; obtaining a preset string variable, and storing port information of each external port of the standard cell in the preset string variable; recording the port information stored in the preset string variable in the blank netlist file to obtain the netlist file corresponding to the standard cell.

4. The method of claim 3, wherein, The method further comprises the following steps: after the netlist file of any standard cell is created, the preset string variable is emptied.

5. The method of claim 1, wherein, The step of configuring the operation conditions of the target standard cell according to the cell information of the target standard cell, and determining the target timing path of the target standard cell comprises the following steps: determining the cell type of the target standard cell according to the cell information of the target standard cell; configuring the operation conditions of the target standard cell according to the cell type of the target standard cell, and determining the target timing path of the target standard cell.

6. The method of claim 5, wherein, The cell type comprises a sequential logic cell and a combinational logic cell. The step of configuring the operation conditions of the target standard cell according to the cell type of the target standard cell, and determining the target timing path of the target standard cell comprises the following steps: if the target standard cell is a sequential logic cell, a clock signal source is configured at a clock port of the target standard cell, timing constraint conditions are configured at data ports of the target standard cell, and input signal transition time and output load are configured; and the target timing path is determined according to the port type of the target standard cell; if the target standard cell is a combinational logic cell, timing constraint conditions are configured at each input port and each output port of the target standard cell, and input signal transition time and output load are configured; and the combination of each input port and each output port of the target standard cell is taken as the target timing path.

7. The method of claim 1, wherein, The static timing analysis is performed on the target timing path under each of the process corners according to the operation condition of the target standard cell to obtain delay data of the target standard cell under different preset working voltages, including: obtaining a process library file corresponding to a target process corner, the process library file including a reference working voltage, delay data corresponding to the reference working voltage, and other process corner parameters of the target process corner, the target process corner being any one of the process corners; under the target process corner, performing static timing analysis on the target timing path according to the operation condition of the target standard cell and the delay data corresponding to the reference working voltage to obtain delay data of the target standard cell under a preset working voltage corresponding to the target process corner.

8. A standard cell timing data processing apparatus, characterized by, including: an obtaining unit, configured to obtain at least one standard cell and a plurality of process corners, wherein the process corners include preset working voltages and other process corner parameters, the preset working voltages included in each of the process corners being different, and the other process corner parameters being the same; a processing unit, configured to: extract cell information of each of the standard cells; configure an operation condition of a target standard cell according to the cell information of the target standard cell and determine a target timing path of the target standard cell, wherein the target standard cell is any one of the standard cells; perform static timing analysis on the target timing path under each of the process corners according to the operation condition of the target standard cell to obtain delay data of the target standard cell under different preset working voltages.

9. An electronic device comprising a memory, a processor, and a computer program stored on the memory for execution by the processor, characterized in that, The processor executes the computer program to implement the steps of the standard cell timing data processing method in any one of claims 1 to 7.

10. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to implement the steps of the standard cell timing data processing method in any one of claims 1 to 7.

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